1 /*
2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
3 *
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
7 *
8 * See MAINTAINERS file for support contact information.
9 */
10
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/pci.h>
14 #include <linux/netdevice.h>
15 #include <linux/etherdevice.h>
16 #include <linux/clk.h>
17 #include <linux/delay.h>
18 #include <linux/ethtool.h>
19 #include <linux/phy.h>
20 #include <linux/if_vlan.h>
21 #include <linux/crc32.h>
22 #include <linux/in.h>
23 #include <linux/io.h>
24 #include <linux/ip.h>
25 #include <linux/tcp.h>
26 #include <linux/interrupt.h>
27 #include <linux/dma-mapping.h>
28 #include <linux/pm_runtime.h>
29 #include <linux/firmware.h>
30 #include <linux/prefetch.h>
31 #include <linux/ipv6.h>
32 #include <net/ip6_checksum.h>
33
34 #define MODULENAME "r8169"
35
36 #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
37 #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
38 #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
39 #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
40 #define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw"
41 #define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw"
42 #define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw"
43 #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
44 #define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw"
45 #define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw"
46 #define FIRMWARE_8411_2 "rtl_nic/rtl8411-2.fw"
47 #define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw"
48 #define FIRMWARE_8106E_2 "rtl_nic/rtl8106e-2.fw"
49 #define FIRMWARE_8168G_2 "rtl_nic/rtl8168g-2.fw"
50 #define FIRMWARE_8168G_3 "rtl_nic/rtl8168g-3.fw"
51 #define FIRMWARE_8168H_1 "rtl_nic/rtl8168h-1.fw"
52 #define FIRMWARE_8168H_2 "rtl_nic/rtl8168h-2.fw"
53 #define FIRMWARE_8107E_1 "rtl_nic/rtl8107e-1.fw"
54 #define FIRMWARE_8107E_2 "rtl_nic/rtl8107e-2.fw"
55
56 #define R8169_MSG_DEFAULT \
57 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
58
59 #define TX_SLOTS_AVAIL(tp) \
60 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx)
61
62 /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
63 #define TX_FRAGS_READY_FOR(tp,nr_frags) \
64 (TX_SLOTS_AVAIL(tp) >= (nr_frags + 1))
65
66 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
67 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
68 static const int multicast_filter_limit = 32;
69
70 #define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */
71 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
72
73 #define R8169_REGS_SIZE 256
74 #define R8169_RX_BUF_SIZE (SZ_16K - 1)
75 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
76 #define NUM_RX_DESC 256U /* Number of Rx descriptor registers */
77 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
78 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
79
80 #define RTL8169_TX_TIMEOUT (6*HZ)
81
82 /* write/read MMIO register */
83 #define RTL_W8(tp, reg, val8) writeb((val8), tp->mmio_addr + (reg))
84 #define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg))
85 #define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg))
86 #define RTL_R8(tp, reg) readb(tp->mmio_addr + (reg))
87 #define RTL_R16(tp, reg) readw(tp->mmio_addr + (reg))
88 #define RTL_R32(tp, reg) readl(tp->mmio_addr + (reg))
89
90 enum mac_version {
91 RTL_GIGA_MAC_VER_01 = 0,
92 RTL_GIGA_MAC_VER_02,
93 RTL_GIGA_MAC_VER_03,
94 RTL_GIGA_MAC_VER_04,
95 RTL_GIGA_MAC_VER_05,
96 RTL_GIGA_MAC_VER_06,
97 RTL_GIGA_MAC_VER_07,
98 RTL_GIGA_MAC_VER_08,
99 RTL_GIGA_MAC_VER_09,
100 RTL_GIGA_MAC_VER_10,
101 RTL_GIGA_MAC_VER_11,
102 RTL_GIGA_MAC_VER_12,
103 RTL_GIGA_MAC_VER_13,
104 RTL_GIGA_MAC_VER_14,
105 RTL_GIGA_MAC_VER_15,
106 RTL_GIGA_MAC_VER_16,
107 RTL_GIGA_MAC_VER_17,
108 RTL_GIGA_MAC_VER_18,
109 RTL_GIGA_MAC_VER_19,
110 RTL_GIGA_MAC_VER_20,
111 RTL_GIGA_MAC_VER_21,
112 RTL_GIGA_MAC_VER_22,
113 RTL_GIGA_MAC_VER_23,
114 RTL_GIGA_MAC_VER_24,
115 RTL_GIGA_MAC_VER_25,
116 RTL_GIGA_MAC_VER_26,
117 RTL_GIGA_MAC_VER_27,
118 RTL_GIGA_MAC_VER_28,
119 RTL_GIGA_MAC_VER_29,
120 RTL_GIGA_MAC_VER_30,
121 RTL_GIGA_MAC_VER_31,
122 RTL_GIGA_MAC_VER_32,
123 RTL_GIGA_MAC_VER_33,
124 RTL_GIGA_MAC_VER_34,
125 RTL_GIGA_MAC_VER_35,
126 RTL_GIGA_MAC_VER_36,
127 RTL_GIGA_MAC_VER_37,
128 RTL_GIGA_MAC_VER_38,
129 RTL_GIGA_MAC_VER_39,
130 RTL_GIGA_MAC_VER_40,
131 RTL_GIGA_MAC_VER_41,
132 RTL_GIGA_MAC_VER_42,
133 RTL_GIGA_MAC_VER_43,
134 RTL_GIGA_MAC_VER_44,
135 RTL_GIGA_MAC_VER_45,
136 RTL_GIGA_MAC_VER_46,
137 RTL_GIGA_MAC_VER_47,
138 RTL_GIGA_MAC_VER_48,
139 RTL_GIGA_MAC_VER_49,
140 RTL_GIGA_MAC_VER_50,
141 RTL_GIGA_MAC_VER_51,
142 RTL_GIGA_MAC_NONE = 0xff,
143 };
144
145 #define JUMBO_1K ETH_DATA_LEN
146 #define JUMBO_4K (4*1024 - ETH_HLEN - 2)
147 #define JUMBO_6K (6*1024 - ETH_HLEN - 2)
148 #define JUMBO_7K (7*1024 - ETH_HLEN - 2)
149 #define JUMBO_9K (9*1024 - ETH_HLEN - 2)
150
151 static const struct {
152 const char *name;
153 const char *fw_name;
154 } rtl_chip_infos[] = {
155 /* PCI devices. */
156 [RTL_GIGA_MAC_VER_01] = {"RTL8169" },
157 [RTL_GIGA_MAC_VER_02] = {"RTL8169s" },
158 [RTL_GIGA_MAC_VER_03] = {"RTL8110s" },
159 [RTL_GIGA_MAC_VER_04] = {"RTL8169sb/8110sb" },
160 [RTL_GIGA_MAC_VER_05] = {"RTL8169sc/8110sc" },
161 [RTL_GIGA_MAC_VER_06] = {"RTL8169sc/8110sc" },
162 /* PCI-E devices. */
163 [RTL_GIGA_MAC_VER_07] = {"RTL8102e" },
164 [RTL_GIGA_MAC_VER_08] = {"RTL8102e" },
165 [RTL_GIGA_MAC_VER_09] = {"RTL8102e" },
166 [RTL_GIGA_MAC_VER_10] = {"RTL8101e" },
167 [RTL_GIGA_MAC_VER_11] = {"RTL8168b/8111b" },
168 [RTL_GIGA_MAC_VER_12] = {"RTL8168b/8111b" },
169 [RTL_GIGA_MAC_VER_13] = {"RTL8101e" },
170 [RTL_GIGA_MAC_VER_14] = {"RTL8100e" },
171 [RTL_GIGA_MAC_VER_15] = {"RTL8100e" },
172 [RTL_GIGA_MAC_VER_16] = {"RTL8101e" },
173 [RTL_GIGA_MAC_VER_17] = {"RTL8168b/8111b" },
174 [RTL_GIGA_MAC_VER_18] = {"RTL8168cp/8111cp" },
175 [RTL_GIGA_MAC_VER_19] = {"RTL8168c/8111c" },
176 [RTL_GIGA_MAC_VER_20] = {"RTL8168c/8111c" },
177 [RTL_GIGA_MAC_VER_21] = {"RTL8168c/8111c" },
178 [RTL_GIGA_MAC_VER_22] = {"RTL8168c/8111c" },
179 [RTL_GIGA_MAC_VER_23] = {"RTL8168cp/8111cp" },
180 [RTL_GIGA_MAC_VER_24] = {"RTL8168cp/8111cp" },
181 [RTL_GIGA_MAC_VER_25] = {"RTL8168d/8111d", FIRMWARE_8168D_1},
182 [RTL_GIGA_MAC_VER_26] = {"RTL8168d/8111d", FIRMWARE_8168D_2},
183 [RTL_GIGA_MAC_VER_27] = {"RTL8168dp/8111dp" },
184 [RTL_GIGA_MAC_VER_28] = {"RTL8168dp/8111dp" },
185 [RTL_GIGA_MAC_VER_29] = {"RTL8105e", FIRMWARE_8105E_1},
186 [RTL_GIGA_MAC_VER_30] = {"RTL8105e", FIRMWARE_8105E_1},
187 [RTL_GIGA_MAC_VER_31] = {"RTL8168dp/8111dp" },
188 [RTL_GIGA_MAC_VER_32] = {"RTL8168e/8111e", FIRMWARE_8168E_1},
189 [RTL_GIGA_MAC_VER_33] = {"RTL8168e/8111e", FIRMWARE_8168E_2},
190 [RTL_GIGA_MAC_VER_34] = {"RTL8168evl/8111evl", FIRMWARE_8168E_3},
191 [RTL_GIGA_MAC_VER_35] = {"RTL8168f/8111f", FIRMWARE_8168F_1},
192 [RTL_GIGA_MAC_VER_36] = {"RTL8168f/8111f", FIRMWARE_8168F_2},
193 [RTL_GIGA_MAC_VER_37] = {"RTL8402", FIRMWARE_8402_1 },
194 [RTL_GIGA_MAC_VER_38] = {"RTL8411", FIRMWARE_8411_1 },
195 [RTL_GIGA_MAC_VER_39] = {"RTL8106e", FIRMWARE_8106E_1},
196 [RTL_GIGA_MAC_VER_40] = {"RTL8168g/8111g", FIRMWARE_8168G_2},
197 [RTL_GIGA_MAC_VER_41] = {"RTL8168g/8111g" },
198 [RTL_GIGA_MAC_VER_42] = {"RTL8168g/8111g", FIRMWARE_8168G_3},
199 [RTL_GIGA_MAC_VER_43] = {"RTL8106e", FIRMWARE_8106E_2},
200 [RTL_GIGA_MAC_VER_44] = {"RTL8411", FIRMWARE_8411_2 },
201 [RTL_GIGA_MAC_VER_45] = {"RTL8168h/8111h", FIRMWARE_8168H_1},
202 [RTL_GIGA_MAC_VER_46] = {"RTL8168h/8111h", FIRMWARE_8168H_2},
203 [RTL_GIGA_MAC_VER_47] = {"RTL8107e", FIRMWARE_8107E_1},
204 [RTL_GIGA_MAC_VER_48] = {"RTL8107e", FIRMWARE_8107E_2},
205 [RTL_GIGA_MAC_VER_49] = {"RTL8168ep/8111ep" },
206 [RTL_GIGA_MAC_VER_50] = {"RTL8168ep/8111ep" },
207 [RTL_GIGA_MAC_VER_51] = {"RTL8168ep/8111ep" },
208 };
209
210 enum cfg_version {
211 RTL_CFG_0 = 0x00,
212 RTL_CFG_1,
213 RTL_CFG_2
214 };
215
216 static const struct pci_device_id rtl8169_pci_tbl[] = {
217 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
218 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
219 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8161), 0, 0, RTL_CFG_1 },
220 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
221 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
222 { PCI_DEVICE(PCI_VENDOR_ID_NCUBE, 0x8168), 0, 0, RTL_CFG_1 },
223 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
224 { PCI_VENDOR_ID_DLINK, 0x4300,
225 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0, RTL_CFG_1 },
226 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
227 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4302), 0, 0, RTL_CFG_0 },
228 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
229 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
230 { PCI_VENDOR_ID_LINKSYS, 0x1032,
231 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
232 { 0x0001, 0x8168,
233 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
234 {0,},
235 };
236
237 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
238
239 static int use_dac = -1;
240 static struct {
241 u32 msg_enable;
242 } debug = { -1 };
243
244 enum rtl_registers {
245 MAC0 = 0, /* Ethernet hardware address. */
246 MAC4 = 4,
247 MAR0 = 8, /* Multicast filter. */
248 CounterAddrLow = 0x10,
249 CounterAddrHigh = 0x14,
250 TxDescStartAddrLow = 0x20,
251 TxDescStartAddrHigh = 0x24,
252 TxHDescStartAddrLow = 0x28,
253 TxHDescStartAddrHigh = 0x2c,
254 FLASH = 0x30,
255 ERSR = 0x36,
256 ChipCmd = 0x37,
257 TxPoll = 0x38,
258 IntrMask = 0x3c,
259 IntrStatus = 0x3e,
260
261 TxConfig = 0x40,
262 #define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */
263 #define TXCFG_EMPTY (1 << 11) /* 8111e-vl */
264
265 RxConfig = 0x44,
266 #define RX128_INT_EN (1 << 15) /* 8111c and later */
267 #define RX_MULTI_EN (1 << 14) /* 8111c only */
268 #define RXCFG_FIFO_SHIFT 13
269 /* No threshold before first PCI xfer */
270 #define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT)
271 #define RX_EARLY_OFF (1 << 11)
272 #define RXCFG_DMA_SHIFT 8
273 /* Unlimited maximum PCI burst. */
274 #define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT)
275
276 RxMissed = 0x4c,
277 Cfg9346 = 0x50,
278 Config0 = 0x51,
279 Config1 = 0x52,
280 Config2 = 0x53,
281 #define PME_SIGNAL (1 << 5) /* 8168c and later */
282
283 Config3 = 0x54,
284 Config4 = 0x55,
285 Config5 = 0x56,
286 MultiIntr = 0x5c,
287 PHYAR = 0x60,
288 PHYstatus = 0x6c,
289 RxMaxSize = 0xda,
290 CPlusCmd = 0xe0,
291 IntrMitigate = 0xe2,
292
293 #define RTL_COALESCE_MASK 0x0f
294 #define RTL_COALESCE_SHIFT 4
295 #define RTL_COALESCE_T_MAX (RTL_COALESCE_MASK)
296 #define RTL_COALESCE_FRAME_MAX (RTL_COALESCE_MASK << 2)
297
298 RxDescAddrLow = 0xe4,
299 RxDescAddrHigh = 0xe8,
300 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
301
302 #define NoEarlyTx 0x3f /* Max value : no early transmit. */
303
304 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
305
306 #define TxPacketMax (8064 >> 7)
307 #define EarlySize 0x27
308
309 FuncEvent = 0xf0,
310 FuncEventMask = 0xf4,
311 FuncPresetState = 0xf8,
312 IBCR0 = 0xf8,
313 IBCR2 = 0xf9,
314 IBIMR0 = 0xfa,
315 IBISR0 = 0xfb,
316 FuncForceEvent = 0xfc,
317 };
318
319 enum rtl8168_8101_registers {
320 CSIDR = 0x64,
321 CSIAR = 0x68,
322 #define CSIAR_FLAG 0x80000000
323 #define CSIAR_WRITE_CMD 0x80000000
324 #define CSIAR_BYTE_ENABLE 0x0000f000
325 #define CSIAR_ADDR_MASK 0x00000fff
326 PMCH = 0x6f,
327 EPHYAR = 0x80,
328 #define EPHYAR_FLAG 0x80000000
329 #define EPHYAR_WRITE_CMD 0x80000000
330 #define EPHYAR_REG_MASK 0x1f
331 #define EPHYAR_REG_SHIFT 16
332 #define EPHYAR_DATA_MASK 0xffff
333 DLLPR = 0xd0,
334 #define PFM_EN (1 << 6)
335 #define TX_10M_PS_EN (1 << 7)
336 DBG_REG = 0xd1,
337 #define FIX_NAK_1 (1 << 4)
338 #define FIX_NAK_2 (1 << 3)
339 TWSI = 0xd2,
340 MCU = 0xd3,
341 #define NOW_IS_OOB (1 << 7)
342 #define TX_EMPTY (1 << 5)
343 #define RX_EMPTY (1 << 4)
344 #define RXTX_EMPTY (TX_EMPTY | RX_EMPTY)
345 #define EN_NDP (1 << 3)
346 #define EN_OOB_RESET (1 << 2)
347 #define LINK_LIST_RDY (1 << 1)
348 EFUSEAR = 0xdc,
349 #define EFUSEAR_FLAG 0x80000000
350 #define EFUSEAR_WRITE_CMD 0x80000000
351 #define EFUSEAR_READ_CMD 0x00000000
352 #define EFUSEAR_REG_MASK 0x03ff
353 #define EFUSEAR_REG_SHIFT 8
354 #define EFUSEAR_DATA_MASK 0xff
355 MISC_1 = 0xf2,
356 #define PFM_D3COLD_EN (1 << 6)
357 };
358
359 enum rtl8168_registers {
360 LED_FREQ = 0x1a,
361 EEE_LED = 0x1b,
362 ERIDR = 0x70,
363 ERIAR = 0x74,
364 #define ERIAR_FLAG 0x80000000
365 #define ERIAR_WRITE_CMD 0x80000000
366 #define ERIAR_READ_CMD 0x00000000
367 #define ERIAR_ADDR_BYTE_ALIGN 4
368 #define ERIAR_TYPE_SHIFT 16
369 #define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT)
370 #define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT)
371 #define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT)
372 #define ERIAR_OOB (0x02 << ERIAR_TYPE_SHIFT)
373 #define ERIAR_MASK_SHIFT 12
374 #define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT)
375 #define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT)
376 #define ERIAR_MASK_0100 (0x4 << ERIAR_MASK_SHIFT)
377 #define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT)
378 #define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT)
379 EPHY_RXER_NUM = 0x7c,
380 OCPDR = 0xb0, /* OCP GPHY access */
381 #define OCPDR_WRITE_CMD 0x80000000
382 #define OCPDR_READ_CMD 0x00000000
383 #define OCPDR_REG_MASK 0x7f
384 #define OCPDR_GPHY_REG_SHIFT 16
385 #define OCPDR_DATA_MASK 0xffff
386 OCPAR = 0xb4,
387 #define OCPAR_FLAG 0x80000000
388 #define OCPAR_GPHY_WRITE_CMD 0x8000f060
389 #define OCPAR_GPHY_READ_CMD 0x0000f060
390 GPHY_OCP = 0xb8,
391 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */
392 MISC = 0xf0, /* 8168e only. */
393 #define TXPLA_RST (1 << 29)
394 #define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */
395 #define PWM_EN (1 << 22)
396 #define RXDV_GATED_EN (1 << 19)
397 #define EARLY_TALLY_EN (1 << 16)
398 };
399
400 enum rtl_register_content {
401 /* InterruptStatusBits */
402 SYSErr = 0x8000,
403 PCSTimeout = 0x4000,
404 SWInt = 0x0100,
405 TxDescUnavail = 0x0080,
406 RxFIFOOver = 0x0040,
407 LinkChg = 0x0020,
408 RxOverflow = 0x0010,
409 TxErr = 0x0008,
410 TxOK = 0x0004,
411 RxErr = 0x0002,
412 RxOK = 0x0001,
413
414 /* RxStatusDesc */
415 RxBOVF = (1 << 24),
416 RxFOVF = (1 << 23),
417 RxRWT = (1 << 22),
418 RxRES = (1 << 21),
419 RxRUNT = (1 << 20),
420 RxCRC = (1 << 19),
421
422 /* ChipCmdBits */
423 StopReq = 0x80,
424 CmdReset = 0x10,
425 CmdRxEnb = 0x08,
426 CmdTxEnb = 0x04,
427 RxBufEmpty = 0x01,
428
429 /* TXPoll register p.5 */
430 HPQ = 0x80, /* Poll cmd on the high prio queue */
431 NPQ = 0x40, /* Poll cmd on the low prio queue */
432 FSWInt = 0x01, /* Forced software interrupt */
433
434 /* Cfg9346Bits */
435 Cfg9346_Lock = 0x00,
436 Cfg9346_Unlock = 0xc0,
437
438 /* rx_mode_bits */
439 AcceptErr = 0x20,
440 AcceptRunt = 0x10,
441 AcceptBroadcast = 0x08,
442 AcceptMulticast = 0x04,
443 AcceptMyPhys = 0x02,
444 AcceptAllPhys = 0x01,
445 #define RX_CONFIG_ACCEPT_MASK 0x3f
446
447 /* TxConfigBits */
448 TxInterFrameGapShift = 24,
449 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
450
451 /* Config1 register p.24 */
452 LEDS1 = (1 << 7),
453 LEDS0 = (1 << 6),
454 Speed_down = (1 << 4),
455 MEMMAP = (1 << 3),
456 IOMAP = (1 << 2),
457 VPD = (1 << 1),
458 PMEnable = (1 << 0), /* Power Management Enable */
459
460 /* Config2 register p. 25 */
461 ClkReqEn = (1 << 7), /* Clock Request Enable */
462 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */
463 PCI_Clock_66MHz = 0x01,
464 PCI_Clock_33MHz = 0x00,
465
466 /* Config3 register p.25 */
467 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
468 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
469 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */
470 Rdy_to_L23 = (1 << 1), /* L23 Enable */
471 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
472
473 /* Config4 register */
474 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */
475
476 /* Config5 register p.27 */
477 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
478 MWF = (1 << 5), /* Accept Multicast wakeup frame */
479 UWF = (1 << 4), /* Accept Unicast wakeup frame */
480 Spi_en = (1 << 3),
481 LanWake = (1 << 1), /* LanWake enable/disable */
482 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
483 ASPM_en = (1 << 0), /* ASPM enable */
484
485 /* CPlusCmd p.31 */
486 EnableBist = (1 << 15), // 8168 8101
487 Mac_dbgo_oe = (1 << 14), // 8168 8101
488 Normal_mode = (1 << 13), // unused
489 Force_half_dup = (1 << 12), // 8168 8101
490 Force_rxflow_en = (1 << 11), // 8168 8101
491 Force_txflow_en = (1 << 10), // 8168 8101
492 Cxpl_dbg_sel = (1 << 9), // 8168 8101
493 ASF = (1 << 8), // 8168 8101
494 PktCntrDisable = (1 << 7), // 8168 8101
495 Mac_dbgo_sel = 0x001c, // 8168
496 RxVlan = (1 << 6),
497 RxChkSum = (1 << 5),
498 PCIDAC = (1 << 4),
499 PCIMulRW = (1 << 3),
500 #define INTT_MASK GENMASK(1, 0)
501 INTT_0 = 0x0000, // 8168
502 INTT_1 = 0x0001, // 8168
503 INTT_2 = 0x0002, // 8168
504 INTT_3 = 0x0003, // 8168
505
506 /* rtl8169_PHYstatus */
507 TBI_Enable = 0x80,
508 TxFlowCtrl = 0x40,
509 RxFlowCtrl = 0x20,
510 _1000bpsF = 0x10,
511 _100bps = 0x08,
512 _10bps = 0x04,
513 LinkStatus = 0x02,
514 FullDup = 0x01,
515
516 /* _TBICSRBit */
517 TBILinkOK = 0x02000000,
518
519 /* ResetCounterCommand */
520 CounterReset = 0x1,
521
522 /* DumpCounterCommand */
523 CounterDump = 0x8,
524
525 /* magic enable v2 */
526 MagicPacket_v2 = (1 << 16), /* Wake up when receives a Magic Packet */
527 };
528
529 enum rtl_desc_bit {
530 /* First doubleword. */
531 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
532 RingEnd = (1 << 30), /* End of descriptor ring */
533 FirstFrag = (1 << 29), /* First segment of a packet */
534 LastFrag = (1 << 28), /* Final segment of a packet */
535 };
536
537 /* Generic case. */
538 enum rtl_tx_desc_bit {
539 /* First doubleword. */
540 TD_LSO = (1 << 27), /* Large Send Offload */
541 #define TD_MSS_MAX 0x07ffu /* MSS value */
542
543 /* Second doubleword. */
544 TxVlanTag = (1 << 17), /* Add VLAN tag */
545 };
546
547 /* 8169, 8168b and 810x except 8102e. */
548 enum rtl_tx_desc_bit_0 {
549 /* First doubleword. */
550 #define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */
551 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */
552 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */
553 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */
554 };
555
556 /* 8102e, 8168c and beyond. */
557 enum rtl_tx_desc_bit_1 {
558 /* First doubleword. */
559 TD1_GTSENV4 = (1 << 26), /* Giant Send for IPv4 */
560 TD1_GTSENV6 = (1 << 25), /* Giant Send for IPv6 */
561 #define GTTCPHO_SHIFT 18
562 #define GTTCPHO_MAX 0x7fU
563
564 /* Second doubleword. */
565 #define TCPHO_SHIFT 18
566 #define TCPHO_MAX 0x3ffU
567 #define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */
568 TD1_IPv6_CS = (1 << 28), /* Calculate IPv6 checksum */
569 TD1_IPv4_CS = (1 << 29), /* Calculate IPv4 checksum */
570 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */
571 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */
572 };
573
574 enum rtl_rx_desc_bit {
575 /* Rx private */
576 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
577 PID0 = (1 << 17), /* Protocol ID bit 0/2 */
578
579 #define RxProtoUDP (PID1)
580 #define RxProtoTCP (PID0)
581 #define RxProtoIP (PID1 | PID0)
582 #define RxProtoMask RxProtoIP
583
584 IPFail = (1 << 16), /* IP checksum failed */
585 UDPFail = (1 << 15), /* UDP/IP checksum failed */
586 TCPFail = (1 << 14), /* TCP/IP checksum failed */
587 RxVlanTag = (1 << 16), /* VLAN tag available */
588 };
589
590 #define RsvdMask 0x3fffc000
591 #define CPCMD_QUIRK_MASK (Normal_mode | RxVlan | RxChkSum | INTT_MASK)
592
593 struct TxDesc {
594 __le32 opts1;
595 __le32 opts2;
596 __le64 addr;
597 };
598
599 struct RxDesc {
600 __le32 opts1;
601 __le32 opts2;
602 __le64 addr;
603 };
604
605 struct ring_info {
606 struct sk_buff *skb;
607 u32 len;
608 u8 __pad[sizeof(void *) - sizeof(u32)];
609 };
610
611 struct rtl8169_counters {
612 __le64 tx_packets;
613 __le64 rx_packets;
614 __le64 tx_errors;
615 __le32 rx_errors;
616 __le16 rx_missed;
617 __le16 align_errors;
618 __le32 tx_one_collision;
619 __le32 tx_multi_collision;
620 __le64 rx_unicast;
621 __le64 rx_broadcast;
622 __le32 rx_multicast;
623 __le16 tx_aborted;
624 __le16 tx_underun;
625 };
626
627 struct rtl8169_tc_offsets {
628 bool inited;
629 __le64 tx_errors;
630 __le32 tx_multi_collision;
631 __le16 tx_aborted;
632 };
633
634 enum rtl_flag {
635 RTL_FLAG_TASK_ENABLED = 0,
636 RTL_FLAG_TASK_SLOW_PENDING,
637 RTL_FLAG_TASK_RESET_PENDING,
638 RTL_FLAG_MAX
639 };
640
641 struct rtl8169_stats {
642 u64 packets;
643 u64 bytes;
644 struct u64_stats_sync syncp;
645 };
646
647 struct rtl8169_private {
648 void __iomem *mmio_addr; /* memory map physical address */
649 struct pci_dev *pci_dev;
650 struct net_device *dev;
651 struct napi_struct napi;
652 u32 msg_enable;
653 u16 mac_version;
654 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
655 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
656 u32 dirty_tx;
657 struct rtl8169_stats rx_stats;
658 struct rtl8169_stats tx_stats;
659 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
660 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
661 dma_addr_t TxPhyAddr;
662 dma_addr_t RxPhyAddr;
663 void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
664 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
665 u16 cp_cmd;
666
667 u16 event_slow;
668 const struct rtl_coalesce_info *coalesce_info;
669 struct clk *clk;
670
671 struct mdio_ops {
672 void (*write)(struct rtl8169_private *, int, int);
673 int (*read)(struct rtl8169_private *, int);
674 } mdio_ops;
675
676 struct jumbo_ops {
677 void (*enable)(struct rtl8169_private *);
678 void (*disable)(struct rtl8169_private *);
679 } jumbo_ops;
680
681 void (*hw_start)(struct rtl8169_private *tp);
682 bool (*tso_csum)(struct rtl8169_private *, struct sk_buff *, u32 *);
683
684 struct {
685 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
686 struct mutex mutex;
687 struct work_struct work;
688 } wk;
689
690 unsigned supports_gmii:1;
691 struct mii_bus *mii_bus;
692 dma_addr_t counters_phys_addr;
693 struct rtl8169_counters *counters;
694 struct rtl8169_tc_offsets tc_offset;
695 u32 saved_wolopts;
696
697 struct rtl_fw {
698 const struct firmware *fw;
699
700 #define RTL_VER_SIZE 32
701
702 char version[RTL_VER_SIZE];
703
704 struct rtl_fw_phy_action {
705 __le32 *code;
706 size_t size;
707 } phy_action;
708 } *rtl_fw;
709 #define RTL_FIRMWARE_UNKNOWN ERR_PTR(-EAGAIN)
710
711 u32 ocp_base;
712 };
713
714 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
715 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
716 module_param(use_dac, int, 0);
717 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
718 module_param_named(debug, debug.msg_enable, int, 0);
719 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
720 MODULE_LICENSE("GPL");
721 MODULE_FIRMWARE(FIRMWARE_8168D_1);
722 MODULE_FIRMWARE(FIRMWARE_8168D_2);
723 MODULE_FIRMWARE(FIRMWARE_8168E_1);
724 MODULE_FIRMWARE(FIRMWARE_8168E_2);
725 MODULE_FIRMWARE(FIRMWARE_8168E_3);
726 MODULE_FIRMWARE(FIRMWARE_8105E_1);
727 MODULE_FIRMWARE(FIRMWARE_8168F_1);
728 MODULE_FIRMWARE(FIRMWARE_8168F_2);
729 MODULE_FIRMWARE(FIRMWARE_8402_1);
730 MODULE_FIRMWARE(FIRMWARE_8411_1);
731 MODULE_FIRMWARE(FIRMWARE_8411_2);
732 MODULE_FIRMWARE(FIRMWARE_8106E_1);
733 MODULE_FIRMWARE(FIRMWARE_8106E_2);
734 MODULE_FIRMWARE(FIRMWARE_8168G_2);
735 MODULE_FIRMWARE(FIRMWARE_8168G_3);
736 MODULE_FIRMWARE(FIRMWARE_8168H_1);
737 MODULE_FIRMWARE(FIRMWARE_8168H_2);
738 MODULE_FIRMWARE(FIRMWARE_8107E_1);
739 MODULE_FIRMWARE(FIRMWARE_8107E_2);
740
tp_to_dev(struct rtl8169_private * tp)741 static inline struct device *tp_to_dev(struct rtl8169_private *tp)
742 {
743 return &tp->pci_dev->dev;
744 }
745
rtl_lock_work(struct rtl8169_private * tp)746 static void rtl_lock_work(struct rtl8169_private *tp)
747 {
748 mutex_lock(&tp->wk.mutex);
749 }
750
rtl_unlock_work(struct rtl8169_private * tp)751 static void rtl_unlock_work(struct rtl8169_private *tp)
752 {
753 mutex_unlock(&tp->wk.mutex);
754 }
755
rtl_tx_performance_tweak(struct rtl8169_private * tp,u16 force)756 static void rtl_tx_performance_tweak(struct rtl8169_private *tp, u16 force)
757 {
758 pcie_capability_clear_and_set_word(tp->pci_dev, PCI_EXP_DEVCTL,
759 PCI_EXP_DEVCTL_READRQ, force);
760 }
761
762 struct rtl_cond {
763 bool (*check)(struct rtl8169_private *);
764 const char *msg;
765 };
766
rtl_udelay(unsigned int d)767 static void rtl_udelay(unsigned int d)
768 {
769 udelay(d);
770 }
771
rtl_loop_wait(struct rtl8169_private * tp,const struct rtl_cond * c,void (* delay)(unsigned int),unsigned int d,int n,bool high)772 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
773 void (*delay)(unsigned int), unsigned int d, int n,
774 bool high)
775 {
776 int i;
777
778 for (i = 0; i < n; i++) {
779 delay(d);
780 if (c->check(tp) == high)
781 return true;
782 }
783 netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n",
784 c->msg, !high, n, d);
785 return false;
786 }
787
rtl_udelay_loop_wait_high(struct rtl8169_private * tp,const struct rtl_cond * c,unsigned int d,int n)788 static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp,
789 const struct rtl_cond *c,
790 unsigned int d, int n)
791 {
792 return rtl_loop_wait(tp, c, rtl_udelay, d, n, true);
793 }
794
rtl_udelay_loop_wait_low(struct rtl8169_private * tp,const struct rtl_cond * c,unsigned int d,int n)795 static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp,
796 const struct rtl_cond *c,
797 unsigned int d, int n)
798 {
799 return rtl_loop_wait(tp, c, rtl_udelay, d, n, false);
800 }
801
rtl_msleep_loop_wait_high(struct rtl8169_private * tp,const struct rtl_cond * c,unsigned int d,int n)802 static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp,
803 const struct rtl_cond *c,
804 unsigned int d, int n)
805 {
806 return rtl_loop_wait(tp, c, msleep, d, n, true);
807 }
808
rtl_msleep_loop_wait_low(struct rtl8169_private * tp,const struct rtl_cond * c,unsigned int d,int n)809 static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp,
810 const struct rtl_cond *c,
811 unsigned int d, int n)
812 {
813 return rtl_loop_wait(tp, c, msleep, d, n, false);
814 }
815
816 #define DECLARE_RTL_COND(name) \
817 static bool name ## _check(struct rtl8169_private *); \
818 \
819 static const struct rtl_cond name = { \
820 .check = name ## _check, \
821 .msg = #name \
822 }; \
823 \
824 static bool name ## _check(struct rtl8169_private *tp)
825
rtl_ocp_reg_failure(struct rtl8169_private * tp,u32 reg)826 static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg)
827 {
828 if (reg & 0xffff0001) {
829 netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg);
830 return true;
831 }
832 return false;
833 }
834
DECLARE_RTL_COND(rtl_ocp_gphy_cond)835 DECLARE_RTL_COND(rtl_ocp_gphy_cond)
836 {
837 return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG;
838 }
839
r8168_phy_ocp_write(struct rtl8169_private * tp,u32 reg,u32 data)840 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
841 {
842 if (rtl_ocp_reg_failure(tp, reg))
843 return;
844
845 RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
846
847 rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
848 }
849
r8168_phy_ocp_read(struct rtl8169_private * tp,u32 reg)850 static u16 r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
851 {
852 if (rtl_ocp_reg_failure(tp, reg))
853 return 0;
854
855 RTL_W32(tp, GPHY_OCP, reg << 15);
856
857 return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
858 (RTL_R32(tp, GPHY_OCP) & 0xffff) : ~0;
859 }
860
r8168_mac_ocp_write(struct rtl8169_private * tp,u32 reg,u32 data)861 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
862 {
863 if (rtl_ocp_reg_failure(tp, reg))
864 return;
865
866 RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data);
867 }
868
r8168_mac_ocp_read(struct rtl8169_private * tp,u32 reg)869 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
870 {
871 if (rtl_ocp_reg_failure(tp, reg))
872 return 0;
873
874 RTL_W32(tp, OCPDR, reg << 15);
875
876 return RTL_R32(tp, OCPDR);
877 }
878
879 #define OCP_STD_PHY_BASE 0xa400
880
r8168g_mdio_write(struct rtl8169_private * tp,int reg,int value)881 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
882 {
883 if (reg == 0x1f) {
884 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
885 return;
886 }
887
888 if (tp->ocp_base != OCP_STD_PHY_BASE)
889 reg -= 0x10;
890
891 r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
892 }
893
r8168g_mdio_read(struct rtl8169_private * tp,int reg)894 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
895 {
896 if (tp->ocp_base != OCP_STD_PHY_BASE)
897 reg -= 0x10;
898
899 return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
900 }
901
mac_mcu_write(struct rtl8169_private * tp,int reg,int value)902 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
903 {
904 if (reg == 0x1f) {
905 tp->ocp_base = value << 4;
906 return;
907 }
908
909 r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
910 }
911
mac_mcu_read(struct rtl8169_private * tp,int reg)912 static int mac_mcu_read(struct rtl8169_private *tp, int reg)
913 {
914 return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
915 }
916
DECLARE_RTL_COND(rtl_phyar_cond)917 DECLARE_RTL_COND(rtl_phyar_cond)
918 {
919 return RTL_R32(tp, PHYAR) & 0x80000000;
920 }
921
r8169_mdio_write(struct rtl8169_private * tp,int reg,int value)922 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
923 {
924 RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
925
926 rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
927 /*
928 * According to hardware specs a 20us delay is required after write
929 * complete indication, but before sending next command.
930 */
931 udelay(20);
932 }
933
r8169_mdio_read(struct rtl8169_private * tp,int reg)934 static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
935 {
936 int value;
937
938 RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16);
939
940 value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
941 RTL_R32(tp, PHYAR) & 0xffff : ~0;
942
943 /*
944 * According to hardware specs a 20us delay is required after read
945 * complete indication, but before sending next command.
946 */
947 udelay(20);
948
949 return value;
950 }
951
DECLARE_RTL_COND(rtl_ocpar_cond)952 DECLARE_RTL_COND(rtl_ocpar_cond)
953 {
954 return RTL_R32(tp, OCPAR) & OCPAR_FLAG;
955 }
956
r8168dp_1_mdio_access(struct rtl8169_private * tp,int reg,u32 data)957 static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
958 {
959 RTL_W32(tp, OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
960 RTL_W32(tp, OCPAR, OCPAR_GPHY_WRITE_CMD);
961 RTL_W32(tp, EPHY_RXER_NUM, 0);
962
963 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
964 }
965
r8168dp_1_mdio_write(struct rtl8169_private * tp,int reg,int value)966 static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
967 {
968 r8168dp_1_mdio_access(tp, reg,
969 OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK));
970 }
971
r8168dp_1_mdio_read(struct rtl8169_private * tp,int reg)972 static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
973 {
974 r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);
975
976 mdelay(1);
977 RTL_W32(tp, OCPAR, OCPAR_GPHY_READ_CMD);
978 RTL_W32(tp, EPHY_RXER_NUM, 0);
979
980 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
981 RTL_R32(tp, OCPDR) & OCPDR_DATA_MASK : ~0;
982 }
983
984 #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
985
r8168dp_2_mdio_start(struct rtl8169_private * tp)986 static void r8168dp_2_mdio_start(struct rtl8169_private *tp)
987 {
988 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
989 }
990
r8168dp_2_mdio_stop(struct rtl8169_private * tp)991 static void r8168dp_2_mdio_stop(struct rtl8169_private *tp)
992 {
993 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
994 }
995
r8168dp_2_mdio_write(struct rtl8169_private * tp,int reg,int value)996 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
997 {
998 r8168dp_2_mdio_start(tp);
999
1000 r8169_mdio_write(tp, reg, value);
1001
1002 r8168dp_2_mdio_stop(tp);
1003 }
1004
r8168dp_2_mdio_read(struct rtl8169_private * tp,int reg)1005 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
1006 {
1007 int value;
1008
1009 r8168dp_2_mdio_start(tp);
1010
1011 value = r8169_mdio_read(tp, reg);
1012
1013 r8168dp_2_mdio_stop(tp);
1014
1015 return value;
1016 }
1017
rtl_writephy(struct rtl8169_private * tp,int location,u32 val)1018 static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
1019 {
1020 tp->mdio_ops.write(tp, location, val);
1021 }
1022
rtl_readphy(struct rtl8169_private * tp,int location)1023 static int rtl_readphy(struct rtl8169_private *tp, int location)
1024 {
1025 return tp->mdio_ops.read(tp, location);
1026 }
1027
rtl_patchphy(struct rtl8169_private * tp,int reg_addr,int value)1028 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1029 {
1030 rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1031 }
1032
rtl_w0w1_phy(struct rtl8169_private * tp,int reg_addr,int p,int m)1033 static void rtl_w0w1_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
1034 {
1035 int val;
1036
1037 val = rtl_readphy(tp, reg_addr);
1038 rtl_writephy(tp, reg_addr, (val & ~m) | p);
1039 }
1040
DECLARE_RTL_COND(rtl_ephyar_cond)1041 DECLARE_RTL_COND(rtl_ephyar_cond)
1042 {
1043 return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG;
1044 }
1045
rtl_ephy_write(struct rtl8169_private * tp,int reg_addr,int value)1046 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
1047 {
1048 RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1049 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1050
1051 rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1052
1053 udelay(10);
1054 }
1055
rtl_ephy_read(struct rtl8169_private * tp,int reg_addr)1056 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
1057 {
1058 RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1059
1060 return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1061 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0;
1062 }
1063
DECLARE_RTL_COND(rtl_eriar_cond)1064 DECLARE_RTL_COND(rtl_eriar_cond)
1065 {
1066 return RTL_R32(tp, ERIAR) & ERIAR_FLAG;
1067 }
1068
rtl_eri_write(struct rtl8169_private * tp,int addr,u32 mask,u32 val,int type)1069 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1070 u32 val, int type)
1071 {
1072 BUG_ON((addr & 3) || (mask == 0));
1073 RTL_W32(tp, ERIDR, val);
1074 RTL_W32(tp, ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1075
1076 rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
1077 }
1078
rtl_eri_read(struct rtl8169_private * tp,int addr,int type)1079 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
1080 {
1081 RTL_W32(tp, ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1082
1083 return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
1084 RTL_R32(tp, ERIDR) : ~0;
1085 }
1086
rtl_w0w1_eri(struct rtl8169_private * tp,int addr,u32 mask,u32 p,u32 m,int type)1087 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p,
1088 u32 m, int type)
1089 {
1090 u32 val;
1091
1092 val = rtl_eri_read(tp, addr, type);
1093 rtl_eri_write(tp, addr, mask, (val & ~m) | p, type);
1094 }
1095
r8168dp_ocp_read(struct rtl8169_private * tp,u8 mask,u16 reg)1096 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1097 {
1098 RTL_W32(tp, OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1099 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
1100 RTL_R32(tp, OCPDR) : ~0;
1101 }
1102
r8168ep_ocp_read(struct rtl8169_private * tp,u8 mask,u16 reg)1103 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1104 {
1105 return rtl_eri_read(tp, reg, ERIAR_OOB);
1106 }
1107
ocp_read(struct rtl8169_private * tp,u8 mask,u16 reg)1108 static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1109 {
1110 switch (tp->mac_version) {
1111 case RTL_GIGA_MAC_VER_27:
1112 case RTL_GIGA_MAC_VER_28:
1113 case RTL_GIGA_MAC_VER_31:
1114 return r8168dp_ocp_read(tp, mask, reg);
1115 case RTL_GIGA_MAC_VER_49:
1116 case RTL_GIGA_MAC_VER_50:
1117 case RTL_GIGA_MAC_VER_51:
1118 return r8168ep_ocp_read(tp, mask, reg);
1119 default:
1120 BUG();
1121 return ~0;
1122 }
1123 }
1124
r8168dp_ocp_write(struct rtl8169_private * tp,u8 mask,u16 reg,u32 data)1125 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1126 u32 data)
1127 {
1128 RTL_W32(tp, OCPDR, data);
1129 RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1130 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
1131 }
1132
r8168ep_ocp_write(struct rtl8169_private * tp,u8 mask,u16 reg,u32 data)1133 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1134 u32 data)
1135 {
1136 rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT,
1137 data, ERIAR_OOB);
1138 }
1139
ocp_write(struct rtl8169_private * tp,u8 mask,u16 reg,u32 data)1140 static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
1141 {
1142 switch (tp->mac_version) {
1143 case RTL_GIGA_MAC_VER_27:
1144 case RTL_GIGA_MAC_VER_28:
1145 case RTL_GIGA_MAC_VER_31:
1146 r8168dp_ocp_write(tp, mask, reg, data);
1147 break;
1148 case RTL_GIGA_MAC_VER_49:
1149 case RTL_GIGA_MAC_VER_50:
1150 case RTL_GIGA_MAC_VER_51:
1151 r8168ep_ocp_write(tp, mask, reg, data);
1152 break;
1153 default:
1154 BUG();
1155 break;
1156 }
1157 }
1158
rtl8168_oob_notify(struct rtl8169_private * tp,u8 cmd)1159 static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
1160 {
1161 rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd, ERIAR_EXGMAC);
1162
1163 ocp_write(tp, 0x1, 0x30, 0x00000001);
1164 }
1165
1166 #define OOB_CMD_RESET 0x00
1167 #define OOB_CMD_DRIVER_START 0x05
1168 #define OOB_CMD_DRIVER_STOP 0x06
1169
rtl8168_get_ocp_reg(struct rtl8169_private * tp)1170 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
1171 {
1172 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
1173 }
1174
DECLARE_RTL_COND(rtl_ocp_read_cond)1175 DECLARE_RTL_COND(rtl_ocp_read_cond)
1176 {
1177 u16 reg;
1178
1179 reg = rtl8168_get_ocp_reg(tp);
1180
1181 return ocp_read(tp, 0x0f, reg) & 0x00000800;
1182 }
1183
DECLARE_RTL_COND(rtl_ep_ocp_read_cond)1184 DECLARE_RTL_COND(rtl_ep_ocp_read_cond)
1185 {
1186 return ocp_read(tp, 0x0f, 0x124) & 0x00000001;
1187 }
1188
DECLARE_RTL_COND(rtl_ocp_tx_cond)1189 DECLARE_RTL_COND(rtl_ocp_tx_cond)
1190 {
1191 return RTL_R8(tp, IBISR0) & 0x20;
1192 }
1193
rtl8168ep_stop_cmac(struct rtl8169_private * tp)1194 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp)
1195 {
1196 RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01);
1197 rtl_msleep_loop_wait_high(tp, &rtl_ocp_tx_cond, 50, 2000);
1198 RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20);
1199 RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01);
1200 }
1201
rtl8168dp_driver_start(struct rtl8169_private * tp)1202 static void rtl8168dp_driver_start(struct rtl8169_private *tp)
1203 {
1204 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
1205 rtl_msleep_loop_wait_high(tp, &rtl_ocp_read_cond, 10, 10);
1206 }
1207
rtl8168ep_driver_start(struct rtl8169_private * tp)1208 static void rtl8168ep_driver_start(struct rtl8169_private *tp)
1209 {
1210 ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START);
1211 ocp_write(tp, 0x01, 0x30, ocp_read(tp, 0x01, 0x30) | 0x01);
1212 rtl_msleep_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10, 10);
1213 }
1214
rtl8168_driver_start(struct rtl8169_private * tp)1215 static void rtl8168_driver_start(struct rtl8169_private *tp)
1216 {
1217 switch (tp->mac_version) {
1218 case RTL_GIGA_MAC_VER_27:
1219 case RTL_GIGA_MAC_VER_28:
1220 case RTL_GIGA_MAC_VER_31:
1221 rtl8168dp_driver_start(tp);
1222 break;
1223 case RTL_GIGA_MAC_VER_49:
1224 case RTL_GIGA_MAC_VER_50:
1225 case RTL_GIGA_MAC_VER_51:
1226 rtl8168ep_driver_start(tp);
1227 break;
1228 default:
1229 BUG();
1230 break;
1231 }
1232 }
1233
rtl8168dp_driver_stop(struct rtl8169_private * tp)1234 static void rtl8168dp_driver_stop(struct rtl8169_private *tp)
1235 {
1236 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
1237 rtl_msleep_loop_wait_low(tp, &rtl_ocp_read_cond, 10, 10);
1238 }
1239
rtl8168ep_driver_stop(struct rtl8169_private * tp)1240 static void rtl8168ep_driver_stop(struct rtl8169_private *tp)
1241 {
1242 rtl8168ep_stop_cmac(tp);
1243 ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP);
1244 ocp_write(tp, 0x01, 0x30, ocp_read(tp, 0x01, 0x30) | 0x01);
1245 rtl_msleep_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10, 10);
1246 }
1247
rtl8168_driver_stop(struct rtl8169_private * tp)1248 static void rtl8168_driver_stop(struct rtl8169_private *tp)
1249 {
1250 switch (tp->mac_version) {
1251 case RTL_GIGA_MAC_VER_27:
1252 case RTL_GIGA_MAC_VER_28:
1253 case RTL_GIGA_MAC_VER_31:
1254 rtl8168dp_driver_stop(tp);
1255 break;
1256 case RTL_GIGA_MAC_VER_49:
1257 case RTL_GIGA_MAC_VER_50:
1258 case RTL_GIGA_MAC_VER_51:
1259 rtl8168ep_driver_stop(tp);
1260 break;
1261 default:
1262 BUG();
1263 break;
1264 }
1265 }
1266
r8168dp_check_dash(struct rtl8169_private * tp)1267 static bool r8168dp_check_dash(struct rtl8169_private *tp)
1268 {
1269 u16 reg = rtl8168_get_ocp_reg(tp);
1270
1271 return !!(ocp_read(tp, 0x0f, reg) & 0x00008000);
1272 }
1273
r8168ep_check_dash(struct rtl8169_private * tp)1274 static bool r8168ep_check_dash(struct rtl8169_private *tp)
1275 {
1276 return !!(ocp_read(tp, 0x0f, 0x128) & 0x00000001);
1277 }
1278
r8168_check_dash(struct rtl8169_private * tp)1279 static bool r8168_check_dash(struct rtl8169_private *tp)
1280 {
1281 switch (tp->mac_version) {
1282 case RTL_GIGA_MAC_VER_27:
1283 case RTL_GIGA_MAC_VER_28:
1284 case RTL_GIGA_MAC_VER_31:
1285 return r8168dp_check_dash(tp);
1286 case RTL_GIGA_MAC_VER_49:
1287 case RTL_GIGA_MAC_VER_50:
1288 case RTL_GIGA_MAC_VER_51:
1289 return r8168ep_check_dash(tp);
1290 default:
1291 return false;
1292 }
1293 }
1294
1295 struct exgmac_reg {
1296 u16 addr;
1297 u16 mask;
1298 u32 val;
1299 };
1300
rtl_write_exgmac_batch(struct rtl8169_private * tp,const struct exgmac_reg * r,int len)1301 static void rtl_write_exgmac_batch(struct rtl8169_private *tp,
1302 const struct exgmac_reg *r, int len)
1303 {
1304 while (len-- > 0) {
1305 rtl_eri_write(tp, r->addr, r->mask, r->val, ERIAR_EXGMAC);
1306 r++;
1307 }
1308 }
1309
DECLARE_RTL_COND(rtl_efusear_cond)1310 DECLARE_RTL_COND(rtl_efusear_cond)
1311 {
1312 return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG;
1313 }
1314
rtl8168d_efuse_read(struct rtl8169_private * tp,int reg_addr)1315 static u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
1316 {
1317 RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1318
1319 return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1320 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
1321 }
1322
rtl_get_events(struct rtl8169_private * tp)1323 static u16 rtl_get_events(struct rtl8169_private *tp)
1324 {
1325 return RTL_R16(tp, IntrStatus);
1326 }
1327
rtl_ack_events(struct rtl8169_private * tp,u16 bits)1328 static void rtl_ack_events(struct rtl8169_private *tp, u16 bits)
1329 {
1330 RTL_W16(tp, IntrStatus, bits);
1331 mmiowb();
1332 }
1333
rtl_irq_disable(struct rtl8169_private * tp)1334 static void rtl_irq_disable(struct rtl8169_private *tp)
1335 {
1336 RTL_W16(tp, IntrMask, 0);
1337 mmiowb();
1338 }
1339
rtl_irq_enable(struct rtl8169_private * tp,u16 bits)1340 static void rtl_irq_enable(struct rtl8169_private *tp, u16 bits)
1341 {
1342 RTL_W16(tp, IntrMask, bits);
1343 }
1344
1345 #define RTL_EVENT_NAPI_RX (RxOK | RxErr)
1346 #define RTL_EVENT_NAPI_TX (TxOK | TxErr)
1347 #define RTL_EVENT_NAPI (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1348
rtl_irq_enable_all(struct rtl8169_private * tp)1349 static void rtl_irq_enable_all(struct rtl8169_private *tp)
1350 {
1351 rtl_irq_enable(tp, RTL_EVENT_NAPI | tp->event_slow);
1352 }
1353
rtl8169_irq_mask_and_ack(struct rtl8169_private * tp)1354 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1355 {
1356 rtl_irq_disable(tp);
1357 rtl_ack_events(tp, RTL_EVENT_NAPI | tp->event_slow);
1358 RTL_R8(tp, ChipCmd);
1359 }
1360
rtl_link_chg_patch(struct rtl8169_private * tp)1361 static void rtl_link_chg_patch(struct rtl8169_private *tp)
1362 {
1363 struct net_device *dev = tp->dev;
1364 struct phy_device *phydev = dev->phydev;
1365
1366 if (!netif_running(dev))
1367 return;
1368
1369 if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1370 tp->mac_version == RTL_GIGA_MAC_VER_38) {
1371 if (phydev->speed == SPEED_1000) {
1372 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1373 ERIAR_EXGMAC);
1374 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1375 ERIAR_EXGMAC);
1376 } else if (phydev->speed == SPEED_100) {
1377 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1378 ERIAR_EXGMAC);
1379 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1380 ERIAR_EXGMAC);
1381 } else {
1382 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1383 ERIAR_EXGMAC);
1384 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1385 ERIAR_EXGMAC);
1386 }
1387 /* Reset packet filter */
1388 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
1389 ERIAR_EXGMAC);
1390 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
1391 ERIAR_EXGMAC);
1392 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1393 tp->mac_version == RTL_GIGA_MAC_VER_36) {
1394 if (phydev->speed == SPEED_1000) {
1395 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1396 ERIAR_EXGMAC);
1397 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1398 ERIAR_EXGMAC);
1399 } else {
1400 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1401 ERIAR_EXGMAC);
1402 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1403 ERIAR_EXGMAC);
1404 }
1405 } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1406 if (phydev->speed == SPEED_10) {
1407 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02,
1408 ERIAR_EXGMAC);
1409 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060,
1410 ERIAR_EXGMAC);
1411 } else {
1412 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000,
1413 ERIAR_EXGMAC);
1414 }
1415 }
1416 }
1417
1418 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1419
__rtl8169_get_wol(struct rtl8169_private * tp)1420 static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
1421 {
1422 u8 options;
1423 u32 wolopts = 0;
1424
1425 options = RTL_R8(tp, Config1);
1426 if (!(options & PMEnable))
1427 return 0;
1428
1429 options = RTL_R8(tp, Config3);
1430 if (options & LinkUp)
1431 wolopts |= WAKE_PHY;
1432 switch (tp->mac_version) {
1433 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
1434 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1435 if (rtl_eri_read(tp, 0xdc, ERIAR_EXGMAC) & MagicPacket_v2)
1436 wolopts |= WAKE_MAGIC;
1437 break;
1438 default:
1439 if (options & MagicPacket)
1440 wolopts |= WAKE_MAGIC;
1441 break;
1442 }
1443
1444 options = RTL_R8(tp, Config5);
1445 if (options & UWF)
1446 wolopts |= WAKE_UCAST;
1447 if (options & BWF)
1448 wolopts |= WAKE_BCAST;
1449 if (options & MWF)
1450 wolopts |= WAKE_MCAST;
1451
1452 return wolopts;
1453 }
1454
rtl8169_get_wol(struct net_device * dev,struct ethtool_wolinfo * wol)1455 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1456 {
1457 struct rtl8169_private *tp = netdev_priv(dev);
1458
1459 rtl_lock_work(tp);
1460 wol->supported = WAKE_ANY;
1461 wol->wolopts = tp->saved_wolopts;
1462 rtl_unlock_work(tp);
1463 }
1464
__rtl8169_set_wol(struct rtl8169_private * tp,u32 wolopts)1465 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1466 {
1467 unsigned int i, tmp;
1468 static const struct {
1469 u32 opt;
1470 u16 reg;
1471 u8 mask;
1472 } cfg[] = {
1473 { WAKE_PHY, Config3, LinkUp },
1474 { WAKE_UCAST, Config5, UWF },
1475 { WAKE_BCAST, Config5, BWF },
1476 { WAKE_MCAST, Config5, MWF },
1477 { WAKE_ANY, Config5, LanWake },
1478 { WAKE_MAGIC, Config3, MagicPacket }
1479 };
1480 u8 options;
1481
1482 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
1483
1484 switch (tp->mac_version) {
1485 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
1486 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1487 tmp = ARRAY_SIZE(cfg) - 1;
1488 if (wolopts & WAKE_MAGIC)
1489 rtl_w0w1_eri(tp,
1490 0x0dc,
1491 ERIAR_MASK_0100,
1492 MagicPacket_v2,
1493 0x0000,
1494 ERIAR_EXGMAC);
1495 else
1496 rtl_w0w1_eri(tp,
1497 0x0dc,
1498 ERIAR_MASK_0100,
1499 0x0000,
1500 MagicPacket_v2,
1501 ERIAR_EXGMAC);
1502 break;
1503 default:
1504 tmp = ARRAY_SIZE(cfg);
1505 break;
1506 }
1507
1508 for (i = 0; i < tmp; i++) {
1509 options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask;
1510 if (wolopts & cfg[i].opt)
1511 options |= cfg[i].mask;
1512 RTL_W8(tp, cfg[i].reg, options);
1513 }
1514
1515 switch (tp->mac_version) {
1516 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_17:
1517 options = RTL_R8(tp, Config1) & ~PMEnable;
1518 if (wolopts)
1519 options |= PMEnable;
1520 RTL_W8(tp, Config1, options);
1521 break;
1522 default:
1523 options = RTL_R8(tp, Config2) & ~PME_SIGNAL;
1524 if (wolopts)
1525 options |= PME_SIGNAL;
1526 RTL_W8(tp, Config2, options);
1527 break;
1528 }
1529
1530 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
1531 }
1532
rtl8169_set_wol(struct net_device * dev,struct ethtool_wolinfo * wol)1533 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1534 {
1535 struct rtl8169_private *tp = netdev_priv(dev);
1536 struct device *d = tp_to_dev(tp);
1537
1538 if (wol->wolopts & ~WAKE_ANY)
1539 return -EINVAL;
1540
1541 pm_runtime_get_noresume(d);
1542
1543 rtl_lock_work(tp);
1544
1545 tp->saved_wolopts = wol->wolopts;
1546
1547 if (pm_runtime_active(d))
1548 __rtl8169_set_wol(tp, tp->saved_wolopts);
1549
1550 rtl_unlock_work(tp);
1551
1552 device_set_wakeup_enable(d, tp->saved_wolopts);
1553
1554 pm_runtime_put_noidle(d);
1555
1556 return 0;
1557 }
1558
rtl_lookup_firmware_name(struct rtl8169_private * tp)1559 static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1560 {
1561 return rtl_chip_infos[tp->mac_version].fw_name;
1562 }
1563
rtl8169_get_drvinfo(struct net_device * dev,struct ethtool_drvinfo * info)1564 static void rtl8169_get_drvinfo(struct net_device *dev,
1565 struct ethtool_drvinfo *info)
1566 {
1567 struct rtl8169_private *tp = netdev_priv(dev);
1568 struct rtl_fw *rtl_fw = tp->rtl_fw;
1569
1570 strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1571 strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1572 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1573 if (!IS_ERR_OR_NULL(rtl_fw))
1574 strlcpy(info->fw_version, rtl_fw->version,
1575 sizeof(info->fw_version));
1576 }
1577
rtl8169_get_regs_len(struct net_device * dev)1578 static int rtl8169_get_regs_len(struct net_device *dev)
1579 {
1580 return R8169_REGS_SIZE;
1581 }
1582
rtl8169_fix_features(struct net_device * dev,netdev_features_t features)1583 static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1584 netdev_features_t features)
1585 {
1586 struct rtl8169_private *tp = netdev_priv(dev);
1587
1588 if (dev->mtu > TD_MSS_MAX)
1589 features &= ~NETIF_F_ALL_TSO;
1590
1591 if (dev->mtu > JUMBO_1K &&
1592 tp->mac_version > RTL_GIGA_MAC_VER_06)
1593 features &= ~NETIF_F_IP_CSUM;
1594
1595 return features;
1596 }
1597
rtl8169_set_features(struct net_device * dev,netdev_features_t features)1598 static int rtl8169_set_features(struct net_device *dev,
1599 netdev_features_t features)
1600 {
1601 struct rtl8169_private *tp = netdev_priv(dev);
1602 u32 rx_config;
1603
1604 rtl_lock_work(tp);
1605
1606 rx_config = RTL_R32(tp, RxConfig);
1607 if (features & NETIF_F_RXALL)
1608 rx_config |= (AcceptErr | AcceptRunt);
1609 else
1610 rx_config &= ~(AcceptErr | AcceptRunt);
1611
1612 RTL_W32(tp, RxConfig, rx_config);
1613
1614 if (features & NETIF_F_RXCSUM)
1615 tp->cp_cmd |= RxChkSum;
1616 else
1617 tp->cp_cmd &= ~RxChkSum;
1618
1619 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1620 tp->cp_cmd |= RxVlan;
1621 else
1622 tp->cp_cmd &= ~RxVlan;
1623
1624 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1625 RTL_R16(tp, CPlusCmd);
1626
1627 rtl_unlock_work(tp);
1628
1629 return 0;
1630 }
1631
rtl8169_tx_vlan_tag(struct sk_buff * skb)1632 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
1633 {
1634 return (skb_vlan_tag_present(skb)) ?
1635 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00;
1636 }
1637
rtl8169_rx_vlan_tag(struct RxDesc * desc,struct sk_buff * skb)1638 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1639 {
1640 u32 opts2 = le32_to_cpu(desc->opts2);
1641
1642 if (opts2 & RxVlanTag)
1643 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
1644 }
1645
rtl8169_get_regs(struct net_device * dev,struct ethtool_regs * regs,void * p)1646 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1647 void *p)
1648 {
1649 struct rtl8169_private *tp = netdev_priv(dev);
1650 u32 __iomem *data = tp->mmio_addr;
1651 u32 *dw = p;
1652 int i;
1653
1654 rtl_lock_work(tp);
1655 for (i = 0; i < R8169_REGS_SIZE; i += 4)
1656 memcpy_fromio(dw++, data++, 4);
1657 rtl_unlock_work(tp);
1658 }
1659
rtl8169_get_msglevel(struct net_device * dev)1660 static u32 rtl8169_get_msglevel(struct net_device *dev)
1661 {
1662 struct rtl8169_private *tp = netdev_priv(dev);
1663
1664 return tp->msg_enable;
1665 }
1666
rtl8169_set_msglevel(struct net_device * dev,u32 value)1667 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1668 {
1669 struct rtl8169_private *tp = netdev_priv(dev);
1670
1671 tp->msg_enable = value;
1672 }
1673
1674 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1675 "tx_packets",
1676 "rx_packets",
1677 "tx_errors",
1678 "rx_errors",
1679 "rx_missed",
1680 "align_errors",
1681 "tx_single_collisions",
1682 "tx_multi_collisions",
1683 "unicast",
1684 "broadcast",
1685 "multicast",
1686 "tx_aborted",
1687 "tx_underrun",
1688 };
1689
rtl8169_get_sset_count(struct net_device * dev,int sset)1690 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1691 {
1692 switch (sset) {
1693 case ETH_SS_STATS:
1694 return ARRAY_SIZE(rtl8169_gstrings);
1695 default:
1696 return -EOPNOTSUPP;
1697 }
1698 }
1699
DECLARE_RTL_COND(rtl_counters_cond)1700 DECLARE_RTL_COND(rtl_counters_cond)
1701 {
1702 return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump);
1703 }
1704
rtl8169_do_counters(struct rtl8169_private * tp,u32 counter_cmd)1705 static bool rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd)
1706 {
1707 dma_addr_t paddr = tp->counters_phys_addr;
1708 u32 cmd;
1709
1710 RTL_W32(tp, CounterAddrHigh, (u64)paddr >> 32);
1711 RTL_R32(tp, CounterAddrHigh);
1712 cmd = (u64)paddr & DMA_BIT_MASK(32);
1713 RTL_W32(tp, CounterAddrLow, cmd);
1714 RTL_W32(tp, CounterAddrLow, cmd | counter_cmd);
1715
1716 return rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000);
1717 }
1718
rtl8169_reset_counters(struct rtl8169_private * tp)1719 static bool rtl8169_reset_counters(struct rtl8169_private *tp)
1720 {
1721 /*
1722 * Versions prior to RTL_GIGA_MAC_VER_19 don't support resetting the
1723 * tally counters.
1724 */
1725 if (tp->mac_version < RTL_GIGA_MAC_VER_19)
1726 return true;
1727
1728 return rtl8169_do_counters(tp, CounterReset);
1729 }
1730
rtl8169_update_counters(struct rtl8169_private * tp)1731 static bool rtl8169_update_counters(struct rtl8169_private *tp)
1732 {
1733 /*
1734 * Some chips are unable to dump tally counters when the receiver
1735 * is disabled.
1736 */
1737 if ((RTL_R8(tp, ChipCmd) & CmdRxEnb) == 0)
1738 return true;
1739
1740 return rtl8169_do_counters(tp, CounterDump);
1741 }
1742
rtl8169_init_counter_offsets(struct rtl8169_private * tp)1743 static bool rtl8169_init_counter_offsets(struct rtl8169_private *tp)
1744 {
1745 struct rtl8169_counters *counters = tp->counters;
1746 bool ret = false;
1747
1748 /*
1749 * rtl8169_init_counter_offsets is called from rtl_open. On chip
1750 * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only
1751 * reset by a power cycle, while the counter values collected by the
1752 * driver are reset at every driver unload/load cycle.
1753 *
1754 * To make sure the HW values returned by @get_stats64 match the SW
1755 * values, we collect the initial values at first open(*) and use them
1756 * as offsets to normalize the values returned by @get_stats64.
1757 *
1758 * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one
1759 * for the reason stated in rtl8169_update_counters; CmdRxEnb is only
1760 * set at open time by rtl_hw_start.
1761 */
1762
1763 if (tp->tc_offset.inited)
1764 return true;
1765
1766 /* If both, reset and update fail, propagate to caller. */
1767 if (rtl8169_reset_counters(tp))
1768 ret = true;
1769
1770 if (rtl8169_update_counters(tp))
1771 ret = true;
1772
1773 tp->tc_offset.tx_errors = counters->tx_errors;
1774 tp->tc_offset.tx_multi_collision = counters->tx_multi_collision;
1775 tp->tc_offset.tx_aborted = counters->tx_aborted;
1776 tp->tc_offset.inited = true;
1777
1778 return ret;
1779 }
1780
rtl8169_get_ethtool_stats(struct net_device * dev,struct ethtool_stats * stats,u64 * data)1781 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1782 struct ethtool_stats *stats, u64 *data)
1783 {
1784 struct rtl8169_private *tp = netdev_priv(dev);
1785 struct device *d = tp_to_dev(tp);
1786 struct rtl8169_counters *counters = tp->counters;
1787
1788 ASSERT_RTNL();
1789
1790 pm_runtime_get_noresume(d);
1791
1792 if (pm_runtime_active(d))
1793 rtl8169_update_counters(tp);
1794
1795 pm_runtime_put_noidle(d);
1796
1797 data[0] = le64_to_cpu(counters->tx_packets);
1798 data[1] = le64_to_cpu(counters->rx_packets);
1799 data[2] = le64_to_cpu(counters->tx_errors);
1800 data[3] = le32_to_cpu(counters->rx_errors);
1801 data[4] = le16_to_cpu(counters->rx_missed);
1802 data[5] = le16_to_cpu(counters->align_errors);
1803 data[6] = le32_to_cpu(counters->tx_one_collision);
1804 data[7] = le32_to_cpu(counters->tx_multi_collision);
1805 data[8] = le64_to_cpu(counters->rx_unicast);
1806 data[9] = le64_to_cpu(counters->rx_broadcast);
1807 data[10] = le32_to_cpu(counters->rx_multicast);
1808 data[11] = le16_to_cpu(counters->tx_aborted);
1809 data[12] = le16_to_cpu(counters->tx_underun);
1810 }
1811
rtl8169_get_strings(struct net_device * dev,u32 stringset,u8 * data)1812 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1813 {
1814 switch(stringset) {
1815 case ETH_SS_STATS:
1816 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1817 break;
1818 }
1819 }
1820
1821 /*
1822 * Interrupt coalescing
1823 *
1824 * > 1 - the availability of the IntrMitigate (0xe2) register through the
1825 * > 8169, 8168 and 810x line of chipsets
1826 *
1827 * 8169, 8168, and 8136(810x) serial chipsets support it.
1828 *
1829 * > 2 - the Tx timer unit at gigabit speed
1830 *
1831 * The unit of the timer depends on both the speed and the setting of CPlusCmd
1832 * (0xe0) bit 1 and bit 0.
1833 *
1834 * For 8169
1835 * bit[1:0] \ speed 1000M 100M 10M
1836 * 0 0 320ns 2.56us 40.96us
1837 * 0 1 2.56us 20.48us 327.7us
1838 * 1 0 5.12us 40.96us 655.4us
1839 * 1 1 10.24us 81.92us 1.31ms
1840 *
1841 * For the other
1842 * bit[1:0] \ speed 1000M 100M 10M
1843 * 0 0 5us 2.56us 40.96us
1844 * 0 1 40us 20.48us 327.7us
1845 * 1 0 80us 40.96us 655.4us
1846 * 1 1 160us 81.92us 1.31ms
1847 */
1848
1849 /* rx/tx scale factors for one particular CPlusCmd[0:1] value */
1850 struct rtl_coalesce_scale {
1851 /* Rx / Tx */
1852 u32 nsecs[2];
1853 };
1854
1855 /* rx/tx scale factors for all CPlusCmd[0:1] cases */
1856 struct rtl_coalesce_info {
1857 u32 speed;
1858 struct rtl_coalesce_scale scalev[4]; /* each CPlusCmd[0:1] case */
1859 };
1860
1861 /* produce (r,t) pairs with each being in series of *1, *8, *8*2, *8*2*2 */
1862 #define rxtx_x1822(r, t) { \
1863 {{(r), (t)}}, \
1864 {{(r)*8, (t)*8}}, \
1865 {{(r)*8*2, (t)*8*2}}, \
1866 {{(r)*8*2*2, (t)*8*2*2}}, \
1867 }
1868 static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = {
1869 /* speed delays: rx00 tx00 */
1870 { SPEED_10, rxtx_x1822(40960, 40960) },
1871 { SPEED_100, rxtx_x1822( 2560, 2560) },
1872 { SPEED_1000, rxtx_x1822( 320, 320) },
1873 { 0 },
1874 };
1875
1876 static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = {
1877 /* speed delays: rx00 tx00 */
1878 { SPEED_10, rxtx_x1822(40960, 40960) },
1879 { SPEED_100, rxtx_x1822( 2560, 2560) },
1880 { SPEED_1000, rxtx_x1822( 5000, 5000) },
1881 { 0 },
1882 };
1883 #undef rxtx_x1822
1884
1885 /* get rx/tx scale vector corresponding to current speed */
rtl_coalesce_info(struct net_device * dev)1886 static const struct rtl_coalesce_info *rtl_coalesce_info(struct net_device *dev)
1887 {
1888 struct rtl8169_private *tp = netdev_priv(dev);
1889 struct ethtool_link_ksettings ecmd;
1890 const struct rtl_coalesce_info *ci;
1891 int rc;
1892
1893 rc = phy_ethtool_get_link_ksettings(dev, &ecmd);
1894 if (rc < 0)
1895 return ERR_PTR(rc);
1896
1897 for (ci = tp->coalesce_info; ci->speed != 0; ci++) {
1898 if (ecmd.base.speed == ci->speed) {
1899 return ci;
1900 }
1901 }
1902
1903 return ERR_PTR(-ELNRNG);
1904 }
1905
rtl_get_coalesce(struct net_device * dev,struct ethtool_coalesce * ec)1906 static int rtl_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1907 {
1908 struct rtl8169_private *tp = netdev_priv(dev);
1909 const struct rtl_coalesce_info *ci;
1910 const struct rtl_coalesce_scale *scale;
1911 struct {
1912 u32 *max_frames;
1913 u32 *usecs;
1914 } coal_settings [] = {
1915 { &ec->rx_max_coalesced_frames, &ec->rx_coalesce_usecs },
1916 { &ec->tx_max_coalesced_frames, &ec->tx_coalesce_usecs }
1917 }, *p = coal_settings;
1918 int i;
1919 u16 w;
1920
1921 memset(ec, 0, sizeof(*ec));
1922
1923 /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */
1924 ci = rtl_coalesce_info(dev);
1925 if (IS_ERR(ci))
1926 return PTR_ERR(ci);
1927
1928 scale = &ci->scalev[tp->cp_cmd & INTT_MASK];
1929
1930 /* read IntrMitigate and adjust according to scale */
1931 for (w = RTL_R16(tp, IntrMitigate); w; w >>= RTL_COALESCE_SHIFT, p++) {
1932 *p->max_frames = (w & RTL_COALESCE_MASK) << 2;
1933 w >>= RTL_COALESCE_SHIFT;
1934 *p->usecs = w & RTL_COALESCE_MASK;
1935 }
1936
1937 for (i = 0; i < 2; i++) {
1938 p = coal_settings + i;
1939 *p->usecs = (*p->usecs * scale->nsecs[i]) / 1000;
1940
1941 /*
1942 * ethtool_coalesce says it is illegal to set both usecs and
1943 * max_frames to 0.
1944 */
1945 if (!*p->usecs && !*p->max_frames)
1946 *p->max_frames = 1;
1947 }
1948
1949 return 0;
1950 }
1951
1952 /* choose appropriate scale factor and CPlusCmd[0:1] for (speed, nsec) */
rtl_coalesce_choose_scale(struct net_device * dev,u32 nsec,u16 * cp01)1953 static const struct rtl_coalesce_scale *rtl_coalesce_choose_scale(
1954 struct net_device *dev, u32 nsec, u16 *cp01)
1955 {
1956 const struct rtl_coalesce_info *ci;
1957 u16 i;
1958
1959 ci = rtl_coalesce_info(dev);
1960 if (IS_ERR(ci))
1961 return ERR_CAST(ci);
1962
1963 for (i = 0; i < 4; i++) {
1964 u32 rxtx_maxscale = max(ci->scalev[i].nsecs[0],
1965 ci->scalev[i].nsecs[1]);
1966 if (nsec <= rxtx_maxscale * RTL_COALESCE_T_MAX) {
1967 *cp01 = i;
1968 return &ci->scalev[i];
1969 }
1970 }
1971
1972 return ERR_PTR(-EINVAL);
1973 }
1974
rtl_set_coalesce(struct net_device * dev,struct ethtool_coalesce * ec)1975 static int rtl_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1976 {
1977 struct rtl8169_private *tp = netdev_priv(dev);
1978 const struct rtl_coalesce_scale *scale;
1979 struct {
1980 u32 frames;
1981 u32 usecs;
1982 } coal_settings [] = {
1983 { ec->rx_max_coalesced_frames, ec->rx_coalesce_usecs },
1984 { ec->tx_max_coalesced_frames, ec->tx_coalesce_usecs }
1985 }, *p = coal_settings;
1986 u16 w = 0, cp01;
1987 int i;
1988
1989 scale = rtl_coalesce_choose_scale(dev,
1990 max(p[0].usecs, p[1].usecs) * 1000, &cp01);
1991 if (IS_ERR(scale))
1992 return PTR_ERR(scale);
1993
1994 for (i = 0; i < 2; i++, p++) {
1995 u32 units;
1996
1997 /*
1998 * accept max_frames=1 we returned in rtl_get_coalesce.
1999 * accept it not only when usecs=0 because of e.g. the following scenario:
2000 *
2001 * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX)
2002 * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1
2003 * - then user does `ethtool -C eth0 rx-usecs 100`
2004 *
2005 * since ethtool sends to kernel whole ethtool_coalesce
2006 * settings, if we do not handle rx_usecs=!0, rx_frames=1
2007 * we'll reject it below in `frames % 4 != 0`.
2008 */
2009 if (p->frames == 1) {
2010 p->frames = 0;
2011 }
2012
2013 units = p->usecs * 1000 / scale->nsecs[i];
2014 if (p->frames > RTL_COALESCE_FRAME_MAX || p->frames % 4)
2015 return -EINVAL;
2016
2017 w <<= RTL_COALESCE_SHIFT;
2018 w |= units;
2019 w <<= RTL_COALESCE_SHIFT;
2020 w |= p->frames >> 2;
2021 }
2022
2023 rtl_lock_work(tp);
2024
2025 RTL_W16(tp, IntrMitigate, swab16(w));
2026
2027 tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01;
2028 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
2029 RTL_R16(tp, CPlusCmd);
2030
2031 rtl_unlock_work(tp);
2032
2033 return 0;
2034 }
2035
2036 static const struct ethtool_ops rtl8169_ethtool_ops = {
2037 .get_drvinfo = rtl8169_get_drvinfo,
2038 .get_regs_len = rtl8169_get_regs_len,
2039 .get_link = ethtool_op_get_link,
2040 .get_coalesce = rtl_get_coalesce,
2041 .set_coalesce = rtl_set_coalesce,
2042 .get_msglevel = rtl8169_get_msglevel,
2043 .set_msglevel = rtl8169_set_msglevel,
2044 .get_regs = rtl8169_get_regs,
2045 .get_wol = rtl8169_get_wol,
2046 .set_wol = rtl8169_set_wol,
2047 .get_strings = rtl8169_get_strings,
2048 .get_sset_count = rtl8169_get_sset_count,
2049 .get_ethtool_stats = rtl8169_get_ethtool_stats,
2050 .get_ts_info = ethtool_op_get_ts_info,
2051 .nway_reset = phy_ethtool_nway_reset,
2052 .get_link_ksettings = phy_ethtool_get_link_ksettings,
2053 .set_link_ksettings = phy_ethtool_set_link_ksettings,
2054 };
2055
rtl8169_get_mac_version(struct rtl8169_private * tp,u8 default_version)2056 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
2057 u8 default_version)
2058 {
2059 /*
2060 * The driver currently handles the 8168Bf and the 8168Be identically
2061 * but they can be identified more specifically through the test below
2062 * if needed:
2063 *
2064 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
2065 *
2066 * Same thing for the 8101Eb and the 8101Ec:
2067 *
2068 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
2069 */
2070 static const struct rtl_mac_info {
2071 u32 mask;
2072 u32 val;
2073 int mac_version;
2074 } mac_info[] = {
2075 /* 8168EP family. */
2076 { 0x7cf00000, 0x50200000, RTL_GIGA_MAC_VER_51 },
2077 { 0x7cf00000, 0x50100000, RTL_GIGA_MAC_VER_50 },
2078 { 0x7cf00000, 0x50000000, RTL_GIGA_MAC_VER_49 },
2079
2080 /* 8168H family. */
2081 { 0x7cf00000, 0x54100000, RTL_GIGA_MAC_VER_46 },
2082 { 0x7cf00000, 0x54000000, RTL_GIGA_MAC_VER_45 },
2083
2084 /* 8168G family. */
2085 { 0x7cf00000, 0x5c800000, RTL_GIGA_MAC_VER_44 },
2086 { 0x7cf00000, 0x50900000, RTL_GIGA_MAC_VER_42 },
2087 { 0x7cf00000, 0x4c100000, RTL_GIGA_MAC_VER_41 },
2088 { 0x7cf00000, 0x4c000000, RTL_GIGA_MAC_VER_40 },
2089
2090 /* 8168F family. */
2091 { 0x7c800000, 0x48800000, RTL_GIGA_MAC_VER_38 },
2092 { 0x7cf00000, 0x48100000, RTL_GIGA_MAC_VER_36 },
2093 { 0x7cf00000, 0x48000000, RTL_GIGA_MAC_VER_35 },
2094
2095 /* 8168E family. */
2096 { 0x7c800000, 0x2c800000, RTL_GIGA_MAC_VER_34 },
2097 { 0x7cf00000, 0x2c100000, RTL_GIGA_MAC_VER_32 },
2098 { 0x7c800000, 0x2c000000, RTL_GIGA_MAC_VER_33 },
2099
2100 /* 8168D family. */
2101 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 },
2102 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 },
2103
2104 /* 8168DP family. */
2105 { 0x7cf00000, 0x28800000, RTL_GIGA_MAC_VER_27 },
2106 { 0x7cf00000, 0x28a00000, RTL_GIGA_MAC_VER_28 },
2107 { 0x7cf00000, 0x28b00000, RTL_GIGA_MAC_VER_31 },
2108
2109 /* 8168C family. */
2110 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 },
2111 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
2112 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 },
2113 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
2114 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
2115 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 },
2116 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 },
2117
2118 /* 8168B family. */
2119 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
2120 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
2121 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
2122
2123 /* 8101 family. */
2124 { 0x7c800000, 0x44800000, RTL_GIGA_MAC_VER_39 },
2125 { 0x7c800000, 0x44000000, RTL_GIGA_MAC_VER_37 },
2126 { 0x7cf00000, 0x40900000, RTL_GIGA_MAC_VER_29 },
2127 { 0x7c800000, 0x40800000, RTL_GIGA_MAC_VER_30 },
2128 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
2129 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 },
2130 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 },
2131 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 },
2132 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
2133 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 },
2134 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
2135 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 },
2136 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 },
2137 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
2138 /* FIXME: where did these entries come from ? -- FR */
2139 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
2140 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
2141
2142 /* 8110 family. */
2143 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
2144 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
2145 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
2146 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
2147 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
2148 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
2149
2150 /* Catch-all */
2151 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE }
2152 };
2153 const struct rtl_mac_info *p = mac_info;
2154 u32 reg;
2155
2156 reg = RTL_R32(tp, TxConfig);
2157 while ((reg & p->mask) != p->val)
2158 p++;
2159 tp->mac_version = p->mac_version;
2160
2161 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
2162 dev_notice(tp_to_dev(tp),
2163 "unknown MAC, using family default\n");
2164 tp->mac_version = default_version;
2165 } else if (tp->mac_version == RTL_GIGA_MAC_VER_42) {
2166 tp->mac_version = tp->supports_gmii ?
2167 RTL_GIGA_MAC_VER_42 :
2168 RTL_GIGA_MAC_VER_43;
2169 } else if (tp->mac_version == RTL_GIGA_MAC_VER_45) {
2170 tp->mac_version = tp->supports_gmii ?
2171 RTL_GIGA_MAC_VER_45 :
2172 RTL_GIGA_MAC_VER_47;
2173 } else if (tp->mac_version == RTL_GIGA_MAC_VER_46) {
2174 tp->mac_version = tp->supports_gmii ?
2175 RTL_GIGA_MAC_VER_46 :
2176 RTL_GIGA_MAC_VER_48;
2177 }
2178 }
2179
rtl8169_print_mac_version(struct rtl8169_private * tp)2180 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
2181 {
2182 netif_dbg(tp, drv, tp->dev, "mac_version = 0x%02x\n", tp->mac_version);
2183 }
2184
2185 struct phy_reg {
2186 u16 reg;
2187 u16 val;
2188 };
2189
rtl_writephy_batch(struct rtl8169_private * tp,const struct phy_reg * regs,int len)2190 static void rtl_writephy_batch(struct rtl8169_private *tp,
2191 const struct phy_reg *regs, int len)
2192 {
2193 while (len-- > 0) {
2194 rtl_writephy(tp, regs->reg, regs->val);
2195 regs++;
2196 }
2197 }
2198
2199 #define PHY_READ 0x00000000
2200 #define PHY_DATA_OR 0x10000000
2201 #define PHY_DATA_AND 0x20000000
2202 #define PHY_BJMPN 0x30000000
2203 #define PHY_MDIO_CHG 0x40000000
2204 #define PHY_CLEAR_READCOUNT 0x70000000
2205 #define PHY_WRITE 0x80000000
2206 #define PHY_READCOUNT_EQ_SKIP 0x90000000
2207 #define PHY_COMP_EQ_SKIPN 0xa0000000
2208 #define PHY_COMP_NEQ_SKIPN 0xb0000000
2209 #define PHY_WRITE_PREVIOUS 0xc0000000
2210 #define PHY_SKIPN 0xd0000000
2211 #define PHY_DELAY_MS 0xe0000000
2212
2213 struct fw_info {
2214 u32 magic;
2215 char version[RTL_VER_SIZE];
2216 __le32 fw_start;
2217 __le32 fw_len;
2218 u8 chksum;
2219 } __packed;
2220
2221 #define FW_OPCODE_SIZE sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
2222
rtl_fw_format_ok(struct rtl8169_private * tp,struct rtl_fw * rtl_fw)2223 static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2224 {
2225 const struct firmware *fw = rtl_fw->fw;
2226 struct fw_info *fw_info = (struct fw_info *)fw->data;
2227 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2228 char *version = rtl_fw->version;
2229 bool rc = false;
2230
2231 if (fw->size < FW_OPCODE_SIZE)
2232 goto out;
2233
2234 if (!fw_info->magic) {
2235 size_t i, size, start;
2236 u8 checksum = 0;
2237
2238 if (fw->size < sizeof(*fw_info))
2239 goto out;
2240
2241 for (i = 0; i < fw->size; i++)
2242 checksum += fw->data[i];
2243 if (checksum != 0)
2244 goto out;
2245
2246 start = le32_to_cpu(fw_info->fw_start);
2247 if (start > fw->size)
2248 goto out;
2249
2250 size = le32_to_cpu(fw_info->fw_len);
2251 if (size > (fw->size - start) / FW_OPCODE_SIZE)
2252 goto out;
2253
2254 memcpy(version, fw_info->version, RTL_VER_SIZE);
2255
2256 pa->code = (__le32 *)(fw->data + start);
2257 pa->size = size;
2258 } else {
2259 if (fw->size % FW_OPCODE_SIZE)
2260 goto out;
2261
2262 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
2263
2264 pa->code = (__le32 *)fw->data;
2265 pa->size = fw->size / FW_OPCODE_SIZE;
2266 }
2267 version[RTL_VER_SIZE - 1] = 0;
2268
2269 rc = true;
2270 out:
2271 return rc;
2272 }
2273
rtl_fw_data_ok(struct rtl8169_private * tp,struct net_device * dev,struct rtl_fw_phy_action * pa)2274 static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
2275 struct rtl_fw_phy_action *pa)
2276 {
2277 bool rc = false;
2278 size_t index;
2279
2280 for (index = 0; index < pa->size; index++) {
2281 u32 action = le32_to_cpu(pa->code[index]);
2282 u32 regno = (action & 0x0fff0000) >> 16;
2283
2284 switch(action & 0xf0000000) {
2285 case PHY_READ:
2286 case PHY_DATA_OR:
2287 case PHY_DATA_AND:
2288 case PHY_MDIO_CHG:
2289 case PHY_CLEAR_READCOUNT:
2290 case PHY_WRITE:
2291 case PHY_WRITE_PREVIOUS:
2292 case PHY_DELAY_MS:
2293 break;
2294
2295 case PHY_BJMPN:
2296 if (regno > index) {
2297 netif_err(tp, ifup, tp->dev,
2298 "Out of range of firmware\n");
2299 goto out;
2300 }
2301 break;
2302 case PHY_READCOUNT_EQ_SKIP:
2303 if (index + 2 >= pa->size) {
2304 netif_err(tp, ifup, tp->dev,
2305 "Out of range of firmware\n");
2306 goto out;
2307 }
2308 break;
2309 case PHY_COMP_EQ_SKIPN:
2310 case PHY_COMP_NEQ_SKIPN:
2311 case PHY_SKIPN:
2312 if (index + 1 + regno >= pa->size) {
2313 netif_err(tp, ifup, tp->dev,
2314 "Out of range of firmware\n");
2315 goto out;
2316 }
2317 break;
2318
2319 default:
2320 netif_err(tp, ifup, tp->dev,
2321 "Invalid action 0x%08x\n", action);
2322 goto out;
2323 }
2324 }
2325 rc = true;
2326 out:
2327 return rc;
2328 }
2329
rtl_check_firmware(struct rtl8169_private * tp,struct rtl_fw * rtl_fw)2330 static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2331 {
2332 struct net_device *dev = tp->dev;
2333 int rc = -EINVAL;
2334
2335 if (!rtl_fw_format_ok(tp, rtl_fw)) {
2336 netif_err(tp, ifup, dev, "invalid firmware\n");
2337 goto out;
2338 }
2339
2340 if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
2341 rc = 0;
2342 out:
2343 return rc;
2344 }
2345
rtl_phy_write_fw(struct rtl8169_private * tp,struct rtl_fw * rtl_fw)2346 static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2347 {
2348 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2349 struct mdio_ops org, *ops = &tp->mdio_ops;
2350 u32 predata, count;
2351 size_t index;
2352
2353 predata = count = 0;
2354 org.write = ops->write;
2355 org.read = ops->read;
2356
2357 for (index = 0; index < pa->size; ) {
2358 u32 action = le32_to_cpu(pa->code[index]);
2359 u32 data = action & 0x0000ffff;
2360 u32 regno = (action & 0x0fff0000) >> 16;
2361
2362 if (!action)
2363 break;
2364
2365 switch(action & 0xf0000000) {
2366 case PHY_READ:
2367 predata = rtl_readphy(tp, regno);
2368 count++;
2369 index++;
2370 break;
2371 case PHY_DATA_OR:
2372 predata |= data;
2373 index++;
2374 break;
2375 case PHY_DATA_AND:
2376 predata &= data;
2377 index++;
2378 break;
2379 case PHY_BJMPN:
2380 index -= regno;
2381 break;
2382 case PHY_MDIO_CHG:
2383 if (data == 0) {
2384 ops->write = org.write;
2385 ops->read = org.read;
2386 } else if (data == 1) {
2387 ops->write = mac_mcu_write;
2388 ops->read = mac_mcu_read;
2389 }
2390
2391 index++;
2392 break;
2393 case PHY_CLEAR_READCOUNT:
2394 count = 0;
2395 index++;
2396 break;
2397 case PHY_WRITE:
2398 rtl_writephy(tp, regno, data);
2399 index++;
2400 break;
2401 case PHY_READCOUNT_EQ_SKIP:
2402 index += (count == data) ? 2 : 1;
2403 break;
2404 case PHY_COMP_EQ_SKIPN:
2405 if (predata == data)
2406 index += regno;
2407 index++;
2408 break;
2409 case PHY_COMP_NEQ_SKIPN:
2410 if (predata != data)
2411 index += regno;
2412 index++;
2413 break;
2414 case PHY_WRITE_PREVIOUS:
2415 rtl_writephy(tp, regno, predata);
2416 index++;
2417 break;
2418 case PHY_SKIPN:
2419 index += regno + 1;
2420 break;
2421 case PHY_DELAY_MS:
2422 mdelay(data);
2423 index++;
2424 break;
2425
2426 default:
2427 BUG();
2428 }
2429 }
2430
2431 ops->write = org.write;
2432 ops->read = org.read;
2433 }
2434
rtl_release_firmware(struct rtl8169_private * tp)2435 static void rtl_release_firmware(struct rtl8169_private *tp)
2436 {
2437 if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
2438 release_firmware(tp->rtl_fw->fw);
2439 kfree(tp->rtl_fw);
2440 }
2441 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
2442 }
2443
rtl_apply_firmware(struct rtl8169_private * tp)2444 static void rtl_apply_firmware(struct rtl8169_private *tp)
2445 {
2446 struct rtl_fw *rtl_fw = tp->rtl_fw;
2447
2448 /* TODO: release firmware once rtl_phy_write_fw signals failures. */
2449 if (!IS_ERR_OR_NULL(rtl_fw))
2450 rtl_phy_write_fw(tp, rtl_fw);
2451 }
2452
rtl_apply_firmware_cond(struct rtl8169_private * tp,u8 reg,u16 val)2453 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2454 {
2455 if (rtl_readphy(tp, reg) != val)
2456 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2457 else
2458 rtl_apply_firmware(tp);
2459 }
2460
rtl8169s_hw_phy_config(struct rtl8169_private * tp)2461 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
2462 {
2463 static const struct phy_reg phy_reg_init[] = {
2464 { 0x1f, 0x0001 },
2465 { 0x06, 0x006e },
2466 { 0x08, 0x0708 },
2467 { 0x15, 0x4000 },
2468 { 0x18, 0x65c7 },
2469
2470 { 0x1f, 0x0001 },
2471 { 0x03, 0x00a1 },
2472 { 0x02, 0x0008 },
2473 { 0x01, 0x0120 },
2474 { 0x00, 0x1000 },
2475 { 0x04, 0x0800 },
2476 { 0x04, 0x0000 },
2477
2478 { 0x03, 0xff41 },
2479 { 0x02, 0xdf60 },
2480 { 0x01, 0x0140 },
2481 { 0x00, 0x0077 },
2482 { 0x04, 0x7800 },
2483 { 0x04, 0x7000 },
2484
2485 { 0x03, 0x802f },
2486 { 0x02, 0x4f02 },
2487 { 0x01, 0x0409 },
2488 { 0x00, 0xf0f9 },
2489 { 0x04, 0x9800 },
2490 { 0x04, 0x9000 },
2491
2492 { 0x03, 0xdf01 },
2493 { 0x02, 0xdf20 },
2494 { 0x01, 0xff95 },
2495 { 0x00, 0xba00 },
2496 { 0x04, 0xa800 },
2497 { 0x04, 0xa000 },
2498
2499 { 0x03, 0xff41 },
2500 { 0x02, 0xdf20 },
2501 { 0x01, 0x0140 },
2502 { 0x00, 0x00bb },
2503 { 0x04, 0xb800 },
2504 { 0x04, 0xb000 },
2505
2506 { 0x03, 0xdf41 },
2507 { 0x02, 0xdc60 },
2508 { 0x01, 0x6340 },
2509 { 0x00, 0x007d },
2510 { 0x04, 0xd800 },
2511 { 0x04, 0xd000 },
2512
2513 { 0x03, 0xdf01 },
2514 { 0x02, 0xdf20 },
2515 { 0x01, 0x100a },
2516 { 0x00, 0xa0ff },
2517 { 0x04, 0xf800 },
2518 { 0x04, 0xf000 },
2519
2520 { 0x1f, 0x0000 },
2521 { 0x0b, 0x0000 },
2522 { 0x00, 0x9200 }
2523 };
2524
2525 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2526 }
2527
rtl8169sb_hw_phy_config(struct rtl8169_private * tp)2528 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
2529 {
2530 static const struct phy_reg phy_reg_init[] = {
2531 { 0x1f, 0x0002 },
2532 { 0x01, 0x90d0 },
2533 { 0x1f, 0x0000 }
2534 };
2535
2536 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2537 }
2538
rtl8169scd_hw_phy_config_quirk(struct rtl8169_private * tp)2539 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2540 {
2541 struct pci_dev *pdev = tp->pci_dev;
2542
2543 if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2544 (pdev->subsystem_device != 0xe000))
2545 return;
2546
2547 rtl_writephy(tp, 0x1f, 0x0001);
2548 rtl_writephy(tp, 0x10, 0xf01b);
2549 rtl_writephy(tp, 0x1f, 0x0000);
2550 }
2551
rtl8169scd_hw_phy_config(struct rtl8169_private * tp)2552 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2553 {
2554 static const struct phy_reg phy_reg_init[] = {
2555 { 0x1f, 0x0001 },
2556 { 0x04, 0x0000 },
2557 { 0x03, 0x00a1 },
2558 { 0x02, 0x0008 },
2559 { 0x01, 0x0120 },
2560 { 0x00, 0x1000 },
2561 { 0x04, 0x0800 },
2562 { 0x04, 0x9000 },
2563 { 0x03, 0x802f },
2564 { 0x02, 0x4f02 },
2565 { 0x01, 0x0409 },
2566 { 0x00, 0xf099 },
2567 { 0x04, 0x9800 },
2568 { 0x04, 0xa000 },
2569 { 0x03, 0xdf01 },
2570 { 0x02, 0xdf20 },
2571 { 0x01, 0xff95 },
2572 { 0x00, 0xba00 },
2573 { 0x04, 0xa800 },
2574 { 0x04, 0xf000 },
2575 { 0x03, 0xdf01 },
2576 { 0x02, 0xdf20 },
2577 { 0x01, 0x101a },
2578 { 0x00, 0xa0ff },
2579 { 0x04, 0xf800 },
2580 { 0x04, 0x0000 },
2581 { 0x1f, 0x0000 },
2582
2583 { 0x1f, 0x0001 },
2584 { 0x10, 0xf41b },
2585 { 0x14, 0xfb54 },
2586 { 0x18, 0xf5c7 },
2587 { 0x1f, 0x0000 },
2588
2589 { 0x1f, 0x0001 },
2590 { 0x17, 0x0cc0 },
2591 { 0x1f, 0x0000 }
2592 };
2593
2594 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2595
2596 rtl8169scd_hw_phy_config_quirk(tp);
2597 }
2598
rtl8169sce_hw_phy_config(struct rtl8169_private * tp)2599 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
2600 {
2601 static const struct phy_reg phy_reg_init[] = {
2602 { 0x1f, 0x0001 },
2603 { 0x04, 0x0000 },
2604 { 0x03, 0x00a1 },
2605 { 0x02, 0x0008 },
2606 { 0x01, 0x0120 },
2607 { 0x00, 0x1000 },
2608 { 0x04, 0x0800 },
2609 { 0x04, 0x9000 },
2610 { 0x03, 0x802f },
2611 { 0x02, 0x4f02 },
2612 { 0x01, 0x0409 },
2613 { 0x00, 0xf099 },
2614 { 0x04, 0x9800 },
2615 { 0x04, 0xa000 },
2616 { 0x03, 0xdf01 },
2617 { 0x02, 0xdf20 },
2618 { 0x01, 0xff95 },
2619 { 0x00, 0xba00 },
2620 { 0x04, 0xa800 },
2621 { 0x04, 0xf000 },
2622 { 0x03, 0xdf01 },
2623 { 0x02, 0xdf20 },
2624 { 0x01, 0x101a },
2625 { 0x00, 0xa0ff },
2626 { 0x04, 0xf800 },
2627 { 0x04, 0x0000 },
2628 { 0x1f, 0x0000 },
2629
2630 { 0x1f, 0x0001 },
2631 { 0x0b, 0x8480 },
2632 { 0x1f, 0x0000 },
2633
2634 { 0x1f, 0x0001 },
2635 { 0x18, 0x67c7 },
2636 { 0x04, 0x2000 },
2637 { 0x03, 0x002f },
2638 { 0x02, 0x4360 },
2639 { 0x01, 0x0109 },
2640 { 0x00, 0x3022 },
2641 { 0x04, 0x2800 },
2642 { 0x1f, 0x0000 },
2643
2644 { 0x1f, 0x0001 },
2645 { 0x17, 0x0cc0 },
2646 { 0x1f, 0x0000 }
2647 };
2648
2649 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2650 }
2651
rtl8168bb_hw_phy_config(struct rtl8169_private * tp)2652 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
2653 {
2654 static const struct phy_reg phy_reg_init[] = {
2655 { 0x10, 0xf41b },
2656 { 0x1f, 0x0000 }
2657 };
2658
2659 rtl_writephy(tp, 0x1f, 0x0001);
2660 rtl_patchphy(tp, 0x16, 1 << 0);
2661
2662 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2663 }
2664
rtl8168bef_hw_phy_config(struct rtl8169_private * tp)2665 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
2666 {
2667 static const struct phy_reg phy_reg_init[] = {
2668 { 0x1f, 0x0001 },
2669 { 0x10, 0xf41b },
2670 { 0x1f, 0x0000 }
2671 };
2672
2673 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2674 }
2675
rtl8168cp_1_hw_phy_config(struct rtl8169_private * tp)2676 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
2677 {
2678 static const struct phy_reg phy_reg_init[] = {
2679 { 0x1f, 0x0000 },
2680 { 0x1d, 0x0f00 },
2681 { 0x1f, 0x0002 },
2682 { 0x0c, 0x1ec8 },
2683 { 0x1f, 0x0000 }
2684 };
2685
2686 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2687 }
2688
rtl8168cp_2_hw_phy_config(struct rtl8169_private * tp)2689 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
2690 {
2691 static const struct phy_reg phy_reg_init[] = {
2692 { 0x1f, 0x0001 },
2693 { 0x1d, 0x3d98 },
2694 { 0x1f, 0x0000 }
2695 };
2696
2697 rtl_writephy(tp, 0x1f, 0x0000);
2698 rtl_patchphy(tp, 0x14, 1 << 5);
2699 rtl_patchphy(tp, 0x0d, 1 << 5);
2700
2701 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2702 }
2703
rtl8168c_1_hw_phy_config(struct rtl8169_private * tp)2704 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
2705 {
2706 static const struct phy_reg phy_reg_init[] = {
2707 { 0x1f, 0x0001 },
2708 { 0x12, 0x2300 },
2709 { 0x1f, 0x0002 },
2710 { 0x00, 0x88d4 },
2711 { 0x01, 0x82b1 },
2712 { 0x03, 0x7002 },
2713 { 0x08, 0x9e30 },
2714 { 0x09, 0x01f0 },
2715 { 0x0a, 0x5500 },
2716 { 0x0c, 0x00c8 },
2717 { 0x1f, 0x0003 },
2718 { 0x12, 0xc096 },
2719 { 0x16, 0x000a },
2720 { 0x1f, 0x0000 },
2721 { 0x1f, 0x0000 },
2722 { 0x09, 0x2000 },
2723 { 0x09, 0x0000 }
2724 };
2725
2726 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2727
2728 rtl_patchphy(tp, 0x14, 1 << 5);
2729 rtl_patchphy(tp, 0x0d, 1 << 5);
2730 rtl_writephy(tp, 0x1f, 0x0000);
2731 }
2732
rtl8168c_2_hw_phy_config(struct rtl8169_private * tp)2733 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
2734 {
2735 static const struct phy_reg phy_reg_init[] = {
2736 { 0x1f, 0x0001 },
2737 { 0x12, 0x2300 },
2738 { 0x03, 0x802f },
2739 { 0x02, 0x4f02 },
2740 { 0x01, 0x0409 },
2741 { 0x00, 0xf099 },
2742 { 0x04, 0x9800 },
2743 { 0x04, 0x9000 },
2744 { 0x1d, 0x3d98 },
2745 { 0x1f, 0x0002 },
2746 { 0x0c, 0x7eb8 },
2747 { 0x06, 0x0761 },
2748 { 0x1f, 0x0003 },
2749 { 0x16, 0x0f0a },
2750 { 0x1f, 0x0000 }
2751 };
2752
2753 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2754
2755 rtl_patchphy(tp, 0x16, 1 << 0);
2756 rtl_patchphy(tp, 0x14, 1 << 5);
2757 rtl_patchphy(tp, 0x0d, 1 << 5);
2758 rtl_writephy(tp, 0x1f, 0x0000);
2759 }
2760
rtl8168c_3_hw_phy_config(struct rtl8169_private * tp)2761 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
2762 {
2763 static const struct phy_reg phy_reg_init[] = {
2764 { 0x1f, 0x0001 },
2765 { 0x12, 0x2300 },
2766 { 0x1d, 0x3d98 },
2767 { 0x1f, 0x0002 },
2768 { 0x0c, 0x7eb8 },
2769 { 0x06, 0x5461 },
2770 { 0x1f, 0x0003 },
2771 { 0x16, 0x0f0a },
2772 { 0x1f, 0x0000 }
2773 };
2774
2775 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2776
2777 rtl_patchphy(tp, 0x16, 1 << 0);
2778 rtl_patchphy(tp, 0x14, 1 << 5);
2779 rtl_patchphy(tp, 0x0d, 1 << 5);
2780 rtl_writephy(tp, 0x1f, 0x0000);
2781 }
2782
rtl8168c_4_hw_phy_config(struct rtl8169_private * tp)2783 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
2784 {
2785 rtl8168c_3_hw_phy_config(tp);
2786 }
2787
rtl8168d_1_hw_phy_config(struct rtl8169_private * tp)2788 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
2789 {
2790 static const struct phy_reg phy_reg_init_0[] = {
2791 /* Channel Estimation */
2792 { 0x1f, 0x0001 },
2793 { 0x06, 0x4064 },
2794 { 0x07, 0x2863 },
2795 { 0x08, 0x059c },
2796 { 0x09, 0x26b4 },
2797 { 0x0a, 0x6a19 },
2798 { 0x0b, 0xdcc8 },
2799 { 0x10, 0xf06d },
2800 { 0x14, 0x7f68 },
2801 { 0x18, 0x7fd9 },
2802 { 0x1c, 0xf0ff },
2803 { 0x1d, 0x3d9c },
2804 { 0x1f, 0x0003 },
2805 { 0x12, 0xf49f },
2806 { 0x13, 0x070b },
2807 { 0x1a, 0x05ad },
2808 { 0x14, 0x94c0 },
2809
2810 /*
2811 * Tx Error Issue
2812 * Enhance line driver power
2813 */
2814 { 0x1f, 0x0002 },
2815 { 0x06, 0x5561 },
2816 { 0x1f, 0x0005 },
2817 { 0x05, 0x8332 },
2818 { 0x06, 0x5561 },
2819
2820 /*
2821 * Can not link to 1Gbps with bad cable
2822 * Decrease SNR threshold form 21.07dB to 19.04dB
2823 */
2824 { 0x1f, 0x0001 },
2825 { 0x17, 0x0cc0 },
2826
2827 { 0x1f, 0x0000 },
2828 { 0x0d, 0xf880 }
2829 };
2830
2831 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2832
2833 /*
2834 * Rx Error Issue
2835 * Fine Tune Switching regulator parameter
2836 */
2837 rtl_writephy(tp, 0x1f, 0x0002);
2838 rtl_w0w1_phy(tp, 0x0b, 0x0010, 0x00ef);
2839 rtl_w0w1_phy(tp, 0x0c, 0xa200, 0x5d00);
2840
2841 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
2842 static const struct phy_reg phy_reg_init[] = {
2843 { 0x1f, 0x0002 },
2844 { 0x05, 0x669a },
2845 { 0x1f, 0x0005 },
2846 { 0x05, 0x8330 },
2847 { 0x06, 0x669a },
2848 { 0x1f, 0x0002 }
2849 };
2850 int val;
2851
2852 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2853
2854 val = rtl_readphy(tp, 0x0d);
2855
2856 if ((val & 0x00ff) != 0x006c) {
2857 static const u32 set[] = {
2858 0x0065, 0x0066, 0x0067, 0x0068,
2859 0x0069, 0x006a, 0x006b, 0x006c
2860 };
2861 int i;
2862
2863 rtl_writephy(tp, 0x1f, 0x0002);
2864
2865 val &= 0xff00;
2866 for (i = 0; i < ARRAY_SIZE(set); i++)
2867 rtl_writephy(tp, 0x0d, val | set[i]);
2868 }
2869 } else {
2870 static const struct phy_reg phy_reg_init[] = {
2871 { 0x1f, 0x0002 },
2872 { 0x05, 0x6662 },
2873 { 0x1f, 0x0005 },
2874 { 0x05, 0x8330 },
2875 { 0x06, 0x6662 }
2876 };
2877
2878 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2879 }
2880
2881 /* RSET couple improve */
2882 rtl_writephy(tp, 0x1f, 0x0002);
2883 rtl_patchphy(tp, 0x0d, 0x0300);
2884 rtl_patchphy(tp, 0x0f, 0x0010);
2885
2886 /* Fine tune PLL performance */
2887 rtl_writephy(tp, 0x1f, 0x0002);
2888 rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
2889 rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
2890
2891 rtl_writephy(tp, 0x1f, 0x0005);
2892 rtl_writephy(tp, 0x05, 0x001b);
2893
2894 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
2895
2896 rtl_writephy(tp, 0x1f, 0x0000);
2897 }
2898
rtl8168d_2_hw_phy_config(struct rtl8169_private * tp)2899 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
2900 {
2901 static const struct phy_reg phy_reg_init_0[] = {
2902 /* Channel Estimation */
2903 { 0x1f, 0x0001 },
2904 { 0x06, 0x4064 },
2905 { 0x07, 0x2863 },
2906 { 0x08, 0x059c },
2907 { 0x09, 0x26b4 },
2908 { 0x0a, 0x6a19 },
2909 { 0x0b, 0xdcc8 },
2910 { 0x10, 0xf06d },
2911 { 0x14, 0x7f68 },
2912 { 0x18, 0x7fd9 },
2913 { 0x1c, 0xf0ff },
2914 { 0x1d, 0x3d9c },
2915 { 0x1f, 0x0003 },
2916 { 0x12, 0xf49f },
2917 { 0x13, 0x070b },
2918 { 0x1a, 0x05ad },
2919 { 0x14, 0x94c0 },
2920
2921 /*
2922 * Tx Error Issue
2923 * Enhance line driver power
2924 */
2925 { 0x1f, 0x0002 },
2926 { 0x06, 0x5561 },
2927 { 0x1f, 0x0005 },
2928 { 0x05, 0x8332 },
2929 { 0x06, 0x5561 },
2930
2931 /*
2932 * Can not link to 1Gbps with bad cable
2933 * Decrease SNR threshold form 21.07dB to 19.04dB
2934 */
2935 { 0x1f, 0x0001 },
2936 { 0x17, 0x0cc0 },
2937
2938 { 0x1f, 0x0000 },
2939 { 0x0d, 0xf880 }
2940 };
2941
2942 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2943
2944 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
2945 static const struct phy_reg phy_reg_init[] = {
2946 { 0x1f, 0x0002 },
2947 { 0x05, 0x669a },
2948 { 0x1f, 0x0005 },
2949 { 0x05, 0x8330 },
2950 { 0x06, 0x669a },
2951
2952 { 0x1f, 0x0002 }
2953 };
2954 int val;
2955
2956 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2957
2958 val = rtl_readphy(tp, 0x0d);
2959 if ((val & 0x00ff) != 0x006c) {
2960 static const u32 set[] = {
2961 0x0065, 0x0066, 0x0067, 0x0068,
2962 0x0069, 0x006a, 0x006b, 0x006c
2963 };
2964 int i;
2965
2966 rtl_writephy(tp, 0x1f, 0x0002);
2967
2968 val &= 0xff00;
2969 for (i = 0; i < ARRAY_SIZE(set); i++)
2970 rtl_writephy(tp, 0x0d, val | set[i]);
2971 }
2972 } else {
2973 static const struct phy_reg phy_reg_init[] = {
2974 { 0x1f, 0x0002 },
2975 { 0x05, 0x2642 },
2976 { 0x1f, 0x0005 },
2977 { 0x05, 0x8330 },
2978 { 0x06, 0x2642 }
2979 };
2980
2981 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2982 }
2983
2984 /* Fine tune PLL performance */
2985 rtl_writephy(tp, 0x1f, 0x0002);
2986 rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
2987 rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
2988
2989 /* Switching regulator Slew rate */
2990 rtl_writephy(tp, 0x1f, 0x0002);
2991 rtl_patchphy(tp, 0x0f, 0x0017);
2992
2993 rtl_writephy(tp, 0x1f, 0x0005);
2994 rtl_writephy(tp, 0x05, 0x001b);
2995
2996 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
2997
2998 rtl_writephy(tp, 0x1f, 0x0000);
2999 }
3000
rtl8168d_3_hw_phy_config(struct rtl8169_private * tp)3001 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
3002 {
3003 static const struct phy_reg phy_reg_init[] = {
3004 { 0x1f, 0x0002 },
3005 { 0x10, 0x0008 },
3006 { 0x0d, 0x006c },
3007
3008 { 0x1f, 0x0000 },
3009 { 0x0d, 0xf880 },
3010
3011 { 0x1f, 0x0001 },
3012 { 0x17, 0x0cc0 },
3013
3014 { 0x1f, 0x0001 },
3015 { 0x0b, 0xa4d8 },
3016 { 0x09, 0x281c },
3017 { 0x07, 0x2883 },
3018 { 0x0a, 0x6b35 },
3019 { 0x1d, 0x3da4 },
3020 { 0x1c, 0xeffd },
3021 { 0x14, 0x7f52 },
3022 { 0x18, 0x7fc6 },
3023 { 0x08, 0x0601 },
3024 { 0x06, 0x4063 },
3025 { 0x10, 0xf074 },
3026 { 0x1f, 0x0003 },
3027 { 0x13, 0x0789 },
3028 { 0x12, 0xf4bd },
3029 { 0x1a, 0x04fd },
3030 { 0x14, 0x84b0 },
3031 { 0x1f, 0x0000 },
3032 { 0x00, 0x9200 },
3033
3034 { 0x1f, 0x0005 },
3035 { 0x01, 0x0340 },
3036 { 0x1f, 0x0001 },
3037 { 0x04, 0x4000 },
3038 { 0x03, 0x1d21 },
3039 { 0x02, 0x0c32 },
3040 { 0x01, 0x0200 },
3041 { 0x00, 0x5554 },
3042 { 0x04, 0x4800 },
3043 { 0x04, 0x4000 },
3044 { 0x04, 0xf000 },
3045 { 0x03, 0xdf01 },
3046 { 0x02, 0xdf20 },
3047 { 0x01, 0x101a },
3048 { 0x00, 0xa0ff },
3049 { 0x04, 0xf800 },
3050 { 0x04, 0xf000 },
3051 { 0x1f, 0x0000 },
3052
3053 { 0x1f, 0x0007 },
3054 { 0x1e, 0x0023 },
3055 { 0x16, 0x0000 },
3056 { 0x1f, 0x0000 }
3057 };
3058
3059 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3060 }
3061
rtl8168d_4_hw_phy_config(struct rtl8169_private * tp)3062 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
3063 {
3064 static const struct phy_reg phy_reg_init[] = {
3065 { 0x1f, 0x0001 },
3066 { 0x17, 0x0cc0 },
3067
3068 { 0x1f, 0x0007 },
3069 { 0x1e, 0x002d },
3070 { 0x18, 0x0040 },
3071 { 0x1f, 0x0000 }
3072 };
3073
3074 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3075 rtl_patchphy(tp, 0x0d, 1 << 5);
3076 }
3077
rtl8168e_1_hw_phy_config(struct rtl8169_private * tp)3078 static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
3079 {
3080 static const struct phy_reg phy_reg_init[] = {
3081 /* Enable Delay cap */
3082 { 0x1f, 0x0005 },
3083 { 0x05, 0x8b80 },
3084 { 0x06, 0xc896 },
3085 { 0x1f, 0x0000 },
3086
3087 /* Channel estimation fine tune */
3088 { 0x1f, 0x0001 },
3089 { 0x0b, 0x6c20 },
3090 { 0x07, 0x2872 },
3091 { 0x1c, 0xefff },
3092 { 0x1f, 0x0003 },
3093 { 0x14, 0x6420 },
3094 { 0x1f, 0x0000 },
3095
3096 /* Update PFM & 10M TX idle timer */
3097 { 0x1f, 0x0007 },
3098 { 0x1e, 0x002f },
3099 { 0x15, 0x1919 },
3100 { 0x1f, 0x0000 },
3101
3102 { 0x1f, 0x0007 },
3103 { 0x1e, 0x00ac },
3104 { 0x18, 0x0006 },
3105 { 0x1f, 0x0000 }
3106 };
3107
3108 rtl_apply_firmware(tp);
3109
3110 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3111
3112 /* DCO enable for 10M IDLE Power */
3113 rtl_writephy(tp, 0x1f, 0x0007);
3114 rtl_writephy(tp, 0x1e, 0x0023);
3115 rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
3116 rtl_writephy(tp, 0x1f, 0x0000);
3117
3118 /* For impedance matching */
3119 rtl_writephy(tp, 0x1f, 0x0002);
3120 rtl_w0w1_phy(tp, 0x08, 0x8000, 0x7f00);
3121 rtl_writephy(tp, 0x1f, 0x0000);
3122
3123 /* PHY auto speed down */
3124 rtl_writephy(tp, 0x1f, 0x0007);
3125 rtl_writephy(tp, 0x1e, 0x002d);
3126 rtl_w0w1_phy(tp, 0x18, 0x0050, 0x0000);
3127 rtl_writephy(tp, 0x1f, 0x0000);
3128 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3129
3130 rtl_writephy(tp, 0x1f, 0x0005);
3131 rtl_writephy(tp, 0x05, 0x8b86);
3132 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3133 rtl_writephy(tp, 0x1f, 0x0000);
3134
3135 rtl_writephy(tp, 0x1f, 0x0005);
3136 rtl_writephy(tp, 0x05, 0x8b85);
3137 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
3138 rtl_writephy(tp, 0x1f, 0x0007);
3139 rtl_writephy(tp, 0x1e, 0x0020);
3140 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x1100);
3141 rtl_writephy(tp, 0x1f, 0x0006);
3142 rtl_writephy(tp, 0x00, 0x5a00);
3143 rtl_writephy(tp, 0x1f, 0x0000);
3144 rtl_writephy(tp, 0x0d, 0x0007);
3145 rtl_writephy(tp, 0x0e, 0x003c);
3146 rtl_writephy(tp, 0x0d, 0x4007);
3147 rtl_writephy(tp, 0x0e, 0x0000);
3148 rtl_writephy(tp, 0x0d, 0x0000);
3149 }
3150
rtl_rar_exgmac_set(struct rtl8169_private * tp,u8 * addr)3151 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr)
3152 {
3153 const u16 w[] = {
3154 addr[0] | (addr[1] << 8),
3155 addr[2] | (addr[3] << 8),
3156 addr[4] | (addr[5] << 8)
3157 };
3158 const struct exgmac_reg e[] = {
3159 { .addr = 0xe0, ERIAR_MASK_1111, .val = w[0] | (w[1] << 16) },
3160 { .addr = 0xe4, ERIAR_MASK_1111, .val = w[2] },
3161 { .addr = 0xf0, ERIAR_MASK_1111, .val = w[0] << 16 },
3162 { .addr = 0xf4, ERIAR_MASK_1111, .val = w[1] | (w[2] << 16) }
3163 };
3164
3165 rtl_write_exgmac_batch(tp, e, ARRAY_SIZE(e));
3166 }
3167
rtl8168e_2_hw_phy_config(struct rtl8169_private * tp)3168 static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
3169 {
3170 static const struct phy_reg phy_reg_init[] = {
3171 /* Enable Delay cap */
3172 { 0x1f, 0x0004 },
3173 { 0x1f, 0x0007 },
3174 { 0x1e, 0x00ac },
3175 { 0x18, 0x0006 },
3176 { 0x1f, 0x0002 },
3177 { 0x1f, 0x0000 },
3178 { 0x1f, 0x0000 },
3179
3180 /* Channel estimation fine tune */
3181 { 0x1f, 0x0003 },
3182 { 0x09, 0xa20f },
3183 { 0x1f, 0x0000 },
3184 { 0x1f, 0x0000 },
3185
3186 /* Green Setting */
3187 { 0x1f, 0x0005 },
3188 { 0x05, 0x8b5b },
3189 { 0x06, 0x9222 },
3190 { 0x05, 0x8b6d },
3191 { 0x06, 0x8000 },
3192 { 0x05, 0x8b76 },
3193 { 0x06, 0x8000 },
3194 { 0x1f, 0x0000 }
3195 };
3196
3197 rtl_apply_firmware(tp);
3198
3199 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3200
3201 /* For 4-corner performance improve */
3202 rtl_writephy(tp, 0x1f, 0x0005);
3203 rtl_writephy(tp, 0x05, 0x8b80);
3204 rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
3205 rtl_writephy(tp, 0x1f, 0x0000);
3206
3207 /* PHY auto speed down */
3208 rtl_writephy(tp, 0x1f, 0x0004);
3209 rtl_writephy(tp, 0x1f, 0x0007);
3210 rtl_writephy(tp, 0x1e, 0x002d);
3211 rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
3212 rtl_writephy(tp, 0x1f, 0x0002);
3213 rtl_writephy(tp, 0x1f, 0x0000);
3214 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3215
3216 /* improve 10M EEE waveform */
3217 rtl_writephy(tp, 0x1f, 0x0005);
3218 rtl_writephy(tp, 0x05, 0x8b86);
3219 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3220 rtl_writephy(tp, 0x1f, 0x0000);
3221
3222 /* Improve 2-pair detection performance */
3223 rtl_writephy(tp, 0x1f, 0x0005);
3224 rtl_writephy(tp, 0x05, 0x8b85);
3225 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3226 rtl_writephy(tp, 0x1f, 0x0000);
3227
3228 /* EEE setting */
3229 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_1111, 0x0003, 0x0000, ERIAR_EXGMAC);
3230 rtl_writephy(tp, 0x1f, 0x0005);
3231 rtl_writephy(tp, 0x05, 0x8b85);
3232 rtl_w0w1_phy(tp, 0x06, 0x2000, 0x0000);
3233 rtl_writephy(tp, 0x1f, 0x0004);
3234 rtl_writephy(tp, 0x1f, 0x0007);
3235 rtl_writephy(tp, 0x1e, 0x0020);
3236 rtl_w0w1_phy(tp, 0x15, 0x0100, 0x0000);
3237 rtl_writephy(tp, 0x1f, 0x0002);
3238 rtl_writephy(tp, 0x1f, 0x0000);
3239 rtl_writephy(tp, 0x0d, 0x0007);
3240 rtl_writephy(tp, 0x0e, 0x003c);
3241 rtl_writephy(tp, 0x0d, 0x4007);
3242 rtl_writephy(tp, 0x0e, 0x0006);
3243 rtl_writephy(tp, 0x0d, 0x0000);
3244
3245 /* Green feature */
3246 rtl_writephy(tp, 0x1f, 0x0003);
3247 rtl_w0w1_phy(tp, 0x19, 0x0001, 0x0000);
3248 rtl_w0w1_phy(tp, 0x10, 0x0400, 0x0000);
3249 rtl_writephy(tp, 0x1f, 0x0000);
3250 rtl_writephy(tp, 0x1f, 0x0005);
3251 rtl_w0w1_phy(tp, 0x01, 0x0100, 0x0000);
3252 rtl_writephy(tp, 0x1f, 0x0000);
3253
3254 /* Broken BIOS workaround: feed GigaMAC registers with MAC address. */
3255 rtl_rar_exgmac_set(tp, tp->dev->dev_addr);
3256 }
3257
rtl8168f_hw_phy_config(struct rtl8169_private * tp)3258 static void rtl8168f_hw_phy_config(struct rtl8169_private *tp)
3259 {
3260 /* For 4-corner performance improve */
3261 rtl_writephy(tp, 0x1f, 0x0005);
3262 rtl_writephy(tp, 0x05, 0x8b80);
3263 rtl_w0w1_phy(tp, 0x06, 0x0006, 0x0000);
3264 rtl_writephy(tp, 0x1f, 0x0000);
3265
3266 /* PHY auto speed down */
3267 rtl_writephy(tp, 0x1f, 0x0007);
3268 rtl_writephy(tp, 0x1e, 0x002d);
3269 rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
3270 rtl_writephy(tp, 0x1f, 0x0000);
3271 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3272
3273 /* Improve 10M EEE waveform */
3274 rtl_writephy(tp, 0x1f, 0x0005);
3275 rtl_writephy(tp, 0x05, 0x8b86);
3276 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3277 rtl_writephy(tp, 0x1f, 0x0000);
3278 }
3279
rtl8168f_1_hw_phy_config(struct rtl8169_private * tp)3280 static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
3281 {
3282 static const struct phy_reg phy_reg_init[] = {
3283 /* Channel estimation fine tune */
3284 { 0x1f, 0x0003 },
3285 { 0x09, 0xa20f },
3286 { 0x1f, 0x0000 },
3287
3288 /* Modify green table for giga & fnet */
3289 { 0x1f, 0x0005 },
3290 { 0x05, 0x8b55 },
3291 { 0x06, 0x0000 },
3292 { 0x05, 0x8b5e },
3293 { 0x06, 0x0000 },
3294 { 0x05, 0x8b67 },
3295 { 0x06, 0x0000 },
3296 { 0x05, 0x8b70 },
3297 { 0x06, 0x0000 },
3298 { 0x1f, 0x0000 },
3299 { 0x1f, 0x0007 },
3300 { 0x1e, 0x0078 },
3301 { 0x17, 0x0000 },
3302 { 0x19, 0x00fb },
3303 { 0x1f, 0x0000 },
3304
3305 /* Modify green table for 10M */
3306 { 0x1f, 0x0005 },
3307 { 0x05, 0x8b79 },
3308 { 0x06, 0xaa00 },
3309 { 0x1f, 0x0000 },
3310
3311 /* Disable hiimpedance detection (RTCT) */
3312 { 0x1f, 0x0003 },
3313 { 0x01, 0x328a },
3314 { 0x1f, 0x0000 }
3315 };
3316
3317 rtl_apply_firmware(tp);
3318
3319 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3320
3321 rtl8168f_hw_phy_config(tp);
3322
3323 /* Improve 2-pair detection performance */
3324 rtl_writephy(tp, 0x1f, 0x0005);
3325 rtl_writephy(tp, 0x05, 0x8b85);
3326 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3327 rtl_writephy(tp, 0x1f, 0x0000);
3328 }
3329
rtl8168f_2_hw_phy_config(struct rtl8169_private * tp)3330 static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3331 {
3332 rtl_apply_firmware(tp);
3333
3334 rtl8168f_hw_phy_config(tp);
3335 }
3336
rtl8411_hw_phy_config(struct rtl8169_private * tp)3337 static void rtl8411_hw_phy_config(struct rtl8169_private *tp)
3338 {
3339 static const struct phy_reg phy_reg_init[] = {
3340 /* Channel estimation fine tune */
3341 { 0x1f, 0x0003 },
3342 { 0x09, 0xa20f },
3343 { 0x1f, 0x0000 },
3344
3345 /* Modify green table for giga & fnet */
3346 { 0x1f, 0x0005 },
3347 { 0x05, 0x8b55 },
3348 { 0x06, 0x0000 },
3349 { 0x05, 0x8b5e },
3350 { 0x06, 0x0000 },
3351 { 0x05, 0x8b67 },
3352 { 0x06, 0x0000 },
3353 { 0x05, 0x8b70 },
3354 { 0x06, 0x0000 },
3355 { 0x1f, 0x0000 },
3356 { 0x1f, 0x0007 },
3357 { 0x1e, 0x0078 },
3358 { 0x17, 0x0000 },
3359 { 0x19, 0x00aa },
3360 { 0x1f, 0x0000 },
3361
3362 /* Modify green table for 10M */
3363 { 0x1f, 0x0005 },
3364 { 0x05, 0x8b79 },
3365 { 0x06, 0xaa00 },
3366 { 0x1f, 0x0000 },
3367
3368 /* Disable hiimpedance detection (RTCT) */
3369 { 0x1f, 0x0003 },
3370 { 0x01, 0x328a },
3371 { 0x1f, 0x0000 }
3372 };
3373
3374
3375 rtl_apply_firmware(tp);
3376
3377 rtl8168f_hw_phy_config(tp);
3378
3379 /* Improve 2-pair detection performance */
3380 rtl_writephy(tp, 0x1f, 0x0005);
3381 rtl_writephy(tp, 0x05, 0x8b85);
3382 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3383 rtl_writephy(tp, 0x1f, 0x0000);
3384
3385 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3386
3387 /* Modify green table for giga */
3388 rtl_writephy(tp, 0x1f, 0x0005);
3389 rtl_writephy(tp, 0x05, 0x8b54);
3390 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
3391 rtl_writephy(tp, 0x05, 0x8b5d);
3392 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
3393 rtl_writephy(tp, 0x05, 0x8a7c);
3394 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3395 rtl_writephy(tp, 0x05, 0x8a7f);
3396 rtl_w0w1_phy(tp, 0x06, 0x0100, 0x0000);
3397 rtl_writephy(tp, 0x05, 0x8a82);
3398 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3399 rtl_writephy(tp, 0x05, 0x8a85);
3400 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3401 rtl_writephy(tp, 0x05, 0x8a88);
3402 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3403 rtl_writephy(tp, 0x1f, 0x0000);
3404
3405 /* uc same-seed solution */
3406 rtl_writephy(tp, 0x1f, 0x0005);
3407 rtl_writephy(tp, 0x05, 0x8b85);
3408 rtl_w0w1_phy(tp, 0x06, 0x8000, 0x0000);
3409 rtl_writephy(tp, 0x1f, 0x0000);
3410
3411 /* eee setting */
3412 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x00, 0x03, ERIAR_EXGMAC);
3413 rtl_writephy(tp, 0x1f, 0x0005);
3414 rtl_writephy(tp, 0x05, 0x8b85);
3415 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
3416 rtl_writephy(tp, 0x1f, 0x0004);
3417 rtl_writephy(tp, 0x1f, 0x0007);
3418 rtl_writephy(tp, 0x1e, 0x0020);
3419 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0100);
3420 rtl_writephy(tp, 0x1f, 0x0000);
3421 rtl_writephy(tp, 0x0d, 0x0007);
3422 rtl_writephy(tp, 0x0e, 0x003c);
3423 rtl_writephy(tp, 0x0d, 0x4007);
3424 rtl_writephy(tp, 0x0e, 0x0000);
3425 rtl_writephy(tp, 0x0d, 0x0000);
3426
3427 /* Green feature */
3428 rtl_writephy(tp, 0x1f, 0x0003);
3429 rtl_w0w1_phy(tp, 0x19, 0x0000, 0x0001);
3430 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0400);
3431 rtl_writephy(tp, 0x1f, 0x0000);
3432 }
3433
rtl8168g_1_hw_phy_config(struct rtl8169_private * tp)3434 static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp)
3435 {
3436 rtl_apply_firmware(tp);
3437
3438 rtl_writephy(tp, 0x1f, 0x0a46);
3439 if (rtl_readphy(tp, 0x10) & 0x0100) {
3440 rtl_writephy(tp, 0x1f, 0x0bcc);
3441 rtl_w0w1_phy(tp, 0x12, 0x0000, 0x8000);
3442 } else {
3443 rtl_writephy(tp, 0x1f, 0x0bcc);
3444 rtl_w0w1_phy(tp, 0x12, 0x8000, 0x0000);
3445 }
3446
3447 rtl_writephy(tp, 0x1f, 0x0a46);
3448 if (rtl_readphy(tp, 0x13) & 0x0100) {
3449 rtl_writephy(tp, 0x1f, 0x0c41);
3450 rtl_w0w1_phy(tp, 0x15, 0x0002, 0x0000);
3451 } else {
3452 rtl_writephy(tp, 0x1f, 0x0c41);
3453 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0002);
3454 }
3455
3456 /* Enable PHY auto speed down */
3457 rtl_writephy(tp, 0x1f, 0x0a44);
3458 rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000);
3459
3460 rtl_writephy(tp, 0x1f, 0x0bcc);
3461 rtl_w0w1_phy(tp, 0x14, 0x0100, 0x0000);
3462 rtl_writephy(tp, 0x1f, 0x0a44);
3463 rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
3464 rtl_writephy(tp, 0x1f, 0x0a43);
3465 rtl_writephy(tp, 0x13, 0x8084);
3466 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
3467 rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
3468
3469 /* EEE auto-fallback function */
3470 rtl_writephy(tp, 0x1f, 0x0a4b);
3471 rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000);
3472
3473 /* Enable UC LPF tune function */
3474 rtl_writephy(tp, 0x1f, 0x0a43);
3475 rtl_writephy(tp, 0x13, 0x8012);
3476 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3477
3478 rtl_writephy(tp, 0x1f, 0x0c42);
3479 rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
3480
3481 /* Improve SWR Efficiency */
3482 rtl_writephy(tp, 0x1f, 0x0bcd);
3483 rtl_writephy(tp, 0x14, 0x5065);
3484 rtl_writephy(tp, 0x14, 0xd065);
3485 rtl_writephy(tp, 0x1f, 0x0bc8);
3486 rtl_writephy(tp, 0x11, 0x5655);
3487 rtl_writephy(tp, 0x1f, 0x0bcd);
3488 rtl_writephy(tp, 0x14, 0x1065);
3489 rtl_writephy(tp, 0x14, 0x9065);
3490 rtl_writephy(tp, 0x14, 0x1065);
3491
3492 /* Check ALDPS bit, disable it if enabled */
3493 rtl_writephy(tp, 0x1f, 0x0a43);
3494 if (rtl_readphy(tp, 0x10) & 0x0004)
3495 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3496
3497 rtl_writephy(tp, 0x1f, 0x0000);
3498 }
3499
rtl8168g_2_hw_phy_config(struct rtl8169_private * tp)3500 static void rtl8168g_2_hw_phy_config(struct rtl8169_private *tp)
3501 {
3502 rtl_apply_firmware(tp);
3503 }
3504
rtl8168h_1_hw_phy_config(struct rtl8169_private * tp)3505 static void rtl8168h_1_hw_phy_config(struct rtl8169_private *tp)
3506 {
3507 u16 dout_tapbin;
3508 u32 data;
3509
3510 rtl_apply_firmware(tp);
3511
3512 /* CHN EST parameters adjust - giga master */
3513 rtl_writephy(tp, 0x1f, 0x0a43);
3514 rtl_writephy(tp, 0x13, 0x809b);
3515 rtl_w0w1_phy(tp, 0x14, 0x8000, 0xf800);
3516 rtl_writephy(tp, 0x13, 0x80a2);
3517 rtl_w0w1_phy(tp, 0x14, 0x8000, 0xff00);
3518 rtl_writephy(tp, 0x13, 0x80a4);
3519 rtl_w0w1_phy(tp, 0x14, 0x8500, 0xff00);
3520 rtl_writephy(tp, 0x13, 0x809c);
3521 rtl_w0w1_phy(tp, 0x14, 0xbd00, 0xff00);
3522 rtl_writephy(tp, 0x1f, 0x0000);
3523
3524 /* CHN EST parameters adjust - giga slave */
3525 rtl_writephy(tp, 0x1f, 0x0a43);
3526 rtl_writephy(tp, 0x13, 0x80ad);
3527 rtl_w0w1_phy(tp, 0x14, 0x7000, 0xf800);
3528 rtl_writephy(tp, 0x13, 0x80b4);
3529 rtl_w0w1_phy(tp, 0x14, 0x5000, 0xff00);
3530 rtl_writephy(tp, 0x13, 0x80ac);
3531 rtl_w0w1_phy(tp, 0x14, 0x4000, 0xff00);
3532 rtl_writephy(tp, 0x1f, 0x0000);
3533
3534 /* CHN EST parameters adjust - fnet */
3535 rtl_writephy(tp, 0x1f, 0x0a43);
3536 rtl_writephy(tp, 0x13, 0x808e);
3537 rtl_w0w1_phy(tp, 0x14, 0x1200, 0xff00);
3538 rtl_writephy(tp, 0x13, 0x8090);
3539 rtl_w0w1_phy(tp, 0x14, 0xe500, 0xff00);
3540 rtl_writephy(tp, 0x13, 0x8092);
3541 rtl_w0w1_phy(tp, 0x14, 0x9f00, 0xff00);
3542 rtl_writephy(tp, 0x1f, 0x0000);
3543
3544 /* enable R-tune & PGA-retune function */
3545 dout_tapbin = 0;
3546 rtl_writephy(tp, 0x1f, 0x0a46);
3547 data = rtl_readphy(tp, 0x13);
3548 data &= 3;
3549 data <<= 2;
3550 dout_tapbin |= data;
3551 data = rtl_readphy(tp, 0x12);
3552 data &= 0xc000;
3553 data >>= 14;
3554 dout_tapbin |= data;
3555 dout_tapbin = ~(dout_tapbin^0x08);
3556 dout_tapbin <<= 12;
3557 dout_tapbin &= 0xf000;
3558 rtl_writephy(tp, 0x1f, 0x0a43);
3559 rtl_writephy(tp, 0x13, 0x827a);
3560 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3561 rtl_writephy(tp, 0x13, 0x827b);
3562 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3563 rtl_writephy(tp, 0x13, 0x827c);
3564 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3565 rtl_writephy(tp, 0x13, 0x827d);
3566 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3567
3568 rtl_writephy(tp, 0x1f, 0x0a43);
3569 rtl_writephy(tp, 0x13, 0x0811);
3570 rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
3571 rtl_writephy(tp, 0x1f, 0x0a42);
3572 rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
3573 rtl_writephy(tp, 0x1f, 0x0000);
3574
3575 /* enable GPHY 10M */
3576 rtl_writephy(tp, 0x1f, 0x0a44);
3577 rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000);
3578 rtl_writephy(tp, 0x1f, 0x0000);
3579
3580 /* SAR ADC performance */
3581 rtl_writephy(tp, 0x1f, 0x0bca);
3582 rtl_w0w1_phy(tp, 0x17, 0x4000, 0x3000);
3583 rtl_writephy(tp, 0x1f, 0x0000);
3584
3585 rtl_writephy(tp, 0x1f, 0x0a43);
3586 rtl_writephy(tp, 0x13, 0x803f);
3587 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3588 rtl_writephy(tp, 0x13, 0x8047);
3589 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3590 rtl_writephy(tp, 0x13, 0x804f);
3591 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3592 rtl_writephy(tp, 0x13, 0x8057);
3593 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3594 rtl_writephy(tp, 0x13, 0x805f);
3595 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3596 rtl_writephy(tp, 0x13, 0x8067);
3597 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3598 rtl_writephy(tp, 0x13, 0x806f);
3599 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3600 rtl_writephy(tp, 0x1f, 0x0000);
3601
3602 /* disable phy pfm mode */
3603 rtl_writephy(tp, 0x1f, 0x0a44);
3604 rtl_w0w1_phy(tp, 0x11, 0x0000, 0x0080);
3605 rtl_writephy(tp, 0x1f, 0x0000);
3606
3607 /* Check ALDPS bit, disable it if enabled */
3608 rtl_writephy(tp, 0x1f, 0x0a43);
3609 if (rtl_readphy(tp, 0x10) & 0x0004)
3610 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3611
3612 rtl_writephy(tp, 0x1f, 0x0000);
3613 }
3614
rtl8168h_2_hw_phy_config(struct rtl8169_private * tp)3615 static void rtl8168h_2_hw_phy_config(struct rtl8169_private *tp)
3616 {
3617 u16 ioffset_p3, ioffset_p2, ioffset_p1, ioffset_p0;
3618 u16 rlen;
3619 u32 data;
3620
3621 rtl_apply_firmware(tp);
3622
3623 /* CHIN EST parameter update */
3624 rtl_writephy(tp, 0x1f, 0x0a43);
3625 rtl_writephy(tp, 0x13, 0x808a);
3626 rtl_w0w1_phy(tp, 0x14, 0x000a, 0x003f);
3627 rtl_writephy(tp, 0x1f, 0x0000);
3628
3629 /* enable R-tune & PGA-retune function */
3630 rtl_writephy(tp, 0x1f, 0x0a43);
3631 rtl_writephy(tp, 0x13, 0x0811);
3632 rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
3633 rtl_writephy(tp, 0x1f, 0x0a42);
3634 rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
3635 rtl_writephy(tp, 0x1f, 0x0000);
3636
3637 /* enable GPHY 10M */
3638 rtl_writephy(tp, 0x1f, 0x0a44);
3639 rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000);
3640 rtl_writephy(tp, 0x1f, 0x0000);
3641
3642 r8168_mac_ocp_write(tp, 0xdd02, 0x807d);
3643 data = r8168_mac_ocp_read(tp, 0xdd02);
3644 ioffset_p3 = ((data & 0x80)>>7);
3645 ioffset_p3 <<= 3;
3646
3647 data = r8168_mac_ocp_read(tp, 0xdd00);
3648 ioffset_p3 |= ((data & (0xe000))>>13);
3649 ioffset_p2 = ((data & (0x1e00))>>9);
3650 ioffset_p1 = ((data & (0x01e0))>>5);
3651 ioffset_p0 = ((data & 0x0010)>>4);
3652 ioffset_p0 <<= 3;
3653 ioffset_p0 |= (data & (0x07));
3654 data = (ioffset_p3<<12)|(ioffset_p2<<8)|(ioffset_p1<<4)|(ioffset_p0);
3655
3656 if ((ioffset_p3 != 0x0f) || (ioffset_p2 != 0x0f) ||
3657 (ioffset_p1 != 0x0f) || (ioffset_p0 != 0x0f)) {
3658 rtl_writephy(tp, 0x1f, 0x0bcf);
3659 rtl_writephy(tp, 0x16, data);
3660 rtl_writephy(tp, 0x1f, 0x0000);
3661 }
3662
3663 /* Modify rlen (TX LPF corner frequency) level */
3664 rtl_writephy(tp, 0x1f, 0x0bcd);
3665 data = rtl_readphy(tp, 0x16);
3666 data &= 0x000f;
3667 rlen = 0;
3668 if (data > 3)
3669 rlen = data - 3;
3670 data = rlen | (rlen<<4) | (rlen<<8) | (rlen<<12);
3671 rtl_writephy(tp, 0x17, data);
3672 rtl_writephy(tp, 0x1f, 0x0bcd);
3673 rtl_writephy(tp, 0x1f, 0x0000);
3674
3675 /* disable phy pfm mode */
3676 rtl_writephy(tp, 0x1f, 0x0a44);
3677 rtl_w0w1_phy(tp, 0x11, 0x0000, 0x0080);
3678 rtl_writephy(tp, 0x1f, 0x0000);
3679
3680 /* Check ALDPS bit, disable it if enabled */
3681 rtl_writephy(tp, 0x1f, 0x0a43);
3682 if (rtl_readphy(tp, 0x10) & 0x0004)
3683 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3684
3685 rtl_writephy(tp, 0x1f, 0x0000);
3686 }
3687
rtl8168ep_1_hw_phy_config(struct rtl8169_private * tp)3688 static void rtl8168ep_1_hw_phy_config(struct rtl8169_private *tp)
3689 {
3690 /* Enable PHY auto speed down */
3691 rtl_writephy(tp, 0x1f, 0x0a44);
3692 rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000);
3693 rtl_writephy(tp, 0x1f, 0x0000);
3694
3695 /* patch 10M & ALDPS */
3696 rtl_writephy(tp, 0x1f, 0x0bcc);
3697 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0100);
3698 rtl_writephy(tp, 0x1f, 0x0a44);
3699 rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
3700 rtl_writephy(tp, 0x1f, 0x0a43);
3701 rtl_writephy(tp, 0x13, 0x8084);
3702 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
3703 rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
3704 rtl_writephy(tp, 0x1f, 0x0000);
3705
3706 /* Enable EEE auto-fallback function */
3707 rtl_writephy(tp, 0x1f, 0x0a4b);
3708 rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000);
3709 rtl_writephy(tp, 0x1f, 0x0000);
3710
3711 /* Enable UC LPF tune function */
3712 rtl_writephy(tp, 0x1f, 0x0a43);
3713 rtl_writephy(tp, 0x13, 0x8012);
3714 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3715 rtl_writephy(tp, 0x1f, 0x0000);
3716
3717 /* set rg_sel_sdm_rate */
3718 rtl_writephy(tp, 0x1f, 0x0c42);
3719 rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
3720 rtl_writephy(tp, 0x1f, 0x0000);
3721
3722 /* Check ALDPS bit, disable it if enabled */
3723 rtl_writephy(tp, 0x1f, 0x0a43);
3724 if (rtl_readphy(tp, 0x10) & 0x0004)
3725 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3726
3727 rtl_writephy(tp, 0x1f, 0x0000);
3728 }
3729
rtl8168ep_2_hw_phy_config(struct rtl8169_private * tp)3730 static void rtl8168ep_2_hw_phy_config(struct rtl8169_private *tp)
3731 {
3732 /* patch 10M & ALDPS */
3733 rtl_writephy(tp, 0x1f, 0x0bcc);
3734 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0100);
3735 rtl_writephy(tp, 0x1f, 0x0a44);
3736 rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
3737 rtl_writephy(tp, 0x1f, 0x0a43);
3738 rtl_writephy(tp, 0x13, 0x8084);
3739 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
3740 rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
3741 rtl_writephy(tp, 0x1f, 0x0000);
3742
3743 /* Enable UC LPF tune function */
3744 rtl_writephy(tp, 0x1f, 0x0a43);
3745 rtl_writephy(tp, 0x13, 0x8012);
3746 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3747 rtl_writephy(tp, 0x1f, 0x0000);
3748
3749 /* Set rg_sel_sdm_rate */
3750 rtl_writephy(tp, 0x1f, 0x0c42);
3751 rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
3752 rtl_writephy(tp, 0x1f, 0x0000);
3753
3754 /* Channel estimation parameters */
3755 rtl_writephy(tp, 0x1f, 0x0a43);
3756 rtl_writephy(tp, 0x13, 0x80f3);
3757 rtl_w0w1_phy(tp, 0x14, 0x8b00, ~0x8bff);
3758 rtl_writephy(tp, 0x13, 0x80f0);
3759 rtl_w0w1_phy(tp, 0x14, 0x3a00, ~0x3aff);
3760 rtl_writephy(tp, 0x13, 0x80ef);
3761 rtl_w0w1_phy(tp, 0x14, 0x0500, ~0x05ff);
3762 rtl_writephy(tp, 0x13, 0x80f6);
3763 rtl_w0w1_phy(tp, 0x14, 0x6e00, ~0x6eff);
3764 rtl_writephy(tp, 0x13, 0x80ec);
3765 rtl_w0w1_phy(tp, 0x14, 0x6800, ~0x68ff);
3766 rtl_writephy(tp, 0x13, 0x80ed);
3767 rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
3768 rtl_writephy(tp, 0x13, 0x80f2);
3769 rtl_w0w1_phy(tp, 0x14, 0xf400, ~0xf4ff);
3770 rtl_writephy(tp, 0x13, 0x80f4);
3771 rtl_w0w1_phy(tp, 0x14, 0x8500, ~0x85ff);
3772 rtl_writephy(tp, 0x1f, 0x0a43);
3773 rtl_writephy(tp, 0x13, 0x8110);
3774 rtl_w0w1_phy(tp, 0x14, 0xa800, ~0xa8ff);
3775 rtl_writephy(tp, 0x13, 0x810f);
3776 rtl_w0w1_phy(tp, 0x14, 0x1d00, ~0x1dff);
3777 rtl_writephy(tp, 0x13, 0x8111);
3778 rtl_w0w1_phy(tp, 0x14, 0xf500, ~0xf5ff);
3779 rtl_writephy(tp, 0x13, 0x8113);
3780 rtl_w0w1_phy(tp, 0x14, 0x6100, ~0x61ff);
3781 rtl_writephy(tp, 0x13, 0x8115);
3782 rtl_w0w1_phy(tp, 0x14, 0x9200, ~0x92ff);
3783 rtl_writephy(tp, 0x13, 0x810e);
3784 rtl_w0w1_phy(tp, 0x14, 0x0400, ~0x04ff);
3785 rtl_writephy(tp, 0x13, 0x810c);
3786 rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
3787 rtl_writephy(tp, 0x13, 0x810b);
3788 rtl_w0w1_phy(tp, 0x14, 0x5a00, ~0x5aff);
3789 rtl_writephy(tp, 0x1f, 0x0a43);
3790 rtl_writephy(tp, 0x13, 0x80d1);
3791 rtl_w0w1_phy(tp, 0x14, 0xff00, ~0xffff);
3792 rtl_writephy(tp, 0x13, 0x80cd);
3793 rtl_w0w1_phy(tp, 0x14, 0x9e00, ~0x9eff);
3794 rtl_writephy(tp, 0x13, 0x80d3);
3795 rtl_w0w1_phy(tp, 0x14, 0x0e00, ~0x0eff);
3796 rtl_writephy(tp, 0x13, 0x80d5);
3797 rtl_w0w1_phy(tp, 0x14, 0xca00, ~0xcaff);
3798 rtl_writephy(tp, 0x13, 0x80d7);
3799 rtl_w0w1_phy(tp, 0x14, 0x8400, ~0x84ff);
3800
3801 /* Force PWM-mode */
3802 rtl_writephy(tp, 0x1f, 0x0bcd);
3803 rtl_writephy(tp, 0x14, 0x5065);
3804 rtl_writephy(tp, 0x14, 0xd065);
3805 rtl_writephy(tp, 0x1f, 0x0bc8);
3806 rtl_writephy(tp, 0x12, 0x00ed);
3807 rtl_writephy(tp, 0x1f, 0x0bcd);
3808 rtl_writephy(tp, 0x14, 0x1065);
3809 rtl_writephy(tp, 0x14, 0x9065);
3810 rtl_writephy(tp, 0x14, 0x1065);
3811 rtl_writephy(tp, 0x1f, 0x0000);
3812
3813 /* Check ALDPS bit, disable it if enabled */
3814 rtl_writephy(tp, 0x1f, 0x0a43);
3815 if (rtl_readphy(tp, 0x10) & 0x0004)
3816 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3817
3818 rtl_writephy(tp, 0x1f, 0x0000);
3819 }
3820
rtl8102e_hw_phy_config(struct rtl8169_private * tp)3821 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
3822 {
3823 static const struct phy_reg phy_reg_init[] = {
3824 { 0x1f, 0x0003 },
3825 { 0x08, 0x441d },
3826 { 0x01, 0x9100 },
3827 { 0x1f, 0x0000 }
3828 };
3829
3830 rtl_writephy(tp, 0x1f, 0x0000);
3831 rtl_patchphy(tp, 0x11, 1 << 12);
3832 rtl_patchphy(tp, 0x19, 1 << 13);
3833 rtl_patchphy(tp, 0x10, 1 << 15);
3834
3835 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3836 }
3837
rtl8105e_hw_phy_config(struct rtl8169_private * tp)3838 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
3839 {
3840 static const struct phy_reg phy_reg_init[] = {
3841 { 0x1f, 0x0005 },
3842 { 0x1a, 0x0000 },
3843 { 0x1f, 0x0000 },
3844
3845 { 0x1f, 0x0004 },
3846 { 0x1c, 0x0000 },
3847 { 0x1f, 0x0000 },
3848
3849 { 0x1f, 0x0001 },
3850 { 0x15, 0x7701 },
3851 { 0x1f, 0x0000 }
3852 };
3853
3854 /* Disable ALDPS before ram code */
3855 rtl_writephy(tp, 0x1f, 0x0000);
3856 rtl_writephy(tp, 0x18, 0x0310);
3857 msleep(100);
3858
3859 rtl_apply_firmware(tp);
3860
3861 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3862 }
3863
rtl8402_hw_phy_config(struct rtl8169_private * tp)3864 static void rtl8402_hw_phy_config(struct rtl8169_private *tp)
3865 {
3866 /* Disable ALDPS before setting firmware */
3867 rtl_writephy(tp, 0x1f, 0x0000);
3868 rtl_writephy(tp, 0x18, 0x0310);
3869 msleep(20);
3870
3871 rtl_apply_firmware(tp);
3872
3873 /* EEE setting */
3874 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
3875 rtl_writephy(tp, 0x1f, 0x0004);
3876 rtl_writephy(tp, 0x10, 0x401f);
3877 rtl_writephy(tp, 0x19, 0x7030);
3878 rtl_writephy(tp, 0x1f, 0x0000);
3879 }
3880
rtl8106e_hw_phy_config(struct rtl8169_private * tp)3881 static void rtl8106e_hw_phy_config(struct rtl8169_private *tp)
3882 {
3883 static const struct phy_reg phy_reg_init[] = {
3884 { 0x1f, 0x0004 },
3885 { 0x10, 0xc07f },
3886 { 0x19, 0x7030 },
3887 { 0x1f, 0x0000 }
3888 };
3889
3890 /* Disable ALDPS before ram code */
3891 rtl_writephy(tp, 0x1f, 0x0000);
3892 rtl_writephy(tp, 0x18, 0x0310);
3893 msleep(100);
3894
3895 rtl_apply_firmware(tp);
3896
3897 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
3898 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3899
3900 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
3901 }
3902
rtl_hw_phy_config(struct net_device * dev)3903 static void rtl_hw_phy_config(struct net_device *dev)
3904 {
3905 struct rtl8169_private *tp = netdev_priv(dev);
3906
3907 rtl8169_print_mac_version(tp);
3908
3909 switch (tp->mac_version) {
3910 case RTL_GIGA_MAC_VER_01:
3911 break;
3912 case RTL_GIGA_MAC_VER_02:
3913 case RTL_GIGA_MAC_VER_03:
3914 rtl8169s_hw_phy_config(tp);
3915 break;
3916 case RTL_GIGA_MAC_VER_04:
3917 rtl8169sb_hw_phy_config(tp);
3918 break;
3919 case RTL_GIGA_MAC_VER_05:
3920 rtl8169scd_hw_phy_config(tp);
3921 break;
3922 case RTL_GIGA_MAC_VER_06:
3923 rtl8169sce_hw_phy_config(tp);
3924 break;
3925 case RTL_GIGA_MAC_VER_07:
3926 case RTL_GIGA_MAC_VER_08:
3927 case RTL_GIGA_MAC_VER_09:
3928 rtl8102e_hw_phy_config(tp);
3929 break;
3930 case RTL_GIGA_MAC_VER_11:
3931 rtl8168bb_hw_phy_config(tp);
3932 break;
3933 case RTL_GIGA_MAC_VER_12:
3934 rtl8168bef_hw_phy_config(tp);
3935 break;
3936 case RTL_GIGA_MAC_VER_17:
3937 rtl8168bef_hw_phy_config(tp);
3938 break;
3939 case RTL_GIGA_MAC_VER_18:
3940 rtl8168cp_1_hw_phy_config(tp);
3941 break;
3942 case RTL_GIGA_MAC_VER_19:
3943 rtl8168c_1_hw_phy_config(tp);
3944 break;
3945 case RTL_GIGA_MAC_VER_20:
3946 rtl8168c_2_hw_phy_config(tp);
3947 break;
3948 case RTL_GIGA_MAC_VER_21:
3949 rtl8168c_3_hw_phy_config(tp);
3950 break;
3951 case RTL_GIGA_MAC_VER_22:
3952 rtl8168c_4_hw_phy_config(tp);
3953 break;
3954 case RTL_GIGA_MAC_VER_23:
3955 case RTL_GIGA_MAC_VER_24:
3956 rtl8168cp_2_hw_phy_config(tp);
3957 break;
3958 case RTL_GIGA_MAC_VER_25:
3959 rtl8168d_1_hw_phy_config(tp);
3960 break;
3961 case RTL_GIGA_MAC_VER_26:
3962 rtl8168d_2_hw_phy_config(tp);
3963 break;
3964 case RTL_GIGA_MAC_VER_27:
3965 rtl8168d_3_hw_phy_config(tp);
3966 break;
3967 case RTL_GIGA_MAC_VER_28:
3968 rtl8168d_4_hw_phy_config(tp);
3969 break;
3970 case RTL_GIGA_MAC_VER_29:
3971 case RTL_GIGA_MAC_VER_30:
3972 rtl8105e_hw_phy_config(tp);
3973 break;
3974 case RTL_GIGA_MAC_VER_31:
3975 /* None. */
3976 break;
3977 case RTL_GIGA_MAC_VER_32:
3978 case RTL_GIGA_MAC_VER_33:
3979 rtl8168e_1_hw_phy_config(tp);
3980 break;
3981 case RTL_GIGA_MAC_VER_34:
3982 rtl8168e_2_hw_phy_config(tp);
3983 break;
3984 case RTL_GIGA_MAC_VER_35:
3985 rtl8168f_1_hw_phy_config(tp);
3986 break;
3987 case RTL_GIGA_MAC_VER_36:
3988 rtl8168f_2_hw_phy_config(tp);
3989 break;
3990
3991 case RTL_GIGA_MAC_VER_37:
3992 rtl8402_hw_phy_config(tp);
3993 break;
3994
3995 case RTL_GIGA_MAC_VER_38:
3996 rtl8411_hw_phy_config(tp);
3997 break;
3998
3999 case RTL_GIGA_MAC_VER_39:
4000 rtl8106e_hw_phy_config(tp);
4001 break;
4002
4003 case RTL_GIGA_MAC_VER_40:
4004 rtl8168g_1_hw_phy_config(tp);
4005 break;
4006 case RTL_GIGA_MAC_VER_42:
4007 case RTL_GIGA_MAC_VER_43:
4008 case RTL_GIGA_MAC_VER_44:
4009 rtl8168g_2_hw_phy_config(tp);
4010 break;
4011 case RTL_GIGA_MAC_VER_45:
4012 case RTL_GIGA_MAC_VER_47:
4013 rtl8168h_1_hw_phy_config(tp);
4014 break;
4015 case RTL_GIGA_MAC_VER_46:
4016 case RTL_GIGA_MAC_VER_48:
4017 rtl8168h_2_hw_phy_config(tp);
4018 break;
4019
4020 case RTL_GIGA_MAC_VER_49:
4021 rtl8168ep_1_hw_phy_config(tp);
4022 break;
4023 case RTL_GIGA_MAC_VER_50:
4024 case RTL_GIGA_MAC_VER_51:
4025 rtl8168ep_2_hw_phy_config(tp);
4026 break;
4027
4028 case RTL_GIGA_MAC_VER_41:
4029 default:
4030 break;
4031 }
4032 }
4033
rtl_schedule_task(struct rtl8169_private * tp,enum rtl_flag flag)4034 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
4035 {
4036 if (!test_and_set_bit(flag, tp->wk.flags))
4037 schedule_work(&tp->wk.work);
4038 }
4039
rtl_tbi_enabled(struct rtl8169_private * tp)4040 static bool rtl_tbi_enabled(struct rtl8169_private *tp)
4041 {
4042 return (tp->mac_version == RTL_GIGA_MAC_VER_01) &&
4043 (RTL_R8(tp, PHYstatus) & TBI_Enable);
4044 }
4045
rtl8169_init_phy(struct net_device * dev,struct rtl8169_private * tp)4046 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
4047 {
4048 rtl_hw_phy_config(dev);
4049
4050 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
4051 netif_dbg(tp, drv, dev,
4052 "Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
4053 RTL_W8(tp, 0x82, 0x01);
4054 }
4055
4056 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
4057
4058 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
4059 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4060
4061 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
4062 netif_dbg(tp, drv, dev,
4063 "Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
4064 RTL_W8(tp, 0x82, 0x01);
4065 netif_dbg(tp, drv, dev,
4066 "Set PHY Reg 0x0bh = 0x00h\n");
4067 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
4068 }
4069
4070 /* We may have called phy_speed_down before */
4071 phy_speed_up(dev->phydev);
4072
4073 genphy_soft_reset(dev->phydev);
4074
4075 /* It was reported that several chips end up with 10MBit/Half on a
4076 * 1GBit link after resuming from S3. For whatever reason the PHY on
4077 * these chips doesn't properly start a renegotiation when soft-reset.
4078 * Explicitly requesting a renegotiation fixes this.
4079 */
4080 if (dev->phydev->autoneg == AUTONEG_ENABLE)
4081 phy_restart_aneg(dev->phydev);
4082 }
4083
rtl_rar_set(struct rtl8169_private * tp,u8 * addr)4084 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
4085 {
4086 rtl_lock_work(tp);
4087
4088 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
4089
4090 RTL_W32(tp, MAC4, addr[4] | addr[5] << 8);
4091 RTL_R32(tp, MAC4);
4092
4093 RTL_W32(tp, MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24);
4094 RTL_R32(tp, MAC0);
4095
4096 if (tp->mac_version == RTL_GIGA_MAC_VER_34)
4097 rtl_rar_exgmac_set(tp, addr);
4098
4099 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
4100
4101 rtl_unlock_work(tp);
4102 }
4103
rtl_set_mac_address(struct net_device * dev,void * p)4104 static int rtl_set_mac_address(struct net_device *dev, void *p)
4105 {
4106 struct rtl8169_private *tp = netdev_priv(dev);
4107 struct device *d = tp_to_dev(tp);
4108 int ret;
4109
4110 ret = eth_mac_addr(dev, p);
4111 if (ret)
4112 return ret;
4113
4114 pm_runtime_get_noresume(d);
4115
4116 if (pm_runtime_active(d))
4117 rtl_rar_set(tp, dev->dev_addr);
4118
4119 pm_runtime_put_noidle(d);
4120
4121 return 0;
4122 }
4123
rtl8169_ioctl(struct net_device * dev,struct ifreq * ifr,int cmd)4124 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4125 {
4126 if (!netif_running(dev))
4127 return -ENODEV;
4128
4129 return phy_mii_ioctl(dev->phydev, ifr, cmd);
4130 }
4131
rtl_init_mdio_ops(struct rtl8169_private * tp)4132 static void rtl_init_mdio_ops(struct rtl8169_private *tp)
4133 {
4134 struct mdio_ops *ops = &tp->mdio_ops;
4135
4136 switch (tp->mac_version) {
4137 case RTL_GIGA_MAC_VER_27:
4138 ops->write = r8168dp_1_mdio_write;
4139 ops->read = r8168dp_1_mdio_read;
4140 break;
4141 case RTL_GIGA_MAC_VER_28:
4142 case RTL_GIGA_MAC_VER_31:
4143 ops->write = r8168dp_2_mdio_write;
4144 ops->read = r8168dp_2_mdio_read;
4145 break;
4146 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
4147 ops->write = r8168g_mdio_write;
4148 ops->read = r8168g_mdio_read;
4149 break;
4150 default:
4151 ops->write = r8169_mdio_write;
4152 ops->read = r8169_mdio_read;
4153 break;
4154 }
4155 }
4156
rtl_wol_suspend_quirk(struct rtl8169_private * tp)4157 static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
4158 {
4159 switch (tp->mac_version) {
4160 case RTL_GIGA_MAC_VER_25:
4161 case RTL_GIGA_MAC_VER_26:
4162 case RTL_GIGA_MAC_VER_29:
4163 case RTL_GIGA_MAC_VER_30:
4164 case RTL_GIGA_MAC_VER_32:
4165 case RTL_GIGA_MAC_VER_33:
4166 case RTL_GIGA_MAC_VER_34:
4167 case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_51:
4168 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) |
4169 AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
4170 break;
4171 default:
4172 break;
4173 }
4174 }
4175
rtl_wol_pll_power_down(struct rtl8169_private * tp)4176 static bool rtl_wol_pll_power_down(struct rtl8169_private *tp)
4177 {
4178 if (!netif_running(tp->dev) || !__rtl8169_get_wol(tp))
4179 return false;
4180
4181 phy_speed_down(tp->dev->phydev, false);
4182 rtl_wol_suspend_quirk(tp);
4183
4184 return true;
4185 }
4186
r8168_pll_power_down(struct rtl8169_private * tp)4187 static void r8168_pll_power_down(struct rtl8169_private *tp)
4188 {
4189 if (r8168_check_dash(tp))
4190 return;
4191
4192 if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
4193 tp->mac_version == RTL_GIGA_MAC_VER_33)
4194 rtl_ephy_write(tp, 0x19, 0xff64);
4195
4196 if (rtl_wol_pll_power_down(tp))
4197 return;
4198
4199 switch (tp->mac_version) {
4200 case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33:
4201 case RTL_GIGA_MAC_VER_37:
4202 case RTL_GIGA_MAC_VER_39:
4203 case RTL_GIGA_MAC_VER_43:
4204 case RTL_GIGA_MAC_VER_44:
4205 case RTL_GIGA_MAC_VER_45:
4206 case RTL_GIGA_MAC_VER_46:
4207 case RTL_GIGA_MAC_VER_47:
4208 case RTL_GIGA_MAC_VER_48:
4209 case RTL_GIGA_MAC_VER_50:
4210 case RTL_GIGA_MAC_VER_51:
4211 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
4212 break;
4213 case RTL_GIGA_MAC_VER_40:
4214 case RTL_GIGA_MAC_VER_41:
4215 case RTL_GIGA_MAC_VER_49:
4216 rtl_w0w1_eri(tp, 0x1a8, ERIAR_MASK_1111, 0x00000000,
4217 0xfc000000, ERIAR_EXGMAC);
4218 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
4219 break;
4220 }
4221 }
4222
r8168_pll_power_up(struct rtl8169_private * tp)4223 static void r8168_pll_power_up(struct rtl8169_private *tp)
4224 {
4225 switch (tp->mac_version) {
4226 case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33:
4227 case RTL_GIGA_MAC_VER_37:
4228 case RTL_GIGA_MAC_VER_39:
4229 case RTL_GIGA_MAC_VER_43:
4230 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0x80);
4231 break;
4232 case RTL_GIGA_MAC_VER_44:
4233 case RTL_GIGA_MAC_VER_45:
4234 case RTL_GIGA_MAC_VER_46:
4235 case RTL_GIGA_MAC_VER_47:
4236 case RTL_GIGA_MAC_VER_48:
4237 case RTL_GIGA_MAC_VER_50:
4238 case RTL_GIGA_MAC_VER_51:
4239 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
4240 break;
4241 case RTL_GIGA_MAC_VER_40:
4242 case RTL_GIGA_MAC_VER_41:
4243 case RTL_GIGA_MAC_VER_49:
4244 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
4245 rtl_w0w1_eri(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000,
4246 0x00000000, ERIAR_EXGMAC);
4247 break;
4248 }
4249
4250 phy_resume(tp->dev->phydev);
4251 /* give MAC/PHY some time to resume */
4252 msleep(20);
4253 }
4254
rtl_pll_power_down(struct rtl8169_private * tp)4255 static void rtl_pll_power_down(struct rtl8169_private *tp)
4256 {
4257 switch (tp->mac_version) {
4258 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
4259 case RTL_GIGA_MAC_VER_13 ... RTL_GIGA_MAC_VER_15:
4260 break;
4261 default:
4262 r8168_pll_power_down(tp);
4263 }
4264 }
4265
rtl_pll_power_up(struct rtl8169_private * tp)4266 static void rtl_pll_power_up(struct rtl8169_private *tp)
4267 {
4268 switch (tp->mac_version) {
4269 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
4270 case RTL_GIGA_MAC_VER_13 ... RTL_GIGA_MAC_VER_15:
4271 break;
4272 default:
4273 r8168_pll_power_up(tp);
4274 }
4275 }
4276
rtl_init_rxcfg(struct rtl8169_private * tp)4277 static void rtl_init_rxcfg(struct rtl8169_private *tp)
4278 {
4279 switch (tp->mac_version) {
4280 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
4281 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
4282 RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
4283 break;
4284 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
4285 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36:
4286 case RTL_GIGA_MAC_VER_38:
4287 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
4288 break;
4289 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
4290 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);
4291 break;
4292 default:
4293 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST);
4294 break;
4295 }
4296 }
4297
rtl8169_init_ring_indexes(struct rtl8169_private * tp)4298 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4299 {
4300 tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
4301 }
4302
rtl_hw_jumbo_enable(struct rtl8169_private * tp)4303 static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
4304 {
4305 if (tp->jumbo_ops.enable) {
4306 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
4307 tp->jumbo_ops.enable(tp);
4308 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
4309 }
4310 }
4311
rtl_hw_jumbo_disable(struct rtl8169_private * tp)4312 static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
4313 {
4314 if (tp->jumbo_ops.disable) {
4315 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
4316 tp->jumbo_ops.disable(tp);
4317 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
4318 }
4319 }
4320
r8168c_hw_jumbo_enable(struct rtl8169_private * tp)4321 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
4322 {
4323 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
4324 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1);
4325 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_512B);
4326 }
4327
r8168c_hw_jumbo_disable(struct rtl8169_private * tp)4328 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
4329 {
4330 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
4331 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1);
4332 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4333 }
4334
r8168dp_hw_jumbo_enable(struct rtl8169_private * tp)4335 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
4336 {
4337 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
4338 }
4339
r8168dp_hw_jumbo_disable(struct rtl8169_private * tp)4340 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
4341 {
4342 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
4343 }
4344
r8168e_hw_jumbo_enable(struct rtl8169_private * tp)4345 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
4346 {
4347 RTL_W8(tp, MaxTxPacketSize, 0x3f);
4348 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
4349 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01);
4350 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_512B);
4351 }
4352
r8168e_hw_jumbo_disable(struct rtl8169_private * tp)4353 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
4354 {
4355 RTL_W8(tp, MaxTxPacketSize, 0x0c);
4356 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
4357 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01);
4358 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4359 }
4360
r8168b_0_hw_jumbo_enable(struct rtl8169_private * tp)4361 static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
4362 {
4363 rtl_tx_performance_tweak(tp,
4364 PCI_EXP_DEVCTL_READRQ_512B | PCI_EXP_DEVCTL_NOSNOOP_EN);
4365 }
4366
r8168b_0_hw_jumbo_disable(struct rtl8169_private * tp)4367 static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
4368 {
4369 rtl_tx_performance_tweak(tp,
4370 PCI_EXP_DEVCTL_READRQ_4096B | PCI_EXP_DEVCTL_NOSNOOP_EN);
4371 }
4372
r8168b_1_hw_jumbo_enable(struct rtl8169_private * tp)4373 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
4374 {
4375 r8168b_0_hw_jumbo_enable(tp);
4376
4377 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0));
4378 }
4379
r8168b_1_hw_jumbo_disable(struct rtl8169_private * tp)4380 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
4381 {
4382 r8168b_0_hw_jumbo_disable(tp);
4383
4384 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
4385 }
4386
rtl_init_jumbo_ops(struct rtl8169_private * tp)4387 static void rtl_init_jumbo_ops(struct rtl8169_private *tp)
4388 {
4389 struct jumbo_ops *ops = &tp->jumbo_ops;
4390
4391 switch (tp->mac_version) {
4392 case RTL_GIGA_MAC_VER_11:
4393 ops->disable = r8168b_0_hw_jumbo_disable;
4394 ops->enable = r8168b_0_hw_jumbo_enable;
4395 break;
4396 case RTL_GIGA_MAC_VER_12:
4397 case RTL_GIGA_MAC_VER_17:
4398 ops->disable = r8168b_1_hw_jumbo_disable;
4399 ops->enable = r8168b_1_hw_jumbo_enable;
4400 break;
4401 case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */
4402 case RTL_GIGA_MAC_VER_19:
4403 case RTL_GIGA_MAC_VER_20:
4404 case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */
4405 case RTL_GIGA_MAC_VER_22:
4406 case RTL_GIGA_MAC_VER_23:
4407 case RTL_GIGA_MAC_VER_24:
4408 case RTL_GIGA_MAC_VER_25:
4409 case RTL_GIGA_MAC_VER_26:
4410 ops->disable = r8168c_hw_jumbo_disable;
4411 ops->enable = r8168c_hw_jumbo_enable;
4412 break;
4413 case RTL_GIGA_MAC_VER_27:
4414 case RTL_GIGA_MAC_VER_28:
4415 ops->disable = r8168dp_hw_jumbo_disable;
4416 ops->enable = r8168dp_hw_jumbo_enable;
4417 break;
4418 case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */
4419 case RTL_GIGA_MAC_VER_32:
4420 case RTL_GIGA_MAC_VER_33:
4421 case RTL_GIGA_MAC_VER_34:
4422 ops->disable = r8168e_hw_jumbo_disable;
4423 ops->enable = r8168e_hw_jumbo_enable;
4424 break;
4425
4426 /*
4427 * No action needed for jumbo frames with 8169.
4428 * No jumbo for 810x at all.
4429 */
4430 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
4431 default:
4432 ops->disable = NULL;
4433 ops->enable = NULL;
4434 break;
4435 }
4436 }
4437
DECLARE_RTL_COND(rtl_chipcmd_cond)4438 DECLARE_RTL_COND(rtl_chipcmd_cond)
4439 {
4440 return RTL_R8(tp, ChipCmd) & CmdReset;
4441 }
4442
rtl_hw_reset(struct rtl8169_private * tp)4443 static void rtl_hw_reset(struct rtl8169_private *tp)
4444 {
4445 RTL_W8(tp, ChipCmd, CmdReset);
4446
4447 rtl_udelay_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
4448 }
4449
rtl_request_uncached_firmware(struct rtl8169_private * tp)4450 static void rtl_request_uncached_firmware(struct rtl8169_private *tp)
4451 {
4452 struct rtl_fw *rtl_fw;
4453 const char *name;
4454 int rc = -ENOMEM;
4455
4456 name = rtl_lookup_firmware_name(tp);
4457 if (!name)
4458 goto out_no_firmware;
4459
4460 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
4461 if (!rtl_fw)
4462 goto err_warn;
4463
4464 rc = request_firmware(&rtl_fw->fw, name, tp_to_dev(tp));
4465 if (rc < 0)
4466 goto err_free;
4467
4468 rc = rtl_check_firmware(tp, rtl_fw);
4469 if (rc < 0)
4470 goto err_release_firmware;
4471
4472 tp->rtl_fw = rtl_fw;
4473 out:
4474 return;
4475
4476 err_release_firmware:
4477 release_firmware(rtl_fw->fw);
4478 err_free:
4479 kfree(rtl_fw);
4480 err_warn:
4481 netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
4482 name, rc);
4483 out_no_firmware:
4484 tp->rtl_fw = NULL;
4485 goto out;
4486 }
4487
rtl_request_firmware(struct rtl8169_private * tp)4488 static void rtl_request_firmware(struct rtl8169_private *tp)
4489 {
4490 if (IS_ERR(tp->rtl_fw))
4491 rtl_request_uncached_firmware(tp);
4492 }
4493
rtl_rx_close(struct rtl8169_private * tp)4494 static void rtl_rx_close(struct rtl8169_private *tp)
4495 {
4496 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
4497 }
4498
DECLARE_RTL_COND(rtl_npq_cond)4499 DECLARE_RTL_COND(rtl_npq_cond)
4500 {
4501 return RTL_R8(tp, TxPoll) & NPQ;
4502 }
4503
DECLARE_RTL_COND(rtl_txcfg_empty_cond)4504 DECLARE_RTL_COND(rtl_txcfg_empty_cond)
4505 {
4506 return RTL_R32(tp, TxConfig) & TXCFG_EMPTY;
4507 }
4508
rtl8169_hw_reset(struct rtl8169_private * tp)4509 static void rtl8169_hw_reset(struct rtl8169_private *tp)
4510 {
4511 /* Disable interrupts */
4512 rtl8169_irq_mask_and_ack(tp);
4513
4514 rtl_rx_close(tp);
4515
4516 switch (tp->mac_version) {
4517 case RTL_GIGA_MAC_VER_27:
4518 case RTL_GIGA_MAC_VER_28:
4519 case RTL_GIGA_MAC_VER_31:
4520 rtl_udelay_loop_wait_low(tp, &rtl_npq_cond, 20, 42*42);
4521 break;
4522 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
4523 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
4524 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
4525 rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
4526 break;
4527 default:
4528 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
4529 udelay(100);
4530 break;
4531 }
4532
4533 rtl_hw_reset(tp);
4534 }
4535
rtl_set_tx_config_registers(struct rtl8169_private * tp)4536 static void rtl_set_tx_config_registers(struct rtl8169_private *tp)
4537 {
4538 u32 val = TX_DMA_BURST << TxDMAShift |
4539 InterFrameGap << TxInterFrameGapShift;
4540
4541 if (tp->mac_version >= RTL_GIGA_MAC_VER_34 &&
4542 tp->mac_version != RTL_GIGA_MAC_VER_39)
4543 val |= TXCFG_AUTO_FIFO;
4544
4545 RTL_W32(tp, TxConfig, val);
4546 }
4547
rtl_set_rx_max_size(struct rtl8169_private * tp)4548 static void rtl_set_rx_max_size(struct rtl8169_private *tp)
4549 {
4550 /* Low hurts. Let's disable the filtering. */
4551 RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1);
4552 }
4553
rtl_set_rx_tx_desc_registers(struct rtl8169_private * tp)4554 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp)
4555 {
4556 /*
4557 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
4558 * register to be written before TxDescAddrLow to work.
4559 * Switching from MMIO to I/O access fixes the issue as well.
4560 */
4561 RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
4562 RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
4563 RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
4564 RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
4565 }
4566
rtl8169_set_magic_reg(struct rtl8169_private * tp,unsigned mac_version)4567 static void rtl8169_set_magic_reg(struct rtl8169_private *tp, unsigned mac_version)
4568 {
4569 static const struct rtl_cfg2_info {
4570 u32 mac_version;
4571 u32 clk;
4572 u32 val;
4573 } cfg2_info [] = {
4574 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
4575 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
4576 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
4577 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
4578 };
4579 const struct rtl_cfg2_info *p = cfg2_info;
4580 unsigned int i;
4581 u32 clk;
4582
4583 clk = RTL_R8(tp, Config2) & PCI_Clock_66MHz;
4584 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
4585 if ((p->mac_version == mac_version) && (p->clk == clk)) {
4586 RTL_W32(tp, 0x7c, p->val);
4587 break;
4588 }
4589 }
4590 }
4591
rtl_set_rx_mode(struct net_device * dev)4592 static void rtl_set_rx_mode(struct net_device *dev)
4593 {
4594 struct rtl8169_private *tp = netdev_priv(dev);
4595 u32 mc_filter[2]; /* Multicast hash filter */
4596 int rx_mode;
4597 u32 tmp = 0;
4598
4599 if (dev->flags & IFF_PROMISC) {
4600 /* Unconditionally log net taps. */
4601 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
4602 rx_mode =
4603 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
4604 AcceptAllPhys;
4605 mc_filter[1] = mc_filter[0] = 0xffffffff;
4606 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
4607 (dev->flags & IFF_ALLMULTI)) {
4608 /* Too many to filter perfectly -- accept all multicasts. */
4609 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
4610 mc_filter[1] = mc_filter[0] = 0xffffffff;
4611 } else {
4612 struct netdev_hw_addr *ha;
4613
4614 rx_mode = AcceptBroadcast | AcceptMyPhys;
4615 mc_filter[1] = mc_filter[0] = 0;
4616 netdev_for_each_mc_addr(ha, dev) {
4617 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
4618 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
4619 rx_mode |= AcceptMulticast;
4620 }
4621 }
4622
4623 if (dev->features & NETIF_F_RXALL)
4624 rx_mode |= (AcceptErr | AcceptRunt);
4625
4626 tmp = (RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
4627
4628 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
4629 u32 data = mc_filter[0];
4630
4631 mc_filter[0] = swab32(mc_filter[1]);
4632 mc_filter[1] = swab32(data);
4633 }
4634
4635 if (tp->mac_version == RTL_GIGA_MAC_VER_35)
4636 mc_filter[1] = mc_filter[0] = 0xffffffff;
4637
4638 RTL_W32(tp, MAR0 + 4, mc_filter[1]);
4639 RTL_W32(tp, MAR0 + 0, mc_filter[0]);
4640
4641 RTL_W32(tp, RxConfig, tmp);
4642 }
4643
rtl_hw_start(struct rtl8169_private * tp)4644 static void rtl_hw_start(struct rtl8169_private *tp)
4645 {
4646 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
4647
4648 tp->hw_start(tp);
4649
4650 rtl_set_rx_max_size(tp);
4651 rtl_set_rx_tx_desc_registers(tp);
4652 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
4653
4654 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
4655 RTL_R8(tp, IntrMask);
4656 RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb);
4657 rtl_init_rxcfg(tp);
4658 rtl_set_tx_config_registers(tp);
4659
4660 rtl_set_rx_mode(tp->dev);
4661 /* no early-rx interrupts */
4662 RTL_W16(tp, MultiIntr, RTL_R16(tp, MultiIntr) & 0xf000);
4663 rtl_irq_enable_all(tp);
4664 }
4665
rtl_hw_start_8169(struct rtl8169_private * tp)4666 static void rtl_hw_start_8169(struct rtl8169_private *tp)
4667 {
4668 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
4669 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4670
4671 RTL_W8(tp, EarlyTxThres, NoEarlyTx);
4672
4673 tp->cp_cmd |= PCIMulRW;
4674
4675 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4676 tp->mac_version == RTL_GIGA_MAC_VER_03) {
4677 netif_dbg(tp, drv, tp->dev,
4678 "Set MAC Reg C+CR Offset 0xe0. Bit 3 and Bit 14 MUST be 1\n");
4679 tp->cp_cmd |= (1 << 14);
4680 }
4681
4682 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4683
4684 rtl8169_set_magic_reg(tp, tp->mac_version);
4685
4686 /*
4687 * Undocumented corner. Supposedly:
4688 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
4689 */
4690 RTL_W16(tp, IntrMitigate, 0x0000);
4691
4692 RTL_W32(tp, RxMissed, 0);
4693 }
4694
DECLARE_RTL_COND(rtl_csiar_cond)4695 DECLARE_RTL_COND(rtl_csiar_cond)
4696 {
4697 return RTL_R32(tp, CSIAR) & CSIAR_FLAG;
4698 }
4699
rtl_csi_write(struct rtl8169_private * tp,int addr,int value)4700 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
4701 {
4702 u32 func = PCI_FUNC(tp->pci_dev->devfn);
4703
4704 RTL_W32(tp, CSIDR, value);
4705 RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
4706 CSIAR_BYTE_ENABLE | func << 16);
4707
4708 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
4709 }
4710
rtl_csi_read(struct rtl8169_private * tp,int addr)4711 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
4712 {
4713 u32 func = PCI_FUNC(tp->pci_dev->devfn);
4714
4715 RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 |
4716 CSIAR_BYTE_ENABLE);
4717
4718 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
4719 RTL_R32(tp, CSIDR) : ~0;
4720 }
4721
rtl_csi_access_enable(struct rtl8169_private * tp,u8 val)4722 static void rtl_csi_access_enable(struct rtl8169_private *tp, u8 val)
4723 {
4724 struct pci_dev *pdev = tp->pci_dev;
4725 u32 csi;
4726
4727 /* According to Realtek the value at config space address 0x070f
4728 * controls the L0s/L1 entrance latency. We try standard ECAM access
4729 * first and if it fails fall back to CSI.
4730 */
4731 if (pdev->cfg_size > 0x070f &&
4732 pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL)
4733 return;
4734
4735 netdev_notice_once(tp->dev,
4736 "No native access to PCI extended config space, falling back to CSI\n");
4737 csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
4738 rtl_csi_write(tp, 0x070c, csi | val << 24);
4739 }
4740
rtl_set_def_aspm_entry_latency(struct rtl8169_private * tp)4741 static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp)
4742 {
4743 rtl_csi_access_enable(tp, 0x27);
4744 }
4745
4746 struct ephy_info {
4747 unsigned int offset;
4748 u16 mask;
4749 u16 bits;
4750 };
4751
rtl_ephy_init(struct rtl8169_private * tp,const struct ephy_info * e,int len)4752 static void rtl_ephy_init(struct rtl8169_private *tp, const struct ephy_info *e,
4753 int len)
4754 {
4755 u16 w;
4756
4757 while (len-- > 0) {
4758 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
4759 rtl_ephy_write(tp, e->offset, w);
4760 e++;
4761 }
4762 }
4763
rtl_disable_clock_request(struct rtl8169_private * tp)4764 static void rtl_disable_clock_request(struct rtl8169_private *tp)
4765 {
4766 pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL,
4767 PCI_EXP_LNKCTL_CLKREQ_EN);
4768 }
4769
rtl_enable_clock_request(struct rtl8169_private * tp)4770 static void rtl_enable_clock_request(struct rtl8169_private *tp)
4771 {
4772 pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL,
4773 PCI_EXP_LNKCTL_CLKREQ_EN);
4774 }
4775
rtl_pcie_state_l2l3_enable(struct rtl8169_private * tp,bool enable)4776 static void rtl_pcie_state_l2l3_enable(struct rtl8169_private *tp, bool enable)
4777 {
4778 u8 data;
4779
4780 data = RTL_R8(tp, Config3);
4781
4782 if (enable)
4783 data |= Rdy_to_L23;
4784 else
4785 data &= ~Rdy_to_L23;
4786
4787 RTL_W8(tp, Config3, data);
4788 }
4789
rtl_hw_aspm_clkreq_enable(struct rtl8169_private * tp,bool enable)4790 static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable)
4791 {
4792 if (enable) {
4793 RTL_W8(tp, Config5, RTL_R8(tp, Config5) | ASPM_en);
4794 RTL_W8(tp, Config2, RTL_R8(tp, Config2) | ClkReqEn);
4795 } else {
4796 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
4797 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
4798 }
4799
4800 udelay(10);
4801 }
4802
rtl_hw_start_8168bb(struct rtl8169_private * tp)4803 static void rtl_hw_start_8168bb(struct rtl8169_private *tp)
4804 {
4805 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4806
4807 tp->cp_cmd &= CPCMD_QUIRK_MASK;
4808 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4809
4810 if (tp->dev->mtu <= ETH_DATA_LEN) {
4811 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B |
4812 PCI_EXP_DEVCTL_NOSNOOP_EN);
4813 }
4814 }
4815
rtl_hw_start_8168bef(struct rtl8169_private * tp)4816 static void rtl_hw_start_8168bef(struct rtl8169_private *tp)
4817 {
4818 rtl_hw_start_8168bb(tp);
4819
4820 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4821
4822 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
4823 }
4824
__rtl_hw_start_8168cp(struct rtl8169_private * tp)4825 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
4826 {
4827 RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down);
4828
4829 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4830
4831 if (tp->dev->mtu <= ETH_DATA_LEN)
4832 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4833
4834 rtl_disable_clock_request(tp);
4835
4836 tp->cp_cmd &= CPCMD_QUIRK_MASK;
4837 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4838 }
4839
rtl_hw_start_8168cp_1(struct rtl8169_private * tp)4840 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
4841 {
4842 static const struct ephy_info e_info_8168cp[] = {
4843 { 0x01, 0, 0x0001 },
4844 { 0x02, 0x0800, 0x1000 },
4845 { 0x03, 0, 0x0042 },
4846 { 0x06, 0x0080, 0x0000 },
4847 { 0x07, 0, 0x2000 }
4848 };
4849
4850 rtl_set_def_aspm_entry_latency(tp);
4851
4852 rtl_ephy_init(tp, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
4853
4854 __rtl_hw_start_8168cp(tp);
4855 }
4856
rtl_hw_start_8168cp_2(struct rtl8169_private * tp)4857 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
4858 {
4859 rtl_set_def_aspm_entry_latency(tp);
4860
4861 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4862
4863 if (tp->dev->mtu <= ETH_DATA_LEN)
4864 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4865
4866 tp->cp_cmd &= CPCMD_QUIRK_MASK;
4867 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4868 }
4869
rtl_hw_start_8168cp_3(struct rtl8169_private * tp)4870 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
4871 {
4872 rtl_set_def_aspm_entry_latency(tp);
4873
4874 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4875
4876 /* Magic. */
4877 RTL_W8(tp, DBG_REG, 0x20);
4878
4879 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4880
4881 if (tp->dev->mtu <= ETH_DATA_LEN)
4882 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4883
4884 tp->cp_cmd &= CPCMD_QUIRK_MASK;
4885 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4886 }
4887
rtl_hw_start_8168c_1(struct rtl8169_private * tp)4888 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
4889 {
4890 static const struct ephy_info e_info_8168c_1[] = {
4891 { 0x02, 0x0800, 0x1000 },
4892 { 0x03, 0, 0x0002 },
4893 { 0x06, 0x0080, 0x0000 }
4894 };
4895
4896 rtl_set_def_aspm_entry_latency(tp);
4897
4898 RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
4899
4900 rtl_ephy_init(tp, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
4901
4902 __rtl_hw_start_8168cp(tp);
4903 }
4904
rtl_hw_start_8168c_2(struct rtl8169_private * tp)4905 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
4906 {
4907 static const struct ephy_info e_info_8168c_2[] = {
4908 { 0x01, 0, 0x0001 },
4909 { 0x03, 0x0400, 0x0220 }
4910 };
4911
4912 rtl_set_def_aspm_entry_latency(tp);
4913
4914 rtl_ephy_init(tp, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
4915
4916 __rtl_hw_start_8168cp(tp);
4917 }
4918
rtl_hw_start_8168c_3(struct rtl8169_private * tp)4919 static void rtl_hw_start_8168c_3(struct rtl8169_private *tp)
4920 {
4921 rtl_hw_start_8168c_2(tp);
4922 }
4923
rtl_hw_start_8168c_4(struct rtl8169_private * tp)4924 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
4925 {
4926 rtl_set_def_aspm_entry_latency(tp);
4927
4928 __rtl_hw_start_8168cp(tp);
4929 }
4930
rtl_hw_start_8168d(struct rtl8169_private * tp)4931 static void rtl_hw_start_8168d(struct rtl8169_private *tp)
4932 {
4933 rtl_set_def_aspm_entry_latency(tp);
4934
4935 rtl_disable_clock_request(tp);
4936
4937 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4938
4939 if (tp->dev->mtu <= ETH_DATA_LEN)
4940 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4941
4942 tp->cp_cmd &= CPCMD_QUIRK_MASK;
4943 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4944 }
4945
rtl_hw_start_8168dp(struct rtl8169_private * tp)4946 static void rtl_hw_start_8168dp(struct rtl8169_private *tp)
4947 {
4948 rtl_set_def_aspm_entry_latency(tp);
4949
4950 if (tp->dev->mtu <= ETH_DATA_LEN)
4951 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4952
4953 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4954
4955 rtl_disable_clock_request(tp);
4956 }
4957
rtl_hw_start_8168d_4(struct rtl8169_private * tp)4958 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
4959 {
4960 static const struct ephy_info e_info_8168d_4[] = {
4961 { 0x0b, 0x0000, 0x0048 },
4962 { 0x19, 0x0020, 0x0050 },
4963 { 0x0c, 0x0100, 0x0020 }
4964 };
4965
4966 rtl_set_def_aspm_entry_latency(tp);
4967
4968 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4969
4970 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4971
4972 rtl_ephy_init(tp, e_info_8168d_4, ARRAY_SIZE(e_info_8168d_4));
4973
4974 rtl_enable_clock_request(tp);
4975 }
4976
rtl_hw_start_8168e_1(struct rtl8169_private * tp)4977 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
4978 {
4979 static const struct ephy_info e_info_8168e_1[] = {
4980 { 0x00, 0x0200, 0x0100 },
4981 { 0x00, 0x0000, 0x0004 },
4982 { 0x06, 0x0002, 0x0001 },
4983 { 0x06, 0x0000, 0x0030 },
4984 { 0x07, 0x0000, 0x2000 },
4985 { 0x00, 0x0000, 0x0020 },
4986 { 0x03, 0x5800, 0x2000 },
4987 { 0x03, 0x0000, 0x0001 },
4988 { 0x01, 0x0800, 0x1000 },
4989 { 0x07, 0x0000, 0x4000 },
4990 { 0x1e, 0x0000, 0x2000 },
4991 { 0x19, 0xffff, 0xfe6c },
4992 { 0x0a, 0x0000, 0x0040 }
4993 };
4994
4995 rtl_set_def_aspm_entry_latency(tp);
4996
4997 rtl_ephy_init(tp, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));
4998
4999 if (tp->dev->mtu <= ETH_DATA_LEN)
5000 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5001
5002 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
5003
5004 rtl_disable_clock_request(tp);
5005
5006 /* Reset tx FIFO pointer */
5007 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST);
5008 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST);
5009
5010 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
5011 }
5012
rtl_hw_start_8168e_2(struct rtl8169_private * tp)5013 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
5014 {
5015 static const struct ephy_info e_info_8168e_2[] = {
5016 { 0x09, 0x0000, 0x0080 },
5017 { 0x19, 0x0000, 0x0224 }
5018 };
5019
5020 rtl_set_def_aspm_entry_latency(tp);
5021
5022 rtl_ephy_init(tp, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));
5023
5024 if (tp->dev->mtu <= ETH_DATA_LEN)
5025 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5026
5027 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5028 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5029 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5030 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5031 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5032 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC);
5033 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5034 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
5035
5036 RTL_W8(tp, MaxTxPacketSize, EarlySize);
5037
5038 rtl_disable_clock_request(tp);
5039
5040 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5041
5042 /* Adjust EEE LED frequency */
5043 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
5044
5045 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
5046 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
5047 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
5048
5049 rtl_hw_aspm_clkreq_enable(tp, true);
5050 }
5051
rtl_hw_start_8168f(struct rtl8169_private * tp)5052 static void rtl_hw_start_8168f(struct rtl8169_private *tp)
5053 {
5054 rtl_set_def_aspm_entry_latency(tp);
5055
5056 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5057
5058 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5059 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5060 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5061 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5062 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5063 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5064 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5065 rtl_w0w1_eri(tp, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5066 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5067 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC);
5068
5069 RTL_W8(tp, MaxTxPacketSize, EarlySize);
5070
5071 rtl_disable_clock_request(tp);
5072
5073 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5074 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
5075 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
5076 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
5077 }
5078
rtl_hw_start_8168f_1(struct rtl8169_private * tp)5079 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
5080 {
5081 static const struct ephy_info e_info_8168f_1[] = {
5082 { 0x06, 0x00c0, 0x0020 },
5083 { 0x08, 0x0001, 0x0002 },
5084 { 0x09, 0x0000, 0x0080 },
5085 { 0x19, 0x0000, 0x0224 }
5086 };
5087
5088 rtl_hw_start_8168f(tp);
5089
5090 rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
5091
5092 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
5093
5094 /* Adjust EEE LED frequency */
5095 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
5096 }
5097
rtl_hw_start_8411(struct rtl8169_private * tp)5098 static void rtl_hw_start_8411(struct rtl8169_private *tp)
5099 {
5100 static const struct ephy_info e_info_8168f_1[] = {
5101 { 0x06, 0x00c0, 0x0020 },
5102 { 0x0f, 0xffff, 0x5200 },
5103 { 0x1e, 0x0000, 0x4000 },
5104 { 0x19, 0x0000, 0x0224 }
5105 };
5106
5107 rtl_hw_start_8168f(tp);
5108 rtl_pcie_state_l2l3_enable(tp, false);
5109
5110 rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
5111
5112 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0x0000, ERIAR_EXGMAC);
5113 }
5114
rtl_hw_start_8168g(struct rtl8169_private * tp)5115 static void rtl_hw_start_8168g(struct rtl8169_private *tp)
5116 {
5117 rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x080002, ERIAR_EXGMAC);
5118 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
5119 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
5120 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5121
5122 rtl_set_def_aspm_entry_latency(tp);
5123
5124 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5125
5126 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5127 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5128 rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f, ERIAR_EXGMAC);
5129
5130 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
5131 RTL_W8(tp, MaxTxPacketSize, EarlySize);
5132
5133 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5134 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5135
5136 /* Adjust EEE LED frequency */
5137 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
5138
5139 rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
5140 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
5141
5142 rtl_pcie_state_l2l3_enable(tp, false);
5143 }
5144
rtl_hw_start_8168g_1(struct rtl8169_private * tp)5145 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
5146 {
5147 static const struct ephy_info e_info_8168g_1[] = {
5148 { 0x00, 0x0000, 0x0008 },
5149 { 0x0c, 0x37d0, 0x0820 },
5150 { 0x1e, 0x0000, 0x0001 },
5151 { 0x19, 0x8000, 0x0000 }
5152 };
5153
5154 rtl_hw_start_8168g(tp);
5155
5156 /* disable aspm and clock request before access ephy */
5157 rtl_hw_aspm_clkreq_enable(tp, false);
5158 rtl_ephy_init(tp, e_info_8168g_1, ARRAY_SIZE(e_info_8168g_1));
5159 rtl_hw_aspm_clkreq_enable(tp, true);
5160 }
5161
rtl_hw_start_8168g_2(struct rtl8169_private * tp)5162 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
5163 {
5164 static const struct ephy_info e_info_8168g_2[] = {
5165 { 0x00, 0x0000, 0x0008 },
5166 { 0x0c, 0x3df0, 0x0200 },
5167 { 0x19, 0xffff, 0xfc00 },
5168 { 0x1e, 0xffff, 0x20eb }
5169 };
5170
5171 rtl_hw_start_8168g(tp);
5172
5173 /* disable aspm and clock request before access ephy */
5174 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
5175 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
5176 rtl_ephy_init(tp, e_info_8168g_2, ARRAY_SIZE(e_info_8168g_2));
5177 }
5178
rtl_hw_start_8411_2(struct rtl8169_private * tp)5179 static void rtl_hw_start_8411_2(struct rtl8169_private *tp)
5180 {
5181 static const struct ephy_info e_info_8411_2[] = {
5182 { 0x00, 0x0000, 0x0008 },
5183 { 0x0c, 0x3df0, 0x0200 },
5184 { 0x0f, 0xffff, 0x5200 },
5185 { 0x19, 0x0020, 0x0000 },
5186 { 0x1e, 0x0000, 0x2000 }
5187 };
5188
5189 rtl_hw_start_8168g(tp);
5190
5191 /* disable aspm and clock request before access ephy */
5192 rtl_hw_aspm_clkreq_enable(tp, false);
5193 rtl_ephy_init(tp, e_info_8411_2, ARRAY_SIZE(e_info_8411_2));
5194 rtl_hw_aspm_clkreq_enable(tp, true);
5195 }
5196
rtl_hw_start_8168h_1(struct rtl8169_private * tp)5197 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp)
5198 {
5199 int rg_saw_cnt;
5200 u32 data;
5201 static const struct ephy_info e_info_8168h_1[] = {
5202 { 0x1e, 0x0800, 0x0001 },
5203 { 0x1d, 0x0000, 0x0800 },
5204 { 0x05, 0xffff, 0x2089 },
5205 { 0x06, 0xffff, 0x5881 },
5206 { 0x04, 0xffff, 0x154a },
5207 { 0x01, 0xffff, 0x068b }
5208 };
5209
5210 /* disable aspm and clock request before access ephy */
5211 rtl_hw_aspm_clkreq_enable(tp, false);
5212 rtl_ephy_init(tp, e_info_8168h_1, ARRAY_SIZE(e_info_8168h_1));
5213
5214 rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002, ERIAR_EXGMAC);
5215 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
5216 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
5217 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5218
5219 rtl_set_def_aspm_entry_latency(tp);
5220
5221 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5222
5223 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5224 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5225
5226 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_1111, 0x0010, 0x00, ERIAR_EXGMAC);
5227
5228 rtl_w0w1_eri(tp, 0xd4, ERIAR_MASK_1111, 0x1f00, 0x00, ERIAR_EXGMAC);
5229
5230 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87, ERIAR_EXGMAC);
5231
5232 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
5233 RTL_W8(tp, MaxTxPacketSize, EarlySize);
5234
5235 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5236 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5237
5238 /* Adjust EEE LED frequency */
5239 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
5240
5241 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5242 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
5243
5244 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
5245
5246 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
5247
5248 rtl_pcie_state_l2l3_enable(tp, false);
5249
5250 rtl_writephy(tp, 0x1f, 0x0c42);
5251 rg_saw_cnt = (rtl_readphy(tp, 0x13) & 0x3fff);
5252 rtl_writephy(tp, 0x1f, 0x0000);
5253 if (rg_saw_cnt > 0) {
5254 u16 sw_cnt_1ms_ini;
5255
5256 sw_cnt_1ms_ini = 16000000/rg_saw_cnt;
5257 sw_cnt_1ms_ini &= 0x0fff;
5258 data = r8168_mac_ocp_read(tp, 0xd412);
5259 data &= ~0x0fff;
5260 data |= sw_cnt_1ms_ini;
5261 r8168_mac_ocp_write(tp, 0xd412, data);
5262 }
5263
5264 data = r8168_mac_ocp_read(tp, 0xe056);
5265 data &= ~0xf0;
5266 data |= 0x70;
5267 r8168_mac_ocp_write(tp, 0xe056, data);
5268
5269 data = r8168_mac_ocp_read(tp, 0xe052);
5270 data &= ~0x6000;
5271 data |= 0x8008;
5272 r8168_mac_ocp_write(tp, 0xe052, data);
5273
5274 data = r8168_mac_ocp_read(tp, 0xe0d6);
5275 data &= ~0x01ff;
5276 data |= 0x017f;
5277 r8168_mac_ocp_write(tp, 0xe0d6, data);
5278
5279 data = r8168_mac_ocp_read(tp, 0xd420);
5280 data &= ~0x0fff;
5281 data |= 0x047f;
5282 r8168_mac_ocp_write(tp, 0xd420, data);
5283
5284 r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
5285 r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
5286 r8168_mac_ocp_write(tp, 0xc094, 0x0000);
5287 r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
5288
5289 rtl_hw_aspm_clkreq_enable(tp, true);
5290 }
5291
rtl_hw_start_8168ep(struct rtl8169_private * tp)5292 static void rtl_hw_start_8168ep(struct rtl8169_private *tp)
5293 {
5294 rtl8168ep_stop_cmac(tp);
5295
5296 rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002, ERIAR_EXGMAC);
5297 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x2f, ERIAR_EXGMAC);
5298 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x5f, ERIAR_EXGMAC);
5299 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5300
5301 rtl_set_def_aspm_entry_latency(tp);
5302
5303 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5304
5305 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5306 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5307
5308 rtl_w0w1_eri(tp, 0xd4, ERIAR_MASK_1111, 0x1f80, 0x00, ERIAR_EXGMAC);
5309
5310 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87, ERIAR_EXGMAC);
5311
5312 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
5313 RTL_W8(tp, MaxTxPacketSize, EarlySize);
5314
5315 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5316 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5317
5318 /* Adjust EEE LED frequency */
5319 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
5320
5321 rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
5322
5323 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
5324
5325 rtl_pcie_state_l2l3_enable(tp, false);
5326 }
5327
rtl_hw_start_8168ep_1(struct rtl8169_private * tp)5328 static void rtl_hw_start_8168ep_1(struct rtl8169_private *tp)
5329 {
5330 static const struct ephy_info e_info_8168ep_1[] = {
5331 { 0x00, 0xffff, 0x10ab },
5332 { 0x06, 0xffff, 0xf030 },
5333 { 0x08, 0xffff, 0x2006 },
5334 { 0x0d, 0xffff, 0x1666 },
5335 { 0x0c, 0x3ff0, 0x0000 }
5336 };
5337
5338 /* disable aspm and clock request before access ephy */
5339 rtl_hw_aspm_clkreq_enable(tp, false);
5340 rtl_ephy_init(tp, e_info_8168ep_1, ARRAY_SIZE(e_info_8168ep_1));
5341
5342 rtl_hw_start_8168ep(tp);
5343
5344 rtl_hw_aspm_clkreq_enable(tp, true);
5345 }
5346
rtl_hw_start_8168ep_2(struct rtl8169_private * tp)5347 static void rtl_hw_start_8168ep_2(struct rtl8169_private *tp)
5348 {
5349 static const struct ephy_info e_info_8168ep_2[] = {
5350 { 0x00, 0xffff, 0x10a3 },
5351 { 0x19, 0xffff, 0xfc00 },
5352 { 0x1e, 0xffff, 0x20ea }
5353 };
5354
5355 /* disable aspm and clock request before access ephy */
5356 rtl_hw_aspm_clkreq_enable(tp, false);
5357 rtl_ephy_init(tp, e_info_8168ep_2, ARRAY_SIZE(e_info_8168ep_2));
5358
5359 rtl_hw_start_8168ep(tp);
5360
5361 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5362 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
5363
5364 rtl_hw_aspm_clkreq_enable(tp, true);
5365 }
5366
rtl_hw_start_8168ep_3(struct rtl8169_private * tp)5367 static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp)
5368 {
5369 u32 data;
5370 static const struct ephy_info e_info_8168ep_3[] = {
5371 { 0x00, 0xffff, 0x10a3 },
5372 { 0x19, 0xffff, 0x7c00 },
5373 { 0x1e, 0xffff, 0x20eb },
5374 { 0x0d, 0xffff, 0x1666 }
5375 };
5376
5377 /* disable aspm and clock request before access ephy */
5378 rtl_hw_aspm_clkreq_enable(tp, false);
5379 rtl_ephy_init(tp, e_info_8168ep_3, ARRAY_SIZE(e_info_8168ep_3));
5380
5381 rtl_hw_start_8168ep(tp);
5382
5383 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5384 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
5385
5386 data = r8168_mac_ocp_read(tp, 0xd3e2);
5387 data &= 0xf000;
5388 data |= 0x0271;
5389 r8168_mac_ocp_write(tp, 0xd3e2, data);
5390
5391 data = r8168_mac_ocp_read(tp, 0xd3e4);
5392 data &= 0xff00;
5393 r8168_mac_ocp_write(tp, 0xd3e4, data);
5394
5395 data = r8168_mac_ocp_read(tp, 0xe860);
5396 data |= 0x0080;
5397 r8168_mac_ocp_write(tp, 0xe860, data);
5398
5399 rtl_hw_aspm_clkreq_enable(tp, true);
5400 }
5401
rtl_hw_start_8168(struct rtl8169_private * tp)5402 static void rtl_hw_start_8168(struct rtl8169_private *tp)
5403 {
5404 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
5405
5406 tp->cp_cmd &= ~INTT_MASK;
5407 tp->cp_cmd |= PktCntrDisable | INTT_1;
5408 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
5409
5410 RTL_W16(tp, IntrMitigate, 0x5151);
5411
5412 /* Work around for RxFIFO overflow. */
5413 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
5414 tp->event_slow |= RxFIFOOver | PCSTimeout;
5415 tp->event_slow &= ~RxOverflow;
5416 }
5417
5418 switch (tp->mac_version) {
5419 case RTL_GIGA_MAC_VER_11:
5420 rtl_hw_start_8168bb(tp);
5421 break;
5422
5423 case RTL_GIGA_MAC_VER_12:
5424 case RTL_GIGA_MAC_VER_17:
5425 rtl_hw_start_8168bef(tp);
5426 break;
5427
5428 case RTL_GIGA_MAC_VER_18:
5429 rtl_hw_start_8168cp_1(tp);
5430 break;
5431
5432 case RTL_GIGA_MAC_VER_19:
5433 rtl_hw_start_8168c_1(tp);
5434 break;
5435
5436 case RTL_GIGA_MAC_VER_20:
5437 rtl_hw_start_8168c_2(tp);
5438 break;
5439
5440 case RTL_GIGA_MAC_VER_21:
5441 rtl_hw_start_8168c_3(tp);
5442 break;
5443
5444 case RTL_GIGA_MAC_VER_22:
5445 rtl_hw_start_8168c_4(tp);
5446 break;
5447
5448 case RTL_GIGA_MAC_VER_23:
5449 rtl_hw_start_8168cp_2(tp);
5450 break;
5451
5452 case RTL_GIGA_MAC_VER_24:
5453 rtl_hw_start_8168cp_3(tp);
5454 break;
5455
5456 case RTL_GIGA_MAC_VER_25:
5457 case RTL_GIGA_MAC_VER_26:
5458 case RTL_GIGA_MAC_VER_27:
5459 rtl_hw_start_8168d(tp);
5460 break;
5461
5462 case RTL_GIGA_MAC_VER_28:
5463 rtl_hw_start_8168d_4(tp);
5464 break;
5465
5466 case RTL_GIGA_MAC_VER_31:
5467 rtl_hw_start_8168dp(tp);
5468 break;
5469
5470 case RTL_GIGA_MAC_VER_32:
5471 case RTL_GIGA_MAC_VER_33:
5472 rtl_hw_start_8168e_1(tp);
5473 break;
5474 case RTL_GIGA_MAC_VER_34:
5475 rtl_hw_start_8168e_2(tp);
5476 break;
5477
5478 case RTL_GIGA_MAC_VER_35:
5479 case RTL_GIGA_MAC_VER_36:
5480 rtl_hw_start_8168f_1(tp);
5481 break;
5482
5483 case RTL_GIGA_MAC_VER_38:
5484 rtl_hw_start_8411(tp);
5485 break;
5486
5487 case RTL_GIGA_MAC_VER_40:
5488 case RTL_GIGA_MAC_VER_41:
5489 rtl_hw_start_8168g_1(tp);
5490 break;
5491 case RTL_GIGA_MAC_VER_42:
5492 rtl_hw_start_8168g_2(tp);
5493 break;
5494
5495 case RTL_GIGA_MAC_VER_44:
5496 rtl_hw_start_8411_2(tp);
5497 break;
5498
5499 case RTL_GIGA_MAC_VER_45:
5500 case RTL_GIGA_MAC_VER_46:
5501 rtl_hw_start_8168h_1(tp);
5502 break;
5503
5504 case RTL_GIGA_MAC_VER_49:
5505 rtl_hw_start_8168ep_1(tp);
5506 break;
5507
5508 case RTL_GIGA_MAC_VER_50:
5509 rtl_hw_start_8168ep_2(tp);
5510 break;
5511
5512 case RTL_GIGA_MAC_VER_51:
5513 rtl_hw_start_8168ep_3(tp);
5514 break;
5515
5516 default:
5517 netif_err(tp, drv, tp->dev,
5518 "unknown chipset (mac_version = %d)\n",
5519 tp->mac_version);
5520 break;
5521 }
5522 }
5523
rtl_hw_start_8102e_1(struct rtl8169_private * tp)5524 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
5525 {
5526 static const struct ephy_info e_info_8102e_1[] = {
5527 { 0x01, 0, 0x6e65 },
5528 { 0x02, 0, 0x091f },
5529 { 0x03, 0, 0xc2f9 },
5530 { 0x06, 0, 0xafb5 },
5531 { 0x07, 0, 0x0e00 },
5532 { 0x19, 0, 0xec80 },
5533 { 0x01, 0, 0x2e65 },
5534 { 0x01, 0, 0x6e65 }
5535 };
5536 u8 cfg1;
5537
5538 rtl_set_def_aspm_entry_latency(tp);
5539
5540 RTL_W8(tp, DBG_REG, FIX_NAK_1);
5541
5542 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5543
5544 RTL_W8(tp, Config1,
5545 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
5546 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
5547
5548 cfg1 = RTL_R8(tp, Config1);
5549 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
5550 RTL_W8(tp, Config1, cfg1 & ~LEDS0);
5551
5552 rtl_ephy_init(tp, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
5553 }
5554
rtl_hw_start_8102e_2(struct rtl8169_private * tp)5555 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
5556 {
5557 rtl_set_def_aspm_entry_latency(tp);
5558
5559 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5560
5561 RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable);
5562 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
5563 }
5564
rtl_hw_start_8102e_3(struct rtl8169_private * tp)5565 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
5566 {
5567 rtl_hw_start_8102e_2(tp);
5568
5569 rtl_ephy_write(tp, 0x03, 0xc2f9);
5570 }
5571
rtl_hw_start_8105e_1(struct rtl8169_private * tp)5572 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
5573 {
5574 static const struct ephy_info e_info_8105e_1[] = {
5575 { 0x07, 0, 0x4000 },
5576 { 0x19, 0, 0x0200 },
5577 { 0x19, 0, 0x0020 },
5578 { 0x1e, 0, 0x2000 },
5579 { 0x03, 0, 0x0001 },
5580 { 0x19, 0, 0x0100 },
5581 { 0x19, 0, 0x0004 },
5582 { 0x0a, 0, 0x0020 }
5583 };
5584
5585 /* Force LAN exit from ASPM if Rx/Tx are not idle */
5586 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5587
5588 /* Disable Early Tally Counter */
5589 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000);
5590
5591 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
5592 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
5593
5594 rtl_ephy_init(tp, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
5595
5596 rtl_pcie_state_l2l3_enable(tp, false);
5597 }
5598
rtl_hw_start_8105e_2(struct rtl8169_private * tp)5599 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
5600 {
5601 rtl_hw_start_8105e_1(tp);
5602 rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
5603 }
5604
rtl_hw_start_8402(struct rtl8169_private * tp)5605 static void rtl_hw_start_8402(struct rtl8169_private *tp)
5606 {
5607 static const struct ephy_info e_info_8402[] = {
5608 { 0x19, 0xffff, 0xff64 },
5609 { 0x1e, 0, 0x4000 }
5610 };
5611
5612 rtl_set_def_aspm_entry_latency(tp);
5613
5614 /* Force LAN exit from ASPM if Rx/Tx are not idle */
5615 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5616
5617 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5618
5619 rtl_ephy_init(tp, e_info_8402, ARRAY_SIZE(e_info_8402));
5620
5621 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5622
5623 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00000002, ERIAR_EXGMAC);
5624 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00000006, ERIAR_EXGMAC);
5625 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5626 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5627 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5628 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5629 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00, ERIAR_EXGMAC);
5630
5631 rtl_pcie_state_l2l3_enable(tp, false);
5632 }
5633
rtl_hw_start_8106(struct rtl8169_private * tp)5634 static void rtl_hw_start_8106(struct rtl8169_private *tp)
5635 {
5636 rtl_hw_aspm_clkreq_enable(tp, false);
5637
5638 /* Force LAN exit from ASPM if Rx/Tx are not idle */
5639 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5640
5641 RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
5642 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
5643 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5644
5645 rtl_pcie_state_l2l3_enable(tp, false);
5646 rtl_hw_aspm_clkreq_enable(tp, true);
5647 }
5648
rtl_hw_start_8101(struct rtl8169_private * tp)5649 static void rtl_hw_start_8101(struct rtl8169_private *tp)
5650 {
5651 if (tp->mac_version >= RTL_GIGA_MAC_VER_30)
5652 tp->event_slow &= ~RxFIFOOver;
5653
5654 if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
5655 tp->mac_version == RTL_GIGA_MAC_VER_16)
5656 pcie_capability_set_word(tp->pci_dev, PCI_EXP_DEVCTL,
5657 PCI_EXP_DEVCTL_NOSNOOP_EN);
5658
5659 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
5660
5661 tp->cp_cmd &= CPCMD_QUIRK_MASK;
5662 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
5663
5664 switch (tp->mac_version) {
5665 case RTL_GIGA_MAC_VER_07:
5666 rtl_hw_start_8102e_1(tp);
5667 break;
5668
5669 case RTL_GIGA_MAC_VER_08:
5670 rtl_hw_start_8102e_3(tp);
5671 break;
5672
5673 case RTL_GIGA_MAC_VER_09:
5674 rtl_hw_start_8102e_2(tp);
5675 break;
5676
5677 case RTL_GIGA_MAC_VER_29:
5678 rtl_hw_start_8105e_1(tp);
5679 break;
5680 case RTL_GIGA_MAC_VER_30:
5681 rtl_hw_start_8105e_2(tp);
5682 break;
5683
5684 case RTL_GIGA_MAC_VER_37:
5685 rtl_hw_start_8402(tp);
5686 break;
5687
5688 case RTL_GIGA_MAC_VER_39:
5689 rtl_hw_start_8106(tp);
5690 break;
5691 case RTL_GIGA_MAC_VER_43:
5692 rtl_hw_start_8168g_2(tp);
5693 break;
5694 case RTL_GIGA_MAC_VER_47:
5695 case RTL_GIGA_MAC_VER_48:
5696 rtl_hw_start_8168h_1(tp);
5697 break;
5698 }
5699
5700 RTL_W16(tp, IntrMitigate, 0x0000);
5701 }
5702
rtl8169_change_mtu(struct net_device * dev,int new_mtu)5703 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
5704 {
5705 struct rtl8169_private *tp = netdev_priv(dev);
5706
5707 if (new_mtu > ETH_DATA_LEN)
5708 rtl_hw_jumbo_enable(tp);
5709 else
5710 rtl_hw_jumbo_disable(tp);
5711
5712 dev->mtu = new_mtu;
5713 netdev_update_features(dev);
5714
5715 return 0;
5716 }
5717
rtl8169_make_unusable_by_asic(struct RxDesc * desc)5718 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
5719 {
5720 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
5721 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
5722 }
5723
rtl8169_free_rx_databuff(struct rtl8169_private * tp,void ** data_buff,struct RxDesc * desc)5724 static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
5725 void **data_buff, struct RxDesc *desc)
5726 {
5727 dma_unmap_single(tp_to_dev(tp), le64_to_cpu(desc->addr),
5728 R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
5729
5730 kfree(*data_buff);
5731 *data_buff = NULL;
5732 rtl8169_make_unusable_by_asic(desc);
5733 }
5734
rtl8169_mark_to_asic(struct RxDesc * desc)5735 static inline void rtl8169_mark_to_asic(struct RxDesc *desc)
5736 {
5737 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
5738
5739 /* Force memory writes to complete before releasing descriptor */
5740 dma_wmb();
5741
5742 desc->opts1 = cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE);
5743 }
5744
rtl8169_align(void * data)5745 static inline void *rtl8169_align(void *data)
5746 {
5747 return (void *)ALIGN((long)data, 16);
5748 }
5749
rtl8169_alloc_rx_data(struct rtl8169_private * tp,struct RxDesc * desc)5750 static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
5751 struct RxDesc *desc)
5752 {
5753 void *data;
5754 dma_addr_t mapping;
5755 struct device *d = tp_to_dev(tp);
5756 int node = dev_to_node(d);
5757
5758 data = kmalloc_node(R8169_RX_BUF_SIZE, GFP_KERNEL, node);
5759 if (!data)
5760 return NULL;
5761
5762 if (rtl8169_align(data) != data) {
5763 kfree(data);
5764 data = kmalloc_node(R8169_RX_BUF_SIZE + 15, GFP_KERNEL, node);
5765 if (!data)
5766 return NULL;
5767 }
5768
5769 mapping = dma_map_single(d, rtl8169_align(data), R8169_RX_BUF_SIZE,
5770 DMA_FROM_DEVICE);
5771 if (unlikely(dma_mapping_error(d, mapping))) {
5772 if (net_ratelimit())
5773 netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
5774 goto err_out;
5775 }
5776
5777 desc->addr = cpu_to_le64(mapping);
5778 rtl8169_mark_to_asic(desc);
5779 return data;
5780
5781 err_out:
5782 kfree(data);
5783 return NULL;
5784 }
5785
rtl8169_rx_clear(struct rtl8169_private * tp)5786 static void rtl8169_rx_clear(struct rtl8169_private *tp)
5787 {
5788 unsigned int i;
5789
5790 for (i = 0; i < NUM_RX_DESC; i++) {
5791 if (tp->Rx_databuff[i]) {
5792 rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
5793 tp->RxDescArray + i);
5794 }
5795 }
5796 }
5797
rtl8169_mark_as_last_descriptor(struct RxDesc * desc)5798 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
5799 {
5800 desc->opts1 |= cpu_to_le32(RingEnd);
5801 }
5802
rtl8169_rx_fill(struct rtl8169_private * tp)5803 static int rtl8169_rx_fill(struct rtl8169_private *tp)
5804 {
5805 unsigned int i;
5806
5807 for (i = 0; i < NUM_RX_DESC; i++) {
5808 void *data;
5809
5810 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
5811 if (!data) {
5812 rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
5813 goto err_out;
5814 }
5815 tp->Rx_databuff[i] = data;
5816 }
5817
5818 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
5819 return 0;
5820
5821 err_out:
5822 rtl8169_rx_clear(tp);
5823 return -ENOMEM;
5824 }
5825
rtl8169_init_ring(struct rtl8169_private * tp)5826 static int rtl8169_init_ring(struct rtl8169_private *tp)
5827 {
5828 rtl8169_init_ring_indexes(tp);
5829
5830 memset(tp->tx_skb, 0, sizeof(tp->tx_skb));
5831 memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff));
5832
5833 return rtl8169_rx_fill(tp);
5834 }
5835
rtl8169_unmap_tx_skb(struct device * d,struct ring_info * tx_skb,struct TxDesc * desc)5836 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
5837 struct TxDesc *desc)
5838 {
5839 unsigned int len = tx_skb->len;
5840
5841 dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
5842
5843 desc->opts1 = 0x00;
5844 desc->opts2 = 0x00;
5845 desc->addr = 0x00;
5846 tx_skb->len = 0;
5847 }
5848
rtl8169_tx_clear_range(struct rtl8169_private * tp,u32 start,unsigned int n)5849 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
5850 unsigned int n)
5851 {
5852 unsigned int i;
5853
5854 for (i = 0; i < n; i++) {
5855 unsigned int entry = (start + i) % NUM_TX_DESC;
5856 struct ring_info *tx_skb = tp->tx_skb + entry;
5857 unsigned int len = tx_skb->len;
5858
5859 if (len) {
5860 struct sk_buff *skb = tx_skb->skb;
5861
5862 rtl8169_unmap_tx_skb(tp_to_dev(tp), tx_skb,
5863 tp->TxDescArray + entry);
5864 if (skb) {
5865 dev_consume_skb_any(skb);
5866 tx_skb->skb = NULL;
5867 }
5868 }
5869 }
5870 }
5871
rtl8169_tx_clear(struct rtl8169_private * tp)5872 static void rtl8169_tx_clear(struct rtl8169_private *tp)
5873 {
5874 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
5875 tp->cur_tx = tp->dirty_tx = 0;
5876 }
5877
rtl_reset_work(struct rtl8169_private * tp)5878 static void rtl_reset_work(struct rtl8169_private *tp)
5879 {
5880 struct net_device *dev = tp->dev;
5881 int i;
5882
5883 napi_disable(&tp->napi);
5884 netif_stop_queue(dev);
5885 synchronize_sched();
5886
5887 rtl8169_hw_reset(tp);
5888
5889 for (i = 0; i < NUM_RX_DESC; i++)
5890 rtl8169_mark_to_asic(tp->RxDescArray + i);
5891
5892 rtl8169_tx_clear(tp);
5893 rtl8169_init_ring_indexes(tp);
5894
5895 napi_enable(&tp->napi);
5896 rtl_hw_start(tp);
5897 netif_wake_queue(dev);
5898 }
5899
rtl8169_tx_timeout(struct net_device * dev)5900 static void rtl8169_tx_timeout(struct net_device *dev)
5901 {
5902 struct rtl8169_private *tp = netdev_priv(dev);
5903
5904 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
5905 }
5906
rtl8169_xmit_frags(struct rtl8169_private * tp,struct sk_buff * skb,u32 * opts)5907 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
5908 u32 *opts)
5909 {
5910 struct skb_shared_info *info = skb_shinfo(skb);
5911 unsigned int cur_frag, entry;
5912 struct TxDesc *uninitialized_var(txd);
5913 struct device *d = tp_to_dev(tp);
5914
5915 entry = tp->cur_tx;
5916 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
5917 const skb_frag_t *frag = info->frags + cur_frag;
5918 dma_addr_t mapping;
5919 u32 status, len;
5920 void *addr;
5921
5922 entry = (entry + 1) % NUM_TX_DESC;
5923
5924 txd = tp->TxDescArray + entry;
5925 len = skb_frag_size(frag);
5926 addr = skb_frag_address(frag);
5927 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
5928 if (unlikely(dma_mapping_error(d, mapping))) {
5929 if (net_ratelimit())
5930 netif_err(tp, drv, tp->dev,
5931 "Failed to map TX fragments DMA!\n");
5932 goto err_out;
5933 }
5934
5935 /* Anti gcc 2.95.3 bugware (sic) */
5936 status = opts[0] | len |
5937 (RingEnd * !((entry + 1) % NUM_TX_DESC));
5938
5939 txd->opts1 = cpu_to_le32(status);
5940 txd->opts2 = cpu_to_le32(opts[1]);
5941 txd->addr = cpu_to_le64(mapping);
5942
5943 tp->tx_skb[entry].len = len;
5944 }
5945
5946 if (cur_frag) {
5947 tp->tx_skb[entry].skb = skb;
5948 txd->opts1 |= cpu_to_le32(LastFrag);
5949 }
5950
5951 return cur_frag;
5952
5953 err_out:
5954 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
5955 return -EIO;
5956 }
5957
rtl_test_hw_pad_bug(struct rtl8169_private * tp,struct sk_buff * skb)5958 static bool rtl_test_hw_pad_bug(struct rtl8169_private *tp, struct sk_buff *skb)
5959 {
5960 return skb->len < ETH_ZLEN && tp->mac_version == RTL_GIGA_MAC_VER_34;
5961 }
5962
5963 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
5964 struct net_device *dev);
5965 /* r8169_csum_workaround()
5966 * The hw limites the value the transport offset. When the offset is out of the
5967 * range, calculate the checksum by sw.
5968 */
r8169_csum_workaround(struct rtl8169_private * tp,struct sk_buff * skb)5969 static void r8169_csum_workaround(struct rtl8169_private *tp,
5970 struct sk_buff *skb)
5971 {
5972 if (skb_shinfo(skb)->gso_size) {
5973 netdev_features_t features = tp->dev->features;
5974 struct sk_buff *segs, *nskb;
5975
5976 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
5977 segs = skb_gso_segment(skb, features);
5978 if (IS_ERR(segs) || !segs)
5979 goto drop;
5980
5981 do {
5982 nskb = segs;
5983 segs = segs->next;
5984 nskb->next = NULL;
5985 rtl8169_start_xmit(nskb, tp->dev);
5986 } while (segs);
5987
5988 dev_consume_skb_any(skb);
5989 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5990 if (skb_checksum_help(skb) < 0)
5991 goto drop;
5992
5993 rtl8169_start_xmit(skb, tp->dev);
5994 } else {
5995 struct net_device_stats *stats;
5996
5997 drop:
5998 stats = &tp->dev->stats;
5999 stats->tx_dropped++;
6000 dev_kfree_skb_any(skb);
6001 }
6002 }
6003
6004 /* msdn_giant_send_check()
6005 * According to the document of microsoft, the TCP Pseudo Header excludes the
6006 * packet length for IPv6 TCP large packets.
6007 */
msdn_giant_send_check(struct sk_buff * skb)6008 static int msdn_giant_send_check(struct sk_buff *skb)
6009 {
6010 const struct ipv6hdr *ipv6h;
6011 struct tcphdr *th;
6012 int ret;
6013
6014 ret = skb_cow_head(skb, 0);
6015 if (ret)
6016 return ret;
6017
6018 ipv6h = ipv6_hdr(skb);
6019 th = tcp_hdr(skb);
6020
6021 th->check = 0;
6022 th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
6023
6024 return ret;
6025 }
6026
rtl8169_tso_csum_v1(struct rtl8169_private * tp,struct sk_buff * skb,u32 * opts)6027 static bool rtl8169_tso_csum_v1(struct rtl8169_private *tp,
6028 struct sk_buff *skb, u32 *opts)
6029 {
6030 u32 mss = skb_shinfo(skb)->gso_size;
6031
6032 if (mss) {
6033 opts[0] |= TD_LSO;
6034 opts[0] |= min(mss, TD_MSS_MAX) << TD0_MSS_SHIFT;
6035 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
6036 const struct iphdr *ip = ip_hdr(skb);
6037
6038 if (ip->protocol == IPPROTO_TCP)
6039 opts[0] |= TD0_IP_CS | TD0_TCP_CS;
6040 else if (ip->protocol == IPPROTO_UDP)
6041 opts[0] |= TD0_IP_CS | TD0_UDP_CS;
6042 else
6043 WARN_ON_ONCE(1);
6044 }
6045
6046 return true;
6047 }
6048
rtl8169_tso_csum_v2(struct rtl8169_private * tp,struct sk_buff * skb,u32 * opts)6049 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp,
6050 struct sk_buff *skb, u32 *opts)
6051 {
6052 u32 transport_offset = (u32)skb_transport_offset(skb);
6053 u32 mss = skb_shinfo(skb)->gso_size;
6054
6055 if (mss) {
6056 if (transport_offset > GTTCPHO_MAX) {
6057 netif_warn(tp, tx_err, tp->dev,
6058 "Invalid transport offset 0x%x for TSO\n",
6059 transport_offset);
6060 return false;
6061 }
6062
6063 switch (vlan_get_protocol(skb)) {
6064 case htons(ETH_P_IP):
6065 opts[0] |= TD1_GTSENV4;
6066 break;
6067
6068 case htons(ETH_P_IPV6):
6069 if (msdn_giant_send_check(skb))
6070 return false;
6071
6072 opts[0] |= TD1_GTSENV6;
6073 break;
6074
6075 default:
6076 WARN_ON_ONCE(1);
6077 break;
6078 }
6079
6080 opts[0] |= transport_offset << GTTCPHO_SHIFT;
6081 opts[1] |= min(mss, TD_MSS_MAX) << TD1_MSS_SHIFT;
6082 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
6083 u8 ip_protocol;
6084
6085 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
6086 return !(skb_checksum_help(skb) || eth_skb_pad(skb));
6087
6088 if (transport_offset > TCPHO_MAX) {
6089 netif_warn(tp, tx_err, tp->dev,
6090 "Invalid transport offset 0x%x\n",
6091 transport_offset);
6092 return false;
6093 }
6094
6095 switch (vlan_get_protocol(skb)) {
6096 case htons(ETH_P_IP):
6097 opts[1] |= TD1_IPv4_CS;
6098 ip_protocol = ip_hdr(skb)->protocol;
6099 break;
6100
6101 case htons(ETH_P_IPV6):
6102 opts[1] |= TD1_IPv6_CS;
6103 ip_protocol = ipv6_hdr(skb)->nexthdr;
6104 break;
6105
6106 default:
6107 ip_protocol = IPPROTO_RAW;
6108 break;
6109 }
6110
6111 if (ip_protocol == IPPROTO_TCP)
6112 opts[1] |= TD1_TCP_CS;
6113 else if (ip_protocol == IPPROTO_UDP)
6114 opts[1] |= TD1_UDP_CS;
6115 else
6116 WARN_ON_ONCE(1);
6117
6118 opts[1] |= transport_offset << TCPHO_SHIFT;
6119 } else {
6120 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
6121 return !eth_skb_pad(skb);
6122 }
6123
6124 return true;
6125 }
6126
rtl8169_start_xmit(struct sk_buff * skb,struct net_device * dev)6127 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
6128 struct net_device *dev)
6129 {
6130 struct rtl8169_private *tp = netdev_priv(dev);
6131 unsigned int entry = tp->cur_tx % NUM_TX_DESC;
6132 struct TxDesc *txd = tp->TxDescArray + entry;
6133 struct device *d = tp_to_dev(tp);
6134 dma_addr_t mapping;
6135 u32 status, len;
6136 u32 opts[2];
6137 int frags;
6138
6139 if (unlikely(!TX_FRAGS_READY_FOR(tp, skb_shinfo(skb)->nr_frags))) {
6140 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
6141 goto err_stop_0;
6142 }
6143
6144 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
6145 goto err_stop_0;
6146
6147 opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(skb));
6148 opts[0] = DescOwn;
6149
6150 if (!tp->tso_csum(tp, skb, opts)) {
6151 r8169_csum_workaround(tp, skb);
6152 return NETDEV_TX_OK;
6153 }
6154
6155 len = skb_headlen(skb);
6156 mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
6157 if (unlikely(dma_mapping_error(d, mapping))) {
6158 if (net_ratelimit())
6159 netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
6160 goto err_dma_0;
6161 }
6162
6163 tp->tx_skb[entry].len = len;
6164 txd->addr = cpu_to_le64(mapping);
6165
6166 frags = rtl8169_xmit_frags(tp, skb, opts);
6167 if (frags < 0)
6168 goto err_dma_1;
6169 else if (frags)
6170 opts[0] |= FirstFrag;
6171 else {
6172 opts[0] |= FirstFrag | LastFrag;
6173 tp->tx_skb[entry].skb = skb;
6174 }
6175
6176 txd->opts2 = cpu_to_le32(opts[1]);
6177
6178 skb_tx_timestamp(skb);
6179
6180 /* Force memory writes to complete before releasing descriptor */
6181 dma_wmb();
6182
6183 /* Anti gcc 2.95.3 bugware (sic) */
6184 status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
6185 txd->opts1 = cpu_to_le32(status);
6186
6187 /* Force all memory writes to complete before notifying device */
6188 wmb();
6189
6190 tp->cur_tx += frags + 1;
6191
6192 RTL_W8(tp, TxPoll, NPQ);
6193
6194 mmiowb();
6195
6196 if (!TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
6197 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
6198 * not miss a ring update when it notices a stopped queue.
6199 */
6200 smp_wmb();
6201 netif_stop_queue(dev);
6202 /* Sync with rtl_tx:
6203 * - publish queue status and cur_tx ring index (write barrier)
6204 * - refresh dirty_tx ring index (read barrier).
6205 * May the current thread have a pessimistic view of the ring
6206 * status and forget to wake up queue, a racing rtl_tx thread
6207 * can't.
6208 */
6209 smp_mb();
6210 if (TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS))
6211 netif_wake_queue(dev);
6212 }
6213
6214 return NETDEV_TX_OK;
6215
6216 err_dma_1:
6217 rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
6218 err_dma_0:
6219 dev_kfree_skb_any(skb);
6220 dev->stats.tx_dropped++;
6221 return NETDEV_TX_OK;
6222
6223 err_stop_0:
6224 netif_stop_queue(dev);
6225 dev->stats.tx_dropped++;
6226 return NETDEV_TX_BUSY;
6227 }
6228
rtl8169_pcierr_interrupt(struct net_device * dev)6229 static void rtl8169_pcierr_interrupt(struct net_device *dev)
6230 {
6231 struct rtl8169_private *tp = netdev_priv(dev);
6232 struct pci_dev *pdev = tp->pci_dev;
6233 u16 pci_status, pci_cmd;
6234
6235 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
6236 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
6237
6238 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
6239 pci_cmd, pci_status);
6240
6241 /*
6242 * The recovery sequence below admits a very elaborated explanation:
6243 * - it seems to work;
6244 * - I did not see what else could be done;
6245 * - it makes iop3xx happy.
6246 *
6247 * Feel free to adjust to your needs.
6248 */
6249 if (pdev->broken_parity_status)
6250 pci_cmd &= ~PCI_COMMAND_PARITY;
6251 else
6252 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
6253
6254 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
6255
6256 pci_write_config_word(pdev, PCI_STATUS,
6257 pci_status & (PCI_STATUS_DETECTED_PARITY |
6258 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
6259 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
6260
6261 /* The infamous DAC f*ckup only happens at boot time */
6262 if ((tp->cp_cmd & PCIDAC) && !tp->cur_rx) {
6263 netif_info(tp, intr, dev, "disabling PCI DAC\n");
6264 tp->cp_cmd &= ~PCIDAC;
6265 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
6266 dev->features &= ~NETIF_F_HIGHDMA;
6267 }
6268
6269 rtl8169_hw_reset(tp);
6270
6271 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
6272 }
6273
rtl_tx(struct net_device * dev,struct rtl8169_private * tp)6274 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp)
6275 {
6276 unsigned int dirty_tx, tx_left;
6277
6278 dirty_tx = tp->dirty_tx;
6279 smp_rmb();
6280 tx_left = tp->cur_tx - dirty_tx;
6281
6282 while (tx_left > 0) {
6283 unsigned int entry = dirty_tx % NUM_TX_DESC;
6284 struct ring_info *tx_skb = tp->tx_skb + entry;
6285 u32 status;
6286
6287 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
6288 if (status & DescOwn)
6289 break;
6290
6291 /* This barrier is needed to keep us from reading
6292 * any other fields out of the Tx descriptor until
6293 * we know the status of DescOwn
6294 */
6295 dma_rmb();
6296
6297 rtl8169_unmap_tx_skb(tp_to_dev(tp), tx_skb,
6298 tp->TxDescArray + entry);
6299 if (status & LastFrag) {
6300 u64_stats_update_begin(&tp->tx_stats.syncp);
6301 tp->tx_stats.packets++;
6302 tp->tx_stats.bytes += tx_skb->skb->len;
6303 u64_stats_update_end(&tp->tx_stats.syncp);
6304 dev_consume_skb_any(tx_skb->skb);
6305 tx_skb->skb = NULL;
6306 }
6307 dirty_tx++;
6308 tx_left--;
6309 }
6310
6311 if (tp->dirty_tx != dirty_tx) {
6312 tp->dirty_tx = dirty_tx;
6313 /* Sync with rtl8169_start_xmit:
6314 * - publish dirty_tx ring index (write barrier)
6315 * - refresh cur_tx ring index and queue status (read barrier)
6316 * May the current thread miss the stopped queue condition,
6317 * a racing xmit thread can only have a right view of the
6318 * ring status.
6319 */
6320 smp_mb();
6321 if (netif_queue_stopped(dev) &&
6322 TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
6323 netif_wake_queue(dev);
6324 }
6325 /*
6326 * 8168 hack: TxPoll requests are lost when the Tx packets are
6327 * too close. Let's kick an extra TxPoll request when a burst
6328 * of start_xmit activity is detected (if it is not detected,
6329 * it is slow enough). -- FR
6330 */
6331 if (tp->cur_tx != dirty_tx)
6332 RTL_W8(tp, TxPoll, NPQ);
6333 }
6334 }
6335
rtl8169_fragmented_frame(u32 status)6336 static inline int rtl8169_fragmented_frame(u32 status)
6337 {
6338 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
6339 }
6340
rtl8169_rx_csum(struct sk_buff * skb,u32 opts1)6341 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
6342 {
6343 u32 status = opts1 & RxProtoMask;
6344
6345 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
6346 ((status == RxProtoUDP) && !(opts1 & UDPFail)))
6347 skb->ip_summed = CHECKSUM_UNNECESSARY;
6348 else
6349 skb_checksum_none_assert(skb);
6350 }
6351
rtl8169_try_rx_copy(void * data,struct rtl8169_private * tp,int pkt_size,dma_addr_t addr)6352 static struct sk_buff *rtl8169_try_rx_copy(void *data,
6353 struct rtl8169_private *tp,
6354 int pkt_size,
6355 dma_addr_t addr)
6356 {
6357 struct sk_buff *skb;
6358 struct device *d = tp_to_dev(tp);
6359
6360 data = rtl8169_align(data);
6361 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
6362 prefetch(data);
6363 skb = napi_alloc_skb(&tp->napi, pkt_size);
6364 if (skb)
6365 skb_copy_to_linear_data(skb, data, pkt_size);
6366 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
6367
6368 return skb;
6369 }
6370
rtl_rx(struct net_device * dev,struct rtl8169_private * tp,u32 budget)6371 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
6372 {
6373 unsigned int cur_rx, rx_left;
6374 unsigned int count;
6375
6376 cur_rx = tp->cur_rx;
6377
6378 for (rx_left = min(budget, NUM_RX_DESC); rx_left > 0; rx_left--, cur_rx++) {
6379 unsigned int entry = cur_rx % NUM_RX_DESC;
6380 struct RxDesc *desc = tp->RxDescArray + entry;
6381 u32 status;
6382
6383 status = le32_to_cpu(desc->opts1);
6384 if (status & DescOwn)
6385 break;
6386
6387 /* This barrier is needed to keep us from reading
6388 * any other fields out of the Rx descriptor until
6389 * we know the status of DescOwn
6390 */
6391 dma_rmb();
6392
6393 if (unlikely(status & RxRES)) {
6394 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
6395 status);
6396 dev->stats.rx_errors++;
6397 if (status & (RxRWT | RxRUNT))
6398 dev->stats.rx_length_errors++;
6399 if (status & RxCRC)
6400 dev->stats.rx_crc_errors++;
6401 /* RxFOVF is a reserved bit on later chip versions */
6402 if (tp->mac_version == RTL_GIGA_MAC_VER_01 &&
6403 status & RxFOVF) {
6404 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
6405 dev->stats.rx_fifo_errors++;
6406 } else if (status & (RxRUNT | RxCRC) &&
6407 !(status & RxRWT) &&
6408 dev->features & NETIF_F_RXALL) {
6409 goto process_pkt;
6410 }
6411 } else {
6412 struct sk_buff *skb;
6413 dma_addr_t addr;
6414 int pkt_size;
6415
6416 process_pkt:
6417 addr = le64_to_cpu(desc->addr);
6418 if (likely(!(dev->features & NETIF_F_RXFCS)))
6419 pkt_size = (status & 0x00003fff) - 4;
6420 else
6421 pkt_size = status & 0x00003fff;
6422
6423 /*
6424 * The driver does not support incoming fragmented
6425 * frames. They are seen as a symptom of over-mtu
6426 * sized frames.
6427 */
6428 if (unlikely(rtl8169_fragmented_frame(status))) {
6429 dev->stats.rx_dropped++;
6430 dev->stats.rx_length_errors++;
6431 goto release_descriptor;
6432 }
6433
6434 skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
6435 tp, pkt_size, addr);
6436 if (!skb) {
6437 dev->stats.rx_dropped++;
6438 goto release_descriptor;
6439 }
6440
6441 rtl8169_rx_csum(skb, status);
6442 skb_put(skb, pkt_size);
6443 skb->protocol = eth_type_trans(skb, dev);
6444
6445 rtl8169_rx_vlan_tag(desc, skb);
6446
6447 if (skb->pkt_type == PACKET_MULTICAST)
6448 dev->stats.multicast++;
6449
6450 napi_gro_receive(&tp->napi, skb);
6451
6452 u64_stats_update_begin(&tp->rx_stats.syncp);
6453 tp->rx_stats.packets++;
6454 tp->rx_stats.bytes += pkt_size;
6455 u64_stats_update_end(&tp->rx_stats.syncp);
6456 }
6457 release_descriptor:
6458 desc->opts2 = 0;
6459 rtl8169_mark_to_asic(desc);
6460 }
6461
6462 count = cur_rx - tp->cur_rx;
6463 tp->cur_rx = cur_rx;
6464
6465 return count;
6466 }
6467
rtl8169_interrupt(int irq,void * dev_instance)6468 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
6469 {
6470 struct rtl8169_private *tp = dev_instance;
6471 u16 status = rtl_get_events(tp);
6472
6473 if (status == 0xffff || !(status & (RTL_EVENT_NAPI | tp->event_slow)))
6474 return IRQ_NONE;
6475
6476 rtl_irq_disable(tp);
6477 napi_schedule_irqoff(&tp->napi);
6478
6479 return IRQ_HANDLED;
6480 }
6481
6482 /*
6483 * Workqueue context.
6484 */
rtl_slow_event_work(struct rtl8169_private * tp)6485 static void rtl_slow_event_work(struct rtl8169_private *tp)
6486 {
6487 struct net_device *dev = tp->dev;
6488 u16 status;
6489
6490 status = rtl_get_events(tp) & tp->event_slow;
6491 rtl_ack_events(tp, status);
6492
6493 if (unlikely(status & RxFIFOOver)) {
6494 switch (tp->mac_version) {
6495 /* Work around for rx fifo overflow */
6496 case RTL_GIGA_MAC_VER_11:
6497 netif_stop_queue(dev);
6498 /* XXX - Hack alert. See rtl_task(). */
6499 set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
6500 default:
6501 break;
6502 }
6503 }
6504
6505 if (unlikely(status & SYSErr))
6506 rtl8169_pcierr_interrupt(dev);
6507
6508 if (status & LinkChg)
6509 phy_mac_interrupt(dev->phydev);
6510
6511 rtl_irq_enable_all(tp);
6512 }
6513
rtl_task(struct work_struct * work)6514 static void rtl_task(struct work_struct *work)
6515 {
6516 static const struct {
6517 int bitnr;
6518 void (*action)(struct rtl8169_private *);
6519 } rtl_work[] = {
6520 /* XXX - keep rtl_slow_event_work() as first element. */
6521 { RTL_FLAG_TASK_SLOW_PENDING, rtl_slow_event_work },
6522 { RTL_FLAG_TASK_RESET_PENDING, rtl_reset_work },
6523 };
6524 struct rtl8169_private *tp =
6525 container_of(work, struct rtl8169_private, wk.work);
6526 struct net_device *dev = tp->dev;
6527 int i;
6528
6529 rtl_lock_work(tp);
6530
6531 if (!netif_running(dev) ||
6532 !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
6533 goto out_unlock;
6534
6535 for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
6536 bool pending;
6537
6538 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
6539 if (pending)
6540 rtl_work[i].action(tp);
6541 }
6542
6543 out_unlock:
6544 rtl_unlock_work(tp);
6545 }
6546
rtl8169_poll(struct napi_struct * napi,int budget)6547 static int rtl8169_poll(struct napi_struct *napi, int budget)
6548 {
6549 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
6550 struct net_device *dev = tp->dev;
6551 u16 enable_mask = RTL_EVENT_NAPI | tp->event_slow;
6552 int work_done;
6553 u16 status;
6554
6555 status = rtl_get_events(tp);
6556 rtl_ack_events(tp, status & ~tp->event_slow);
6557
6558 work_done = rtl_rx(dev, tp, (u32) budget);
6559
6560 rtl_tx(dev, tp);
6561
6562 if (status & tp->event_slow) {
6563 enable_mask &= ~tp->event_slow;
6564
6565 rtl_schedule_task(tp, RTL_FLAG_TASK_SLOW_PENDING);
6566 }
6567
6568 if (work_done < budget) {
6569 napi_complete_done(napi, work_done);
6570
6571 rtl_irq_enable(tp, enable_mask);
6572 mmiowb();
6573 }
6574
6575 return work_done;
6576 }
6577
rtl8169_rx_missed(struct net_device * dev)6578 static void rtl8169_rx_missed(struct net_device *dev)
6579 {
6580 struct rtl8169_private *tp = netdev_priv(dev);
6581
6582 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
6583 return;
6584
6585 dev->stats.rx_missed_errors += RTL_R32(tp, RxMissed) & 0xffffff;
6586 RTL_W32(tp, RxMissed, 0);
6587 }
6588
r8169_phylink_handler(struct net_device * ndev)6589 static void r8169_phylink_handler(struct net_device *ndev)
6590 {
6591 struct rtl8169_private *tp = netdev_priv(ndev);
6592
6593 if (netif_carrier_ok(ndev)) {
6594 rtl_link_chg_patch(tp);
6595 pm_request_resume(&tp->pci_dev->dev);
6596 } else {
6597 pm_runtime_idle(&tp->pci_dev->dev);
6598 }
6599
6600 if (net_ratelimit())
6601 phy_print_status(ndev->phydev);
6602 }
6603
r8169_phy_connect(struct rtl8169_private * tp)6604 static int r8169_phy_connect(struct rtl8169_private *tp)
6605 {
6606 struct phy_device *phydev = mdiobus_get_phy(tp->mii_bus, 0);
6607 phy_interface_t phy_mode;
6608 int ret;
6609
6610 phy_mode = tp->supports_gmii ? PHY_INTERFACE_MODE_GMII :
6611 PHY_INTERFACE_MODE_MII;
6612
6613 ret = phy_connect_direct(tp->dev, phydev, r8169_phylink_handler,
6614 phy_mode);
6615 if (ret)
6616 return ret;
6617
6618 if (!tp->supports_gmii)
6619 phy_set_max_speed(phydev, SPEED_100);
6620
6621 /* Ensure to advertise everything, incl. pause */
6622 phydev->advertising = phydev->supported;
6623
6624 phy_attached_info(phydev);
6625
6626 return 0;
6627 }
6628
rtl8169_down(struct net_device * dev)6629 static void rtl8169_down(struct net_device *dev)
6630 {
6631 struct rtl8169_private *tp = netdev_priv(dev);
6632
6633 phy_stop(dev->phydev);
6634
6635 napi_disable(&tp->napi);
6636 netif_stop_queue(dev);
6637
6638 rtl8169_hw_reset(tp);
6639 /*
6640 * At this point device interrupts can not be enabled in any function,
6641 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
6642 * and napi is disabled (rtl8169_poll).
6643 */
6644 rtl8169_rx_missed(dev);
6645
6646 /* Give a racing hard_start_xmit a few cycles to complete. */
6647 synchronize_sched();
6648
6649 rtl8169_tx_clear(tp);
6650
6651 rtl8169_rx_clear(tp);
6652
6653 rtl_pll_power_down(tp);
6654 }
6655
rtl8169_close(struct net_device * dev)6656 static int rtl8169_close(struct net_device *dev)
6657 {
6658 struct rtl8169_private *tp = netdev_priv(dev);
6659 struct pci_dev *pdev = tp->pci_dev;
6660
6661 pm_runtime_get_sync(&pdev->dev);
6662
6663 /* Update counters before going down */
6664 rtl8169_update_counters(tp);
6665
6666 rtl_lock_work(tp);
6667 /* Clear all task flags */
6668 bitmap_zero(tp->wk.flags, RTL_FLAG_MAX);
6669
6670 rtl8169_down(dev);
6671 rtl_unlock_work(tp);
6672
6673 cancel_work_sync(&tp->wk.work);
6674
6675 phy_disconnect(dev->phydev);
6676
6677 pci_free_irq(pdev, 0, tp);
6678
6679 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6680 tp->RxPhyAddr);
6681 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6682 tp->TxPhyAddr);
6683 tp->TxDescArray = NULL;
6684 tp->RxDescArray = NULL;
6685
6686 pm_runtime_put_sync(&pdev->dev);
6687
6688 return 0;
6689 }
6690
6691 #ifdef CONFIG_NET_POLL_CONTROLLER
rtl8169_netpoll(struct net_device * dev)6692 static void rtl8169_netpoll(struct net_device *dev)
6693 {
6694 struct rtl8169_private *tp = netdev_priv(dev);
6695
6696 rtl8169_interrupt(pci_irq_vector(tp->pci_dev, 0), tp);
6697 }
6698 #endif
6699
rtl_open(struct net_device * dev)6700 static int rtl_open(struct net_device *dev)
6701 {
6702 struct rtl8169_private *tp = netdev_priv(dev);
6703 struct pci_dev *pdev = tp->pci_dev;
6704 int retval = -ENOMEM;
6705
6706 pm_runtime_get_sync(&pdev->dev);
6707
6708 /*
6709 * Rx and Tx descriptors needs 256 bytes alignment.
6710 * dma_alloc_coherent provides more.
6711 */
6712 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
6713 &tp->TxPhyAddr, GFP_KERNEL);
6714 if (!tp->TxDescArray)
6715 goto err_pm_runtime_put;
6716
6717 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
6718 &tp->RxPhyAddr, GFP_KERNEL);
6719 if (!tp->RxDescArray)
6720 goto err_free_tx_0;
6721
6722 retval = rtl8169_init_ring(tp);
6723 if (retval < 0)
6724 goto err_free_rx_1;
6725
6726 INIT_WORK(&tp->wk.work, rtl_task);
6727
6728 smp_mb();
6729
6730 rtl_request_firmware(tp);
6731
6732 retval = pci_request_irq(pdev, 0, rtl8169_interrupt, NULL, tp,
6733 dev->name);
6734 if (retval < 0)
6735 goto err_release_fw_2;
6736
6737 retval = r8169_phy_connect(tp);
6738 if (retval)
6739 goto err_free_irq;
6740
6741 rtl_lock_work(tp);
6742
6743 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6744
6745 napi_enable(&tp->napi);
6746
6747 rtl8169_init_phy(dev, tp);
6748
6749 rtl_pll_power_up(tp);
6750
6751 rtl_hw_start(tp);
6752
6753 if (!rtl8169_init_counter_offsets(tp))
6754 netif_warn(tp, hw, dev, "counter reset/update failed\n");
6755
6756 phy_start(dev->phydev);
6757 netif_start_queue(dev);
6758
6759 rtl_unlock_work(tp);
6760
6761 pm_runtime_put_sync(&pdev->dev);
6762 out:
6763 return retval;
6764
6765 err_free_irq:
6766 pci_free_irq(pdev, 0, tp);
6767 err_release_fw_2:
6768 rtl_release_firmware(tp);
6769 rtl8169_rx_clear(tp);
6770 err_free_rx_1:
6771 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6772 tp->RxPhyAddr);
6773 tp->RxDescArray = NULL;
6774 err_free_tx_0:
6775 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6776 tp->TxPhyAddr);
6777 tp->TxDescArray = NULL;
6778 err_pm_runtime_put:
6779 pm_runtime_put_noidle(&pdev->dev);
6780 goto out;
6781 }
6782
6783 static void
rtl8169_get_stats64(struct net_device * dev,struct rtnl_link_stats64 * stats)6784 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
6785 {
6786 struct rtl8169_private *tp = netdev_priv(dev);
6787 struct pci_dev *pdev = tp->pci_dev;
6788 struct rtl8169_counters *counters = tp->counters;
6789 unsigned int start;
6790
6791 pm_runtime_get_noresume(&pdev->dev);
6792
6793 if (netif_running(dev) && pm_runtime_active(&pdev->dev))
6794 rtl8169_rx_missed(dev);
6795
6796 do {
6797 start = u64_stats_fetch_begin_irq(&tp->rx_stats.syncp);
6798 stats->rx_packets = tp->rx_stats.packets;
6799 stats->rx_bytes = tp->rx_stats.bytes;
6800 } while (u64_stats_fetch_retry_irq(&tp->rx_stats.syncp, start));
6801
6802 do {
6803 start = u64_stats_fetch_begin_irq(&tp->tx_stats.syncp);
6804 stats->tx_packets = tp->tx_stats.packets;
6805 stats->tx_bytes = tp->tx_stats.bytes;
6806 } while (u64_stats_fetch_retry_irq(&tp->tx_stats.syncp, start));
6807
6808 stats->rx_dropped = dev->stats.rx_dropped;
6809 stats->tx_dropped = dev->stats.tx_dropped;
6810 stats->rx_length_errors = dev->stats.rx_length_errors;
6811 stats->rx_errors = dev->stats.rx_errors;
6812 stats->rx_crc_errors = dev->stats.rx_crc_errors;
6813 stats->rx_fifo_errors = dev->stats.rx_fifo_errors;
6814 stats->rx_missed_errors = dev->stats.rx_missed_errors;
6815 stats->multicast = dev->stats.multicast;
6816
6817 /*
6818 * Fetch additonal counter values missing in stats collected by driver
6819 * from tally counters.
6820 */
6821 if (pm_runtime_active(&pdev->dev))
6822 rtl8169_update_counters(tp);
6823
6824 /*
6825 * Subtract values fetched during initalization.
6826 * See rtl8169_init_counter_offsets for a description why we do that.
6827 */
6828 stats->tx_errors = le64_to_cpu(counters->tx_errors) -
6829 le64_to_cpu(tp->tc_offset.tx_errors);
6830 stats->collisions = le32_to_cpu(counters->tx_multi_collision) -
6831 le32_to_cpu(tp->tc_offset.tx_multi_collision);
6832 stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) -
6833 le16_to_cpu(tp->tc_offset.tx_aborted);
6834
6835 pm_runtime_put_noidle(&pdev->dev);
6836 }
6837
rtl8169_net_suspend(struct net_device * dev)6838 static void rtl8169_net_suspend(struct net_device *dev)
6839 {
6840 struct rtl8169_private *tp = netdev_priv(dev);
6841
6842 if (!netif_running(dev))
6843 return;
6844
6845 phy_stop(dev->phydev);
6846 netif_device_detach(dev);
6847 netif_stop_queue(dev);
6848
6849 rtl_lock_work(tp);
6850 napi_disable(&tp->napi);
6851 /* Clear all task flags */
6852 bitmap_zero(tp->wk.flags, RTL_FLAG_MAX);
6853
6854 rtl_unlock_work(tp);
6855
6856 rtl_pll_power_down(tp);
6857 }
6858
6859 #ifdef CONFIG_PM
6860
rtl8169_suspend(struct device * device)6861 static int rtl8169_suspend(struct device *device)
6862 {
6863 struct pci_dev *pdev = to_pci_dev(device);
6864 struct net_device *dev = pci_get_drvdata(pdev);
6865 struct rtl8169_private *tp = netdev_priv(dev);
6866
6867 rtl8169_net_suspend(dev);
6868 clk_disable_unprepare(tp->clk);
6869
6870 return 0;
6871 }
6872
__rtl8169_resume(struct net_device * dev)6873 static void __rtl8169_resume(struct net_device *dev)
6874 {
6875 struct rtl8169_private *tp = netdev_priv(dev);
6876
6877 netif_device_attach(dev);
6878
6879 rtl_pll_power_up(tp);
6880 rtl8169_init_phy(dev, tp);
6881
6882 phy_start(tp->dev->phydev);
6883
6884 rtl_lock_work(tp);
6885 napi_enable(&tp->napi);
6886 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6887 rtl_unlock_work(tp);
6888
6889 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
6890 }
6891
rtl8169_resume(struct device * device)6892 static int rtl8169_resume(struct device *device)
6893 {
6894 struct pci_dev *pdev = to_pci_dev(device);
6895 struct net_device *dev = pci_get_drvdata(pdev);
6896 struct rtl8169_private *tp = netdev_priv(dev);
6897
6898 clk_prepare_enable(tp->clk);
6899
6900 if (netif_running(dev))
6901 __rtl8169_resume(dev);
6902
6903 return 0;
6904 }
6905
rtl8169_runtime_suspend(struct device * device)6906 static int rtl8169_runtime_suspend(struct device *device)
6907 {
6908 struct pci_dev *pdev = to_pci_dev(device);
6909 struct net_device *dev = pci_get_drvdata(pdev);
6910 struct rtl8169_private *tp = netdev_priv(dev);
6911
6912 if (!tp->TxDescArray)
6913 return 0;
6914
6915 rtl_lock_work(tp);
6916 __rtl8169_set_wol(tp, WAKE_ANY);
6917 rtl_unlock_work(tp);
6918
6919 rtl8169_net_suspend(dev);
6920
6921 /* Update counters before going runtime suspend */
6922 rtl8169_rx_missed(dev);
6923 rtl8169_update_counters(tp);
6924
6925 return 0;
6926 }
6927
rtl8169_runtime_resume(struct device * device)6928 static int rtl8169_runtime_resume(struct device *device)
6929 {
6930 struct pci_dev *pdev = to_pci_dev(device);
6931 struct net_device *dev = pci_get_drvdata(pdev);
6932 struct rtl8169_private *tp = netdev_priv(dev);
6933 rtl_rar_set(tp, dev->dev_addr);
6934
6935 if (!tp->TxDescArray)
6936 return 0;
6937
6938 rtl_lock_work(tp);
6939 __rtl8169_set_wol(tp, tp->saved_wolopts);
6940 rtl_unlock_work(tp);
6941
6942 __rtl8169_resume(dev);
6943
6944 return 0;
6945 }
6946
rtl8169_runtime_idle(struct device * device)6947 static int rtl8169_runtime_idle(struct device *device)
6948 {
6949 struct pci_dev *pdev = to_pci_dev(device);
6950 struct net_device *dev = pci_get_drvdata(pdev);
6951
6952 if (!netif_running(dev) || !netif_carrier_ok(dev))
6953 pm_schedule_suspend(device, 10000);
6954
6955 return -EBUSY;
6956 }
6957
6958 static const struct dev_pm_ops rtl8169_pm_ops = {
6959 .suspend = rtl8169_suspend,
6960 .resume = rtl8169_resume,
6961 .freeze = rtl8169_suspend,
6962 .thaw = rtl8169_resume,
6963 .poweroff = rtl8169_suspend,
6964 .restore = rtl8169_resume,
6965 .runtime_suspend = rtl8169_runtime_suspend,
6966 .runtime_resume = rtl8169_runtime_resume,
6967 .runtime_idle = rtl8169_runtime_idle,
6968 };
6969
6970 #define RTL8169_PM_OPS (&rtl8169_pm_ops)
6971
6972 #else /* !CONFIG_PM */
6973
6974 #define RTL8169_PM_OPS NULL
6975
6976 #endif /* !CONFIG_PM */
6977
rtl_wol_shutdown_quirk(struct rtl8169_private * tp)6978 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
6979 {
6980 /* WoL fails with 8168b when the receiver is disabled. */
6981 switch (tp->mac_version) {
6982 case RTL_GIGA_MAC_VER_11:
6983 case RTL_GIGA_MAC_VER_12:
6984 case RTL_GIGA_MAC_VER_17:
6985 pci_clear_master(tp->pci_dev);
6986
6987 RTL_W8(tp, ChipCmd, CmdRxEnb);
6988 /* PCI commit */
6989 RTL_R8(tp, ChipCmd);
6990 break;
6991 default:
6992 break;
6993 }
6994 }
6995
rtl_shutdown(struct pci_dev * pdev)6996 static void rtl_shutdown(struct pci_dev *pdev)
6997 {
6998 struct net_device *dev = pci_get_drvdata(pdev);
6999 struct rtl8169_private *tp = netdev_priv(dev);
7000
7001 rtl8169_net_suspend(dev);
7002
7003 /* Restore original MAC address */
7004 rtl_rar_set(tp, dev->perm_addr);
7005
7006 rtl8169_hw_reset(tp);
7007
7008 if (system_state == SYSTEM_POWER_OFF) {
7009 if (tp->saved_wolopts) {
7010 rtl_wol_suspend_quirk(tp);
7011 rtl_wol_shutdown_quirk(tp);
7012 }
7013
7014 pci_wake_from_d3(pdev, true);
7015 pci_set_power_state(pdev, PCI_D3hot);
7016 }
7017 }
7018
rtl_remove_one(struct pci_dev * pdev)7019 static void rtl_remove_one(struct pci_dev *pdev)
7020 {
7021 struct net_device *dev = pci_get_drvdata(pdev);
7022 struct rtl8169_private *tp = netdev_priv(dev);
7023
7024 if (r8168_check_dash(tp))
7025 rtl8168_driver_stop(tp);
7026
7027 netif_napi_del(&tp->napi);
7028
7029 unregister_netdev(dev);
7030 mdiobus_unregister(tp->mii_bus);
7031
7032 rtl_release_firmware(tp);
7033
7034 if (pci_dev_run_wake(pdev))
7035 pm_runtime_get_noresume(&pdev->dev);
7036
7037 /* restore original MAC address */
7038 rtl_rar_set(tp, dev->perm_addr);
7039 }
7040
7041 static const struct net_device_ops rtl_netdev_ops = {
7042 .ndo_open = rtl_open,
7043 .ndo_stop = rtl8169_close,
7044 .ndo_get_stats64 = rtl8169_get_stats64,
7045 .ndo_start_xmit = rtl8169_start_xmit,
7046 .ndo_tx_timeout = rtl8169_tx_timeout,
7047 .ndo_validate_addr = eth_validate_addr,
7048 .ndo_change_mtu = rtl8169_change_mtu,
7049 .ndo_fix_features = rtl8169_fix_features,
7050 .ndo_set_features = rtl8169_set_features,
7051 .ndo_set_mac_address = rtl_set_mac_address,
7052 .ndo_do_ioctl = rtl8169_ioctl,
7053 .ndo_set_rx_mode = rtl_set_rx_mode,
7054 #ifdef CONFIG_NET_POLL_CONTROLLER
7055 .ndo_poll_controller = rtl8169_netpoll,
7056 #endif
7057
7058 };
7059
7060 static const struct rtl_cfg_info {
7061 void (*hw_start)(struct rtl8169_private *tp);
7062 u16 event_slow;
7063 unsigned int has_gmii:1;
7064 const struct rtl_coalesce_info *coalesce_info;
7065 u8 default_ver;
7066 } rtl_cfg_infos [] = {
7067 [RTL_CFG_0] = {
7068 .hw_start = rtl_hw_start_8169,
7069 .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver,
7070 .has_gmii = 1,
7071 .coalesce_info = rtl_coalesce_info_8169,
7072 .default_ver = RTL_GIGA_MAC_VER_01,
7073 },
7074 [RTL_CFG_1] = {
7075 .hw_start = rtl_hw_start_8168,
7076 .event_slow = SYSErr | LinkChg | RxOverflow,
7077 .has_gmii = 1,
7078 .coalesce_info = rtl_coalesce_info_8168_8136,
7079 .default_ver = RTL_GIGA_MAC_VER_11,
7080 },
7081 [RTL_CFG_2] = {
7082 .hw_start = rtl_hw_start_8101,
7083 .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver |
7084 PCSTimeout,
7085 .coalesce_info = rtl_coalesce_info_8168_8136,
7086 .default_ver = RTL_GIGA_MAC_VER_13,
7087 }
7088 };
7089
rtl_alloc_irq(struct rtl8169_private * tp)7090 static int rtl_alloc_irq(struct rtl8169_private *tp)
7091 {
7092 unsigned int flags;
7093
7094 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
7095 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
7096 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable);
7097 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
7098 flags = PCI_IRQ_LEGACY;
7099 } else {
7100 flags = PCI_IRQ_ALL_TYPES;
7101 }
7102
7103 return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags);
7104 }
7105
DECLARE_RTL_COND(rtl_link_list_ready_cond)7106 DECLARE_RTL_COND(rtl_link_list_ready_cond)
7107 {
7108 return RTL_R8(tp, MCU) & LINK_LIST_RDY;
7109 }
7110
DECLARE_RTL_COND(rtl_rxtx_empty_cond)7111 DECLARE_RTL_COND(rtl_rxtx_empty_cond)
7112 {
7113 return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY;
7114 }
7115
r8169_mdio_read_reg(struct mii_bus * mii_bus,int phyaddr,int phyreg)7116 static int r8169_mdio_read_reg(struct mii_bus *mii_bus, int phyaddr, int phyreg)
7117 {
7118 struct rtl8169_private *tp = mii_bus->priv;
7119
7120 if (phyaddr > 0)
7121 return -ENODEV;
7122
7123 return rtl_readphy(tp, phyreg);
7124 }
7125
r8169_mdio_write_reg(struct mii_bus * mii_bus,int phyaddr,int phyreg,u16 val)7126 static int r8169_mdio_write_reg(struct mii_bus *mii_bus, int phyaddr,
7127 int phyreg, u16 val)
7128 {
7129 struct rtl8169_private *tp = mii_bus->priv;
7130
7131 if (phyaddr > 0)
7132 return -ENODEV;
7133
7134 rtl_writephy(tp, phyreg, val);
7135
7136 return 0;
7137 }
7138
r8169_mdio_register(struct rtl8169_private * tp)7139 static int r8169_mdio_register(struct rtl8169_private *tp)
7140 {
7141 struct pci_dev *pdev = tp->pci_dev;
7142 struct phy_device *phydev;
7143 struct mii_bus *new_bus;
7144 int ret;
7145
7146 new_bus = devm_mdiobus_alloc(&pdev->dev);
7147 if (!new_bus)
7148 return -ENOMEM;
7149
7150 new_bus->name = "r8169";
7151 new_bus->priv = tp;
7152 new_bus->parent = &pdev->dev;
7153 new_bus->irq[0] = PHY_IGNORE_INTERRUPT;
7154 snprintf(new_bus->id, MII_BUS_ID_SIZE, "r8169-%x",
7155 PCI_DEVID(pdev->bus->number, pdev->devfn));
7156
7157 new_bus->read = r8169_mdio_read_reg;
7158 new_bus->write = r8169_mdio_write_reg;
7159
7160 ret = mdiobus_register(new_bus);
7161 if (ret)
7162 return ret;
7163
7164 phydev = mdiobus_get_phy(new_bus, 0);
7165 if (!phydev) {
7166 mdiobus_unregister(new_bus);
7167 return -ENODEV;
7168 }
7169
7170 /* PHY will be woken up in rtl_open() */
7171 phy_suspend(phydev);
7172
7173 tp->mii_bus = new_bus;
7174
7175 return 0;
7176 }
7177
rtl_hw_init_8168g(struct rtl8169_private * tp)7178 static void rtl_hw_init_8168g(struct rtl8169_private *tp)
7179 {
7180 u32 data;
7181
7182 tp->ocp_base = OCP_STD_PHY_BASE;
7183
7184 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN);
7185
7186 if (!rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42))
7187 return;
7188
7189 if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42))
7190 return;
7191
7192 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
7193 msleep(1);
7194 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
7195
7196 data = r8168_mac_ocp_read(tp, 0xe8de);
7197 data &= ~(1 << 14);
7198 r8168_mac_ocp_write(tp, 0xe8de, data);
7199
7200 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
7201 return;
7202
7203 data = r8168_mac_ocp_read(tp, 0xe8de);
7204 data |= (1 << 15);
7205 r8168_mac_ocp_write(tp, 0xe8de, data);
7206
7207 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
7208 return;
7209 }
7210
rtl_hw_init_8168ep(struct rtl8169_private * tp)7211 static void rtl_hw_init_8168ep(struct rtl8169_private *tp)
7212 {
7213 rtl8168ep_stop_cmac(tp);
7214 rtl_hw_init_8168g(tp);
7215 }
7216
rtl_hw_initialize(struct rtl8169_private * tp)7217 static void rtl_hw_initialize(struct rtl8169_private *tp)
7218 {
7219 switch (tp->mac_version) {
7220 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48:
7221 rtl_hw_init_8168g(tp);
7222 break;
7223 case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_51:
7224 rtl_hw_init_8168ep(tp);
7225 break;
7226 default:
7227 break;
7228 }
7229 }
7230
7231 /* Versions RTL8102e and from RTL8168c onwards support csum_v2 */
rtl_chip_supports_csum_v2(struct rtl8169_private * tp)7232 static bool rtl_chip_supports_csum_v2(struct rtl8169_private *tp)
7233 {
7234 switch (tp->mac_version) {
7235 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
7236 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
7237 return false;
7238 default:
7239 return true;
7240 }
7241 }
7242
rtl_jumbo_max(struct rtl8169_private * tp)7243 static int rtl_jumbo_max(struct rtl8169_private *tp)
7244 {
7245 /* Non-GBit versions don't support jumbo frames */
7246 if (!tp->supports_gmii)
7247 return JUMBO_1K;
7248
7249 switch (tp->mac_version) {
7250 /* RTL8169 */
7251 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
7252 return JUMBO_7K;
7253 /* RTL8168b */
7254 case RTL_GIGA_MAC_VER_11:
7255 case RTL_GIGA_MAC_VER_12:
7256 case RTL_GIGA_MAC_VER_17:
7257 return JUMBO_4K;
7258 /* RTL8168c */
7259 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
7260 return JUMBO_6K;
7261 default:
7262 return JUMBO_9K;
7263 }
7264 }
7265
rtl_disable_clk(void * data)7266 static void rtl_disable_clk(void *data)
7267 {
7268 clk_disable_unprepare(data);
7269 }
7270
rtl_init_one(struct pci_dev * pdev,const struct pci_device_id * ent)7271 static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
7272 {
7273 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
7274 struct rtl8169_private *tp;
7275 struct net_device *dev;
7276 int chipset, region, i;
7277 int jumbo_max, rc;
7278
7279 dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp));
7280 if (!dev)
7281 return -ENOMEM;
7282
7283 SET_NETDEV_DEV(dev, &pdev->dev);
7284 dev->netdev_ops = &rtl_netdev_ops;
7285 tp = netdev_priv(dev);
7286 tp->dev = dev;
7287 tp->pci_dev = pdev;
7288 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
7289 tp->supports_gmii = cfg->has_gmii;
7290
7291 /* Get the *optional* external "ether_clk" used on some boards */
7292 tp->clk = devm_clk_get(&pdev->dev, "ether_clk");
7293 if (IS_ERR(tp->clk)) {
7294 rc = PTR_ERR(tp->clk);
7295 if (rc == -ENOENT) {
7296 /* clk-core allows NULL (for suspend / resume) */
7297 tp->clk = NULL;
7298 } else if (rc == -EPROBE_DEFER) {
7299 return rc;
7300 } else {
7301 dev_err(&pdev->dev, "failed to get clk: %d\n", rc);
7302 return rc;
7303 }
7304 } else {
7305 rc = clk_prepare_enable(tp->clk);
7306 if (rc) {
7307 dev_err(&pdev->dev, "failed to enable clk: %d\n", rc);
7308 return rc;
7309 }
7310
7311 rc = devm_add_action_or_reset(&pdev->dev, rtl_disable_clk,
7312 tp->clk);
7313 if (rc)
7314 return rc;
7315 }
7316
7317 /* enable device (incl. PCI PM wakeup and hotplug setup) */
7318 rc = pcim_enable_device(pdev);
7319 if (rc < 0) {
7320 dev_err(&pdev->dev, "enable failure\n");
7321 return rc;
7322 }
7323
7324 if (pcim_set_mwi(pdev) < 0)
7325 dev_info(&pdev->dev, "Mem-Wr-Inval unavailable\n");
7326
7327 /* use first MMIO region */
7328 region = ffs(pci_select_bars(pdev, IORESOURCE_MEM)) - 1;
7329 if (region < 0) {
7330 dev_err(&pdev->dev, "no MMIO resource found\n");
7331 return -ENODEV;
7332 }
7333
7334 /* check for weird/broken PCI region reporting */
7335 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
7336 dev_err(&pdev->dev, "Invalid PCI region size(s), aborting\n");
7337 return -ENODEV;
7338 }
7339
7340 rc = pcim_iomap_regions(pdev, BIT(region), MODULENAME);
7341 if (rc < 0) {
7342 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
7343 return rc;
7344 }
7345
7346 tp->mmio_addr = pcim_iomap_table(pdev)[region];
7347
7348 if (!pci_is_pcie(pdev))
7349 dev_info(&pdev->dev, "not PCI Express\n");
7350
7351 /* Identify chip attached to board */
7352 rtl8169_get_mac_version(tp, cfg->default_ver);
7353
7354 if (rtl_tbi_enabled(tp)) {
7355 dev_err(&pdev->dev, "TBI fiber mode not supported\n");
7356 return -ENODEV;
7357 }
7358
7359 tp->cp_cmd = RTL_R16(tp, CPlusCmd);
7360
7361 if ((sizeof(dma_addr_t) > 4) &&
7362 (use_dac == 1 || (use_dac == -1 && pci_is_pcie(pdev) &&
7363 tp->mac_version >= RTL_GIGA_MAC_VER_18)) &&
7364 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) &&
7365 !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
7366
7367 /* CPlusCmd Dual Access Cycle is only needed for non-PCIe */
7368 if (!pci_is_pcie(pdev))
7369 tp->cp_cmd |= PCIDAC;
7370 dev->features |= NETIF_F_HIGHDMA;
7371 } else {
7372 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
7373 if (rc < 0) {
7374 dev_err(&pdev->dev, "DMA configuration failed\n");
7375 return rc;
7376 }
7377 }
7378
7379 rtl_init_rxcfg(tp);
7380
7381 rtl_irq_disable(tp);
7382
7383 rtl_hw_initialize(tp);
7384
7385 rtl_hw_reset(tp);
7386
7387 rtl_ack_events(tp, 0xffff);
7388
7389 pci_set_master(pdev);
7390
7391 rtl_init_mdio_ops(tp);
7392 rtl_init_jumbo_ops(tp);
7393
7394 rtl8169_print_mac_version(tp);
7395
7396 chipset = tp->mac_version;
7397
7398 rc = rtl_alloc_irq(tp);
7399 if (rc < 0) {
7400 dev_err(&pdev->dev, "Can't allocate interrupt\n");
7401 return rc;
7402 }
7403
7404 tp->saved_wolopts = __rtl8169_get_wol(tp);
7405
7406 mutex_init(&tp->wk.mutex);
7407 u64_stats_init(&tp->rx_stats.syncp);
7408 u64_stats_init(&tp->tx_stats.syncp);
7409
7410 /* Get MAC address */
7411 switch (tp->mac_version) {
7412 u8 mac_addr[ETH_ALEN] __aligned(4);
7413 case RTL_GIGA_MAC_VER_35 ... RTL_GIGA_MAC_VER_38:
7414 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
7415 *(u32 *)&mac_addr[0] = rtl_eri_read(tp, 0xe0, ERIAR_EXGMAC);
7416 *(u16 *)&mac_addr[4] = rtl_eri_read(tp, 0xe4, ERIAR_EXGMAC);
7417
7418 if (is_valid_ether_addr(mac_addr))
7419 rtl_rar_set(tp, mac_addr);
7420 break;
7421 default:
7422 break;
7423 }
7424 for (i = 0; i < ETH_ALEN; i++)
7425 dev->dev_addr[i] = RTL_R8(tp, MAC0 + i);
7426
7427 dev->ethtool_ops = &rtl8169_ethtool_ops;
7428 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
7429
7430 netif_napi_add(dev, &tp->napi, rtl8169_poll, NAPI_POLL_WEIGHT);
7431
7432 /* don't enable SG, IP_CSUM and TSO by default - it might not work
7433 * properly for all devices */
7434 dev->features |= NETIF_F_RXCSUM |
7435 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
7436
7437 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
7438 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX |
7439 NETIF_F_HW_VLAN_CTAG_RX;
7440 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
7441 NETIF_F_HIGHDMA;
7442 dev->priv_flags |= IFF_LIVE_ADDR_CHANGE;
7443
7444 tp->cp_cmd |= RxChkSum | RxVlan;
7445
7446 /*
7447 * Pretend we are using VLANs; This bypasses a nasty bug where
7448 * Interrupts stop flowing on high load on 8110SCd controllers.
7449 */
7450 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
7451 /* Disallow toggling */
7452 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX;
7453
7454 if (rtl_chip_supports_csum_v2(tp)) {
7455 tp->tso_csum = rtl8169_tso_csum_v2;
7456 dev->hw_features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
7457 } else {
7458 tp->tso_csum = rtl8169_tso_csum_v1;
7459 }
7460
7461 dev->hw_features |= NETIF_F_RXALL;
7462 dev->hw_features |= NETIF_F_RXFCS;
7463
7464 /* MTU range: 60 - hw-specific max */
7465 dev->min_mtu = ETH_ZLEN;
7466 jumbo_max = rtl_jumbo_max(tp);
7467 dev->max_mtu = jumbo_max;
7468
7469 tp->hw_start = cfg->hw_start;
7470 tp->event_slow = cfg->event_slow;
7471 tp->coalesce_info = cfg->coalesce_info;
7472
7473 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
7474
7475 tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters),
7476 &tp->counters_phys_addr,
7477 GFP_KERNEL);
7478 if (!tp->counters)
7479 return -ENOMEM;
7480
7481 pci_set_drvdata(pdev, dev);
7482
7483 rc = r8169_mdio_register(tp);
7484 if (rc)
7485 return rc;
7486
7487 /* chip gets powered up in rtl_open() */
7488 rtl_pll_power_down(tp);
7489
7490 rc = register_netdev(dev);
7491 if (rc)
7492 goto err_mdio_unregister;
7493
7494 netif_info(tp, probe, dev, "%s, %pM, XID %08x, IRQ %d\n",
7495 rtl_chip_infos[chipset].name, dev->dev_addr,
7496 (u32)(RTL_R32(tp, TxConfig) & 0xfcf0f8ff),
7497 pci_irq_vector(pdev, 0));
7498
7499 if (jumbo_max > JUMBO_1K)
7500 netif_info(tp, probe, dev,
7501 "jumbo features [frames: %d bytes, tx checksumming: %s]\n",
7502 jumbo_max, tp->mac_version <= RTL_GIGA_MAC_VER_06 ?
7503 "ok" : "ko");
7504
7505 if (r8168_check_dash(tp))
7506 rtl8168_driver_start(tp);
7507
7508 if (pci_dev_run_wake(pdev))
7509 pm_runtime_put_sync(&pdev->dev);
7510
7511 return 0;
7512
7513 err_mdio_unregister:
7514 mdiobus_unregister(tp->mii_bus);
7515 return rc;
7516 }
7517
7518 static struct pci_driver rtl8169_pci_driver = {
7519 .name = MODULENAME,
7520 .id_table = rtl8169_pci_tbl,
7521 .probe = rtl_init_one,
7522 .remove = rtl_remove_one,
7523 .shutdown = rtl_shutdown,
7524 .driver.pm = RTL8169_PM_OPS,
7525 };
7526
7527 module_pci_driver(rtl8169_pci_driver);
7528
