1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * RDC R6040 Fast Ethernet MAC support
4 *
5 * Copyright (C) 2004 Sten Wang <sten.wang@rdc.com.tw>
6 * Copyright (C) 2007
7 * Daniel Gimpelevich <daniel@gimpelevich.san-francisco.ca.us>
8 * Copyright (C) 2007-2012 Florian Fainelli <f.fainelli@gmail.com>
9 */
10
11 #include <linux/kernel.h>
12 #include <linux/module.h>
13 #include <linux/moduleparam.h>
14 #include <linux/string.h>
15 #include <linux/timer.h>
16 #include <linux/errno.h>
17 #include <linux/ioport.h>
18 #include <linux/interrupt.h>
19 #include <linux/pci.h>
20 #include <linux/netdevice.h>
21 #include <linux/etherdevice.h>
22 #include <linux/skbuff.h>
23 #include <linux/delay.h>
24 #include <linux/mii.h>
25 #include <linux/ethtool.h>
26 #include <linux/crc32.h>
27 #include <linux/spinlock.h>
28 #include <linux/bitops.h>
29 #include <linux/io.h>
30 #include <linux/irq.h>
31 #include <linux/uaccess.h>
32 #include <linux/phy.h>
33
34 #include <asm/processor.h>
35
36 #define DRV_NAME "r6040"
37 #define DRV_VERSION "0.29"
38 #define DRV_RELDATE "04Jul2016"
39
40 /* Time in jiffies before concluding the transmitter is hung. */
41 #define TX_TIMEOUT (6000 * HZ / 1000)
42
43 /* RDC MAC I/O Size */
44 #define R6040_IO_SIZE 256
45
46 /* MAX RDC MAC */
47 #define MAX_MAC 2
48
49 /* MAC registers */
50 #define MCR0 0x00 /* Control register 0 */
51 #define MCR0_RCVEN 0x0002 /* Receive enable */
52 #define MCR0_PROMISC 0x0020 /* Promiscuous mode */
53 #define MCR0_HASH_EN 0x0100 /* Enable multicast hash table function */
54 #define MCR0_XMTEN 0x1000 /* Transmission enable */
55 #define MCR0_FD 0x8000 /* Full/Half duplex */
56 #define MCR1 0x04 /* Control register 1 */
57 #define MAC_RST 0x0001 /* Reset the MAC */
58 #define MBCR 0x08 /* Bus control */
59 #define MT_ICR 0x0C /* TX interrupt control */
60 #define MR_ICR 0x10 /* RX interrupt control */
61 #define MTPR 0x14 /* TX poll command register */
62 #define TM2TX 0x0001 /* Trigger MAC to transmit */
63 #define MR_BSR 0x18 /* RX buffer size */
64 #define MR_DCR 0x1A /* RX descriptor control */
65 #define MLSR 0x1C /* Last status */
66 #define TX_FIFO_UNDR 0x0200 /* TX FIFO under-run */
67 #define TX_EXCEEDC 0x2000 /* Transmit exceed collision */
68 #define TX_LATEC 0x4000 /* Transmit late collision */
69 #define MMDIO 0x20 /* MDIO control register */
70 #define MDIO_WRITE 0x4000 /* MDIO write */
71 #define MDIO_READ 0x2000 /* MDIO read */
72 #define MMRD 0x24 /* MDIO read data register */
73 #define MMWD 0x28 /* MDIO write data register */
74 #define MTD_SA0 0x2C /* TX descriptor start address 0 */
75 #define MTD_SA1 0x30 /* TX descriptor start address 1 */
76 #define MRD_SA0 0x34 /* RX descriptor start address 0 */
77 #define MRD_SA1 0x38 /* RX descriptor start address 1 */
78 #define MISR 0x3C /* Status register */
79 #define MIER 0x40 /* INT enable register */
80 #define MSK_INT 0x0000 /* Mask off interrupts */
81 #define RX_FINISH 0x0001 /* RX finished */
82 #define RX_NO_DESC 0x0002 /* No RX descriptor available */
83 #define RX_FIFO_FULL 0x0004 /* RX FIFO full */
84 #define RX_EARLY 0x0008 /* RX early */
85 #define TX_FINISH 0x0010 /* TX finished */
86 #define TX_EARLY 0x0080 /* TX early */
87 #define EVENT_OVRFL 0x0100 /* Event counter overflow */
88 #define LINK_CHANGED 0x0200 /* PHY link changed */
89 #define ME_CISR 0x44 /* Event counter INT status */
90 #define ME_CIER 0x48 /* Event counter INT enable */
91 #define MR_CNT 0x50 /* Successfully received packet counter */
92 #define ME_CNT0 0x52 /* Event counter 0 */
93 #define ME_CNT1 0x54 /* Event counter 1 */
94 #define ME_CNT2 0x56 /* Event counter 2 */
95 #define ME_CNT3 0x58 /* Event counter 3 */
96 #define MT_CNT 0x5A /* Successfully transmit packet counter */
97 #define ME_CNT4 0x5C /* Event counter 4 */
98 #define MP_CNT 0x5E /* Pause frame counter register */
99 #define MAR0 0x60 /* Hash table 0 */
100 #define MAR1 0x62 /* Hash table 1 */
101 #define MAR2 0x64 /* Hash table 2 */
102 #define MAR3 0x66 /* Hash table 3 */
103 #define MID_0L 0x68 /* Multicast address MID0 Low */
104 #define MID_0M 0x6A /* Multicast address MID0 Medium */
105 #define MID_0H 0x6C /* Multicast address MID0 High */
106 #define MID_1L 0x70 /* MID1 Low */
107 #define MID_1M 0x72 /* MID1 Medium */
108 #define MID_1H 0x74 /* MID1 High */
109 #define MID_2L 0x78 /* MID2 Low */
110 #define MID_2M 0x7A /* MID2 Medium */
111 #define MID_2H 0x7C /* MID2 High */
112 #define MID_3L 0x80 /* MID3 Low */
113 #define MID_3M 0x82 /* MID3 Medium */
114 #define MID_3H 0x84 /* MID3 High */
115 #define PHY_CC 0x88 /* PHY status change configuration register */
116 #define SCEN 0x8000 /* PHY status change enable */
117 #define PHYAD_SHIFT 8 /* PHY address shift */
118 #define TMRDIV_SHIFT 0 /* Timer divider shift */
119 #define PHY_ST 0x8A /* PHY status register */
120 #define MAC_SM 0xAC /* MAC status machine */
121 #define MAC_SM_RST 0x0002 /* MAC status machine reset */
122 #define MAC_ID 0xBE /* Identifier register */
123
124 #define TX_DCNT 0x80 /* TX descriptor count */
125 #define RX_DCNT 0x80 /* RX descriptor count */
126 #define MAX_BUF_SIZE 0x600
127 #define RX_DESC_SIZE (RX_DCNT * sizeof(struct r6040_descriptor))
128 #define TX_DESC_SIZE (TX_DCNT * sizeof(struct r6040_descriptor))
129 #define MBCR_DEFAULT 0x012A /* MAC Bus Control Register */
130 #define MCAST_MAX 3 /* Max number multicast addresses to filter */
131
132 #define MAC_DEF_TIMEOUT 2048 /* Default MAC read/write operation timeout */
133
134 /* Descriptor status */
135 #define DSC_OWNER_MAC 0x8000 /* MAC is the owner of this descriptor */
136 #define DSC_RX_OK 0x4000 /* RX was successful */
137 #define DSC_RX_ERR 0x0800 /* RX PHY error */
138 #define DSC_RX_ERR_DRI 0x0400 /* RX dribble packet */
139 #define DSC_RX_ERR_BUF 0x0200 /* RX length exceeds buffer size */
140 #define DSC_RX_ERR_LONG 0x0100 /* RX length > maximum packet length */
141 #define DSC_RX_ERR_RUNT 0x0080 /* RX packet length < 64 byte */
142 #define DSC_RX_ERR_CRC 0x0040 /* RX CRC error */
143 #define DSC_RX_BCAST 0x0020 /* RX broadcast (no error) */
144 #define DSC_RX_MCAST 0x0010 /* RX multicast (no error) */
145 #define DSC_RX_MCH_HIT 0x0008 /* RX multicast hit in hash table (no error) */
146 #define DSC_RX_MIDH_HIT 0x0004 /* RX MID table hit (no error) */
147 #define DSC_RX_IDX_MID_MASK 3 /* RX mask for the index of matched MIDx */
148
149 MODULE_AUTHOR("Sten Wang <sten.wang@rdc.com.tw>,"
150 "Daniel Gimpelevich <daniel@gimpelevich.san-francisco.ca.us>,"
151 "Florian Fainelli <f.fainelli@gmail.com>");
152 MODULE_LICENSE("GPL");
153 MODULE_DESCRIPTION("RDC R6040 NAPI PCI FastEthernet driver");
154 MODULE_VERSION(DRV_VERSION " " DRV_RELDATE);
155
156 /* RX and TX interrupts that we handle */
157 #define RX_INTS (RX_FIFO_FULL | RX_NO_DESC | RX_FINISH)
158 #define TX_INTS (TX_FINISH)
159 #define INT_MASK (RX_INTS | TX_INTS)
160
161 struct r6040_descriptor {
162 u16 status, len; /* 0-3 */
163 __le32 buf; /* 4-7 */
164 __le32 ndesc; /* 8-B */
165 u32 rev1; /* C-F */
166 char *vbufp; /* 10-13 */
167 struct r6040_descriptor *vndescp; /* 14-17 */
168 struct sk_buff *skb_ptr; /* 18-1B */
169 u32 rev2; /* 1C-1F */
170 } __aligned(32);
171
172 struct r6040_private {
173 spinlock_t lock; /* driver lock */
174 struct pci_dev *pdev;
175 struct r6040_descriptor *rx_insert_ptr;
176 struct r6040_descriptor *rx_remove_ptr;
177 struct r6040_descriptor *tx_insert_ptr;
178 struct r6040_descriptor *tx_remove_ptr;
179 struct r6040_descriptor *rx_ring;
180 struct r6040_descriptor *tx_ring;
181 dma_addr_t rx_ring_dma;
182 dma_addr_t tx_ring_dma;
183 u16 tx_free_desc;
184 u16 mcr0;
185 struct net_device *dev;
186 struct mii_bus *mii_bus;
187 struct napi_struct napi;
188 void __iomem *base;
189 int old_link;
190 int old_duplex;
191 };
192
193 static char version[] = DRV_NAME
194 ": RDC R6040 NAPI net driver,"
195 "version "DRV_VERSION " (" DRV_RELDATE ")";
196
197 /* Read a word data from PHY Chip */
r6040_phy_read(void __iomem * ioaddr,int phy_addr,int reg)198 static int r6040_phy_read(void __iomem *ioaddr, int phy_addr, int reg)
199 {
200 int limit = MAC_DEF_TIMEOUT;
201 u16 cmd;
202
203 iowrite16(MDIO_READ + reg + (phy_addr << 8), ioaddr + MMDIO);
204 /* Wait for the read bit to be cleared */
205 while (limit--) {
206 cmd = ioread16(ioaddr + MMDIO);
207 if (!(cmd & MDIO_READ))
208 break;
209 udelay(1);
210 }
211
212 if (limit < 0)
213 return -ETIMEDOUT;
214
215 return ioread16(ioaddr + MMRD);
216 }
217
218 /* Write a word data from PHY Chip */
r6040_phy_write(void __iomem * ioaddr,int phy_addr,int reg,u16 val)219 static int r6040_phy_write(void __iomem *ioaddr,
220 int phy_addr, int reg, u16 val)
221 {
222 int limit = MAC_DEF_TIMEOUT;
223 u16 cmd;
224
225 iowrite16(val, ioaddr + MMWD);
226 /* Write the command to the MDIO bus */
227 iowrite16(MDIO_WRITE + reg + (phy_addr << 8), ioaddr + MMDIO);
228 /* Wait for the write bit to be cleared */
229 while (limit--) {
230 cmd = ioread16(ioaddr + MMDIO);
231 if (!(cmd & MDIO_WRITE))
232 break;
233 udelay(1);
234 }
235
236 return (limit < 0) ? -ETIMEDOUT : 0;
237 }
238
r6040_mdiobus_read(struct mii_bus * bus,int phy_addr,int reg)239 static int r6040_mdiobus_read(struct mii_bus *bus, int phy_addr, int reg)
240 {
241 struct net_device *dev = bus->priv;
242 struct r6040_private *lp = netdev_priv(dev);
243 void __iomem *ioaddr = lp->base;
244
245 return r6040_phy_read(ioaddr, phy_addr, reg);
246 }
247
r6040_mdiobus_write(struct mii_bus * bus,int phy_addr,int reg,u16 value)248 static int r6040_mdiobus_write(struct mii_bus *bus, int phy_addr,
249 int reg, u16 value)
250 {
251 struct net_device *dev = bus->priv;
252 struct r6040_private *lp = netdev_priv(dev);
253 void __iomem *ioaddr = lp->base;
254
255 return r6040_phy_write(ioaddr, phy_addr, reg, value);
256 }
257
r6040_free_txbufs(struct net_device * dev)258 static void r6040_free_txbufs(struct net_device *dev)
259 {
260 struct r6040_private *lp = netdev_priv(dev);
261 int i;
262
263 for (i = 0; i < TX_DCNT; i++) {
264 if (lp->tx_insert_ptr->skb_ptr) {
265 pci_unmap_single(lp->pdev,
266 le32_to_cpu(lp->tx_insert_ptr->buf),
267 MAX_BUF_SIZE, PCI_DMA_TODEVICE);
268 dev_kfree_skb(lp->tx_insert_ptr->skb_ptr);
269 lp->tx_insert_ptr->skb_ptr = NULL;
270 }
271 lp->tx_insert_ptr = lp->tx_insert_ptr->vndescp;
272 }
273 }
274
r6040_free_rxbufs(struct net_device * dev)275 static void r6040_free_rxbufs(struct net_device *dev)
276 {
277 struct r6040_private *lp = netdev_priv(dev);
278 int i;
279
280 for (i = 0; i < RX_DCNT; i++) {
281 if (lp->rx_insert_ptr->skb_ptr) {
282 pci_unmap_single(lp->pdev,
283 le32_to_cpu(lp->rx_insert_ptr->buf),
284 MAX_BUF_SIZE, PCI_DMA_FROMDEVICE);
285 dev_kfree_skb(lp->rx_insert_ptr->skb_ptr);
286 lp->rx_insert_ptr->skb_ptr = NULL;
287 }
288 lp->rx_insert_ptr = lp->rx_insert_ptr->vndescp;
289 }
290 }
291
r6040_init_ring_desc(struct r6040_descriptor * desc_ring,dma_addr_t desc_dma,int size)292 static void r6040_init_ring_desc(struct r6040_descriptor *desc_ring,
293 dma_addr_t desc_dma, int size)
294 {
295 struct r6040_descriptor *desc = desc_ring;
296 dma_addr_t mapping = desc_dma;
297
298 while (size-- > 0) {
299 mapping += sizeof(*desc);
300 desc->ndesc = cpu_to_le32(mapping);
301 desc->vndescp = desc + 1;
302 desc++;
303 }
304 desc--;
305 desc->ndesc = cpu_to_le32(desc_dma);
306 desc->vndescp = desc_ring;
307 }
308
r6040_init_txbufs(struct net_device * dev)309 static void r6040_init_txbufs(struct net_device *dev)
310 {
311 struct r6040_private *lp = netdev_priv(dev);
312
313 lp->tx_free_desc = TX_DCNT;
314
315 lp->tx_remove_ptr = lp->tx_insert_ptr = lp->tx_ring;
316 r6040_init_ring_desc(lp->tx_ring, lp->tx_ring_dma, TX_DCNT);
317 }
318
r6040_alloc_rxbufs(struct net_device * dev)319 static int r6040_alloc_rxbufs(struct net_device *dev)
320 {
321 struct r6040_private *lp = netdev_priv(dev);
322 struct r6040_descriptor *desc;
323 struct sk_buff *skb;
324 int rc;
325
326 lp->rx_remove_ptr = lp->rx_insert_ptr = lp->rx_ring;
327 r6040_init_ring_desc(lp->rx_ring, lp->rx_ring_dma, RX_DCNT);
328
329 /* Allocate skbs for the rx descriptors */
330 desc = lp->rx_ring;
331 do {
332 skb = netdev_alloc_skb(dev, MAX_BUF_SIZE);
333 if (!skb) {
334 rc = -ENOMEM;
335 goto err_exit;
336 }
337 desc->skb_ptr = skb;
338 desc->buf = cpu_to_le32(pci_map_single(lp->pdev,
339 desc->skb_ptr->data,
340 MAX_BUF_SIZE, PCI_DMA_FROMDEVICE));
341 desc->status = DSC_OWNER_MAC;
342 desc = desc->vndescp;
343 } while (desc != lp->rx_ring);
344
345 return 0;
346
347 err_exit:
348 /* Deallocate all previously allocated skbs */
349 r6040_free_rxbufs(dev);
350 return rc;
351 }
352
r6040_reset_mac(struct r6040_private * lp)353 static void r6040_reset_mac(struct r6040_private *lp)
354 {
355 void __iomem *ioaddr = lp->base;
356 int limit = MAC_DEF_TIMEOUT;
357 u16 cmd;
358
359 iowrite16(MAC_RST, ioaddr + MCR1);
360 while (limit--) {
361 cmd = ioread16(ioaddr + MCR1);
362 if (cmd & MAC_RST)
363 break;
364 }
365
366 /* Reset internal state machine */
367 iowrite16(MAC_SM_RST, ioaddr + MAC_SM);
368 iowrite16(0, ioaddr + MAC_SM);
369 mdelay(5);
370 }
371
r6040_init_mac_regs(struct net_device * dev)372 static void r6040_init_mac_regs(struct net_device *dev)
373 {
374 struct r6040_private *lp = netdev_priv(dev);
375 void __iomem *ioaddr = lp->base;
376
377 /* Mask Off Interrupt */
378 iowrite16(MSK_INT, ioaddr + MIER);
379
380 /* Reset RDC MAC */
381 r6040_reset_mac(lp);
382
383 /* MAC Bus Control Register */
384 iowrite16(MBCR_DEFAULT, ioaddr + MBCR);
385
386 /* Buffer Size Register */
387 iowrite16(MAX_BUF_SIZE, ioaddr + MR_BSR);
388
389 /* Write TX ring start address */
390 iowrite16(lp->tx_ring_dma, ioaddr + MTD_SA0);
391 iowrite16(lp->tx_ring_dma >> 16, ioaddr + MTD_SA1);
392
393 /* Write RX ring start address */
394 iowrite16(lp->rx_ring_dma, ioaddr + MRD_SA0);
395 iowrite16(lp->rx_ring_dma >> 16, ioaddr + MRD_SA1);
396
397 /* Set interrupt waiting time and packet numbers */
398 iowrite16(0, ioaddr + MT_ICR);
399 iowrite16(0, ioaddr + MR_ICR);
400
401 /* Enable interrupts */
402 iowrite16(INT_MASK, ioaddr + MIER);
403
404 /* Enable TX and RX */
405 iowrite16(lp->mcr0 | MCR0_RCVEN, ioaddr);
406
407 /* Let TX poll the descriptors
408 * we may got called by r6040_tx_timeout which has left
409 * some unsent tx buffers */
410 iowrite16(TM2TX, ioaddr + MTPR);
411 }
412
r6040_tx_timeout(struct net_device * dev)413 static void r6040_tx_timeout(struct net_device *dev)
414 {
415 struct r6040_private *priv = netdev_priv(dev);
416 void __iomem *ioaddr = priv->base;
417
418 netdev_warn(dev, "transmit timed out, int enable %4.4x "
419 "status %4.4x\n",
420 ioread16(ioaddr + MIER),
421 ioread16(ioaddr + MISR));
422
423 dev->stats.tx_errors++;
424
425 /* Reset MAC and re-init all registers */
426 r6040_init_mac_regs(dev);
427 }
428
r6040_get_stats(struct net_device * dev)429 static struct net_device_stats *r6040_get_stats(struct net_device *dev)
430 {
431 struct r6040_private *priv = netdev_priv(dev);
432 void __iomem *ioaddr = priv->base;
433 unsigned long flags;
434
435 spin_lock_irqsave(&priv->lock, flags);
436 dev->stats.rx_crc_errors += ioread8(ioaddr + ME_CNT1);
437 dev->stats.multicast += ioread8(ioaddr + ME_CNT0);
438 spin_unlock_irqrestore(&priv->lock, flags);
439
440 return &dev->stats;
441 }
442
443 /* Stop RDC MAC and Free the allocated resource */
r6040_down(struct net_device * dev)444 static void r6040_down(struct net_device *dev)
445 {
446 struct r6040_private *lp = netdev_priv(dev);
447 void __iomem *ioaddr = lp->base;
448 u16 *adrp;
449
450 /* Stop MAC */
451 iowrite16(MSK_INT, ioaddr + MIER); /* Mask Off Interrupt */
452
453 /* Reset RDC MAC */
454 r6040_reset_mac(lp);
455
456 /* Restore MAC Address to MIDx */
457 adrp = (u16 *) dev->dev_addr;
458 iowrite16(adrp[0], ioaddr + MID_0L);
459 iowrite16(adrp[1], ioaddr + MID_0M);
460 iowrite16(adrp[2], ioaddr + MID_0H);
461 }
462
r6040_close(struct net_device * dev)463 static int r6040_close(struct net_device *dev)
464 {
465 struct r6040_private *lp = netdev_priv(dev);
466 struct pci_dev *pdev = lp->pdev;
467
468 phy_stop(dev->phydev);
469 napi_disable(&lp->napi);
470 netif_stop_queue(dev);
471
472 spin_lock_irq(&lp->lock);
473 r6040_down(dev);
474
475 /* Free RX buffer */
476 r6040_free_rxbufs(dev);
477
478 /* Free TX buffer */
479 r6040_free_txbufs(dev);
480
481 spin_unlock_irq(&lp->lock);
482
483 free_irq(dev->irq, dev);
484
485 /* Free Descriptor memory */
486 if (lp->rx_ring) {
487 pci_free_consistent(pdev,
488 RX_DESC_SIZE, lp->rx_ring, lp->rx_ring_dma);
489 lp->rx_ring = NULL;
490 }
491
492 if (lp->tx_ring) {
493 pci_free_consistent(pdev,
494 TX_DESC_SIZE, lp->tx_ring, lp->tx_ring_dma);
495 lp->tx_ring = NULL;
496 }
497
498 return 0;
499 }
500
r6040_ioctl(struct net_device * dev,struct ifreq * rq,int cmd)501 static int r6040_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
502 {
503 if (!dev->phydev)
504 return -EINVAL;
505
506 return phy_mii_ioctl(dev->phydev, rq, cmd);
507 }
508
r6040_rx(struct net_device * dev,int limit)509 static int r6040_rx(struct net_device *dev, int limit)
510 {
511 struct r6040_private *priv = netdev_priv(dev);
512 struct r6040_descriptor *descptr = priv->rx_remove_ptr;
513 struct sk_buff *skb_ptr, *new_skb;
514 int count = 0;
515 u16 err;
516
517 /* Limit not reached and the descriptor belongs to the CPU */
518 while (count < limit && !(descptr->status & DSC_OWNER_MAC)) {
519 /* Read the descriptor status */
520 err = descptr->status;
521 /* Global error status set */
522 if (err & DSC_RX_ERR) {
523 /* RX dribble */
524 if (err & DSC_RX_ERR_DRI)
525 dev->stats.rx_frame_errors++;
526 /* Buffer length exceeded */
527 if (err & DSC_RX_ERR_BUF)
528 dev->stats.rx_length_errors++;
529 /* Packet too long */
530 if (err & DSC_RX_ERR_LONG)
531 dev->stats.rx_length_errors++;
532 /* Packet < 64 bytes */
533 if (err & DSC_RX_ERR_RUNT)
534 dev->stats.rx_length_errors++;
535 /* CRC error */
536 if (err & DSC_RX_ERR_CRC) {
537 spin_lock(&priv->lock);
538 dev->stats.rx_crc_errors++;
539 spin_unlock(&priv->lock);
540 }
541 goto next_descr;
542 }
543
544 /* Packet successfully received */
545 new_skb = netdev_alloc_skb(dev, MAX_BUF_SIZE);
546 if (!new_skb) {
547 dev->stats.rx_dropped++;
548 goto next_descr;
549 }
550 skb_ptr = descptr->skb_ptr;
551 skb_ptr->dev = priv->dev;
552
553 /* Do not count the CRC */
554 skb_put(skb_ptr, descptr->len - 4);
555 pci_unmap_single(priv->pdev, le32_to_cpu(descptr->buf),
556 MAX_BUF_SIZE, PCI_DMA_FROMDEVICE);
557 skb_ptr->protocol = eth_type_trans(skb_ptr, priv->dev);
558
559 /* Send to upper layer */
560 netif_receive_skb(skb_ptr);
561 dev->stats.rx_packets++;
562 dev->stats.rx_bytes += descptr->len - 4;
563
564 /* put new skb into descriptor */
565 descptr->skb_ptr = new_skb;
566 descptr->buf = cpu_to_le32(pci_map_single(priv->pdev,
567 descptr->skb_ptr->data,
568 MAX_BUF_SIZE, PCI_DMA_FROMDEVICE));
569
570 next_descr:
571 /* put the descriptor back to the MAC */
572 descptr->status = DSC_OWNER_MAC;
573 descptr = descptr->vndescp;
574 count++;
575 }
576 priv->rx_remove_ptr = descptr;
577
578 return count;
579 }
580
r6040_tx(struct net_device * dev)581 static void r6040_tx(struct net_device *dev)
582 {
583 struct r6040_private *priv = netdev_priv(dev);
584 struct r6040_descriptor *descptr;
585 void __iomem *ioaddr = priv->base;
586 struct sk_buff *skb_ptr;
587 u16 err;
588
589 spin_lock(&priv->lock);
590 descptr = priv->tx_remove_ptr;
591 while (priv->tx_free_desc < TX_DCNT) {
592 /* Check for errors */
593 err = ioread16(ioaddr + MLSR);
594
595 if (err & TX_FIFO_UNDR)
596 dev->stats.tx_fifo_errors++;
597 if (err & (TX_EXCEEDC | TX_LATEC))
598 dev->stats.tx_carrier_errors++;
599
600 if (descptr->status & DSC_OWNER_MAC)
601 break; /* Not complete */
602 skb_ptr = descptr->skb_ptr;
603
604 /* Statistic Counter */
605 dev->stats.tx_packets++;
606 dev->stats.tx_bytes += skb_ptr->len;
607
608 pci_unmap_single(priv->pdev, le32_to_cpu(descptr->buf),
609 skb_ptr->len, PCI_DMA_TODEVICE);
610 /* Free buffer */
611 dev_kfree_skb(skb_ptr);
612 descptr->skb_ptr = NULL;
613 /* To next descriptor */
614 descptr = descptr->vndescp;
615 priv->tx_free_desc++;
616 }
617 priv->tx_remove_ptr = descptr;
618
619 if (priv->tx_free_desc)
620 netif_wake_queue(dev);
621 spin_unlock(&priv->lock);
622 }
623
r6040_poll(struct napi_struct * napi,int budget)624 static int r6040_poll(struct napi_struct *napi, int budget)
625 {
626 struct r6040_private *priv =
627 container_of(napi, struct r6040_private, napi);
628 struct net_device *dev = priv->dev;
629 void __iomem *ioaddr = priv->base;
630 int work_done;
631
632 r6040_tx(dev);
633
634 work_done = r6040_rx(dev, budget);
635
636 if (work_done < budget) {
637 napi_complete_done(napi, work_done);
638 /* Enable RX/TX interrupt */
639 iowrite16(ioread16(ioaddr + MIER) | RX_INTS | TX_INTS,
640 ioaddr + MIER);
641 }
642 return work_done;
643 }
644
645 /* The RDC interrupt handler. */
r6040_interrupt(int irq,void * dev_id)646 static irqreturn_t r6040_interrupt(int irq, void *dev_id)
647 {
648 struct net_device *dev = dev_id;
649 struct r6040_private *lp = netdev_priv(dev);
650 void __iomem *ioaddr = lp->base;
651 u16 misr, status;
652
653 /* Save MIER */
654 misr = ioread16(ioaddr + MIER);
655 /* Mask off RDC MAC interrupt */
656 iowrite16(MSK_INT, ioaddr + MIER);
657 /* Read MISR status and clear */
658 status = ioread16(ioaddr + MISR);
659
660 if (status == 0x0000 || status == 0xffff) {
661 /* Restore RDC MAC interrupt */
662 iowrite16(misr, ioaddr + MIER);
663 return IRQ_NONE;
664 }
665
666 /* RX interrupt request */
667 if (status & (RX_INTS | TX_INTS)) {
668 if (status & RX_NO_DESC) {
669 /* RX descriptor unavailable */
670 dev->stats.rx_dropped++;
671 dev->stats.rx_missed_errors++;
672 }
673 if (status & RX_FIFO_FULL)
674 dev->stats.rx_fifo_errors++;
675
676 if (likely(napi_schedule_prep(&lp->napi))) {
677 /* Mask off RX interrupt */
678 misr &= ~(RX_INTS | TX_INTS);
679 __napi_schedule_irqoff(&lp->napi);
680 }
681 }
682
683 /* Restore RDC MAC interrupt */
684 iowrite16(misr, ioaddr + MIER);
685
686 return IRQ_HANDLED;
687 }
688
689 #ifdef CONFIG_NET_POLL_CONTROLLER
r6040_poll_controller(struct net_device * dev)690 static void r6040_poll_controller(struct net_device *dev)
691 {
692 disable_irq(dev->irq);
693 r6040_interrupt(dev->irq, dev);
694 enable_irq(dev->irq);
695 }
696 #endif
697
698 /* Init RDC MAC */
r6040_up(struct net_device * dev)699 static int r6040_up(struct net_device *dev)
700 {
701 struct r6040_private *lp = netdev_priv(dev);
702 void __iomem *ioaddr = lp->base;
703 int ret;
704
705 /* Initialise and alloc RX/TX buffers */
706 r6040_init_txbufs(dev);
707 ret = r6040_alloc_rxbufs(dev);
708 if (ret)
709 return ret;
710
711 /* improve performance (by RDC guys) */
712 r6040_phy_write(ioaddr, 30, 17,
713 (r6040_phy_read(ioaddr, 30, 17) | 0x4000));
714 r6040_phy_write(ioaddr, 30, 17,
715 ~((~r6040_phy_read(ioaddr, 30, 17)) | 0x2000));
716 r6040_phy_write(ioaddr, 0, 19, 0x0000);
717 r6040_phy_write(ioaddr, 0, 30, 0x01F0);
718
719 /* Initialize all MAC registers */
720 r6040_init_mac_regs(dev);
721
722 phy_start(dev->phydev);
723
724 return 0;
725 }
726
727
728 /* Read/set MAC address routines */
r6040_mac_address(struct net_device * dev)729 static void r6040_mac_address(struct net_device *dev)
730 {
731 struct r6040_private *lp = netdev_priv(dev);
732 void __iomem *ioaddr = lp->base;
733 u16 *adrp;
734
735 /* Reset MAC */
736 r6040_reset_mac(lp);
737
738 /* Restore MAC Address */
739 adrp = (u16 *) dev->dev_addr;
740 iowrite16(adrp[0], ioaddr + MID_0L);
741 iowrite16(adrp[1], ioaddr + MID_0M);
742 iowrite16(adrp[2], ioaddr + MID_0H);
743 }
744
r6040_open(struct net_device * dev)745 static int r6040_open(struct net_device *dev)
746 {
747 struct r6040_private *lp = netdev_priv(dev);
748 int ret;
749
750 /* Request IRQ and Register interrupt handler */
751 ret = request_irq(dev->irq, r6040_interrupt,
752 IRQF_SHARED, dev->name, dev);
753 if (ret)
754 goto out;
755
756 /* Set MAC address */
757 r6040_mac_address(dev);
758
759 /* Allocate Descriptor memory */
760 lp->rx_ring =
761 pci_alloc_consistent(lp->pdev, RX_DESC_SIZE, &lp->rx_ring_dma);
762 if (!lp->rx_ring) {
763 ret = -ENOMEM;
764 goto err_free_irq;
765 }
766
767 lp->tx_ring =
768 pci_alloc_consistent(lp->pdev, TX_DESC_SIZE, &lp->tx_ring_dma);
769 if (!lp->tx_ring) {
770 ret = -ENOMEM;
771 goto err_free_rx_ring;
772 }
773
774 ret = r6040_up(dev);
775 if (ret)
776 goto err_free_tx_ring;
777
778 napi_enable(&lp->napi);
779 netif_start_queue(dev);
780
781 return 0;
782
783 err_free_tx_ring:
784 pci_free_consistent(lp->pdev, TX_DESC_SIZE, lp->tx_ring,
785 lp->tx_ring_dma);
786 err_free_rx_ring:
787 pci_free_consistent(lp->pdev, RX_DESC_SIZE, lp->rx_ring,
788 lp->rx_ring_dma);
789 err_free_irq:
790 free_irq(dev->irq, dev);
791 out:
792 return ret;
793 }
794
r6040_start_xmit(struct sk_buff * skb,struct net_device * dev)795 static netdev_tx_t r6040_start_xmit(struct sk_buff *skb,
796 struct net_device *dev)
797 {
798 struct r6040_private *lp = netdev_priv(dev);
799 struct r6040_descriptor *descptr;
800 void __iomem *ioaddr = lp->base;
801 unsigned long flags;
802
803 if (skb_put_padto(skb, ETH_ZLEN) < 0)
804 return NETDEV_TX_OK;
805
806 /* Critical Section */
807 spin_lock_irqsave(&lp->lock, flags);
808
809 /* TX resource check */
810 if (!lp->tx_free_desc) {
811 spin_unlock_irqrestore(&lp->lock, flags);
812 netif_stop_queue(dev);
813 netdev_err(dev, ": no tx descriptor\n");
814 return NETDEV_TX_BUSY;
815 }
816
817 /* Set TX descriptor & Transmit it */
818 lp->tx_free_desc--;
819 descptr = lp->tx_insert_ptr;
820 descptr->len = skb->len;
821 descptr->skb_ptr = skb;
822 descptr->buf = cpu_to_le32(pci_map_single(lp->pdev,
823 skb->data, skb->len, PCI_DMA_TODEVICE));
824 descptr->status = DSC_OWNER_MAC;
825
826 skb_tx_timestamp(skb);
827
828 /* Trigger the MAC to check the TX descriptor */
829 if (!netdev_xmit_more() || netif_queue_stopped(dev))
830 iowrite16(TM2TX, ioaddr + MTPR);
831 lp->tx_insert_ptr = descptr->vndescp;
832
833 /* If no tx resource, stop */
834 if (!lp->tx_free_desc)
835 netif_stop_queue(dev);
836
837 spin_unlock_irqrestore(&lp->lock, flags);
838
839 return NETDEV_TX_OK;
840 }
841
r6040_multicast_list(struct net_device * dev)842 static void r6040_multicast_list(struct net_device *dev)
843 {
844 struct r6040_private *lp = netdev_priv(dev);
845 void __iomem *ioaddr = lp->base;
846 unsigned long flags;
847 struct netdev_hw_addr *ha;
848 int i;
849 u16 *adrp;
850 u16 hash_table[4] = { 0 };
851
852 spin_lock_irqsave(&lp->lock, flags);
853
854 /* Keep our MAC Address */
855 adrp = (u16 *)dev->dev_addr;
856 iowrite16(adrp[0], ioaddr + MID_0L);
857 iowrite16(adrp[1], ioaddr + MID_0M);
858 iowrite16(adrp[2], ioaddr + MID_0H);
859
860 /* Clear AMCP & PROM bits */
861 lp->mcr0 = ioread16(ioaddr + MCR0) & ~(MCR0_PROMISC | MCR0_HASH_EN);
862
863 /* Promiscuous mode */
864 if (dev->flags & IFF_PROMISC)
865 lp->mcr0 |= MCR0_PROMISC;
866
867 /* Enable multicast hash table function to
868 * receive all multicast packets. */
869 else if (dev->flags & IFF_ALLMULTI) {
870 lp->mcr0 |= MCR0_HASH_EN;
871
872 for (i = 0; i < MCAST_MAX ; i++) {
873 iowrite16(0, ioaddr + MID_1L + 8 * i);
874 iowrite16(0, ioaddr + MID_1M + 8 * i);
875 iowrite16(0, ioaddr + MID_1H + 8 * i);
876 }
877
878 for (i = 0; i < 4; i++)
879 hash_table[i] = 0xffff;
880 }
881 /* Use internal multicast address registers if the number of
882 * multicast addresses is not greater than MCAST_MAX. */
883 else if (netdev_mc_count(dev) <= MCAST_MAX) {
884 i = 0;
885 netdev_for_each_mc_addr(ha, dev) {
886 u16 *adrp = (u16 *) ha->addr;
887 iowrite16(adrp[0], ioaddr + MID_1L + 8 * i);
888 iowrite16(adrp[1], ioaddr + MID_1M + 8 * i);
889 iowrite16(adrp[2], ioaddr + MID_1H + 8 * i);
890 i++;
891 }
892 while (i < MCAST_MAX) {
893 iowrite16(0, ioaddr + MID_1L + 8 * i);
894 iowrite16(0, ioaddr + MID_1M + 8 * i);
895 iowrite16(0, ioaddr + MID_1H + 8 * i);
896 i++;
897 }
898 }
899 /* Otherwise, Enable multicast hash table function. */
900 else {
901 u32 crc;
902
903 lp->mcr0 |= MCR0_HASH_EN;
904
905 for (i = 0; i < MCAST_MAX ; i++) {
906 iowrite16(0, ioaddr + MID_1L + 8 * i);
907 iowrite16(0, ioaddr + MID_1M + 8 * i);
908 iowrite16(0, ioaddr + MID_1H + 8 * i);
909 }
910
911 /* Build multicast hash table */
912 netdev_for_each_mc_addr(ha, dev) {
913 u8 *addrs = ha->addr;
914
915 crc = ether_crc(ETH_ALEN, addrs);
916 crc >>= 26;
917 hash_table[crc >> 4] |= 1 << (crc & 0xf);
918 }
919 }
920
921 iowrite16(lp->mcr0, ioaddr + MCR0);
922
923 /* Fill the MAC hash tables with their values */
924 if (lp->mcr0 & MCR0_HASH_EN) {
925 iowrite16(hash_table[0], ioaddr + MAR0);
926 iowrite16(hash_table[1], ioaddr + MAR1);
927 iowrite16(hash_table[2], ioaddr + MAR2);
928 iowrite16(hash_table[3], ioaddr + MAR3);
929 }
930
931 spin_unlock_irqrestore(&lp->lock, flags);
932 }
933
netdev_get_drvinfo(struct net_device * dev,struct ethtool_drvinfo * info)934 static void netdev_get_drvinfo(struct net_device *dev,
935 struct ethtool_drvinfo *info)
936 {
937 struct r6040_private *rp = netdev_priv(dev);
938
939 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
940 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
941 strlcpy(info->bus_info, pci_name(rp->pdev), sizeof(info->bus_info));
942 }
943
944 static const struct ethtool_ops netdev_ethtool_ops = {
945 .get_drvinfo = netdev_get_drvinfo,
946 .get_link = ethtool_op_get_link,
947 .get_ts_info = ethtool_op_get_ts_info,
948 .get_link_ksettings = phy_ethtool_get_link_ksettings,
949 .set_link_ksettings = phy_ethtool_set_link_ksettings,
950 };
951
952 static const struct net_device_ops r6040_netdev_ops = {
953 .ndo_open = r6040_open,
954 .ndo_stop = r6040_close,
955 .ndo_start_xmit = r6040_start_xmit,
956 .ndo_get_stats = r6040_get_stats,
957 .ndo_set_rx_mode = r6040_multicast_list,
958 .ndo_validate_addr = eth_validate_addr,
959 .ndo_set_mac_address = eth_mac_addr,
960 .ndo_do_ioctl = r6040_ioctl,
961 .ndo_tx_timeout = r6040_tx_timeout,
962 #ifdef CONFIG_NET_POLL_CONTROLLER
963 .ndo_poll_controller = r6040_poll_controller,
964 #endif
965 };
966
r6040_adjust_link(struct net_device * dev)967 static void r6040_adjust_link(struct net_device *dev)
968 {
969 struct r6040_private *lp = netdev_priv(dev);
970 struct phy_device *phydev = dev->phydev;
971 int status_changed = 0;
972 void __iomem *ioaddr = lp->base;
973
974 BUG_ON(!phydev);
975
976 if (lp->old_link != phydev->link) {
977 status_changed = 1;
978 lp->old_link = phydev->link;
979 }
980
981 /* reflect duplex change */
982 if (phydev->link && (lp->old_duplex != phydev->duplex)) {
983 lp->mcr0 |= (phydev->duplex == DUPLEX_FULL ? MCR0_FD : 0);
984 iowrite16(lp->mcr0, ioaddr);
985
986 status_changed = 1;
987 lp->old_duplex = phydev->duplex;
988 }
989
990 if (status_changed)
991 phy_print_status(phydev);
992 }
993
r6040_mii_probe(struct net_device * dev)994 static int r6040_mii_probe(struct net_device *dev)
995 {
996 struct r6040_private *lp = netdev_priv(dev);
997 struct phy_device *phydev = NULL;
998
999 phydev = phy_find_first(lp->mii_bus);
1000 if (!phydev) {
1001 dev_err(&lp->pdev->dev, "no PHY found\n");
1002 return -ENODEV;
1003 }
1004
1005 phydev = phy_connect(dev, phydev_name(phydev), &r6040_adjust_link,
1006 PHY_INTERFACE_MODE_MII);
1007
1008 if (IS_ERR(phydev)) {
1009 dev_err(&lp->pdev->dev, "could not attach to PHY\n");
1010 return PTR_ERR(phydev);
1011 }
1012
1013 phy_set_max_speed(phydev, SPEED_100);
1014
1015 lp->old_link = 0;
1016 lp->old_duplex = -1;
1017
1018 phy_attached_info(phydev);
1019
1020 return 0;
1021 }
1022
r6040_init_one(struct pci_dev * pdev,const struct pci_device_id * ent)1023 static int r6040_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1024 {
1025 struct net_device *dev;
1026 struct r6040_private *lp;
1027 void __iomem *ioaddr;
1028 int err, io_size = R6040_IO_SIZE;
1029 static int card_idx = -1;
1030 int bar = 0;
1031 u16 *adrp;
1032
1033 pr_info("%s\n", version);
1034
1035 err = pci_enable_device(pdev);
1036 if (err)
1037 goto err_out;
1038
1039 /* this should always be supported */
1040 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1041 if (err) {
1042 dev_err(&pdev->dev, "32-bit PCI DMA addresses not supported by the card\n");
1043 goto err_out_disable_dev;
1044 }
1045 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1046 if (err) {
1047 dev_err(&pdev->dev, "32-bit PCI DMA addresses not supported by the card\n");
1048 goto err_out_disable_dev;
1049 }
1050
1051 /* IO Size check */
1052 if (pci_resource_len(pdev, bar) < io_size) {
1053 dev_err(&pdev->dev, "Insufficient PCI resources, aborting\n");
1054 err = -EIO;
1055 goto err_out_disable_dev;
1056 }
1057
1058 pci_set_master(pdev);
1059
1060 dev = alloc_etherdev(sizeof(struct r6040_private));
1061 if (!dev) {
1062 err = -ENOMEM;
1063 goto err_out_disable_dev;
1064 }
1065 SET_NETDEV_DEV(dev, &pdev->dev);
1066 lp = netdev_priv(dev);
1067
1068 err = pci_request_regions(pdev, DRV_NAME);
1069
1070 if (err) {
1071 dev_err(&pdev->dev, "Failed to request PCI regions\n");
1072 goto err_out_free_dev;
1073 }
1074
1075 ioaddr = pci_iomap(pdev, bar, io_size);
1076 if (!ioaddr) {
1077 dev_err(&pdev->dev, "ioremap failed for device\n");
1078 err = -EIO;
1079 goto err_out_free_res;
1080 }
1081
1082 /* If PHY status change register is still set to zero it means the
1083 * bootloader didn't initialize it, so we set it to:
1084 * - enable phy status change
1085 * - enable all phy addresses
1086 * - set to lowest timer divider */
1087 if (ioread16(ioaddr + PHY_CC) == 0)
1088 iowrite16(SCEN | PHY_MAX_ADDR << PHYAD_SHIFT |
1089 7 << TMRDIV_SHIFT, ioaddr + PHY_CC);
1090
1091 /* Init system & device */
1092 lp->base = ioaddr;
1093 dev->irq = pdev->irq;
1094
1095 spin_lock_init(&lp->lock);
1096 pci_set_drvdata(pdev, dev);
1097
1098 /* Set MAC address */
1099 card_idx++;
1100
1101 adrp = (u16 *)dev->dev_addr;
1102 adrp[0] = ioread16(ioaddr + MID_0L);
1103 adrp[1] = ioread16(ioaddr + MID_0M);
1104 adrp[2] = ioread16(ioaddr + MID_0H);
1105
1106 /* Some bootloader/BIOSes do not initialize
1107 * MAC address, warn about that */
1108 if (!(adrp[0] || adrp[1] || adrp[2])) {
1109 netdev_warn(dev, "MAC address not initialized, "
1110 "generating random\n");
1111 eth_hw_addr_random(dev);
1112 }
1113
1114 /* Link new device into r6040_root_dev */
1115 lp->pdev = pdev;
1116 lp->dev = dev;
1117
1118 /* Init RDC private data */
1119 lp->mcr0 = MCR0_XMTEN | MCR0_RCVEN;
1120
1121 /* The RDC-specific entries in the device structure. */
1122 dev->netdev_ops = &r6040_netdev_ops;
1123 dev->ethtool_ops = &netdev_ethtool_ops;
1124 dev->watchdog_timeo = TX_TIMEOUT;
1125
1126 netif_napi_add(dev, &lp->napi, r6040_poll, 64);
1127
1128 lp->mii_bus = mdiobus_alloc();
1129 if (!lp->mii_bus) {
1130 dev_err(&pdev->dev, "mdiobus_alloc() failed\n");
1131 err = -ENOMEM;
1132 goto err_out_unmap;
1133 }
1134
1135 lp->mii_bus->priv = dev;
1136 lp->mii_bus->read = r6040_mdiobus_read;
1137 lp->mii_bus->write = r6040_mdiobus_write;
1138 lp->mii_bus->name = "r6040_eth_mii";
1139 snprintf(lp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
1140 dev_name(&pdev->dev), card_idx);
1141
1142 err = mdiobus_register(lp->mii_bus);
1143 if (err) {
1144 dev_err(&pdev->dev, "failed to register MII bus\n");
1145 goto err_out_mdio;
1146 }
1147
1148 err = r6040_mii_probe(dev);
1149 if (err) {
1150 dev_err(&pdev->dev, "failed to probe MII bus\n");
1151 goto err_out_mdio_unregister;
1152 }
1153
1154 /* Register net device. After this dev->name assign */
1155 err = register_netdev(dev);
1156 if (err) {
1157 dev_err(&pdev->dev, "Failed to register net device\n");
1158 goto err_out_mdio_unregister;
1159 }
1160 return 0;
1161
1162 err_out_mdio_unregister:
1163 mdiobus_unregister(lp->mii_bus);
1164 err_out_mdio:
1165 mdiobus_free(lp->mii_bus);
1166 err_out_unmap:
1167 netif_napi_del(&lp->napi);
1168 pci_iounmap(pdev, ioaddr);
1169 err_out_free_res:
1170 pci_release_regions(pdev);
1171 err_out_free_dev:
1172 free_netdev(dev);
1173 err_out_disable_dev:
1174 pci_disable_device(pdev);
1175 err_out:
1176 return err;
1177 }
1178
r6040_remove_one(struct pci_dev * pdev)1179 static void r6040_remove_one(struct pci_dev *pdev)
1180 {
1181 struct net_device *dev = pci_get_drvdata(pdev);
1182 struct r6040_private *lp = netdev_priv(dev);
1183
1184 unregister_netdev(dev);
1185 mdiobus_unregister(lp->mii_bus);
1186 mdiobus_free(lp->mii_bus);
1187 netif_napi_del(&lp->napi);
1188 pci_iounmap(pdev, lp->base);
1189 pci_release_regions(pdev);
1190 free_netdev(dev);
1191 pci_disable_device(pdev);
1192 }
1193
1194
1195 static const struct pci_device_id r6040_pci_tbl[] = {
1196 { PCI_DEVICE(PCI_VENDOR_ID_RDC, 0x6040) },
1197 { 0 }
1198 };
1199 MODULE_DEVICE_TABLE(pci, r6040_pci_tbl);
1200
1201 static struct pci_driver r6040_driver = {
1202 .name = DRV_NAME,
1203 .id_table = r6040_pci_tbl,
1204 .probe = r6040_init_one,
1205 .remove = r6040_remove_one,
1206 };
1207
1208 module_pci_driver(r6040_driver);
1209
