1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Davicom DM9000 Fast Ethernet driver for Linux.
4 * Copyright (C) 1997 Sten Wang
5 *
6 * (C) Copyright 1997-1998 DAVICOM Semiconductor,Inc. All Rights Reserved.
7 *
8 * Additional updates, Copyright:
9 * Ben Dooks <ben@simtec.co.uk>
10 * Sascha Hauer <s.hauer@pengutronix.de>
11 */
12
13 #include <linux/module.h>
14 #include <linux/ioport.h>
15 #include <linux/netdevice.h>
16 #include <linux/etherdevice.h>
17 #include <linux/interrupt.h>
18 #include <linux/skbuff.h>
19 #include <linux/spinlock.h>
20 #include <linux/crc32.h>
21 #include <linux/mii.h>
22 #include <linux/of.h>
23 #include <linux/of_net.h>
24 #include <linux/ethtool.h>
25 #include <linux/dm9000.h>
26 #include <linux/delay.h>
27 #include <linux/platform_device.h>
28 #include <linux/irq.h>
29 #include <linux/slab.h>
30 #include <linux/regulator/consumer.h>
31 #include <linux/gpio.h>
32 #include <linux/of_gpio.h>
33
34 #include <asm/delay.h>
35 #include <asm/irq.h>
36 #include <asm/io.h>
37
38 #include "dm9000.h"
39
40 /* Board/System/Debug information/definition ---------------- */
41
42 #define DM9000_PHY 0x40 /* PHY address 0x01 */
43
44 #define CARDNAME "dm9000"
45
46 /*
47 * Transmit timeout, default 5 seconds.
48 */
49 static int watchdog = 5000;
50 module_param(watchdog, int, 0400);
51 MODULE_PARM_DESC(watchdog, "transmit timeout in milliseconds");
52
53 /*
54 * Debug messages level
55 */
56 static int debug;
57 module_param(debug, int, 0644);
58 MODULE_PARM_DESC(debug, "dm9000 debug level (0-6)");
59
60 /* DM9000 register address locking.
61 *
62 * The DM9000 uses an address register to control where data written
63 * to the data register goes. This means that the address register
64 * must be preserved over interrupts or similar calls.
65 *
66 * During interrupt and other critical calls, a spinlock is used to
67 * protect the system, but the calls themselves save the address
68 * in the address register in case they are interrupting another
69 * access to the device.
70 *
71 * For general accesses a lock is provided so that calls which are
72 * allowed to sleep are serialised so that the address register does
73 * not need to be saved. This lock also serves to serialise access
74 * to the EEPROM and PHY access registers which are shared between
75 * these two devices.
76 */
77
78 /* The driver supports the original DM9000E, and now the two newer
79 * devices, DM9000A and DM9000B.
80 */
81
82 enum dm9000_type {
83 TYPE_DM9000E, /* original DM9000 */
84 TYPE_DM9000A,
85 TYPE_DM9000B
86 };
87
88 /* Structure/enum declaration ------------------------------- */
89 struct board_info {
90
91 void __iomem *io_addr; /* Register I/O base address */
92 void __iomem *io_data; /* Data I/O address */
93 u16 irq; /* IRQ */
94
95 u16 tx_pkt_cnt;
96 u16 queue_pkt_len;
97 u16 queue_start_addr;
98 u16 queue_ip_summed;
99 u16 dbug_cnt;
100 u8 io_mode; /* 0:word, 2:byte */
101 u8 phy_addr;
102 u8 imr_all;
103
104 unsigned int flags;
105 unsigned int in_timeout:1;
106 unsigned int in_suspend:1;
107 unsigned int wake_supported:1;
108
109 enum dm9000_type type;
110
111 void (*inblk)(void __iomem *port, void *data, int length);
112 void (*outblk)(void __iomem *port, void *data, int length);
113 void (*dumpblk)(void __iomem *port, int length);
114
115 struct device *dev; /* parent device */
116
117 struct resource *addr_res; /* resources found */
118 struct resource *data_res;
119 struct resource *addr_req; /* resources requested */
120 struct resource *data_req;
121
122 int irq_wake;
123
124 struct mutex addr_lock; /* phy and eeprom access lock */
125
126 struct delayed_work phy_poll;
127 struct net_device *ndev;
128
129 spinlock_t lock;
130
131 struct mii_if_info mii;
132 u32 msg_enable;
133 u32 wake_state;
134
135 int ip_summed;
136 };
137
138 /* debug code */
139
140 #define dm9000_dbg(db, lev, msg...) do { \
141 if ((lev) < debug) { \
142 dev_dbg(db->dev, msg); \
143 } \
144 } while (0)
145
to_dm9000_board(struct net_device * dev)146 static inline struct board_info *to_dm9000_board(struct net_device *dev)
147 {
148 return netdev_priv(dev);
149 }
150
151 /* DM9000 network board routine ---------------------------- */
152
153 /*
154 * Read a byte from I/O port
155 */
156 static u8
ior(struct board_info * db,int reg)157 ior(struct board_info *db, int reg)
158 {
159 writeb(reg, db->io_addr);
160 return readb(db->io_data);
161 }
162
163 /*
164 * Write a byte to I/O port
165 */
166
167 static void
iow(struct board_info * db,int reg,int value)168 iow(struct board_info *db, int reg, int value)
169 {
170 writeb(reg, db->io_addr);
171 writeb(value, db->io_data);
172 }
173
174 static void
dm9000_reset(struct board_info * db)175 dm9000_reset(struct board_info *db)
176 {
177 dev_dbg(db->dev, "resetting device\n");
178
179 /* Reset DM9000, see DM9000 Application Notes V1.22 Jun 11, 2004 page 29
180 * The essential point is that we have to do a double reset, and the
181 * instruction is to set LBK into MAC internal loopback mode.
182 */
183 iow(db, DM9000_NCR, NCR_RST | NCR_MAC_LBK);
184 udelay(100); /* Application note says at least 20 us */
185 if (ior(db, DM9000_NCR) & 1)
186 dev_err(db->dev, "dm9000 did not respond to first reset\n");
187
188 iow(db, DM9000_NCR, 0);
189 iow(db, DM9000_NCR, NCR_RST | NCR_MAC_LBK);
190 udelay(100);
191 if (ior(db, DM9000_NCR) & 1)
192 dev_err(db->dev, "dm9000 did not respond to second reset\n");
193 }
194
195 /* routines for sending block to chip */
196
dm9000_outblk_8bit(void __iomem * reg,void * data,int count)197 static void dm9000_outblk_8bit(void __iomem *reg, void *data, int count)
198 {
199 iowrite8_rep(reg, data, count);
200 }
201
dm9000_outblk_16bit(void __iomem * reg,void * data,int count)202 static void dm9000_outblk_16bit(void __iomem *reg, void *data, int count)
203 {
204 iowrite16_rep(reg, data, (count+1) >> 1);
205 }
206
dm9000_outblk_32bit(void __iomem * reg,void * data,int count)207 static void dm9000_outblk_32bit(void __iomem *reg, void *data, int count)
208 {
209 iowrite32_rep(reg, data, (count+3) >> 2);
210 }
211
212 /* input block from chip to memory */
213
dm9000_inblk_8bit(void __iomem * reg,void * data,int count)214 static void dm9000_inblk_8bit(void __iomem *reg, void *data, int count)
215 {
216 ioread8_rep(reg, data, count);
217 }
218
219
dm9000_inblk_16bit(void __iomem * reg,void * data,int count)220 static void dm9000_inblk_16bit(void __iomem *reg, void *data, int count)
221 {
222 ioread16_rep(reg, data, (count+1) >> 1);
223 }
224
dm9000_inblk_32bit(void __iomem * reg,void * data,int count)225 static void dm9000_inblk_32bit(void __iomem *reg, void *data, int count)
226 {
227 ioread32_rep(reg, data, (count+3) >> 2);
228 }
229
230 /* dump block from chip to null */
231
dm9000_dumpblk_8bit(void __iomem * reg,int count)232 static void dm9000_dumpblk_8bit(void __iomem *reg, int count)
233 {
234 int i;
235 int tmp;
236
237 for (i = 0; i < count; i++)
238 tmp = readb(reg);
239 }
240
dm9000_dumpblk_16bit(void __iomem * reg,int count)241 static void dm9000_dumpblk_16bit(void __iomem *reg, int count)
242 {
243 int i;
244 int tmp;
245
246 count = (count + 1) >> 1;
247
248 for (i = 0; i < count; i++)
249 tmp = readw(reg);
250 }
251
dm9000_dumpblk_32bit(void __iomem * reg,int count)252 static void dm9000_dumpblk_32bit(void __iomem *reg, int count)
253 {
254 int i;
255 int tmp;
256
257 count = (count + 3) >> 2;
258
259 for (i = 0; i < count; i++)
260 tmp = readl(reg);
261 }
262
263 /*
264 * Sleep, either by using msleep() or if we are suspending, then
265 * use mdelay() to sleep.
266 */
dm9000_msleep(struct board_info * db,unsigned int ms)267 static void dm9000_msleep(struct board_info *db, unsigned int ms)
268 {
269 if (db->in_suspend || db->in_timeout)
270 mdelay(ms);
271 else
272 msleep(ms);
273 }
274
275 /* Read a word from phyxcer */
276 static int
dm9000_phy_read(struct net_device * dev,int phy_reg_unused,int reg)277 dm9000_phy_read(struct net_device *dev, int phy_reg_unused, int reg)
278 {
279 struct board_info *db = netdev_priv(dev);
280 unsigned long flags;
281 unsigned int reg_save;
282 int ret;
283
284 mutex_lock(&db->addr_lock);
285
286 spin_lock_irqsave(&db->lock, flags);
287
288 /* Save previous register address */
289 reg_save = readb(db->io_addr);
290
291 /* Fill the phyxcer register into REG_0C */
292 iow(db, DM9000_EPAR, DM9000_PHY | reg);
293
294 /* Issue phyxcer read command */
295 iow(db, DM9000_EPCR, EPCR_ERPRR | EPCR_EPOS);
296
297 writeb(reg_save, db->io_addr);
298 spin_unlock_irqrestore(&db->lock, flags);
299
300 dm9000_msleep(db, 1); /* Wait read complete */
301
302 spin_lock_irqsave(&db->lock, flags);
303 reg_save = readb(db->io_addr);
304
305 iow(db, DM9000_EPCR, 0x0); /* Clear phyxcer read command */
306
307 /* The read data keeps on REG_0D & REG_0E */
308 ret = (ior(db, DM9000_EPDRH) << 8) | ior(db, DM9000_EPDRL);
309
310 /* restore the previous address */
311 writeb(reg_save, db->io_addr);
312 spin_unlock_irqrestore(&db->lock, flags);
313
314 mutex_unlock(&db->addr_lock);
315
316 dm9000_dbg(db, 5, "phy_read[%02x] -> %04x\n", reg, ret);
317 return ret;
318 }
319
320 /* Write a word to phyxcer */
321 static void
dm9000_phy_write(struct net_device * dev,int phyaddr_unused,int reg,int value)322 dm9000_phy_write(struct net_device *dev,
323 int phyaddr_unused, int reg, int value)
324 {
325 struct board_info *db = netdev_priv(dev);
326 unsigned long flags;
327 unsigned long reg_save;
328
329 dm9000_dbg(db, 5, "phy_write[%02x] = %04x\n", reg, value);
330 if (!db->in_timeout)
331 mutex_lock(&db->addr_lock);
332
333 spin_lock_irqsave(&db->lock, flags);
334
335 /* Save previous register address */
336 reg_save = readb(db->io_addr);
337
338 /* Fill the phyxcer register into REG_0C */
339 iow(db, DM9000_EPAR, DM9000_PHY | reg);
340
341 /* Fill the written data into REG_0D & REG_0E */
342 iow(db, DM9000_EPDRL, value);
343 iow(db, DM9000_EPDRH, value >> 8);
344
345 /* Issue phyxcer write command */
346 iow(db, DM9000_EPCR, EPCR_EPOS | EPCR_ERPRW);
347
348 writeb(reg_save, db->io_addr);
349 spin_unlock_irqrestore(&db->lock, flags);
350
351 dm9000_msleep(db, 1); /* Wait write complete */
352
353 spin_lock_irqsave(&db->lock, flags);
354 reg_save = readb(db->io_addr);
355
356 iow(db, DM9000_EPCR, 0x0); /* Clear phyxcer write command */
357
358 /* restore the previous address */
359 writeb(reg_save, db->io_addr);
360
361 spin_unlock_irqrestore(&db->lock, flags);
362 if (!db->in_timeout)
363 mutex_unlock(&db->addr_lock);
364 }
365
366 /* dm9000_set_io
367 *
368 * select the specified set of io routines to use with the
369 * device
370 */
371
dm9000_set_io(struct board_info * db,int byte_width)372 static void dm9000_set_io(struct board_info *db, int byte_width)
373 {
374 /* use the size of the data resource to work out what IO
375 * routines we want to use
376 */
377
378 switch (byte_width) {
379 case 1:
380 db->dumpblk = dm9000_dumpblk_8bit;
381 db->outblk = dm9000_outblk_8bit;
382 db->inblk = dm9000_inblk_8bit;
383 break;
384
385
386 case 3:
387 dev_dbg(db->dev, ": 3 byte IO, falling back to 16bit\n");
388 fallthrough;
389 case 2:
390 db->dumpblk = dm9000_dumpblk_16bit;
391 db->outblk = dm9000_outblk_16bit;
392 db->inblk = dm9000_inblk_16bit;
393 break;
394
395 case 4:
396 default:
397 db->dumpblk = dm9000_dumpblk_32bit;
398 db->outblk = dm9000_outblk_32bit;
399 db->inblk = dm9000_inblk_32bit;
400 break;
401 }
402 }
403
dm9000_schedule_poll(struct board_info * db)404 static void dm9000_schedule_poll(struct board_info *db)
405 {
406 if (db->type == TYPE_DM9000E)
407 schedule_delayed_work(&db->phy_poll, HZ * 2);
408 }
409
dm9000_ioctl(struct net_device * dev,struct ifreq * req,int cmd)410 static int dm9000_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
411 {
412 struct board_info *dm = to_dm9000_board(dev);
413
414 if (!netif_running(dev))
415 return -EINVAL;
416
417 return generic_mii_ioctl(&dm->mii, if_mii(req), cmd, NULL);
418 }
419
420 static unsigned int
dm9000_read_locked(struct board_info * db,int reg)421 dm9000_read_locked(struct board_info *db, int reg)
422 {
423 unsigned long flags;
424 unsigned int ret;
425
426 spin_lock_irqsave(&db->lock, flags);
427 ret = ior(db, reg);
428 spin_unlock_irqrestore(&db->lock, flags);
429
430 return ret;
431 }
432
dm9000_wait_eeprom(struct board_info * db)433 static int dm9000_wait_eeprom(struct board_info *db)
434 {
435 unsigned int status;
436 int timeout = 8; /* wait max 8msec */
437
438 /* The DM9000 data sheets say we should be able to
439 * poll the ERRE bit in EPCR to wait for the EEPROM
440 * operation. From testing several chips, this bit
441 * does not seem to work.
442 *
443 * We attempt to use the bit, but fall back to the
444 * timeout (which is why we do not return an error
445 * on expiry) to say that the EEPROM operation has
446 * completed.
447 */
448
449 while (1) {
450 status = dm9000_read_locked(db, DM9000_EPCR);
451
452 if ((status & EPCR_ERRE) == 0)
453 break;
454
455 msleep(1);
456
457 if (timeout-- < 0) {
458 dev_dbg(db->dev, "timeout waiting EEPROM\n");
459 break;
460 }
461 }
462
463 return 0;
464 }
465
466 /*
467 * Read a word data from EEPROM
468 */
469 static void
dm9000_read_eeprom(struct board_info * db,int offset,u8 * to)470 dm9000_read_eeprom(struct board_info *db, int offset, u8 *to)
471 {
472 unsigned long flags;
473
474 if (db->flags & DM9000_PLATF_NO_EEPROM) {
475 to[0] = 0xff;
476 to[1] = 0xff;
477 return;
478 }
479
480 mutex_lock(&db->addr_lock);
481
482 spin_lock_irqsave(&db->lock, flags);
483
484 iow(db, DM9000_EPAR, offset);
485 iow(db, DM9000_EPCR, EPCR_ERPRR);
486
487 spin_unlock_irqrestore(&db->lock, flags);
488
489 dm9000_wait_eeprom(db);
490
491 /* delay for at-least 150uS */
492 msleep(1);
493
494 spin_lock_irqsave(&db->lock, flags);
495
496 iow(db, DM9000_EPCR, 0x0);
497
498 to[0] = ior(db, DM9000_EPDRL);
499 to[1] = ior(db, DM9000_EPDRH);
500
501 spin_unlock_irqrestore(&db->lock, flags);
502
503 mutex_unlock(&db->addr_lock);
504 }
505
506 /*
507 * Write a word data to SROM
508 */
509 static void
dm9000_write_eeprom(struct board_info * db,int offset,u8 * data)510 dm9000_write_eeprom(struct board_info *db, int offset, u8 *data)
511 {
512 unsigned long flags;
513
514 if (db->flags & DM9000_PLATF_NO_EEPROM)
515 return;
516
517 mutex_lock(&db->addr_lock);
518
519 spin_lock_irqsave(&db->lock, flags);
520 iow(db, DM9000_EPAR, offset);
521 iow(db, DM9000_EPDRH, data[1]);
522 iow(db, DM9000_EPDRL, data[0]);
523 iow(db, DM9000_EPCR, EPCR_WEP | EPCR_ERPRW);
524 spin_unlock_irqrestore(&db->lock, flags);
525
526 dm9000_wait_eeprom(db);
527
528 mdelay(1); /* wait at least 150uS to clear */
529
530 spin_lock_irqsave(&db->lock, flags);
531 iow(db, DM9000_EPCR, 0);
532 spin_unlock_irqrestore(&db->lock, flags);
533
534 mutex_unlock(&db->addr_lock);
535 }
536
537 /* ethtool ops */
538
dm9000_get_drvinfo(struct net_device * dev,struct ethtool_drvinfo * info)539 static void dm9000_get_drvinfo(struct net_device *dev,
540 struct ethtool_drvinfo *info)
541 {
542 struct board_info *dm = to_dm9000_board(dev);
543
544 strlcpy(info->driver, CARDNAME, sizeof(info->driver));
545 strlcpy(info->bus_info, to_platform_device(dm->dev)->name,
546 sizeof(info->bus_info));
547 }
548
dm9000_get_msglevel(struct net_device * dev)549 static u32 dm9000_get_msglevel(struct net_device *dev)
550 {
551 struct board_info *dm = to_dm9000_board(dev);
552
553 return dm->msg_enable;
554 }
555
dm9000_set_msglevel(struct net_device * dev,u32 value)556 static void dm9000_set_msglevel(struct net_device *dev, u32 value)
557 {
558 struct board_info *dm = to_dm9000_board(dev);
559
560 dm->msg_enable = value;
561 }
562
dm9000_get_link_ksettings(struct net_device * dev,struct ethtool_link_ksettings * cmd)563 static int dm9000_get_link_ksettings(struct net_device *dev,
564 struct ethtool_link_ksettings *cmd)
565 {
566 struct board_info *dm = to_dm9000_board(dev);
567
568 mii_ethtool_get_link_ksettings(&dm->mii, cmd);
569 return 0;
570 }
571
dm9000_set_link_ksettings(struct net_device * dev,const struct ethtool_link_ksettings * cmd)572 static int dm9000_set_link_ksettings(struct net_device *dev,
573 const struct ethtool_link_ksettings *cmd)
574 {
575 struct board_info *dm = to_dm9000_board(dev);
576
577 return mii_ethtool_set_link_ksettings(&dm->mii, cmd);
578 }
579
dm9000_nway_reset(struct net_device * dev)580 static int dm9000_nway_reset(struct net_device *dev)
581 {
582 struct board_info *dm = to_dm9000_board(dev);
583 return mii_nway_restart(&dm->mii);
584 }
585
dm9000_set_features(struct net_device * dev,netdev_features_t features)586 static int dm9000_set_features(struct net_device *dev,
587 netdev_features_t features)
588 {
589 struct board_info *dm = to_dm9000_board(dev);
590 netdev_features_t changed = dev->features ^ features;
591 unsigned long flags;
592
593 if (!(changed & NETIF_F_RXCSUM))
594 return 0;
595
596 spin_lock_irqsave(&dm->lock, flags);
597 iow(dm, DM9000_RCSR, (features & NETIF_F_RXCSUM) ? RCSR_CSUM : 0);
598 spin_unlock_irqrestore(&dm->lock, flags);
599
600 return 0;
601 }
602
dm9000_get_link(struct net_device * dev)603 static u32 dm9000_get_link(struct net_device *dev)
604 {
605 struct board_info *dm = to_dm9000_board(dev);
606 u32 ret;
607
608 if (dm->flags & DM9000_PLATF_EXT_PHY)
609 ret = mii_link_ok(&dm->mii);
610 else
611 ret = dm9000_read_locked(dm, DM9000_NSR) & NSR_LINKST ? 1 : 0;
612
613 return ret;
614 }
615
616 #define DM_EEPROM_MAGIC (0x444D394B)
617
dm9000_get_eeprom_len(struct net_device * dev)618 static int dm9000_get_eeprom_len(struct net_device *dev)
619 {
620 return 128;
621 }
622
dm9000_get_eeprom(struct net_device * dev,struct ethtool_eeprom * ee,u8 * data)623 static int dm9000_get_eeprom(struct net_device *dev,
624 struct ethtool_eeprom *ee, u8 *data)
625 {
626 struct board_info *dm = to_dm9000_board(dev);
627 int offset = ee->offset;
628 int len = ee->len;
629 int i;
630
631 /* EEPROM access is aligned to two bytes */
632
633 if ((len & 1) != 0 || (offset & 1) != 0)
634 return -EINVAL;
635
636 if (dm->flags & DM9000_PLATF_NO_EEPROM)
637 return -ENOENT;
638
639 ee->magic = DM_EEPROM_MAGIC;
640
641 for (i = 0; i < len; i += 2)
642 dm9000_read_eeprom(dm, (offset + i) / 2, data + i);
643
644 return 0;
645 }
646
dm9000_set_eeprom(struct net_device * dev,struct ethtool_eeprom * ee,u8 * data)647 static int dm9000_set_eeprom(struct net_device *dev,
648 struct ethtool_eeprom *ee, u8 *data)
649 {
650 struct board_info *dm = to_dm9000_board(dev);
651 int offset = ee->offset;
652 int len = ee->len;
653 int done;
654
655 /* EEPROM access is aligned to two bytes */
656
657 if (dm->flags & DM9000_PLATF_NO_EEPROM)
658 return -ENOENT;
659
660 if (ee->magic != DM_EEPROM_MAGIC)
661 return -EINVAL;
662
663 while (len > 0) {
664 if (len & 1 || offset & 1) {
665 int which = offset & 1;
666 u8 tmp[2];
667
668 dm9000_read_eeprom(dm, offset / 2, tmp);
669 tmp[which] = *data;
670 dm9000_write_eeprom(dm, offset / 2, tmp);
671
672 done = 1;
673 } else {
674 dm9000_write_eeprom(dm, offset / 2, data);
675 done = 2;
676 }
677
678 data += done;
679 offset += done;
680 len -= done;
681 }
682
683 return 0;
684 }
685
dm9000_get_wol(struct net_device * dev,struct ethtool_wolinfo * w)686 static void dm9000_get_wol(struct net_device *dev, struct ethtool_wolinfo *w)
687 {
688 struct board_info *dm = to_dm9000_board(dev);
689
690 memset(w, 0, sizeof(struct ethtool_wolinfo));
691
692 /* note, we could probably support wake-phy too */
693 w->supported = dm->wake_supported ? WAKE_MAGIC : 0;
694 w->wolopts = dm->wake_state;
695 }
696
dm9000_set_wol(struct net_device * dev,struct ethtool_wolinfo * w)697 static int dm9000_set_wol(struct net_device *dev, struct ethtool_wolinfo *w)
698 {
699 struct board_info *dm = to_dm9000_board(dev);
700 unsigned long flags;
701 u32 opts = w->wolopts;
702 u32 wcr = 0;
703
704 if (!dm->wake_supported)
705 return -EOPNOTSUPP;
706
707 if (opts & ~WAKE_MAGIC)
708 return -EINVAL;
709
710 if (opts & WAKE_MAGIC)
711 wcr |= WCR_MAGICEN;
712
713 mutex_lock(&dm->addr_lock);
714
715 spin_lock_irqsave(&dm->lock, flags);
716 iow(dm, DM9000_WCR, wcr);
717 spin_unlock_irqrestore(&dm->lock, flags);
718
719 mutex_unlock(&dm->addr_lock);
720
721 if (dm->wake_state != opts) {
722 /* change in wol state, update IRQ state */
723
724 if (!dm->wake_state)
725 irq_set_irq_wake(dm->irq_wake, 1);
726 else if (dm->wake_state && !opts)
727 irq_set_irq_wake(dm->irq_wake, 0);
728 }
729
730 dm->wake_state = opts;
731 return 0;
732 }
733
734 static const struct ethtool_ops dm9000_ethtool_ops = {
735 .get_drvinfo = dm9000_get_drvinfo,
736 .get_msglevel = dm9000_get_msglevel,
737 .set_msglevel = dm9000_set_msglevel,
738 .nway_reset = dm9000_nway_reset,
739 .get_link = dm9000_get_link,
740 .get_wol = dm9000_get_wol,
741 .set_wol = dm9000_set_wol,
742 .get_eeprom_len = dm9000_get_eeprom_len,
743 .get_eeprom = dm9000_get_eeprom,
744 .set_eeprom = dm9000_set_eeprom,
745 .get_link_ksettings = dm9000_get_link_ksettings,
746 .set_link_ksettings = dm9000_set_link_ksettings,
747 };
748
dm9000_show_carrier(struct board_info * db,unsigned carrier,unsigned nsr)749 static void dm9000_show_carrier(struct board_info *db,
750 unsigned carrier, unsigned nsr)
751 {
752 int lpa;
753 struct net_device *ndev = db->ndev;
754 struct mii_if_info *mii = &db->mii;
755 unsigned ncr = dm9000_read_locked(db, DM9000_NCR);
756
757 if (carrier) {
758 lpa = mii->mdio_read(mii->dev, mii->phy_id, MII_LPA);
759 dev_info(db->dev,
760 "%s: link up, %dMbps, %s-duplex, lpa 0x%04X\n",
761 ndev->name, (nsr & NSR_SPEED) ? 10 : 100,
762 (ncr & NCR_FDX) ? "full" : "half", lpa);
763 } else {
764 dev_info(db->dev, "%s: link down\n", ndev->name);
765 }
766 }
767
768 static void
dm9000_poll_work(struct work_struct * w)769 dm9000_poll_work(struct work_struct *w)
770 {
771 struct delayed_work *dw = to_delayed_work(w);
772 struct board_info *db = container_of(dw, struct board_info, phy_poll);
773 struct net_device *ndev = db->ndev;
774
775 if (db->flags & DM9000_PLATF_SIMPLE_PHY &&
776 !(db->flags & DM9000_PLATF_EXT_PHY)) {
777 unsigned nsr = dm9000_read_locked(db, DM9000_NSR);
778 unsigned old_carrier = netif_carrier_ok(ndev) ? 1 : 0;
779 unsigned new_carrier;
780
781 new_carrier = (nsr & NSR_LINKST) ? 1 : 0;
782
783 if (old_carrier != new_carrier) {
784 if (netif_msg_link(db))
785 dm9000_show_carrier(db, new_carrier, nsr);
786
787 if (!new_carrier)
788 netif_carrier_off(ndev);
789 else
790 netif_carrier_on(ndev);
791 }
792 } else
793 mii_check_media(&db->mii, netif_msg_link(db), 0);
794
795 if (netif_running(ndev))
796 dm9000_schedule_poll(db);
797 }
798
799 /* dm9000_release_board
800 *
801 * release a board, and any mapped resources
802 */
803
804 static void
dm9000_release_board(struct platform_device * pdev,struct board_info * db)805 dm9000_release_board(struct platform_device *pdev, struct board_info *db)
806 {
807 /* unmap our resources */
808
809 iounmap(db->io_addr);
810 iounmap(db->io_data);
811
812 /* release the resources */
813
814 if (db->data_req)
815 release_resource(db->data_req);
816 kfree(db->data_req);
817
818 if (db->addr_req)
819 release_resource(db->addr_req);
820 kfree(db->addr_req);
821 }
822
dm9000_type_to_char(enum dm9000_type type)823 static unsigned char dm9000_type_to_char(enum dm9000_type type)
824 {
825 switch (type) {
826 case TYPE_DM9000E: return 'e';
827 case TYPE_DM9000A: return 'a';
828 case TYPE_DM9000B: return 'b';
829 }
830
831 return '?';
832 }
833
834 /*
835 * Set DM9000 multicast address
836 */
837 static void
dm9000_hash_table_unlocked(struct net_device * dev)838 dm9000_hash_table_unlocked(struct net_device *dev)
839 {
840 struct board_info *db = netdev_priv(dev);
841 struct netdev_hw_addr *ha;
842 int i, oft;
843 u32 hash_val;
844 u16 hash_table[4] = { 0, 0, 0, 0x8000 }; /* broadcast address */
845 u8 rcr = RCR_DIS_LONG | RCR_DIS_CRC | RCR_RXEN;
846
847 dm9000_dbg(db, 1, "entering %s\n", __func__);
848
849 for (i = 0, oft = DM9000_PAR; i < 6; i++, oft++)
850 iow(db, oft, dev->dev_addr[i]);
851
852 if (dev->flags & IFF_PROMISC)
853 rcr |= RCR_PRMSC;
854
855 if (dev->flags & IFF_ALLMULTI)
856 rcr |= RCR_ALL;
857
858 /* the multicast address in Hash Table : 64 bits */
859 netdev_for_each_mc_addr(ha, dev) {
860 hash_val = ether_crc_le(6, ha->addr) & 0x3f;
861 hash_table[hash_val / 16] |= (u16) 1 << (hash_val % 16);
862 }
863
864 /* Write the hash table to MAC MD table */
865 for (i = 0, oft = DM9000_MAR; i < 4; i++) {
866 iow(db, oft++, hash_table[i]);
867 iow(db, oft++, hash_table[i] >> 8);
868 }
869
870 iow(db, DM9000_RCR, rcr);
871 }
872
873 static void
dm9000_hash_table(struct net_device * dev)874 dm9000_hash_table(struct net_device *dev)
875 {
876 struct board_info *db = netdev_priv(dev);
877 unsigned long flags;
878
879 spin_lock_irqsave(&db->lock, flags);
880 dm9000_hash_table_unlocked(dev);
881 spin_unlock_irqrestore(&db->lock, flags);
882 }
883
884 static void
dm9000_mask_interrupts(struct board_info * db)885 dm9000_mask_interrupts(struct board_info *db)
886 {
887 iow(db, DM9000_IMR, IMR_PAR);
888 }
889
890 static void
dm9000_unmask_interrupts(struct board_info * db)891 dm9000_unmask_interrupts(struct board_info *db)
892 {
893 iow(db, DM9000_IMR, db->imr_all);
894 }
895
896 /*
897 * Initialize dm9000 board
898 */
899 static void
dm9000_init_dm9000(struct net_device * dev)900 dm9000_init_dm9000(struct net_device *dev)
901 {
902 struct board_info *db = netdev_priv(dev);
903 unsigned int imr;
904 unsigned int ncr;
905
906 dm9000_dbg(db, 1, "entering %s\n", __func__);
907
908 dm9000_reset(db);
909 dm9000_mask_interrupts(db);
910
911 /* I/O mode */
912 db->io_mode = ior(db, DM9000_ISR) >> 6; /* ISR bit7:6 keeps I/O mode */
913
914 /* Checksum mode */
915 if (dev->hw_features & NETIF_F_RXCSUM)
916 iow(db, DM9000_RCSR,
917 (dev->features & NETIF_F_RXCSUM) ? RCSR_CSUM : 0);
918
919 iow(db, DM9000_GPCR, GPCR_GEP_CNTL); /* Let GPIO0 output */
920 iow(db, DM9000_GPR, 0);
921
922 /* If we are dealing with DM9000B, some extra steps are required: a
923 * manual phy reset, and setting init params.
924 */
925 if (db->type == TYPE_DM9000B) {
926 dm9000_phy_write(dev, 0, MII_BMCR, BMCR_RESET);
927 dm9000_phy_write(dev, 0, MII_DM_DSPCR, DSPCR_INIT_PARAM);
928 }
929
930 ncr = (db->flags & DM9000_PLATF_EXT_PHY) ? NCR_EXT_PHY : 0;
931
932 /* if wol is needed, then always set NCR_WAKEEN otherwise we end
933 * up dumping the wake events if we disable this. There is already
934 * a wake-mask in DM9000_WCR */
935 if (db->wake_supported)
936 ncr |= NCR_WAKEEN;
937
938 iow(db, DM9000_NCR, ncr);
939
940 /* Program operating register */
941 iow(db, DM9000_TCR, 0); /* TX Polling clear */
942 iow(db, DM9000_BPTR, 0x3f); /* Less 3Kb, 200us */
943 iow(db, DM9000_FCR, 0xff); /* Flow Control */
944 iow(db, DM9000_SMCR, 0); /* Special Mode */
945 /* clear TX status */
946 iow(db, DM9000_NSR, NSR_WAKEST | NSR_TX2END | NSR_TX1END);
947 iow(db, DM9000_ISR, ISR_CLR_STATUS); /* Clear interrupt status */
948
949 /* Set address filter table */
950 dm9000_hash_table_unlocked(dev);
951
952 imr = IMR_PAR | IMR_PTM | IMR_PRM;
953 if (db->type != TYPE_DM9000E)
954 imr |= IMR_LNKCHNG;
955
956 db->imr_all = imr;
957
958 /* Init Driver variable */
959 db->tx_pkt_cnt = 0;
960 db->queue_pkt_len = 0;
961 netif_trans_update(dev);
962 }
963
964 /* Our watchdog timed out. Called by the networking layer */
dm9000_timeout(struct net_device * dev,unsigned int txqueue)965 static void dm9000_timeout(struct net_device *dev, unsigned int txqueue)
966 {
967 struct board_info *db = netdev_priv(dev);
968 u8 reg_save;
969 unsigned long flags;
970
971 /* Save previous register address */
972 spin_lock_irqsave(&db->lock, flags);
973 db->in_timeout = 1;
974 reg_save = readb(db->io_addr);
975
976 netif_stop_queue(dev);
977 dm9000_init_dm9000(dev);
978 dm9000_unmask_interrupts(db);
979 /* We can accept TX packets again */
980 netif_trans_update(dev); /* prevent tx timeout */
981 netif_wake_queue(dev);
982
983 /* Restore previous register address */
984 writeb(reg_save, db->io_addr);
985 db->in_timeout = 0;
986 spin_unlock_irqrestore(&db->lock, flags);
987 }
988
dm9000_send_packet(struct net_device * dev,int ip_summed,u16 pkt_len)989 static void dm9000_send_packet(struct net_device *dev,
990 int ip_summed,
991 u16 pkt_len)
992 {
993 struct board_info *dm = to_dm9000_board(dev);
994
995 /* The DM9000 is not smart enough to leave fragmented packets alone. */
996 if (dm->ip_summed != ip_summed) {
997 if (ip_summed == CHECKSUM_NONE)
998 iow(dm, DM9000_TCCR, 0);
999 else
1000 iow(dm, DM9000_TCCR, TCCR_IP | TCCR_UDP | TCCR_TCP);
1001 dm->ip_summed = ip_summed;
1002 }
1003
1004 /* Set TX length to DM9000 */
1005 iow(dm, DM9000_TXPLL, pkt_len);
1006 iow(dm, DM9000_TXPLH, pkt_len >> 8);
1007
1008 /* Issue TX polling command */
1009 iow(dm, DM9000_TCR, TCR_TXREQ); /* Cleared after TX complete */
1010 }
1011
1012 /*
1013 * Hardware start transmission.
1014 * Send a packet to media from the upper layer.
1015 */
1016 static int
dm9000_start_xmit(struct sk_buff * skb,struct net_device * dev)1017 dm9000_start_xmit(struct sk_buff *skb, struct net_device *dev)
1018 {
1019 unsigned long flags;
1020 struct board_info *db = netdev_priv(dev);
1021
1022 dm9000_dbg(db, 3, "%s:\n", __func__);
1023
1024 if (db->tx_pkt_cnt > 1)
1025 return NETDEV_TX_BUSY;
1026
1027 spin_lock_irqsave(&db->lock, flags);
1028
1029 /* Move data to DM9000 TX RAM */
1030 writeb(DM9000_MWCMD, db->io_addr);
1031
1032 (db->outblk)(db->io_data, skb->data, skb->len);
1033 dev->stats.tx_bytes += skb->len;
1034
1035 db->tx_pkt_cnt++;
1036 /* TX control: First packet immediately send, second packet queue */
1037 if (db->tx_pkt_cnt == 1) {
1038 dm9000_send_packet(dev, skb->ip_summed, skb->len);
1039 } else {
1040 /* Second packet */
1041 db->queue_pkt_len = skb->len;
1042 db->queue_ip_summed = skb->ip_summed;
1043 netif_stop_queue(dev);
1044 }
1045
1046 spin_unlock_irqrestore(&db->lock, flags);
1047
1048 /* free this SKB */
1049 dev_consume_skb_any(skb);
1050
1051 return NETDEV_TX_OK;
1052 }
1053
1054 /*
1055 * DM9000 interrupt handler
1056 * receive the packet to upper layer, free the transmitted packet
1057 */
1058
dm9000_tx_done(struct net_device * dev,struct board_info * db)1059 static void dm9000_tx_done(struct net_device *dev, struct board_info *db)
1060 {
1061 int tx_status = ior(db, DM9000_NSR); /* Got TX status */
1062
1063 if (tx_status & (NSR_TX2END | NSR_TX1END)) {
1064 /* One packet sent complete */
1065 db->tx_pkt_cnt--;
1066 dev->stats.tx_packets++;
1067
1068 if (netif_msg_tx_done(db))
1069 dev_dbg(db->dev, "tx done, NSR %02x\n", tx_status);
1070
1071 /* Queue packet check & send */
1072 if (db->tx_pkt_cnt > 0)
1073 dm9000_send_packet(dev, db->queue_ip_summed,
1074 db->queue_pkt_len);
1075 netif_wake_queue(dev);
1076 }
1077 }
1078
1079 struct dm9000_rxhdr {
1080 u8 RxPktReady;
1081 u8 RxStatus;
1082 __le16 RxLen;
1083 } __packed;
1084
1085 /*
1086 * Received a packet and pass to upper layer
1087 */
1088 static void
dm9000_rx(struct net_device * dev)1089 dm9000_rx(struct net_device *dev)
1090 {
1091 struct board_info *db = netdev_priv(dev);
1092 struct dm9000_rxhdr rxhdr;
1093 struct sk_buff *skb;
1094 u8 rxbyte, *rdptr;
1095 bool GoodPacket;
1096 int RxLen;
1097
1098 /* Check packet ready or not */
1099 do {
1100 ior(db, DM9000_MRCMDX); /* Dummy read */
1101
1102 /* Get most updated data */
1103 rxbyte = readb(db->io_data);
1104
1105 /* Status check: this byte must be 0 or 1 */
1106 if (rxbyte & DM9000_PKT_ERR) {
1107 dev_warn(db->dev, "status check fail: %d\n", rxbyte);
1108 iow(db, DM9000_RCR, 0x00); /* Stop Device */
1109 return;
1110 }
1111
1112 if (!(rxbyte & DM9000_PKT_RDY))
1113 return;
1114
1115 /* A packet ready now & Get status/length */
1116 GoodPacket = true;
1117 writeb(DM9000_MRCMD, db->io_addr);
1118
1119 (db->inblk)(db->io_data, &rxhdr, sizeof(rxhdr));
1120
1121 RxLen = le16_to_cpu(rxhdr.RxLen);
1122
1123 if (netif_msg_rx_status(db))
1124 dev_dbg(db->dev, "RX: status %02x, length %04x\n",
1125 rxhdr.RxStatus, RxLen);
1126
1127 /* Packet Status check */
1128 if (RxLen < 0x40) {
1129 GoodPacket = false;
1130 if (netif_msg_rx_err(db))
1131 dev_dbg(db->dev, "RX: Bad Packet (runt)\n");
1132 }
1133
1134 if (RxLen > DM9000_PKT_MAX) {
1135 dev_dbg(db->dev, "RST: RX Len:%x\n", RxLen);
1136 }
1137
1138 /* rxhdr.RxStatus is identical to RSR register. */
1139 if (rxhdr.RxStatus & (RSR_FOE | RSR_CE | RSR_AE |
1140 RSR_PLE | RSR_RWTO |
1141 RSR_LCS | RSR_RF)) {
1142 GoodPacket = false;
1143 if (rxhdr.RxStatus & RSR_FOE) {
1144 if (netif_msg_rx_err(db))
1145 dev_dbg(db->dev, "fifo error\n");
1146 dev->stats.rx_fifo_errors++;
1147 }
1148 if (rxhdr.RxStatus & RSR_CE) {
1149 if (netif_msg_rx_err(db))
1150 dev_dbg(db->dev, "crc error\n");
1151 dev->stats.rx_crc_errors++;
1152 }
1153 if (rxhdr.RxStatus & RSR_RF) {
1154 if (netif_msg_rx_err(db))
1155 dev_dbg(db->dev, "length error\n");
1156 dev->stats.rx_length_errors++;
1157 }
1158 }
1159
1160 /* Move data from DM9000 */
1161 if (GoodPacket &&
1162 ((skb = netdev_alloc_skb(dev, RxLen + 4)) != NULL)) {
1163 skb_reserve(skb, 2);
1164 rdptr = skb_put(skb, RxLen - 4);
1165
1166 /* Read received packet from RX SRAM */
1167
1168 (db->inblk)(db->io_data, rdptr, RxLen);
1169 dev->stats.rx_bytes += RxLen;
1170
1171 /* Pass to upper layer */
1172 skb->protocol = eth_type_trans(skb, dev);
1173 if (dev->features & NETIF_F_RXCSUM) {
1174 if ((((rxbyte & 0x1c) << 3) & rxbyte) == 0)
1175 skb->ip_summed = CHECKSUM_UNNECESSARY;
1176 else
1177 skb_checksum_none_assert(skb);
1178 }
1179 netif_rx(skb);
1180 dev->stats.rx_packets++;
1181
1182 } else {
1183 /* need to dump the packet's data */
1184
1185 (db->dumpblk)(db->io_data, RxLen);
1186 }
1187 } while (rxbyte & DM9000_PKT_RDY);
1188 }
1189
dm9000_interrupt(int irq,void * dev_id)1190 static irqreturn_t dm9000_interrupt(int irq, void *dev_id)
1191 {
1192 struct net_device *dev = dev_id;
1193 struct board_info *db = netdev_priv(dev);
1194 int int_status;
1195 unsigned long flags;
1196 u8 reg_save;
1197
1198 dm9000_dbg(db, 3, "entering %s\n", __func__);
1199
1200 /* A real interrupt coming */
1201
1202 /* holders of db->lock must always block IRQs */
1203 spin_lock_irqsave(&db->lock, flags);
1204
1205 /* Save previous register address */
1206 reg_save = readb(db->io_addr);
1207
1208 dm9000_mask_interrupts(db);
1209 /* Got DM9000 interrupt status */
1210 int_status = ior(db, DM9000_ISR); /* Got ISR */
1211 iow(db, DM9000_ISR, int_status); /* Clear ISR status */
1212
1213 if (netif_msg_intr(db))
1214 dev_dbg(db->dev, "interrupt status %02x\n", int_status);
1215
1216 /* Received the coming packet */
1217 if (int_status & ISR_PRS)
1218 dm9000_rx(dev);
1219
1220 /* Transmit Interrupt check */
1221 if (int_status & ISR_PTS)
1222 dm9000_tx_done(dev, db);
1223
1224 if (db->type != TYPE_DM9000E) {
1225 if (int_status & ISR_LNKCHNG) {
1226 /* fire a link-change request */
1227 schedule_delayed_work(&db->phy_poll, 1);
1228 }
1229 }
1230
1231 dm9000_unmask_interrupts(db);
1232 /* Restore previous register address */
1233 writeb(reg_save, db->io_addr);
1234
1235 spin_unlock_irqrestore(&db->lock, flags);
1236
1237 return IRQ_HANDLED;
1238 }
1239
dm9000_wol_interrupt(int irq,void * dev_id)1240 static irqreturn_t dm9000_wol_interrupt(int irq, void *dev_id)
1241 {
1242 struct net_device *dev = dev_id;
1243 struct board_info *db = netdev_priv(dev);
1244 unsigned long flags;
1245 unsigned nsr, wcr;
1246
1247 spin_lock_irqsave(&db->lock, flags);
1248
1249 nsr = ior(db, DM9000_NSR);
1250 wcr = ior(db, DM9000_WCR);
1251
1252 dev_dbg(db->dev, "%s: NSR=0x%02x, WCR=0x%02x\n", __func__, nsr, wcr);
1253
1254 if (nsr & NSR_WAKEST) {
1255 /* clear, so we can avoid */
1256 iow(db, DM9000_NSR, NSR_WAKEST);
1257
1258 if (wcr & WCR_LINKST)
1259 dev_info(db->dev, "wake by link status change\n");
1260 if (wcr & WCR_SAMPLEST)
1261 dev_info(db->dev, "wake by sample packet\n");
1262 if (wcr & WCR_MAGICST)
1263 dev_info(db->dev, "wake by magic packet\n");
1264 if (!(wcr & (WCR_LINKST | WCR_SAMPLEST | WCR_MAGICST)))
1265 dev_err(db->dev, "wake signalled with no reason? "
1266 "NSR=0x%02x, WSR=0x%02x\n", nsr, wcr);
1267 }
1268
1269 spin_unlock_irqrestore(&db->lock, flags);
1270
1271 return (nsr & NSR_WAKEST) ? IRQ_HANDLED : IRQ_NONE;
1272 }
1273
1274 #ifdef CONFIG_NET_POLL_CONTROLLER
1275 /*
1276 *Used by netconsole
1277 */
dm9000_poll_controller(struct net_device * dev)1278 static void dm9000_poll_controller(struct net_device *dev)
1279 {
1280 disable_irq(dev->irq);
1281 dm9000_interrupt(dev->irq, dev);
1282 enable_irq(dev->irq);
1283 }
1284 #endif
1285
1286 /*
1287 * Open the interface.
1288 * The interface is opened whenever "ifconfig" actives it.
1289 */
1290 static int
dm9000_open(struct net_device * dev)1291 dm9000_open(struct net_device *dev)
1292 {
1293 struct board_info *db = netdev_priv(dev);
1294 unsigned int irq_flags = irq_get_trigger_type(dev->irq);
1295
1296 if (netif_msg_ifup(db))
1297 dev_dbg(db->dev, "enabling %s\n", dev->name);
1298
1299 /* If there is no IRQ type specified, tell the user that this is a
1300 * problem
1301 */
1302 if (irq_flags == IRQF_TRIGGER_NONE)
1303 dev_warn(db->dev, "WARNING: no IRQ resource flags set.\n");
1304
1305 irq_flags |= IRQF_SHARED;
1306
1307 /* GPIO0 on pre-activate PHY, Reg 1F is not set by reset */
1308 iow(db, DM9000_GPR, 0); /* REG_1F bit0 activate phyxcer */
1309 mdelay(1); /* delay needs by DM9000B */
1310
1311 /* Initialize DM9000 board */
1312 dm9000_init_dm9000(dev);
1313
1314 if (request_irq(dev->irq, dm9000_interrupt, irq_flags, dev->name, dev))
1315 return -EAGAIN;
1316 /* Now that we have an interrupt handler hooked up we can unmask
1317 * our interrupts
1318 */
1319 dm9000_unmask_interrupts(db);
1320
1321 /* Init driver variable */
1322 db->dbug_cnt = 0;
1323
1324 mii_check_media(&db->mii, netif_msg_link(db), 1);
1325 netif_start_queue(dev);
1326
1327 /* Poll initial link status */
1328 schedule_delayed_work(&db->phy_poll, 1);
1329
1330 return 0;
1331 }
1332
1333 static void
dm9000_shutdown(struct net_device * dev)1334 dm9000_shutdown(struct net_device *dev)
1335 {
1336 struct board_info *db = netdev_priv(dev);
1337
1338 /* RESET device */
1339 dm9000_phy_write(dev, 0, MII_BMCR, BMCR_RESET); /* PHY RESET */
1340 iow(db, DM9000_GPR, 0x01); /* Power-Down PHY */
1341 dm9000_mask_interrupts(db);
1342 iow(db, DM9000_RCR, 0x00); /* Disable RX */
1343 }
1344
1345 /*
1346 * Stop the interface.
1347 * The interface is stopped when it is brought.
1348 */
1349 static int
dm9000_stop(struct net_device * ndev)1350 dm9000_stop(struct net_device *ndev)
1351 {
1352 struct board_info *db = netdev_priv(ndev);
1353
1354 if (netif_msg_ifdown(db))
1355 dev_dbg(db->dev, "shutting down %s\n", ndev->name);
1356
1357 cancel_delayed_work_sync(&db->phy_poll);
1358
1359 netif_stop_queue(ndev);
1360 netif_carrier_off(ndev);
1361
1362 /* free interrupt */
1363 free_irq(ndev->irq, ndev);
1364
1365 dm9000_shutdown(ndev);
1366
1367 return 0;
1368 }
1369
1370 static const struct net_device_ops dm9000_netdev_ops = {
1371 .ndo_open = dm9000_open,
1372 .ndo_stop = dm9000_stop,
1373 .ndo_start_xmit = dm9000_start_xmit,
1374 .ndo_tx_timeout = dm9000_timeout,
1375 .ndo_set_rx_mode = dm9000_hash_table,
1376 .ndo_do_ioctl = dm9000_ioctl,
1377 .ndo_set_features = dm9000_set_features,
1378 .ndo_validate_addr = eth_validate_addr,
1379 .ndo_set_mac_address = eth_mac_addr,
1380 #ifdef CONFIG_NET_POLL_CONTROLLER
1381 .ndo_poll_controller = dm9000_poll_controller,
1382 #endif
1383 };
1384
dm9000_parse_dt(struct device * dev)1385 static struct dm9000_plat_data *dm9000_parse_dt(struct device *dev)
1386 {
1387 struct dm9000_plat_data *pdata;
1388 struct device_node *np = dev->of_node;
1389 const void *mac_addr;
1390
1391 if (!IS_ENABLED(CONFIG_OF) || !np)
1392 return ERR_PTR(-ENXIO);
1393
1394 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
1395 if (!pdata)
1396 return ERR_PTR(-ENOMEM);
1397
1398 if (of_find_property(np, "davicom,ext-phy", NULL))
1399 pdata->flags |= DM9000_PLATF_EXT_PHY;
1400 if (of_find_property(np, "davicom,no-eeprom", NULL))
1401 pdata->flags |= DM9000_PLATF_NO_EEPROM;
1402
1403 mac_addr = of_get_mac_address(np);
1404 if (!IS_ERR(mac_addr))
1405 ether_addr_copy(pdata->dev_addr, mac_addr);
1406 else if (PTR_ERR(mac_addr) == -EPROBE_DEFER)
1407 return ERR_CAST(mac_addr);
1408
1409 return pdata;
1410 }
1411
1412 /*
1413 * Search DM9000 board, allocate space and register it
1414 */
1415 static int
dm9000_probe(struct platform_device * pdev)1416 dm9000_probe(struct platform_device *pdev)
1417 {
1418 struct dm9000_plat_data *pdata = dev_get_platdata(&pdev->dev);
1419 struct board_info *db; /* Point a board information structure */
1420 struct net_device *ndev;
1421 struct device *dev = &pdev->dev;
1422 const unsigned char *mac_src;
1423 int ret = 0;
1424 int iosize;
1425 int i;
1426 u32 id_val;
1427 int reset_gpios;
1428 enum of_gpio_flags flags;
1429 struct regulator *power;
1430 bool inv_mac_addr = false;
1431
1432 power = devm_regulator_get(dev, "vcc");
1433 if (IS_ERR(power)) {
1434 if (PTR_ERR(power) == -EPROBE_DEFER)
1435 return -EPROBE_DEFER;
1436 dev_dbg(dev, "no regulator provided\n");
1437 } else {
1438 ret = regulator_enable(power);
1439 if (ret != 0) {
1440 dev_err(dev,
1441 "Failed to enable power regulator: %d\n", ret);
1442 return ret;
1443 }
1444 dev_dbg(dev, "regulator enabled\n");
1445 }
1446
1447 reset_gpios = of_get_named_gpio_flags(dev->of_node, "reset-gpios", 0,
1448 &flags);
1449 if (gpio_is_valid(reset_gpios)) {
1450 ret = devm_gpio_request_one(dev, reset_gpios, flags,
1451 "dm9000_reset");
1452 if (ret) {
1453 dev_err(dev, "failed to request reset gpio %d: %d\n",
1454 reset_gpios, ret);
1455 return -ENODEV;
1456 }
1457
1458 /* According to manual PWRST# Low Period Min 1ms */
1459 msleep(2);
1460 gpio_set_value(reset_gpios, 1);
1461 /* Needs 3ms to read eeprom when PWRST is deasserted */
1462 msleep(4);
1463 }
1464
1465 if (!pdata) {
1466 pdata = dm9000_parse_dt(&pdev->dev);
1467 if (IS_ERR(pdata))
1468 return PTR_ERR(pdata);
1469 }
1470
1471 /* Init network device */
1472 ndev = alloc_etherdev(sizeof(struct board_info));
1473 if (!ndev)
1474 return -ENOMEM;
1475
1476 SET_NETDEV_DEV(ndev, &pdev->dev);
1477
1478 dev_dbg(&pdev->dev, "dm9000_probe()\n");
1479
1480 /* setup board info structure */
1481 db = netdev_priv(ndev);
1482
1483 db->dev = &pdev->dev;
1484 db->ndev = ndev;
1485
1486 spin_lock_init(&db->lock);
1487 mutex_init(&db->addr_lock);
1488
1489 INIT_DELAYED_WORK(&db->phy_poll, dm9000_poll_work);
1490
1491 db->addr_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1492 db->data_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1493
1494 if (!db->addr_res || !db->data_res) {
1495 dev_err(db->dev, "insufficient resources addr=%p data=%p\n",
1496 db->addr_res, db->data_res);
1497 ret = -ENOENT;
1498 goto out;
1499 }
1500
1501 ndev->irq = platform_get_irq(pdev, 0);
1502 if (ndev->irq < 0) {
1503 ret = ndev->irq;
1504 goto out;
1505 }
1506
1507 db->irq_wake = platform_get_irq(pdev, 1);
1508 if (db->irq_wake >= 0) {
1509 dev_dbg(db->dev, "wakeup irq %d\n", db->irq_wake);
1510
1511 ret = request_irq(db->irq_wake, dm9000_wol_interrupt,
1512 IRQF_SHARED, dev_name(db->dev), ndev);
1513 if (ret) {
1514 dev_err(db->dev, "cannot get wakeup irq (%d)\n", ret);
1515 } else {
1516
1517 /* test to see if irq is really wakeup capable */
1518 ret = irq_set_irq_wake(db->irq_wake, 1);
1519 if (ret) {
1520 dev_err(db->dev, "irq %d cannot set wakeup (%d)\n",
1521 db->irq_wake, ret);
1522 ret = 0;
1523 } else {
1524 irq_set_irq_wake(db->irq_wake, 0);
1525 db->wake_supported = 1;
1526 }
1527 }
1528 }
1529
1530 iosize = resource_size(db->addr_res);
1531 db->addr_req = request_mem_region(db->addr_res->start, iosize,
1532 pdev->name);
1533
1534 if (db->addr_req == NULL) {
1535 dev_err(db->dev, "cannot claim address reg area\n");
1536 ret = -EIO;
1537 goto out;
1538 }
1539
1540 db->io_addr = ioremap(db->addr_res->start, iosize);
1541
1542 if (db->io_addr == NULL) {
1543 dev_err(db->dev, "failed to ioremap address reg\n");
1544 ret = -EINVAL;
1545 goto out;
1546 }
1547
1548 iosize = resource_size(db->data_res);
1549 db->data_req = request_mem_region(db->data_res->start, iosize,
1550 pdev->name);
1551
1552 if (db->data_req == NULL) {
1553 dev_err(db->dev, "cannot claim data reg area\n");
1554 ret = -EIO;
1555 goto out;
1556 }
1557
1558 db->io_data = ioremap(db->data_res->start, iosize);
1559
1560 if (db->io_data == NULL) {
1561 dev_err(db->dev, "failed to ioremap data reg\n");
1562 ret = -EINVAL;
1563 goto out;
1564 }
1565
1566 /* fill in parameters for net-dev structure */
1567 ndev->base_addr = (unsigned long)db->io_addr;
1568
1569 /* ensure at least we have a default set of IO routines */
1570 dm9000_set_io(db, iosize);
1571
1572 /* check to see if anything is being over-ridden */
1573 if (pdata != NULL) {
1574 /* check to see if the driver wants to over-ride the
1575 * default IO width */
1576
1577 if (pdata->flags & DM9000_PLATF_8BITONLY)
1578 dm9000_set_io(db, 1);
1579
1580 if (pdata->flags & DM9000_PLATF_16BITONLY)
1581 dm9000_set_io(db, 2);
1582
1583 if (pdata->flags & DM9000_PLATF_32BITONLY)
1584 dm9000_set_io(db, 4);
1585
1586 /* check to see if there are any IO routine
1587 * over-rides */
1588
1589 if (pdata->inblk != NULL)
1590 db->inblk = pdata->inblk;
1591
1592 if (pdata->outblk != NULL)
1593 db->outblk = pdata->outblk;
1594
1595 if (pdata->dumpblk != NULL)
1596 db->dumpblk = pdata->dumpblk;
1597
1598 db->flags = pdata->flags;
1599 }
1600
1601 #ifdef CONFIG_DM9000_FORCE_SIMPLE_PHY_POLL
1602 db->flags |= DM9000_PLATF_SIMPLE_PHY;
1603 #endif
1604
1605 dm9000_reset(db);
1606
1607 /* try multiple times, DM9000 sometimes gets the read wrong */
1608 for (i = 0; i < 8; i++) {
1609 id_val = ior(db, DM9000_VIDL);
1610 id_val |= (u32)ior(db, DM9000_VIDH) << 8;
1611 id_val |= (u32)ior(db, DM9000_PIDL) << 16;
1612 id_val |= (u32)ior(db, DM9000_PIDH) << 24;
1613
1614 if (id_val == DM9000_ID)
1615 break;
1616 dev_err(db->dev, "read wrong id 0x%08x\n", id_val);
1617 }
1618
1619 if (id_val != DM9000_ID) {
1620 dev_err(db->dev, "wrong id: 0x%08x\n", id_val);
1621 ret = -ENODEV;
1622 goto out;
1623 }
1624
1625 /* Identify what type of DM9000 we are working on */
1626
1627 id_val = ior(db, DM9000_CHIPR);
1628 dev_dbg(db->dev, "dm9000 revision 0x%02x\n", id_val);
1629
1630 switch (id_val) {
1631 case CHIPR_DM9000A:
1632 db->type = TYPE_DM9000A;
1633 break;
1634 case CHIPR_DM9000B:
1635 db->type = TYPE_DM9000B;
1636 break;
1637 default:
1638 dev_dbg(db->dev, "ID %02x => defaulting to DM9000E\n", id_val);
1639 db->type = TYPE_DM9000E;
1640 }
1641
1642 /* dm9000a/b are capable of hardware checksum offload */
1643 if (db->type == TYPE_DM9000A || db->type == TYPE_DM9000B) {
1644 ndev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM;
1645 ndev->features |= ndev->hw_features;
1646 }
1647
1648 /* from this point we assume that we have found a DM9000 */
1649
1650 ndev->netdev_ops = &dm9000_netdev_ops;
1651 ndev->watchdog_timeo = msecs_to_jiffies(watchdog);
1652 ndev->ethtool_ops = &dm9000_ethtool_ops;
1653
1654 db->msg_enable = NETIF_MSG_LINK;
1655 db->mii.phy_id_mask = 0x1f;
1656 db->mii.reg_num_mask = 0x1f;
1657 db->mii.force_media = 0;
1658 db->mii.full_duplex = 0;
1659 db->mii.dev = ndev;
1660 db->mii.mdio_read = dm9000_phy_read;
1661 db->mii.mdio_write = dm9000_phy_write;
1662
1663 mac_src = "eeprom";
1664
1665 /* try reading the node address from the attached EEPROM */
1666 for (i = 0; i < 6; i += 2)
1667 dm9000_read_eeprom(db, i / 2, ndev->dev_addr+i);
1668
1669 if (!is_valid_ether_addr(ndev->dev_addr) && pdata != NULL) {
1670 mac_src = "platform data";
1671 memcpy(ndev->dev_addr, pdata->dev_addr, ETH_ALEN);
1672 }
1673
1674 if (!is_valid_ether_addr(ndev->dev_addr)) {
1675 /* try reading from mac */
1676
1677 mac_src = "chip";
1678 for (i = 0; i < 6; i++)
1679 ndev->dev_addr[i] = ior(db, i+DM9000_PAR);
1680 }
1681
1682 if (!is_valid_ether_addr(ndev->dev_addr)) {
1683 inv_mac_addr = true;
1684 eth_hw_addr_random(ndev);
1685 mac_src = "random";
1686 }
1687
1688
1689 platform_set_drvdata(pdev, ndev);
1690 ret = register_netdev(ndev);
1691
1692 if (ret == 0) {
1693 if (inv_mac_addr)
1694 dev_warn(db->dev, "%s: Invalid ethernet MAC address. Please set using ip\n",
1695 ndev->name);
1696 printk(KERN_INFO "%s: dm9000%c at %p,%p IRQ %d MAC: %pM (%s)\n",
1697 ndev->name, dm9000_type_to_char(db->type),
1698 db->io_addr, db->io_data, ndev->irq,
1699 ndev->dev_addr, mac_src);
1700 }
1701 return 0;
1702
1703 out:
1704 dev_err(db->dev, "not found (%d).\n", ret);
1705
1706 dm9000_release_board(pdev, db);
1707 free_netdev(ndev);
1708
1709 return ret;
1710 }
1711
1712 static int
dm9000_drv_suspend(struct device * dev)1713 dm9000_drv_suspend(struct device *dev)
1714 {
1715 struct net_device *ndev = dev_get_drvdata(dev);
1716 struct board_info *db;
1717
1718 if (ndev) {
1719 db = netdev_priv(ndev);
1720 db->in_suspend = 1;
1721
1722 if (!netif_running(ndev))
1723 return 0;
1724
1725 netif_device_detach(ndev);
1726
1727 /* only shutdown if not using WoL */
1728 if (!db->wake_state)
1729 dm9000_shutdown(ndev);
1730 }
1731 return 0;
1732 }
1733
1734 static int
dm9000_drv_resume(struct device * dev)1735 dm9000_drv_resume(struct device *dev)
1736 {
1737 struct net_device *ndev = dev_get_drvdata(dev);
1738 struct board_info *db = netdev_priv(ndev);
1739
1740 if (ndev) {
1741 if (netif_running(ndev)) {
1742 /* reset if we were not in wake mode to ensure if
1743 * the device was powered off it is in a known state */
1744 if (!db->wake_state) {
1745 dm9000_init_dm9000(ndev);
1746 dm9000_unmask_interrupts(db);
1747 }
1748
1749 netif_device_attach(ndev);
1750 }
1751
1752 db->in_suspend = 0;
1753 }
1754 return 0;
1755 }
1756
1757 static const struct dev_pm_ops dm9000_drv_pm_ops = {
1758 .suspend = dm9000_drv_suspend,
1759 .resume = dm9000_drv_resume,
1760 };
1761
1762 static int
dm9000_drv_remove(struct platform_device * pdev)1763 dm9000_drv_remove(struct platform_device *pdev)
1764 {
1765 struct net_device *ndev = platform_get_drvdata(pdev);
1766
1767 unregister_netdev(ndev);
1768 dm9000_release_board(pdev, netdev_priv(ndev));
1769 free_netdev(ndev); /* free device structure */
1770
1771 dev_dbg(&pdev->dev, "released and freed device\n");
1772 return 0;
1773 }
1774
1775 #ifdef CONFIG_OF
1776 static const struct of_device_id dm9000_of_matches[] = {
1777 { .compatible = "davicom,dm9000", },
1778 { /* sentinel */ }
1779 };
1780 MODULE_DEVICE_TABLE(of, dm9000_of_matches);
1781 #endif
1782
1783 static struct platform_driver dm9000_driver = {
1784 .driver = {
1785 .name = "dm9000",
1786 .pm = &dm9000_drv_pm_ops,
1787 .of_match_table = of_match_ptr(dm9000_of_matches),
1788 },
1789 .probe = dm9000_probe,
1790 .remove = dm9000_drv_remove,
1791 };
1792
1793 module_platform_driver(dm9000_driver);
1794
1795 MODULE_AUTHOR("Sascha Hauer, Ben Dooks");
1796 MODULE_DESCRIPTION("Davicom DM9000 network driver");
1797 MODULE_LICENSE("GPL");
1798 MODULE_ALIAS("platform:dm9000");
1799
