1 /*
2 * Freescale QuadSPI driver.
3 *
4 * Copyright (C) 2013 Freescale Semiconductor, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 */
11 #include <linux/kernel.h>
12 #include <linux/module.h>
13 #include <linux/interrupt.h>
14 #include <linux/errno.h>
15 #include <linux/platform_device.h>
16 #include <linux/sched.h>
17 #include <linux/delay.h>
18 #include <linux/io.h>
19 #include <linux/clk.h>
20 #include <linux/err.h>
21 #include <linux/of.h>
22 #include <linux/of_device.h>
23 #include <linux/timer.h>
24 #include <linux/jiffies.h>
25 #include <linux/completion.h>
26 #include <linux/mtd/mtd.h>
27 #include <linux/mtd/partitions.h>
28 #include <linux/mtd/spi-nor.h>
29 #include <linux/mutex.h>
30 #include <linux/pm_qos.h>
31 #include <linux/sizes.h>
32
33 /* Controller needs driver to swap endian */
34 #define QUADSPI_QUIRK_SWAP_ENDIAN (1 << 0)
35 /* Controller needs 4x internal clock */
36 #define QUADSPI_QUIRK_4X_INT_CLK (1 << 1)
37 /*
38 * TKT253890, Controller needs driver to fill txfifo till 16 byte to
39 * trigger data transfer even though extern data will not transferred.
40 */
41 #define QUADSPI_QUIRK_TKT253890 (1 << 2)
42 /* Controller cannot wake up from wait mode, TKT245618 */
43 #define QUADSPI_QUIRK_TKT245618 (1 << 3)
44
45 /* The registers */
46 #define QUADSPI_MCR 0x00
47 #define QUADSPI_MCR_RESERVED_SHIFT 16
48 #define QUADSPI_MCR_RESERVED_MASK (0xF << QUADSPI_MCR_RESERVED_SHIFT)
49 #define QUADSPI_MCR_MDIS_SHIFT 14
50 #define QUADSPI_MCR_MDIS_MASK (1 << QUADSPI_MCR_MDIS_SHIFT)
51 #define QUADSPI_MCR_CLR_TXF_SHIFT 11
52 #define QUADSPI_MCR_CLR_TXF_MASK (1 << QUADSPI_MCR_CLR_TXF_SHIFT)
53 #define QUADSPI_MCR_CLR_RXF_SHIFT 10
54 #define QUADSPI_MCR_CLR_RXF_MASK (1 << QUADSPI_MCR_CLR_RXF_SHIFT)
55 #define QUADSPI_MCR_DDR_EN_SHIFT 7
56 #define QUADSPI_MCR_DDR_EN_MASK (1 << QUADSPI_MCR_DDR_EN_SHIFT)
57 #define QUADSPI_MCR_END_CFG_SHIFT 2
58 #define QUADSPI_MCR_END_CFG_MASK (3 << QUADSPI_MCR_END_CFG_SHIFT)
59 #define QUADSPI_MCR_SWRSTHD_SHIFT 1
60 #define QUADSPI_MCR_SWRSTHD_MASK (1 << QUADSPI_MCR_SWRSTHD_SHIFT)
61 #define QUADSPI_MCR_SWRSTSD_SHIFT 0
62 #define QUADSPI_MCR_SWRSTSD_MASK (1 << QUADSPI_MCR_SWRSTSD_SHIFT)
63
64 #define QUADSPI_IPCR 0x08
65 #define QUADSPI_IPCR_SEQID_SHIFT 24
66 #define QUADSPI_IPCR_SEQID_MASK (0xF << QUADSPI_IPCR_SEQID_SHIFT)
67
68 #define QUADSPI_BUF0CR 0x10
69 #define QUADSPI_BUF1CR 0x14
70 #define QUADSPI_BUF2CR 0x18
71 #define QUADSPI_BUFXCR_INVALID_MSTRID 0xe
72
73 #define QUADSPI_BUF3CR 0x1c
74 #define QUADSPI_BUF3CR_ALLMST_SHIFT 31
75 #define QUADSPI_BUF3CR_ALLMST_MASK (1 << QUADSPI_BUF3CR_ALLMST_SHIFT)
76 #define QUADSPI_BUF3CR_ADATSZ_SHIFT 8
77 #define QUADSPI_BUF3CR_ADATSZ_MASK (0xFF << QUADSPI_BUF3CR_ADATSZ_SHIFT)
78
79 #define QUADSPI_BFGENCR 0x20
80 #define QUADSPI_BFGENCR_PAR_EN_SHIFT 16
81 #define QUADSPI_BFGENCR_PAR_EN_MASK (1 << (QUADSPI_BFGENCR_PAR_EN_SHIFT))
82 #define QUADSPI_BFGENCR_SEQID_SHIFT 12
83 #define QUADSPI_BFGENCR_SEQID_MASK (0xF << QUADSPI_BFGENCR_SEQID_SHIFT)
84
85 #define QUADSPI_BUF0IND 0x30
86 #define QUADSPI_BUF1IND 0x34
87 #define QUADSPI_BUF2IND 0x38
88 #define QUADSPI_SFAR 0x100
89
90 #define QUADSPI_SMPR 0x108
91 #define QUADSPI_SMPR_DDRSMP_SHIFT 16
92 #define QUADSPI_SMPR_DDRSMP_MASK (7 << QUADSPI_SMPR_DDRSMP_SHIFT)
93 #define QUADSPI_SMPR_FSDLY_SHIFT 6
94 #define QUADSPI_SMPR_FSDLY_MASK (1 << QUADSPI_SMPR_FSDLY_SHIFT)
95 #define QUADSPI_SMPR_FSPHS_SHIFT 5
96 #define QUADSPI_SMPR_FSPHS_MASK (1 << QUADSPI_SMPR_FSPHS_SHIFT)
97 #define QUADSPI_SMPR_HSENA_SHIFT 0
98 #define QUADSPI_SMPR_HSENA_MASK (1 << QUADSPI_SMPR_HSENA_SHIFT)
99
100 #define QUADSPI_RBSR 0x10c
101 #define QUADSPI_RBSR_RDBFL_SHIFT 8
102 #define QUADSPI_RBSR_RDBFL_MASK (0x3F << QUADSPI_RBSR_RDBFL_SHIFT)
103
104 #define QUADSPI_RBCT 0x110
105 #define QUADSPI_RBCT_WMRK_MASK 0x1F
106 #define QUADSPI_RBCT_RXBRD_SHIFT 8
107 #define QUADSPI_RBCT_RXBRD_USEIPS (0x1 << QUADSPI_RBCT_RXBRD_SHIFT)
108
109 #define QUADSPI_TBSR 0x150
110 #define QUADSPI_TBDR 0x154
111 #define QUADSPI_SR 0x15c
112 #define QUADSPI_SR_IP_ACC_SHIFT 1
113 #define QUADSPI_SR_IP_ACC_MASK (0x1 << QUADSPI_SR_IP_ACC_SHIFT)
114 #define QUADSPI_SR_AHB_ACC_SHIFT 2
115 #define QUADSPI_SR_AHB_ACC_MASK (0x1 << QUADSPI_SR_AHB_ACC_SHIFT)
116
117 #define QUADSPI_FR 0x160
118 #define QUADSPI_FR_TFF_MASK 0x1
119
120 #define QUADSPI_SFA1AD 0x180
121 #define QUADSPI_SFA2AD 0x184
122 #define QUADSPI_SFB1AD 0x188
123 #define QUADSPI_SFB2AD 0x18c
124 #define QUADSPI_RBDR 0x200
125
126 #define QUADSPI_LUTKEY 0x300
127 #define QUADSPI_LUTKEY_VALUE 0x5AF05AF0
128
129 #define QUADSPI_LCKCR 0x304
130 #define QUADSPI_LCKER_LOCK 0x1
131 #define QUADSPI_LCKER_UNLOCK 0x2
132
133 #define QUADSPI_RSER 0x164
134 #define QUADSPI_RSER_TFIE (0x1 << 0)
135
136 #define QUADSPI_LUT_BASE 0x310
137
138 /*
139 * The definition of the LUT register shows below:
140 *
141 * ---------------------------------------------------
142 * | INSTR1 | PAD1 | OPRND1 | INSTR0 | PAD0 | OPRND0 |
143 * ---------------------------------------------------
144 */
145 #define OPRND0_SHIFT 0
146 #define PAD0_SHIFT 8
147 #define INSTR0_SHIFT 10
148 #define OPRND1_SHIFT 16
149
150 /* Instruction set for the LUT register. */
151 #define LUT_STOP 0
152 #define LUT_CMD 1
153 #define LUT_ADDR 2
154 #define LUT_DUMMY 3
155 #define LUT_MODE 4
156 #define LUT_MODE2 5
157 #define LUT_MODE4 6
158 #define LUT_FSL_READ 7
159 #define LUT_FSL_WRITE 8
160 #define LUT_JMP_ON_CS 9
161 #define LUT_ADDR_DDR 10
162 #define LUT_MODE_DDR 11
163 #define LUT_MODE2_DDR 12
164 #define LUT_MODE4_DDR 13
165 #define LUT_FSL_READ_DDR 14
166 #define LUT_FSL_WRITE_DDR 15
167 #define LUT_DATA_LEARN 16
168
169 /*
170 * The PAD definitions for LUT register.
171 *
172 * The pad stands for the lines number of IO[0:3].
173 * For example, the Quad read need four IO lines, so you should
174 * set LUT_PAD4 which means we use four IO lines.
175 */
176 #define LUT_PAD1 0
177 #define LUT_PAD2 1
178 #define LUT_PAD4 2
179
180 /* Oprands for the LUT register. */
181 #define ADDR24BIT 0x18
182 #define ADDR32BIT 0x20
183
184 /* Macros for constructing the LUT register. */
185 #define LUT0(ins, pad, opr) \
186 (((opr) << OPRND0_SHIFT) | ((LUT_##pad) << PAD0_SHIFT) | \
187 ((LUT_##ins) << INSTR0_SHIFT))
188
189 #define LUT1(ins, pad, opr) (LUT0(ins, pad, opr) << OPRND1_SHIFT)
190
191 /* other macros for LUT register. */
192 #define QUADSPI_LUT(x) (QUADSPI_LUT_BASE + (x) * 4)
193 #define QUADSPI_LUT_NUM 64
194
195 /* SEQID -- we can have 16 seqids at most. */
196 #define SEQID_READ 0
197 #define SEQID_WREN 1
198 #define SEQID_WRDI 2
199 #define SEQID_RDSR 3
200 #define SEQID_SE 4
201 #define SEQID_CHIP_ERASE 5
202 #define SEQID_PP 6
203 #define SEQID_RDID 7
204 #define SEQID_WRSR 8
205 #define SEQID_RDCR 9
206 #define SEQID_EN4B 10
207 #define SEQID_BRWR 11
208
209 #define QUADSPI_MIN_IOMAP SZ_4M
210
211 enum fsl_qspi_devtype {
212 FSL_QUADSPI_VYBRID,
213 FSL_QUADSPI_IMX6SX,
214 FSL_QUADSPI_IMX7D,
215 FSL_QUADSPI_IMX6UL,
216 FSL_QUADSPI_LS1021A,
217 FSL_QUADSPI_LS2080A,
218 };
219
220 struct fsl_qspi_devtype_data {
221 enum fsl_qspi_devtype devtype;
222 int rxfifo;
223 int txfifo;
224 int ahb_buf_size;
225 int driver_data;
226 };
227
228 static const struct fsl_qspi_devtype_data vybrid_data = {
229 .devtype = FSL_QUADSPI_VYBRID,
230 .rxfifo = 128,
231 .txfifo = 64,
232 .ahb_buf_size = 1024,
233 .driver_data = QUADSPI_QUIRK_SWAP_ENDIAN,
234 };
235
236 static const struct fsl_qspi_devtype_data imx6sx_data = {
237 .devtype = FSL_QUADSPI_IMX6SX,
238 .rxfifo = 128,
239 .txfifo = 512,
240 .ahb_buf_size = 1024,
241 .driver_data = QUADSPI_QUIRK_4X_INT_CLK
242 | QUADSPI_QUIRK_TKT245618,
243 };
244
245 static const struct fsl_qspi_devtype_data imx7d_data = {
246 .devtype = FSL_QUADSPI_IMX7D,
247 .rxfifo = 512,
248 .txfifo = 512,
249 .ahb_buf_size = 1024,
250 .driver_data = QUADSPI_QUIRK_TKT253890
251 | QUADSPI_QUIRK_4X_INT_CLK,
252 };
253
254 static const struct fsl_qspi_devtype_data imx6ul_data = {
255 .devtype = FSL_QUADSPI_IMX6UL,
256 .rxfifo = 128,
257 .txfifo = 512,
258 .ahb_buf_size = 1024,
259 .driver_data = QUADSPI_QUIRK_TKT253890
260 | QUADSPI_QUIRK_4X_INT_CLK,
261 };
262
263 static struct fsl_qspi_devtype_data ls1021a_data = {
264 .devtype = FSL_QUADSPI_LS1021A,
265 .rxfifo = 128,
266 .txfifo = 64,
267 .ahb_buf_size = 1024,
268 .driver_data = 0,
269 };
270
271 static const struct fsl_qspi_devtype_data ls2080a_data = {
272 .devtype = FSL_QUADSPI_LS2080A,
273 .rxfifo = 128,
274 .txfifo = 64,
275 .ahb_buf_size = 1024,
276 .driver_data = QUADSPI_QUIRK_TKT253890,
277 };
278
279
280 #define FSL_QSPI_MAX_CHIP 4
281 struct fsl_qspi {
282 struct spi_nor nor[FSL_QSPI_MAX_CHIP];
283 void __iomem *iobase;
284 void __iomem *ahb_addr;
285 u32 memmap_phy;
286 u32 memmap_offs;
287 u32 memmap_len;
288 struct clk *clk, *clk_en;
289 struct device *dev;
290 struct completion c;
291 const struct fsl_qspi_devtype_data *devtype_data;
292 u32 nor_size;
293 u32 nor_num;
294 u32 clk_rate;
295 unsigned int chip_base_addr; /* We may support two chips. */
296 bool has_second_chip;
297 bool big_endian;
298 struct mutex lock;
299 struct pm_qos_request pm_qos_req;
300 };
301
needs_swap_endian(struct fsl_qspi * q)302 static inline int needs_swap_endian(struct fsl_qspi *q)
303 {
304 return q->devtype_data->driver_data & QUADSPI_QUIRK_SWAP_ENDIAN;
305 }
306
needs_4x_clock(struct fsl_qspi * q)307 static inline int needs_4x_clock(struct fsl_qspi *q)
308 {
309 return q->devtype_data->driver_data & QUADSPI_QUIRK_4X_INT_CLK;
310 }
311
needs_fill_txfifo(struct fsl_qspi * q)312 static inline int needs_fill_txfifo(struct fsl_qspi *q)
313 {
314 return q->devtype_data->driver_data & QUADSPI_QUIRK_TKT253890;
315 }
316
needs_wakeup_wait_mode(struct fsl_qspi * q)317 static inline int needs_wakeup_wait_mode(struct fsl_qspi *q)
318 {
319 return q->devtype_data->driver_data & QUADSPI_QUIRK_TKT245618;
320 }
321
322 /*
323 * R/W functions for big- or little-endian registers:
324 * The qSPI controller's endian is independent of the CPU core's endian.
325 * So far, although the CPU core is little-endian but the qSPI have two
326 * versions for big-endian and little-endian.
327 */
qspi_writel(struct fsl_qspi * q,u32 val,void __iomem * addr)328 static void qspi_writel(struct fsl_qspi *q, u32 val, void __iomem *addr)
329 {
330 if (q->big_endian)
331 iowrite32be(val, addr);
332 else
333 iowrite32(val, addr);
334 }
335
qspi_readl(struct fsl_qspi * q,void __iomem * addr)336 static u32 qspi_readl(struct fsl_qspi *q, void __iomem *addr)
337 {
338 if (q->big_endian)
339 return ioread32be(addr);
340 else
341 return ioread32(addr);
342 }
343
344 /*
345 * An IC bug makes us to re-arrange the 32-bit data.
346 * The following chips, such as IMX6SLX, have fixed this bug.
347 */
fsl_qspi_endian_xchg(struct fsl_qspi * q,u32 a)348 static inline u32 fsl_qspi_endian_xchg(struct fsl_qspi *q, u32 a)
349 {
350 return needs_swap_endian(q) ? __swab32(a) : a;
351 }
352
fsl_qspi_unlock_lut(struct fsl_qspi * q)353 static inline void fsl_qspi_unlock_lut(struct fsl_qspi *q)
354 {
355 qspi_writel(q, QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);
356 qspi_writel(q, QUADSPI_LCKER_UNLOCK, q->iobase + QUADSPI_LCKCR);
357 }
358
fsl_qspi_lock_lut(struct fsl_qspi * q)359 static inline void fsl_qspi_lock_lut(struct fsl_qspi *q)
360 {
361 qspi_writel(q, QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);
362 qspi_writel(q, QUADSPI_LCKER_LOCK, q->iobase + QUADSPI_LCKCR);
363 }
364
fsl_qspi_irq_handler(int irq,void * dev_id)365 static irqreturn_t fsl_qspi_irq_handler(int irq, void *dev_id)
366 {
367 struct fsl_qspi *q = dev_id;
368 u32 reg;
369
370 /* clear interrupt */
371 reg = qspi_readl(q, q->iobase + QUADSPI_FR);
372 qspi_writel(q, reg, q->iobase + QUADSPI_FR);
373
374 if (reg & QUADSPI_FR_TFF_MASK)
375 complete(&q->c);
376
377 dev_dbg(q->dev, "QUADSPI_FR : 0x%.8x:0x%.8x\n", q->chip_base_addr, reg);
378 return IRQ_HANDLED;
379 }
380
fsl_qspi_init_lut(struct fsl_qspi * q)381 static void fsl_qspi_init_lut(struct fsl_qspi *q)
382 {
383 void __iomem *base = q->iobase;
384 int rxfifo = q->devtype_data->rxfifo;
385 u32 lut_base;
386 int i;
387
388 struct spi_nor *nor = &q->nor[0];
389 u8 addrlen = (nor->addr_width == 3) ? ADDR24BIT : ADDR32BIT;
390 u8 read_op = nor->read_opcode;
391 u8 read_dm = nor->read_dummy;
392
393 fsl_qspi_unlock_lut(q);
394
395 /* Clear all the LUT table */
396 for (i = 0; i < QUADSPI_LUT_NUM; i++)
397 qspi_writel(q, 0, base + QUADSPI_LUT_BASE + i * 4);
398
399 /* Read */
400 lut_base = SEQID_READ * 4;
401
402 qspi_writel(q, LUT0(CMD, PAD1, read_op) | LUT1(ADDR, PAD1, addrlen),
403 base + QUADSPI_LUT(lut_base));
404 qspi_writel(q, LUT0(DUMMY, PAD1, read_dm) |
405 LUT1(FSL_READ, PAD4, rxfifo),
406 base + QUADSPI_LUT(lut_base + 1));
407
408 /* Write enable */
409 lut_base = SEQID_WREN * 4;
410 qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_WREN),
411 base + QUADSPI_LUT(lut_base));
412
413 /* Page Program */
414 lut_base = SEQID_PP * 4;
415
416 qspi_writel(q, LUT0(CMD, PAD1, nor->program_opcode) |
417 LUT1(ADDR, PAD1, addrlen),
418 base + QUADSPI_LUT(lut_base));
419 qspi_writel(q, LUT0(FSL_WRITE, PAD1, 0),
420 base + QUADSPI_LUT(lut_base + 1));
421
422 /* Read Status */
423 lut_base = SEQID_RDSR * 4;
424 qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_RDSR) |
425 LUT1(FSL_READ, PAD1, 0x1),
426 base + QUADSPI_LUT(lut_base));
427
428 /* Erase a sector */
429 lut_base = SEQID_SE * 4;
430
431 qspi_writel(q, LUT0(CMD, PAD1, nor->erase_opcode) |
432 LUT1(ADDR, PAD1, addrlen),
433 base + QUADSPI_LUT(lut_base));
434
435 /* Erase the whole chip */
436 lut_base = SEQID_CHIP_ERASE * 4;
437 qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_CHIP_ERASE),
438 base + QUADSPI_LUT(lut_base));
439
440 /* READ ID */
441 lut_base = SEQID_RDID * 4;
442 qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_RDID) |
443 LUT1(FSL_READ, PAD1, 0x8),
444 base + QUADSPI_LUT(lut_base));
445
446 /* Write Register */
447 lut_base = SEQID_WRSR * 4;
448 qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_WRSR) |
449 LUT1(FSL_WRITE, PAD1, 0x2),
450 base + QUADSPI_LUT(lut_base));
451
452 /* Read Configuration Register */
453 lut_base = SEQID_RDCR * 4;
454 qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_RDCR) |
455 LUT1(FSL_READ, PAD1, 0x1),
456 base + QUADSPI_LUT(lut_base));
457
458 /* Write disable */
459 lut_base = SEQID_WRDI * 4;
460 qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_WRDI),
461 base + QUADSPI_LUT(lut_base));
462
463 /* Enter 4 Byte Mode (Micron) */
464 lut_base = SEQID_EN4B * 4;
465 qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_EN4B),
466 base + QUADSPI_LUT(lut_base));
467
468 /* Enter 4 Byte Mode (Spansion) */
469 lut_base = SEQID_BRWR * 4;
470 qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_BRWR),
471 base + QUADSPI_LUT(lut_base));
472
473 fsl_qspi_lock_lut(q);
474 }
475
476 /* Get the SEQID for the command */
fsl_qspi_get_seqid(struct fsl_qspi * q,u8 cmd)477 static int fsl_qspi_get_seqid(struct fsl_qspi *q, u8 cmd)
478 {
479 switch (cmd) {
480 case SPINOR_OP_READ_1_1_4:
481 return SEQID_READ;
482 case SPINOR_OP_WREN:
483 return SEQID_WREN;
484 case SPINOR_OP_WRDI:
485 return SEQID_WRDI;
486 case SPINOR_OP_RDSR:
487 return SEQID_RDSR;
488 case SPINOR_OP_SE:
489 return SEQID_SE;
490 case SPINOR_OP_CHIP_ERASE:
491 return SEQID_CHIP_ERASE;
492 case SPINOR_OP_PP:
493 return SEQID_PP;
494 case SPINOR_OP_RDID:
495 return SEQID_RDID;
496 case SPINOR_OP_WRSR:
497 return SEQID_WRSR;
498 case SPINOR_OP_RDCR:
499 return SEQID_RDCR;
500 case SPINOR_OP_EN4B:
501 return SEQID_EN4B;
502 case SPINOR_OP_BRWR:
503 return SEQID_BRWR;
504 default:
505 if (cmd == q->nor[0].erase_opcode)
506 return SEQID_SE;
507 dev_err(q->dev, "Unsupported cmd 0x%.2x\n", cmd);
508 break;
509 }
510 return -EINVAL;
511 }
512
513 static int
fsl_qspi_runcmd(struct fsl_qspi * q,u8 cmd,unsigned int addr,int len)514 fsl_qspi_runcmd(struct fsl_qspi *q, u8 cmd, unsigned int addr, int len)
515 {
516 void __iomem *base = q->iobase;
517 int seqid;
518 u32 reg, reg2;
519 int err;
520
521 init_completion(&q->c);
522 dev_dbg(q->dev, "to 0x%.8x:0x%.8x, len:%d, cmd:%.2x\n",
523 q->chip_base_addr, addr, len, cmd);
524
525 /* save the reg */
526 reg = qspi_readl(q, base + QUADSPI_MCR);
527
528 qspi_writel(q, q->memmap_phy + q->chip_base_addr + addr,
529 base + QUADSPI_SFAR);
530 qspi_writel(q, QUADSPI_RBCT_WMRK_MASK | QUADSPI_RBCT_RXBRD_USEIPS,
531 base + QUADSPI_RBCT);
532 qspi_writel(q, reg | QUADSPI_MCR_CLR_RXF_MASK, base + QUADSPI_MCR);
533
534 do {
535 reg2 = qspi_readl(q, base + QUADSPI_SR);
536 if (reg2 & (QUADSPI_SR_IP_ACC_MASK | QUADSPI_SR_AHB_ACC_MASK)) {
537 udelay(1);
538 dev_dbg(q->dev, "The controller is busy, 0x%x\n", reg2);
539 continue;
540 }
541 break;
542 } while (1);
543
544 /* trigger the LUT now */
545 seqid = fsl_qspi_get_seqid(q, cmd);
546 qspi_writel(q, (seqid << QUADSPI_IPCR_SEQID_SHIFT) | len,
547 base + QUADSPI_IPCR);
548
549 /* Wait for the interrupt. */
550 if (!wait_for_completion_timeout(&q->c, msecs_to_jiffies(1000))) {
551 dev_err(q->dev,
552 "cmd 0x%.2x timeout, addr@%.8x, FR:0x%.8x, SR:0x%.8x\n",
553 cmd, addr, qspi_readl(q, base + QUADSPI_FR),
554 qspi_readl(q, base + QUADSPI_SR));
555 err = -ETIMEDOUT;
556 } else {
557 err = 0;
558 }
559
560 /* restore the MCR */
561 qspi_writel(q, reg, base + QUADSPI_MCR);
562
563 return err;
564 }
565
566 /* Read out the data from the QUADSPI_RBDR buffer registers. */
fsl_qspi_read_data(struct fsl_qspi * q,int len,u8 * rxbuf)567 static void fsl_qspi_read_data(struct fsl_qspi *q, int len, u8 *rxbuf)
568 {
569 u32 tmp;
570 int i = 0;
571
572 while (len > 0) {
573 tmp = qspi_readl(q, q->iobase + QUADSPI_RBDR + i * 4);
574 tmp = fsl_qspi_endian_xchg(q, tmp);
575 dev_dbg(q->dev, "chip addr:0x%.8x, rcv:0x%.8x\n",
576 q->chip_base_addr, tmp);
577
578 if (len >= 4) {
579 *((u32 *)rxbuf) = tmp;
580 rxbuf += 4;
581 } else {
582 memcpy(rxbuf, &tmp, len);
583 break;
584 }
585
586 len -= 4;
587 i++;
588 }
589 }
590
591 /*
592 * If we have changed the content of the flash by writing or erasing,
593 * we need to invalidate the AHB buffer. If we do not do so, we may read out
594 * the wrong data. The spec tells us reset the AHB domain and Serial Flash
595 * domain at the same time.
596 */
fsl_qspi_invalid(struct fsl_qspi * q)597 static inline void fsl_qspi_invalid(struct fsl_qspi *q)
598 {
599 u32 reg;
600
601 reg = qspi_readl(q, q->iobase + QUADSPI_MCR);
602 reg |= QUADSPI_MCR_SWRSTHD_MASK | QUADSPI_MCR_SWRSTSD_MASK;
603 qspi_writel(q, reg, q->iobase + QUADSPI_MCR);
604
605 /*
606 * The minimum delay : 1 AHB + 2 SFCK clocks.
607 * Delay 1 us is enough.
608 */
609 udelay(1);
610
611 reg &= ~(QUADSPI_MCR_SWRSTHD_MASK | QUADSPI_MCR_SWRSTSD_MASK);
612 qspi_writel(q, reg, q->iobase + QUADSPI_MCR);
613 }
614
fsl_qspi_nor_write(struct fsl_qspi * q,struct spi_nor * nor,u8 opcode,unsigned int to,u32 * txbuf,unsigned count)615 static ssize_t fsl_qspi_nor_write(struct fsl_qspi *q, struct spi_nor *nor,
616 u8 opcode, unsigned int to, u32 *txbuf,
617 unsigned count)
618 {
619 int ret, i, j;
620 u32 tmp;
621
622 dev_dbg(q->dev, "to 0x%.8x:0x%.8x, len : %d\n",
623 q->chip_base_addr, to, count);
624
625 /* clear the TX FIFO. */
626 tmp = qspi_readl(q, q->iobase + QUADSPI_MCR);
627 qspi_writel(q, tmp | QUADSPI_MCR_CLR_TXF_MASK, q->iobase + QUADSPI_MCR);
628
629 /* fill the TX data to the FIFO */
630 for (j = 0, i = ((count + 3) / 4); j < i; j++) {
631 tmp = fsl_qspi_endian_xchg(q, *txbuf);
632 qspi_writel(q, tmp, q->iobase + QUADSPI_TBDR);
633 txbuf++;
634 }
635
636 /* fill the TXFIFO upto 16 bytes for i.MX7d */
637 if (needs_fill_txfifo(q))
638 for (; i < 4; i++)
639 qspi_writel(q, tmp, q->iobase + QUADSPI_TBDR);
640
641 /* Trigger it */
642 ret = fsl_qspi_runcmd(q, opcode, to, count);
643
644 if (ret == 0)
645 return count;
646
647 return ret;
648 }
649
fsl_qspi_set_map_addr(struct fsl_qspi * q)650 static void fsl_qspi_set_map_addr(struct fsl_qspi *q)
651 {
652 int nor_size = q->nor_size;
653 void __iomem *base = q->iobase;
654
655 qspi_writel(q, nor_size + q->memmap_phy, base + QUADSPI_SFA1AD);
656 qspi_writel(q, nor_size * 2 + q->memmap_phy, base + QUADSPI_SFA2AD);
657 qspi_writel(q, nor_size * 3 + q->memmap_phy, base + QUADSPI_SFB1AD);
658 qspi_writel(q, nor_size * 4 + q->memmap_phy, base + QUADSPI_SFB2AD);
659 }
660
661 /*
662 * There are two different ways to read out the data from the flash:
663 * the "IP Command Read" and the "AHB Command Read".
664 *
665 * The IC guy suggests we use the "AHB Command Read" which is faster
666 * then the "IP Command Read". (What's more is that there is a bug in
667 * the "IP Command Read" in the Vybrid.)
668 *
669 * After we set up the registers for the "AHB Command Read", we can use
670 * the memcpy to read the data directly. A "missed" access to the buffer
671 * causes the controller to clear the buffer, and use the sequence pointed
672 * by the QUADSPI_BFGENCR[SEQID] to initiate a read from the flash.
673 */
fsl_qspi_init_ahb_read(struct fsl_qspi * q)674 static void fsl_qspi_init_ahb_read(struct fsl_qspi *q)
675 {
676 void __iomem *base = q->iobase;
677 int seqid;
678
679 /* AHB configuration for access buffer 0/1/2 .*/
680 qspi_writel(q, QUADSPI_BUFXCR_INVALID_MSTRID, base + QUADSPI_BUF0CR);
681 qspi_writel(q, QUADSPI_BUFXCR_INVALID_MSTRID, base + QUADSPI_BUF1CR);
682 qspi_writel(q, QUADSPI_BUFXCR_INVALID_MSTRID, base + QUADSPI_BUF2CR);
683 /*
684 * Set ADATSZ with the maximum AHB buffer size to improve the
685 * read performance.
686 */
687 qspi_writel(q, QUADSPI_BUF3CR_ALLMST_MASK |
688 ((q->devtype_data->ahb_buf_size / 8)
689 << QUADSPI_BUF3CR_ADATSZ_SHIFT),
690 base + QUADSPI_BUF3CR);
691
692 /* We only use the buffer3 */
693 qspi_writel(q, 0, base + QUADSPI_BUF0IND);
694 qspi_writel(q, 0, base + QUADSPI_BUF1IND);
695 qspi_writel(q, 0, base + QUADSPI_BUF2IND);
696
697 /* Set the default lut sequence for AHB Read. */
698 seqid = fsl_qspi_get_seqid(q, q->nor[0].read_opcode);
699 qspi_writel(q, seqid << QUADSPI_BFGENCR_SEQID_SHIFT,
700 q->iobase + QUADSPI_BFGENCR);
701 }
702
703 /* This function was used to prepare and enable QSPI clock */
fsl_qspi_clk_prep_enable(struct fsl_qspi * q)704 static int fsl_qspi_clk_prep_enable(struct fsl_qspi *q)
705 {
706 int ret;
707
708 ret = clk_prepare_enable(q->clk_en);
709 if (ret)
710 return ret;
711
712 ret = clk_prepare_enable(q->clk);
713 if (ret) {
714 clk_disable_unprepare(q->clk_en);
715 return ret;
716 }
717
718 if (needs_wakeup_wait_mode(q))
719 pm_qos_add_request(&q->pm_qos_req, PM_QOS_CPU_DMA_LATENCY, 0);
720
721 return 0;
722 }
723
724 /* This function was used to disable and unprepare QSPI clock */
fsl_qspi_clk_disable_unprep(struct fsl_qspi * q)725 static void fsl_qspi_clk_disable_unprep(struct fsl_qspi *q)
726 {
727 if (needs_wakeup_wait_mode(q))
728 pm_qos_remove_request(&q->pm_qos_req);
729
730 clk_disable_unprepare(q->clk);
731 clk_disable_unprepare(q->clk_en);
732
733 }
734
735 /* We use this function to do some basic init for spi_nor_scan(). */
fsl_qspi_nor_setup(struct fsl_qspi * q)736 static int fsl_qspi_nor_setup(struct fsl_qspi *q)
737 {
738 void __iomem *base = q->iobase;
739 u32 reg;
740 int ret;
741
742 /* disable and unprepare clock to avoid glitch pass to controller */
743 fsl_qspi_clk_disable_unprep(q);
744
745 /* the default frequency, we will change it in the future. */
746 ret = clk_set_rate(q->clk, 66000000);
747 if (ret)
748 return ret;
749
750 ret = fsl_qspi_clk_prep_enable(q);
751 if (ret)
752 return ret;
753
754 /* Reset the module */
755 qspi_writel(q, QUADSPI_MCR_SWRSTSD_MASK | QUADSPI_MCR_SWRSTHD_MASK,
756 base + QUADSPI_MCR);
757 udelay(1);
758
759 /* Init the LUT table. */
760 fsl_qspi_init_lut(q);
761
762 /* Disable the module */
763 qspi_writel(q, QUADSPI_MCR_MDIS_MASK | QUADSPI_MCR_RESERVED_MASK,
764 base + QUADSPI_MCR);
765
766 reg = qspi_readl(q, base + QUADSPI_SMPR);
767 qspi_writel(q, reg & ~(QUADSPI_SMPR_FSDLY_MASK
768 | QUADSPI_SMPR_FSPHS_MASK
769 | QUADSPI_SMPR_HSENA_MASK
770 | QUADSPI_SMPR_DDRSMP_MASK), base + QUADSPI_SMPR);
771
772 /* Enable the module */
773 qspi_writel(q, QUADSPI_MCR_RESERVED_MASK | QUADSPI_MCR_END_CFG_MASK,
774 base + QUADSPI_MCR);
775
776 /* clear all interrupt status */
777 qspi_writel(q, 0xffffffff, q->iobase + QUADSPI_FR);
778
779 /* enable the interrupt */
780 qspi_writel(q, QUADSPI_RSER_TFIE, q->iobase + QUADSPI_RSER);
781
782 return 0;
783 }
784
fsl_qspi_nor_setup_last(struct fsl_qspi * q)785 static int fsl_qspi_nor_setup_last(struct fsl_qspi *q)
786 {
787 unsigned long rate = q->clk_rate;
788 int ret;
789
790 if (needs_4x_clock(q))
791 rate *= 4;
792
793 /* disable and unprepare clock to avoid glitch pass to controller */
794 fsl_qspi_clk_disable_unprep(q);
795
796 ret = clk_set_rate(q->clk, rate);
797 if (ret)
798 return ret;
799
800 ret = fsl_qspi_clk_prep_enable(q);
801 if (ret)
802 return ret;
803
804 /* Init the LUT table again. */
805 fsl_qspi_init_lut(q);
806
807 /* Init for AHB read */
808 fsl_qspi_init_ahb_read(q);
809
810 return 0;
811 }
812
813 static const struct of_device_id fsl_qspi_dt_ids[] = {
814 { .compatible = "fsl,vf610-qspi", .data = &vybrid_data, },
815 { .compatible = "fsl,imx6sx-qspi", .data = &imx6sx_data, },
816 { .compatible = "fsl,imx7d-qspi", .data = &imx7d_data, },
817 { .compatible = "fsl,imx6ul-qspi", .data = &imx6ul_data, },
818 { .compatible = "fsl,ls1021a-qspi", .data = (void *)&ls1021a_data, },
819 { .compatible = "fsl,ls2080a-qspi", .data = &ls2080a_data, },
820 { /* sentinel */ }
821 };
822 MODULE_DEVICE_TABLE(of, fsl_qspi_dt_ids);
823
fsl_qspi_set_base_addr(struct fsl_qspi * q,struct spi_nor * nor)824 static void fsl_qspi_set_base_addr(struct fsl_qspi *q, struct spi_nor *nor)
825 {
826 q->chip_base_addr = q->nor_size * (nor - q->nor);
827 }
828
fsl_qspi_read_reg(struct spi_nor * nor,u8 opcode,u8 * buf,int len)829 static int fsl_qspi_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
830 {
831 int ret;
832 struct fsl_qspi *q = nor->priv;
833
834 ret = fsl_qspi_runcmd(q, opcode, 0, len);
835 if (ret)
836 return ret;
837
838 fsl_qspi_read_data(q, len, buf);
839 return 0;
840 }
841
fsl_qspi_write_reg(struct spi_nor * nor,u8 opcode,u8 * buf,int len)842 static int fsl_qspi_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
843 {
844 struct fsl_qspi *q = nor->priv;
845 int ret;
846
847 if (!buf) {
848 ret = fsl_qspi_runcmd(q, opcode, 0, 1);
849 if (ret)
850 return ret;
851
852 if (opcode == SPINOR_OP_CHIP_ERASE)
853 fsl_qspi_invalid(q);
854
855 } else if (len > 0) {
856 ret = fsl_qspi_nor_write(q, nor, opcode, 0,
857 (u32 *)buf, len);
858 if (ret > 0)
859 return 0;
860 } else {
861 dev_err(q->dev, "invalid cmd %d\n", opcode);
862 ret = -EINVAL;
863 }
864
865 return ret;
866 }
867
fsl_qspi_write(struct spi_nor * nor,loff_t to,size_t len,const u_char * buf)868 static ssize_t fsl_qspi_write(struct spi_nor *nor, loff_t to,
869 size_t len, const u_char *buf)
870 {
871 struct fsl_qspi *q = nor->priv;
872 ssize_t ret = fsl_qspi_nor_write(q, nor, nor->program_opcode, to,
873 (u32 *)buf, len);
874
875 /* invalid the data in the AHB buffer. */
876 fsl_qspi_invalid(q);
877 return ret;
878 }
879
fsl_qspi_read(struct spi_nor * nor,loff_t from,size_t len,u_char * buf)880 static ssize_t fsl_qspi_read(struct spi_nor *nor, loff_t from,
881 size_t len, u_char *buf)
882 {
883 struct fsl_qspi *q = nor->priv;
884 u8 cmd = nor->read_opcode;
885
886 /* if necessary,ioremap buffer before AHB read, */
887 if (!q->ahb_addr) {
888 q->memmap_offs = q->chip_base_addr + from;
889 q->memmap_len = len > QUADSPI_MIN_IOMAP ? len : QUADSPI_MIN_IOMAP;
890
891 q->ahb_addr = ioremap_nocache(
892 q->memmap_phy + q->memmap_offs,
893 q->memmap_len);
894 if (!q->ahb_addr) {
895 dev_err(q->dev, "ioremap failed\n");
896 return -ENOMEM;
897 }
898 /* ioremap if the data requested is out of range */
899 } else if (q->chip_base_addr + from < q->memmap_offs
900 || q->chip_base_addr + from + len >
901 q->memmap_offs + q->memmap_len) {
902 iounmap(q->ahb_addr);
903
904 q->memmap_offs = q->chip_base_addr + from;
905 q->memmap_len = len > QUADSPI_MIN_IOMAP ? len : QUADSPI_MIN_IOMAP;
906 q->ahb_addr = ioremap_nocache(
907 q->memmap_phy + q->memmap_offs,
908 q->memmap_len);
909 if (!q->ahb_addr) {
910 dev_err(q->dev, "ioremap failed\n");
911 return -ENOMEM;
912 }
913 }
914
915 dev_dbg(q->dev, "cmd [%x],read from %p, len:%zd\n",
916 cmd, q->ahb_addr + q->chip_base_addr + from - q->memmap_offs,
917 len);
918
919 /* Read out the data directly from the AHB buffer.*/
920 memcpy(buf, q->ahb_addr + q->chip_base_addr + from - q->memmap_offs,
921 len);
922
923 return len;
924 }
925
fsl_qspi_erase(struct spi_nor * nor,loff_t offs)926 static int fsl_qspi_erase(struct spi_nor *nor, loff_t offs)
927 {
928 struct fsl_qspi *q = nor->priv;
929 int ret;
930
931 dev_dbg(nor->dev, "%dKiB at 0x%08x:0x%08x\n",
932 nor->mtd.erasesize / 1024, q->chip_base_addr, (u32)offs);
933
934 ret = fsl_qspi_runcmd(q, nor->erase_opcode, offs, 0);
935 if (ret)
936 return ret;
937
938 fsl_qspi_invalid(q);
939 return 0;
940 }
941
fsl_qspi_prep(struct spi_nor * nor,enum spi_nor_ops ops)942 static int fsl_qspi_prep(struct spi_nor *nor, enum spi_nor_ops ops)
943 {
944 struct fsl_qspi *q = nor->priv;
945 int ret;
946
947 mutex_lock(&q->lock);
948
949 ret = fsl_qspi_clk_prep_enable(q);
950 if (ret)
951 goto err_mutex;
952
953 fsl_qspi_set_base_addr(q, nor);
954 return 0;
955
956 err_mutex:
957 mutex_unlock(&q->lock);
958 return ret;
959 }
960
fsl_qspi_unprep(struct spi_nor * nor,enum spi_nor_ops ops)961 static void fsl_qspi_unprep(struct spi_nor *nor, enum spi_nor_ops ops)
962 {
963 struct fsl_qspi *q = nor->priv;
964
965 fsl_qspi_clk_disable_unprep(q);
966 mutex_unlock(&q->lock);
967 }
968
fsl_qspi_probe(struct platform_device * pdev)969 static int fsl_qspi_probe(struct platform_device *pdev)
970 {
971 const struct spi_nor_hwcaps hwcaps = {
972 .mask = SNOR_HWCAPS_READ_1_1_4 |
973 SNOR_HWCAPS_PP,
974 };
975 struct device_node *np = pdev->dev.of_node;
976 struct device *dev = &pdev->dev;
977 struct fsl_qspi *q;
978 struct resource *res;
979 struct spi_nor *nor;
980 struct mtd_info *mtd;
981 int ret, i = 0;
982
983 q = devm_kzalloc(dev, sizeof(*q), GFP_KERNEL);
984 if (!q)
985 return -ENOMEM;
986
987 q->nor_num = of_get_child_count(dev->of_node);
988 if (!q->nor_num || q->nor_num > FSL_QSPI_MAX_CHIP)
989 return -ENODEV;
990
991 q->dev = dev;
992 q->devtype_data = of_device_get_match_data(dev);
993 if (!q->devtype_data)
994 return -ENODEV;
995 platform_set_drvdata(pdev, q);
996
997 /* find the resources */
998 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "QuadSPI");
999 q->iobase = devm_ioremap_resource(dev, res);
1000 if (IS_ERR(q->iobase))
1001 return PTR_ERR(q->iobase);
1002
1003 q->big_endian = of_property_read_bool(np, "big-endian");
1004 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
1005 "QuadSPI-memory");
1006 if (!devm_request_mem_region(dev, res->start, resource_size(res),
1007 res->name)) {
1008 dev_err(dev, "can't request region for resource %pR\n", res);
1009 return -EBUSY;
1010 }
1011
1012 q->memmap_phy = res->start;
1013
1014 /* find the clocks */
1015 q->clk_en = devm_clk_get(dev, "qspi_en");
1016 if (IS_ERR(q->clk_en))
1017 return PTR_ERR(q->clk_en);
1018
1019 q->clk = devm_clk_get(dev, "qspi");
1020 if (IS_ERR(q->clk))
1021 return PTR_ERR(q->clk);
1022
1023 ret = fsl_qspi_clk_prep_enable(q);
1024 if (ret) {
1025 dev_err(dev, "can not enable the clock\n");
1026 goto clk_failed;
1027 }
1028
1029 /* find the irq */
1030 ret = platform_get_irq(pdev, 0);
1031 if (ret < 0) {
1032 dev_err(dev, "failed to get the irq: %d\n", ret);
1033 goto irq_failed;
1034 }
1035
1036 ret = devm_request_irq(dev, ret,
1037 fsl_qspi_irq_handler, 0, pdev->name, q);
1038 if (ret) {
1039 dev_err(dev, "failed to request irq: %d\n", ret);
1040 goto irq_failed;
1041 }
1042
1043 ret = fsl_qspi_nor_setup(q);
1044 if (ret)
1045 goto irq_failed;
1046
1047 if (of_get_property(np, "fsl,qspi-has-second-chip", NULL))
1048 q->has_second_chip = true;
1049
1050 mutex_init(&q->lock);
1051
1052 /* iterate the subnodes. */
1053 for_each_available_child_of_node(dev->of_node, np) {
1054 /* skip the holes */
1055 if (!q->has_second_chip)
1056 i *= 2;
1057
1058 nor = &q->nor[i];
1059 mtd = &nor->mtd;
1060
1061 nor->dev = dev;
1062 spi_nor_set_flash_node(nor, np);
1063 nor->priv = q;
1064
1065 if (q->nor_num > 1 && !mtd->name) {
1066 int spiflash_idx;
1067
1068 ret = of_property_read_u32(np, "reg", &spiflash_idx);
1069 if (!ret) {
1070 mtd->name = devm_kasprintf(dev, GFP_KERNEL,
1071 "%s-%d",
1072 dev_name(dev),
1073 spiflash_idx);
1074 if (!mtd->name) {
1075 ret = -ENOMEM;
1076 goto mutex_failed;
1077 }
1078 } else {
1079 dev_warn(dev, "reg property is missing\n");
1080 }
1081 }
1082
1083 /* fill the hooks */
1084 nor->read_reg = fsl_qspi_read_reg;
1085 nor->write_reg = fsl_qspi_write_reg;
1086 nor->read = fsl_qspi_read;
1087 nor->write = fsl_qspi_write;
1088 nor->erase = fsl_qspi_erase;
1089
1090 nor->prepare = fsl_qspi_prep;
1091 nor->unprepare = fsl_qspi_unprep;
1092
1093 ret = of_property_read_u32(np, "spi-max-frequency",
1094 &q->clk_rate);
1095 if (ret < 0)
1096 goto mutex_failed;
1097
1098 /* set the chip address for READID */
1099 fsl_qspi_set_base_addr(q, nor);
1100
1101 ret = spi_nor_scan(nor, NULL, &hwcaps);
1102 if (ret)
1103 goto mutex_failed;
1104
1105 ret = mtd_device_register(mtd, NULL, 0);
1106 if (ret)
1107 goto mutex_failed;
1108
1109 /* Set the correct NOR size now. */
1110 if (q->nor_size == 0) {
1111 q->nor_size = mtd->size;
1112
1113 /* Map the SPI NOR to accessiable address */
1114 fsl_qspi_set_map_addr(q);
1115 }
1116
1117 /*
1118 * The TX FIFO is 64 bytes in the Vybrid, but the Page Program
1119 * may writes 265 bytes per time. The write is working in the
1120 * unit of the TX FIFO, not in the unit of the SPI NOR's page
1121 * size.
1122 *
1123 * So shrink the spi_nor->page_size if it is larger then the
1124 * TX FIFO.
1125 */
1126 if (nor->page_size > q->devtype_data->txfifo)
1127 nor->page_size = q->devtype_data->txfifo;
1128
1129 i++;
1130 }
1131
1132 /* finish the rest init. */
1133 ret = fsl_qspi_nor_setup_last(q);
1134 if (ret)
1135 goto last_init_failed;
1136
1137 fsl_qspi_clk_disable_unprep(q);
1138 return 0;
1139
1140 last_init_failed:
1141 for (i = 0; i < q->nor_num; i++) {
1142 /* skip the holes */
1143 if (!q->has_second_chip)
1144 i *= 2;
1145 mtd_device_unregister(&q->nor[i].mtd);
1146 }
1147 mutex_failed:
1148 mutex_destroy(&q->lock);
1149 irq_failed:
1150 fsl_qspi_clk_disable_unprep(q);
1151 clk_failed:
1152 dev_err(dev, "Freescale QuadSPI probe failed\n");
1153 return ret;
1154 }
1155
fsl_qspi_remove(struct platform_device * pdev)1156 static int fsl_qspi_remove(struct platform_device *pdev)
1157 {
1158 struct fsl_qspi *q = platform_get_drvdata(pdev);
1159 int i;
1160
1161 for (i = 0; i < q->nor_num; i++) {
1162 /* skip the holes */
1163 if (!q->has_second_chip)
1164 i *= 2;
1165 mtd_device_unregister(&q->nor[i].mtd);
1166 }
1167
1168 /* disable the hardware */
1169 qspi_writel(q, QUADSPI_MCR_MDIS_MASK, q->iobase + QUADSPI_MCR);
1170 qspi_writel(q, 0x0, q->iobase + QUADSPI_RSER);
1171
1172 mutex_destroy(&q->lock);
1173
1174 if (q->ahb_addr)
1175 iounmap(q->ahb_addr);
1176
1177 return 0;
1178 }
1179
fsl_qspi_suspend(struct platform_device * pdev,pm_message_t state)1180 static int fsl_qspi_suspend(struct platform_device *pdev, pm_message_t state)
1181 {
1182 return 0;
1183 }
1184
fsl_qspi_resume(struct platform_device * pdev)1185 static int fsl_qspi_resume(struct platform_device *pdev)
1186 {
1187 int ret;
1188 struct fsl_qspi *q = platform_get_drvdata(pdev);
1189
1190 ret = fsl_qspi_clk_prep_enable(q);
1191 if (ret)
1192 return ret;
1193
1194 fsl_qspi_nor_setup(q);
1195 fsl_qspi_set_map_addr(q);
1196 fsl_qspi_nor_setup_last(q);
1197
1198 fsl_qspi_clk_disable_unprep(q);
1199
1200 return 0;
1201 }
1202
1203 static struct platform_driver fsl_qspi_driver = {
1204 .driver = {
1205 .name = "fsl-quadspi",
1206 .of_match_table = fsl_qspi_dt_ids,
1207 },
1208 .probe = fsl_qspi_probe,
1209 .remove = fsl_qspi_remove,
1210 .suspend = fsl_qspi_suspend,
1211 .resume = fsl_qspi_resume,
1212 };
1213 module_platform_driver(fsl_qspi_driver);
1214
1215 MODULE_DESCRIPTION("Freescale QuadSPI Controller Driver");
1216 MODULE_AUTHOR("Freescale Semiconductor Inc.");
1217 MODULE_LICENSE("GPL v2");
1218
