1 /*
2 * Copyright 2009-2015 Freescale Semiconductor, Inc. and others
3 *
4 * Description: MPC5125, VF610, MCF54418 and Kinetis K70 Nand driver.
5 * Jason ported to M54418TWR and MVFA5 (VF610).
6 * Authors: Stefan Agner <stefan.agner@toradex.com>
7 * Bill Pringlemeir <bpringlemeir@nbsps.com>
8 * Shaohui Xie <b21989@freescale.com>
9 * Jason Jin <Jason.jin@freescale.com>
10 *
11 * Based on original driver mpc5121_nfc.c.
12 *
13 * This is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
17 *
18 * Limitations:
19 * - Untested on MPC5125 and M54418.
20 * - DMA and pipelining not used.
21 * - 2K pages or less.
22 * - HW ECC: Only 2K page with 64+ OOB.
23 * - HW ECC: Only 24 and 32-bit error correction implemented.
24 */
25
26 #include <linux/module.h>
27 #include <linux/bitops.h>
28 #include <linux/clk.h>
29 #include <linux/delay.h>
30 #include <linux/init.h>
31 #include <linux/interrupt.h>
32 #include <linux/io.h>
33 #include <linux/mtd/mtd.h>
34 #include <linux/mtd/rawnand.h>
35 #include <linux/mtd/partitions.h>
36 #include <linux/of_device.h>
37 #include <linux/platform_device.h>
38 #include <linux/slab.h>
39 #include <linux/swab.h>
40
41 #define DRV_NAME "vf610_nfc"
42
43 /* Register Offsets */
44 #define NFC_FLASH_CMD1 0x3F00
45 #define NFC_FLASH_CMD2 0x3F04
46 #define NFC_COL_ADDR 0x3F08
47 #define NFC_ROW_ADDR 0x3F0c
48 #define NFC_ROW_ADDR_INC 0x3F14
49 #define NFC_FLASH_STATUS1 0x3F18
50 #define NFC_FLASH_STATUS2 0x3F1c
51 #define NFC_CACHE_SWAP 0x3F28
52 #define NFC_SECTOR_SIZE 0x3F2c
53 #define NFC_FLASH_CONFIG 0x3F30
54 #define NFC_IRQ_STATUS 0x3F38
55
56 /* Addresses for NFC MAIN RAM BUFFER areas */
57 #define NFC_MAIN_AREA(n) ((n) * 0x1000)
58
59 #define PAGE_2K 0x0800
60 #define OOB_64 0x0040
61 #define OOB_MAX 0x0100
62
63 /* NFC_CMD2[CODE] controller cycle bit masks */
64 #define COMMAND_CMD_BYTE1 BIT(14)
65 #define COMMAND_CAR_BYTE1 BIT(13)
66 #define COMMAND_CAR_BYTE2 BIT(12)
67 #define COMMAND_RAR_BYTE1 BIT(11)
68 #define COMMAND_RAR_BYTE2 BIT(10)
69 #define COMMAND_RAR_BYTE3 BIT(9)
70 #define COMMAND_NADDR_BYTES(x) GENMASK(13, 13 - (x) + 1)
71 #define COMMAND_WRITE_DATA BIT(8)
72 #define COMMAND_CMD_BYTE2 BIT(7)
73 #define COMMAND_RB_HANDSHAKE BIT(6)
74 #define COMMAND_READ_DATA BIT(5)
75 #define COMMAND_CMD_BYTE3 BIT(4)
76 #define COMMAND_READ_STATUS BIT(3)
77 #define COMMAND_READ_ID BIT(2)
78
79 /* NFC ECC mode define */
80 #define ECC_BYPASS 0
81 #define ECC_45_BYTE 6
82 #define ECC_60_BYTE 7
83
84 /*** Register Mask and bit definitions */
85
86 /* NFC_FLASH_CMD1 Field */
87 #define CMD_BYTE2_MASK 0xFF000000
88 #define CMD_BYTE2_SHIFT 24
89
90 /* NFC_FLASH_CM2 Field */
91 #define CMD_BYTE1_MASK 0xFF000000
92 #define CMD_BYTE1_SHIFT 24
93 #define CMD_CODE_MASK 0x00FFFF00
94 #define CMD_CODE_SHIFT 8
95 #define BUFNO_MASK 0x00000006
96 #define BUFNO_SHIFT 1
97 #define START_BIT BIT(0)
98
99 /* NFC_COL_ADDR Field */
100 #define COL_ADDR_MASK 0x0000FFFF
101 #define COL_ADDR_SHIFT 0
102 #define COL_ADDR(pos, val) (((val) & 0xFF) << (8 * (pos)))
103
104 /* NFC_ROW_ADDR Field */
105 #define ROW_ADDR_MASK 0x00FFFFFF
106 #define ROW_ADDR_SHIFT 0
107 #define ROW_ADDR(pos, val) (((val) & 0xFF) << (8 * (pos)))
108
109 #define ROW_ADDR_CHIP_SEL_RB_MASK 0xF0000000
110 #define ROW_ADDR_CHIP_SEL_RB_SHIFT 28
111 #define ROW_ADDR_CHIP_SEL_MASK 0x0F000000
112 #define ROW_ADDR_CHIP_SEL_SHIFT 24
113
114 /* NFC_FLASH_STATUS2 Field */
115 #define STATUS_BYTE1_MASK 0x000000FF
116
117 /* NFC_FLASH_CONFIG Field */
118 #define CONFIG_ECC_SRAM_ADDR_MASK 0x7FC00000
119 #define CONFIG_ECC_SRAM_ADDR_SHIFT 22
120 #define CONFIG_ECC_SRAM_REQ_BIT BIT(21)
121 #define CONFIG_DMA_REQ_BIT BIT(20)
122 #define CONFIG_ECC_MODE_MASK 0x000E0000
123 #define CONFIG_ECC_MODE_SHIFT 17
124 #define CONFIG_FAST_FLASH_BIT BIT(16)
125 #define CONFIG_16BIT BIT(7)
126 #define CONFIG_BOOT_MODE_BIT BIT(6)
127 #define CONFIG_ADDR_AUTO_INCR_BIT BIT(5)
128 #define CONFIG_BUFNO_AUTO_INCR_BIT BIT(4)
129 #define CONFIG_PAGE_CNT_MASK 0xF
130 #define CONFIG_PAGE_CNT_SHIFT 0
131
132 /* NFC_IRQ_STATUS Field */
133 #define IDLE_IRQ_BIT BIT(29)
134 #define IDLE_EN_BIT BIT(20)
135 #define CMD_DONE_CLEAR_BIT BIT(18)
136 #define IDLE_CLEAR_BIT BIT(17)
137
138 /*
139 * ECC status - seems to consume 8 bytes (double word). The documented
140 * status byte is located in the lowest byte of the second word (which is
141 * the 4th or 7th byte depending on endianness).
142 * Calculate an offset to store the ECC status at the end of the buffer.
143 */
144 #define ECC_SRAM_ADDR (PAGE_2K + OOB_MAX - 8)
145
146 #define ECC_STATUS 0x4
147 #define ECC_STATUS_MASK 0x80
148 #define ECC_STATUS_ERR_COUNT 0x3F
149
150 enum vf610_nfc_variant {
151 NFC_VFC610 = 1,
152 };
153
154 struct vf610_nfc {
155 struct nand_chip chip;
156 struct device *dev;
157 void __iomem *regs;
158 struct completion cmd_done;
159 /* Status and ID are in alternate locations. */
160 enum vf610_nfc_variant variant;
161 struct clk *clk;
162 /*
163 * Indicate that user data is accessed (full page/oob). This is
164 * useful to indicate the driver whether to swap byte endianness.
165 * See comments in vf610_nfc_rd_from_sram/vf610_nfc_wr_to_sram.
166 */
167 bool data_access;
168 u32 ecc_mode;
169 };
170
mtd_to_nfc(struct mtd_info * mtd)171 static inline struct vf610_nfc *mtd_to_nfc(struct mtd_info *mtd)
172 {
173 return container_of(mtd_to_nand(mtd), struct vf610_nfc, chip);
174 }
175
chip_to_nfc(struct nand_chip * chip)176 static inline struct vf610_nfc *chip_to_nfc(struct nand_chip *chip)
177 {
178 return container_of(chip, struct vf610_nfc, chip);
179 }
180
vf610_nfc_read(struct vf610_nfc * nfc,uint reg)181 static inline u32 vf610_nfc_read(struct vf610_nfc *nfc, uint reg)
182 {
183 return readl(nfc->regs + reg);
184 }
185
vf610_nfc_write(struct vf610_nfc * nfc,uint reg,u32 val)186 static inline void vf610_nfc_write(struct vf610_nfc *nfc, uint reg, u32 val)
187 {
188 writel(val, nfc->regs + reg);
189 }
190
vf610_nfc_set(struct vf610_nfc * nfc,uint reg,u32 bits)191 static inline void vf610_nfc_set(struct vf610_nfc *nfc, uint reg, u32 bits)
192 {
193 vf610_nfc_write(nfc, reg, vf610_nfc_read(nfc, reg) | bits);
194 }
195
vf610_nfc_clear(struct vf610_nfc * nfc,uint reg,u32 bits)196 static inline void vf610_nfc_clear(struct vf610_nfc *nfc, uint reg, u32 bits)
197 {
198 vf610_nfc_write(nfc, reg, vf610_nfc_read(nfc, reg) & ~bits);
199 }
200
vf610_nfc_set_field(struct vf610_nfc * nfc,u32 reg,u32 mask,u32 shift,u32 val)201 static inline void vf610_nfc_set_field(struct vf610_nfc *nfc, u32 reg,
202 u32 mask, u32 shift, u32 val)
203 {
204 vf610_nfc_write(nfc, reg,
205 (vf610_nfc_read(nfc, reg) & (~mask)) | val << shift);
206 }
207
vf610_nfc_kernel_is_little_endian(void)208 static inline bool vf610_nfc_kernel_is_little_endian(void)
209 {
210 #ifdef __LITTLE_ENDIAN
211 return true;
212 #else
213 return false;
214 #endif
215 }
216
217 /**
218 * Read accessor for internal SRAM buffer
219 * @dst: destination address in regular memory
220 * @src: source address in SRAM buffer
221 * @len: bytes to copy
222 * @fix_endian: Fix endianness if required
223 *
224 * Use this accessor for the internal SRAM buffers. On the ARM
225 * Freescale Vybrid SoC it's known that the driver can treat
226 * the SRAM buffer as if it's memory. Other platform might need
227 * to treat the buffers differently.
228 *
229 * The controller stores bytes from the NAND chip internally in big
230 * endianness. On little endian platforms such as Vybrid this leads
231 * to reversed byte order.
232 * For performance reason (and earlier probably due to unawareness)
233 * the driver avoids correcting endianness where it has control over
234 * write and read side (e.g. page wise data access).
235 */
vf610_nfc_rd_from_sram(void * dst,const void __iomem * src,size_t len,bool fix_endian)236 static inline void vf610_nfc_rd_from_sram(void *dst, const void __iomem *src,
237 size_t len, bool fix_endian)
238 {
239 if (vf610_nfc_kernel_is_little_endian() && fix_endian) {
240 unsigned int i;
241
242 for (i = 0; i < len; i += 4) {
243 u32 val = swab32(__raw_readl(src + i));
244
245 memcpy(dst + i, &val, min(sizeof(val), len - i));
246 }
247 } else {
248 memcpy_fromio(dst, src, len);
249 }
250 }
251
252 /**
253 * Write accessor for internal SRAM buffer
254 * @dst: destination address in SRAM buffer
255 * @src: source address in regular memory
256 * @len: bytes to copy
257 * @fix_endian: Fix endianness if required
258 *
259 * Use this accessor for the internal SRAM buffers. On the ARM
260 * Freescale Vybrid SoC it's known that the driver can treat
261 * the SRAM buffer as if it's memory. Other platform might need
262 * to treat the buffers differently.
263 *
264 * The controller stores bytes from the NAND chip internally in big
265 * endianness. On little endian platforms such as Vybrid this leads
266 * to reversed byte order.
267 * For performance reason (and earlier probably due to unawareness)
268 * the driver avoids correcting endianness where it has control over
269 * write and read side (e.g. page wise data access).
270 */
vf610_nfc_wr_to_sram(void __iomem * dst,const void * src,size_t len,bool fix_endian)271 static inline void vf610_nfc_wr_to_sram(void __iomem *dst, const void *src,
272 size_t len, bool fix_endian)
273 {
274 if (vf610_nfc_kernel_is_little_endian() && fix_endian) {
275 unsigned int i;
276
277 for (i = 0; i < len; i += 4) {
278 u32 val;
279
280 memcpy(&val, src + i, min(sizeof(val), len - i));
281 __raw_writel(swab32(val), dst + i);
282 }
283 } else {
284 memcpy_toio(dst, src, len);
285 }
286 }
287
288 /* Clear flags for upcoming command */
vf610_nfc_clear_status(struct vf610_nfc * nfc)289 static inline void vf610_nfc_clear_status(struct vf610_nfc *nfc)
290 {
291 u32 tmp = vf610_nfc_read(nfc, NFC_IRQ_STATUS);
292
293 tmp |= CMD_DONE_CLEAR_BIT | IDLE_CLEAR_BIT;
294 vf610_nfc_write(nfc, NFC_IRQ_STATUS, tmp);
295 }
296
vf610_nfc_done(struct vf610_nfc * nfc)297 static void vf610_nfc_done(struct vf610_nfc *nfc)
298 {
299 unsigned long timeout = msecs_to_jiffies(100);
300
301 /*
302 * Barrier is needed after this write. This write need
303 * to be done before reading the next register the first
304 * time.
305 * vf610_nfc_set implicates such a barrier by using writel
306 * to write to the register.
307 */
308 vf610_nfc_set(nfc, NFC_IRQ_STATUS, IDLE_EN_BIT);
309 vf610_nfc_set(nfc, NFC_FLASH_CMD2, START_BIT);
310
311 if (!wait_for_completion_timeout(&nfc->cmd_done, timeout))
312 dev_warn(nfc->dev, "Timeout while waiting for BUSY.\n");
313
314 vf610_nfc_clear_status(nfc);
315 }
316
vf610_nfc_irq(int irq,void * data)317 static irqreturn_t vf610_nfc_irq(int irq, void *data)
318 {
319 struct mtd_info *mtd = data;
320 struct vf610_nfc *nfc = mtd_to_nfc(mtd);
321
322 vf610_nfc_clear(nfc, NFC_IRQ_STATUS, IDLE_EN_BIT);
323 complete(&nfc->cmd_done);
324
325 return IRQ_HANDLED;
326 }
327
vf610_nfc_ecc_mode(struct vf610_nfc * nfc,int ecc_mode)328 static inline void vf610_nfc_ecc_mode(struct vf610_nfc *nfc, int ecc_mode)
329 {
330 vf610_nfc_set_field(nfc, NFC_FLASH_CONFIG,
331 CONFIG_ECC_MODE_MASK,
332 CONFIG_ECC_MODE_SHIFT, ecc_mode);
333 }
334
vf610_nfc_transfer_size(struct vf610_nfc * nfc,int size)335 static inline void vf610_nfc_transfer_size(struct vf610_nfc *nfc, int size)
336 {
337 vf610_nfc_write(nfc, NFC_SECTOR_SIZE, size);
338 }
339
vf610_nfc_run(struct vf610_nfc * nfc,u32 col,u32 row,u32 cmd1,u32 cmd2,u32 trfr_sz)340 static inline void vf610_nfc_run(struct vf610_nfc *nfc, u32 col, u32 row,
341 u32 cmd1, u32 cmd2, u32 trfr_sz)
342 {
343 vf610_nfc_set_field(nfc, NFC_COL_ADDR, COL_ADDR_MASK,
344 COL_ADDR_SHIFT, col);
345
346 vf610_nfc_set_field(nfc, NFC_ROW_ADDR, ROW_ADDR_MASK,
347 ROW_ADDR_SHIFT, row);
348
349 vf610_nfc_write(nfc, NFC_SECTOR_SIZE, trfr_sz);
350 vf610_nfc_write(nfc, NFC_FLASH_CMD1, cmd1);
351 vf610_nfc_write(nfc, NFC_FLASH_CMD2, cmd2);
352
353 dev_dbg(nfc->dev,
354 "col 0x%04x, row 0x%08x, cmd1 0x%08x, cmd2 0x%08x, len %d\n",
355 col, row, cmd1, cmd2, trfr_sz);
356
357 vf610_nfc_done(nfc);
358 }
359
360 static inline const struct nand_op_instr *
vf610_get_next_instr(const struct nand_subop * subop,int * op_id)361 vf610_get_next_instr(const struct nand_subop *subop, int *op_id)
362 {
363 if (*op_id + 1 >= subop->ninstrs)
364 return NULL;
365
366 (*op_id)++;
367
368 return &subop->instrs[*op_id];
369 }
370
vf610_nfc_cmd(struct nand_chip * chip,const struct nand_subop * subop)371 static int vf610_nfc_cmd(struct nand_chip *chip,
372 const struct nand_subop *subop)
373 {
374 const struct nand_op_instr *instr;
375 struct vf610_nfc *nfc = chip_to_nfc(chip);
376 int op_id = -1, trfr_sz = 0, offset;
377 u32 col = 0, row = 0, cmd1 = 0, cmd2 = 0, code = 0;
378 bool force8bit = false;
379
380 /*
381 * Some ops are optional, but the hardware requires the operations
382 * to be in this exact order.
383 * The op parser enforces the order and makes sure that there isn't
384 * a read and write element in a single operation.
385 */
386 instr = vf610_get_next_instr(subop, &op_id);
387 if (!instr)
388 return -EINVAL;
389
390 if (instr && instr->type == NAND_OP_CMD_INSTR) {
391 cmd2 |= instr->ctx.cmd.opcode << CMD_BYTE1_SHIFT;
392 code |= COMMAND_CMD_BYTE1;
393
394 instr = vf610_get_next_instr(subop, &op_id);
395 }
396
397 if (instr && instr->type == NAND_OP_ADDR_INSTR) {
398 int naddrs = nand_subop_get_num_addr_cyc(subop, op_id);
399 int i = nand_subop_get_addr_start_off(subop, op_id);
400
401 for (; i < naddrs; i++) {
402 u8 val = instr->ctx.addr.addrs[i];
403
404 if (i < 2)
405 col |= COL_ADDR(i, val);
406 else
407 row |= ROW_ADDR(i - 2, val);
408 }
409 code |= COMMAND_NADDR_BYTES(naddrs);
410
411 instr = vf610_get_next_instr(subop, &op_id);
412 }
413
414 if (instr && instr->type == NAND_OP_DATA_OUT_INSTR) {
415 trfr_sz = nand_subop_get_data_len(subop, op_id);
416 offset = nand_subop_get_data_start_off(subop, op_id);
417 force8bit = instr->ctx.data.force_8bit;
418
419 /*
420 * Don't fix endianness on page access for historical reasons.
421 * See comment in vf610_nfc_wr_to_sram
422 */
423 vf610_nfc_wr_to_sram(nfc->regs + NFC_MAIN_AREA(0) + offset,
424 instr->ctx.data.buf.out + offset,
425 trfr_sz, !nfc->data_access);
426 code |= COMMAND_WRITE_DATA;
427
428 instr = vf610_get_next_instr(subop, &op_id);
429 }
430
431 if (instr && instr->type == NAND_OP_CMD_INSTR) {
432 cmd1 |= instr->ctx.cmd.opcode << CMD_BYTE2_SHIFT;
433 code |= COMMAND_CMD_BYTE2;
434
435 instr = vf610_get_next_instr(subop, &op_id);
436 }
437
438 if (instr && instr->type == NAND_OP_WAITRDY_INSTR) {
439 code |= COMMAND_RB_HANDSHAKE;
440
441 instr = vf610_get_next_instr(subop, &op_id);
442 }
443
444 if (instr && instr->type == NAND_OP_DATA_IN_INSTR) {
445 trfr_sz = nand_subop_get_data_len(subop, op_id);
446 offset = nand_subop_get_data_start_off(subop, op_id);
447 force8bit = instr->ctx.data.force_8bit;
448
449 code |= COMMAND_READ_DATA;
450 }
451
452 if (force8bit && (chip->options & NAND_BUSWIDTH_16))
453 vf610_nfc_clear(nfc, NFC_FLASH_CONFIG, CONFIG_16BIT);
454
455 cmd2 |= code << CMD_CODE_SHIFT;
456
457 vf610_nfc_run(nfc, col, row, cmd1, cmd2, trfr_sz);
458
459 if (instr && instr->type == NAND_OP_DATA_IN_INSTR) {
460 /*
461 * Don't fix endianness on page access for historical reasons.
462 * See comment in vf610_nfc_rd_from_sram
463 */
464 vf610_nfc_rd_from_sram(instr->ctx.data.buf.in + offset,
465 nfc->regs + NFC_MAIN_AREA(0) + offset,
466 trfr_sz, !nfc->data_access);
467 }
468
469 if (force8bit && (chip->options & NAND_BUSWIDTH_16))
470 vf610_nfc_set(nfc, NFC_FLASH_CONFIG, CONFIG_16BIT);
471
472 return 0;
473 }
474
475 static const struct nand_op_parser vf610_nfc_op_parser = NAND_OP_PARSER(
476 NAND_OP_PARSER_PATTERN(vf610_nfc_cmd,
477 NAND_OP_PARSER_PAT_CMD_ELEM(true),
478 NAND_OP_PARSER_PAT_ADDR_ELEM(true, 5),
479 NAND_OP_PARSER_PAT_DATA_OUT_ELEM(true, PAGE_2K + OOB_MAX),
480 NAND_OP_PARSER_PAT_CMD_ELEM(true),
481 NAND_OP_PARSER_PAT_WAITRDY_ELEM(true)),
482 NAND_OP_PARSER_PATTERN(vf610_nfc_cmd,
483 NAND_OP_PARSER_PAT_CMD_ELEM(true),
484 NAND_OP_PARSER_PAT_ADDR_ELEM(true, 5),
485 NAND_OP_PARSER_PAT_CMD_ELEM(true),
486 NAND_OP_PARSER_PAT_WAITRDY_ELEM(true),
487 NAND_OP_PARSER_PAT_DATA_IN_ELEM(true, PAGE_2K + OOB_MAX)),
488 );
489
vf610_nfc_exec_op(struct nand_chip * chip,const struct nand_operation * op,bool check_only)490 static int vf610_nfc_exec_op(struct nand_chip *chip,
491 const struct nand_operation *op,
492 bool check_only)
493 {
494 return nand_op_parser_exec_op(chip, &vf610_nfc_op_parser, op,
495 check_only);
496 }
497
498 /*
499 * This function supports Vybrid only (MPC5125 would have full RB and four CS)
500 */
vf610_nfc_select_chip(struct mtd_info * mtd,int chip)501 static void vf610_nfc_select_chip(struct mtd_info *mtd, int chip)
502 {
503 struct vf610_nfc *nfc = mtd_to_nfc(mtd);
504 u32 tmp = vf610_nfc_read(nfc, NFC_ROW_ADDR);
505
506 /* Vybrid only (MPC5125 would have full RB and four CS) */
507 if (nfc->variant != NFC_VFC610)
508 return;
509
510 tmp &= ~(ROW_ADDR_CHIP_SEL_RB_MASK | ROW_ADDR_CHIP_SEL_MASK);
511
512 if (chip >= 0) {
513 tmp |= 1 << ROW_ADDR_CHIP_SEL_RB_SHIFT;
514 tmp |= BIT(chip) << ROW_ADDR_CHIP_SEL_SHIFT;
515 }
516
517 vf610_nfc_write(nfc, NFC_ROW_ADDR, tmp);
518 }
519
vf610_nfc_correct_data(struct mtd_info * mtd,uint8_t * dat,uint8_t * oob,int page)520 static inline int vf610_nfc_correct_data(struct mtd_info *mtd, uint8_t *dat,
521 uint8_t *oob, int page)
522 {
523 struct vf610_nfc *nfc = mtd_to_nfc(mtd);
524 u32 ecc_status_off = NFC_MAIN_AREA(0) + ECC_SRAM_ADDR + ECC_STATUS;
525 u8 ecc_status;
526 u8 ecc_count;
527 int flips_threshold = nfc->chip.ecc.strength / 2;
528
529 ecc_status = vf610_nfc_read(nfc, ecc_status_off) & 0xff;
530 ecc_count = ecc_status & ECC_STATUS_ERR_COUNT;
531
532 if (!(ecc_status & ECC_STATUS_MASK))
533 return ecc_count;
534
535 nfc->data_access = true;
536 nand_read_oob_op(&nfc->chip, page, 0, oob, mtd->oobsize);
537 nfc->data_access = false;
538
539 /*
540 * On an erased page, bit count (including OOB) should be zero or
541 * at least less then half of the ECC strength.
542 */
543 return nand_check_erased_ecc_chunk(dat, nfc->chip.ecc.size, oob,
544 mtd->oobsize, NULL, 0,
545 flips_threshold);
546 }
547
vf610_nfc_fill_row(struct nand_chip * chip,int page,u32 * code,u32 * row)548 static void vf610_nfc_fill_row(struct nand_chip *chip, int page, u32 *code,
549 u32 *row)
550 {
551 *row = ROW_ADDR(0, page & 0xff) | ROW_ADDR(1, page >> 8);
552 *code |= COMMAND_RAR_BYTE1 | COMMAND_RAR_BYTE2;
553
554 if (chip->options & NAND_ROW_ADDR_3) {
555 *row |= ROW_ADDR(2, page >> 16);
556 *code |= COMMAND_RAR_BYTE3;
557 }
558 }
559
vf610_nfc_read_page(struct mtd_info * mtd,struct nand_chip * chip,uint8_t * buf,int oob_required,int page)560 static int vf610_nfc_read_page(struct mtd_info *mtd, struct nand_chip *chip,
561 uint8_t *buf, int oob_required, int page)
562 {
563 struct vf610_nfc *nfc = mtd_to_nfc(mtd);
564 int trfr_sz = mtd->writesize + mtd->oobsize;
565 u32 row = 0, cmd1 = 0, cmd2 = 0, code = 0;
566 int stat;
567
568 cmd2 |= NAND_CMD_READ0 << CMD_BYTE1_SHIFT;
569 code |= COMMAND_CMD_BYTE1 | COMMAND_CAR_BYTE1 | COMMAND_CAR_BYTE2;
570
571 vf610_nfc_fill_row(chip, page, &code, &row);
572
573 cmd1 |= NAND_CMD_READSTART << CMD_BYTE2_SHIFT;
574 code |= COMMAND_CMD_BYTE2 | COMMAND_RB_HANDSHAKE | COMMAND_READ_DATA;
575
576 cmd2 |= code << CMD_CODE_SHIFT;
577
578 vf610_nfc_ecc_mode(nfc, nfc->ecc_mode);
579 vf610_nfc_run(nfc, 0, row, cmd1, cmd2, trfr_sz);
580 vf610_nfc_ecc_mode(nfc, ECC_BYPASS);
581
582 /*
583 * Don't fix endianness on page access for historical reasons.
584 * See comment in vf610_nfc_rd_from_sram
585 */
586 vf610_nfc_rd_from_sram(buf, nfc->regs + NFC_MAIN_AREA(0),
587 mtd->writesize, false);
588 if (oob_required)
589 vf610_nfc_rd_from_sram(chip->oob_poi,
590 nfc->regs + NFC_MAIN_AREA(0) +
591 mtd->writesize,
592 mtd->oobsize, false);
593
594 stat = vf610_nfc_correct_data(mtd, buf, chip->oob_poi, page);
595
596 if (stat < 0) {
597 mtd->ecc_stats.failed++;
598 return 0;
599 } else {
600 mtd->ecc_stats.corrected += stat;
601 return stat;
602 }
603 }
604
vf610_nfc_write_page(struct mtd_info * mtd,struct nand_chip * chip,const uint8_t * buf,int oob_required,int page)605 static int vf610_nfc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
606 const uint8_t *buf, int oob_required, int page)
607 {
608 struct vf610_nfc *nfc = mtd_to_nfc(mtd);
609 int trfr_sz = mtd->writesize + mtd->oobsize;
610 u32 row = 0, cmd1 = 0, cmd2 = 0, code = 0;
611 u8 status;
612 int ret;
613
614 cmd2 |= NAND_CMD_SEQIN << CMD_BYTE1_SHIFT;
615 code |= COMMAND_CMD_BYTE1 | COMMAND_CAR_BYTE1 | COMMAND_CAR_BYTE2;
616
617 vf610_nfc_fill_row(chip, page, &code, &row);
618
619 cmd1 |= NAND_CMD_PAGEPROG << CMD_BYTE2_SHIFT;
620 code |= COMMAND_CMD_BYTE2 | COMMAND_WRITE_DATA;
621
622 /*
623 * Don't fix endianness on page access for historical reasons.
624 * See comment in vf610_nfc_wr_to_sram
625 */
626 vf610_nfc_wr_to_sram(nfc->regs + NFC_MAIN_AREA(0), buf,
627 mtd->writesize, false);
628
629 code |= COMMAND_RB_HANDSHAKE;
630 cmd2 |= code << CMD_CODE_SHIFT;
631
632 vf610_nfc_ecc_mode(nfc, nfc->ecc_mode);
633 vf610_nfc_run(nfc, 0, row, cmd1, cmd2, trfr_sz);
634 vf610_nfc_ecc_mode(nfc, ECC_BYPASS);
635
636 ret = nand_status_op(chip, &status);
637 if (ret)
638 return ret;
639
640 if (status & NAND_STATUS_FAIL)
641 return -EIO;
642
643 return 0;
644 }
645
vf610_nfc_read_page_raw(struct mtd_info * mtd,struct nand_chip * chip,u8 * buf,int oob_required,int page)646 static int vf610_nfc_read_page_raw(struct mtd_info *mtd,
647 struct nand_chip *chip, u8 *buf,
648 int oob_required, int page)
649 {
650 struct vf610_nfc *nfc = mtd_to_nfc(mtd);
651 int ret;
652
653 nfc->data_access = true;
654 ret = nand_read_page_raw(mtd, chip, buf, oob_required, page);
655 nfc->data_access = false;
656
657 return ret;
658 }
659
vf610_nfc_write_page_raw(struct mtd_info * mtd,struct nand_chip * chip,const u8 * buf,int oob_required,int page)660 static int vf610_nfc_write_page_raw(struct mtd_info *mtd,
661 struct nand_chip *chip, const u8 *buf,
662 int oob_required, int page)
663 {
664 struct vf610_nfc *nfc = mtd_to_nfc(mtd);
665 int ret;
666
667 nfc->data_access = true;
668 ret = nand_prog_page_begin_op(chip, page, 0, buf, mtd->writesize);
669 if (!ret && oob_required)
670 ret = nand_write_data_op(chip, chip->oob_poi, mtd->oobsize,
671 false);
672 nfc->data_access = false;
673
674 if (ret)
675 return ret;
676
677 return nand_prog_page_end_op(chip);
678 }
679
vf610_nfc_read_oob(struct mtd_info * mtd,struct nand_chip * chip,int page)680 static int vf610_nfc_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
681 int page)
682 {
683 struct vf610_nfc *nfc = mtd_to_nfc(mtd);
684 int ret;
685
686 nfc->data_access = true;
687 ret = nand_read_oob_std(mtd, chip, page);
688 nfc->data_access = false;
689
690 return ret;
691 }
692
vf610_nfc_write_oob(struct mtd_info * mtd,struct nand_chip * chip,int page)693 static int vf610_nfc_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
694 int page)
695 {
696 struct vf610_nfc *nfc = mtd_to_nfc(mtd);
697 int ret;
698
699 nfc->data_access = true;
700 ret = nand_prog_page_begin_op(chip, page, mtd->writesize,
701 chip->oob_poi, mtd->oobsize);
702 nfc->data_access = false;
703
704 if (ret)
705 return ret;
706
707 return nand_prog_page_end_op(chip);
708 }
709
710 static const struct of_device_id vf610_nfc_dt_ids[] = {
711 { .compatible = "fsl,vf610-nfc", .data = (void *)NFC_VFC610 },
712 { /* sentinel */ }
713 };
714 MODULE_DEVICE_TABLE(of, vf610_nfc_dt_ids);
715
vf610_nfc_preinit_controller(struct vf610_nfc * nfc)716 static void vf610_nfc_preinit_controller(struct vf610_nfc *nfc)
717 {
718 vf610_nfc_clear(nfc, NFC_FLASH_CONFIG, CONFIG_16BIT);
719 vf610_nfc_clear(nfc, NFC_FLASH_CONFIG, CONFIG_ADDR_AUTO_INCR_BIT);
720 vf610_nfc_clear(nfc, NFC_FLASH_CONFIG, CONFIG_BUFNO_AUTO_INCR_BIT);
721 vf610_nfc_clear(nfc, NFC_FLASH_CONFIG, CONFIG_BOOT_MODE_BIT);
722 vf610_nfc_clear(nfc, NFC_FLASH_CONFIG, CONFIG_DMA_REQ_BIT);
723 vf610_nfc_set(nfc, NFC_FLASH_CONFIG, CONFIG_FAST_FLASH_BIT);
724 vf610_nfc_ecc_mode(nfc, ECC_BYPASS);
725
726 /* Disable virtual pages, only one elementary transfer unit */
727 vf610_nfc_set_field(nfc, NFC_FLASH_CONFIG, CONFIG_PAGE_CNT_MASK,
728 CONFIG_PAGE_CNT_SHIFT, 1);
729 }
730
vf610_nfc_init_controller(struct vf610_nfc * nfc)731 static void vf610_nfc_init_controller(struct vf610_nfc *nfc)
732 {
733 if (nfc->chip.options & NAND_BUSWIDTH_16)
734 vf610_nfc_set(nfc, NFC_FLASH_CONFIG, CONFIG_16BIT);
735 else
736 vf610_nfc_clear(nfc, NFC_FLASH_CONFIG, CONFIG_16BIT);
737
738 if (nfc->chip.ecc.mode == NAND_ECC_HW) {
739 /* Set ECC status offset in SRAM */
740 vf610_nfc_set_field(nfc, NFC_FLASH_CONFIG,
741 CONFIG_ECC_SRAM_ADDR_MASK,
742 CONFIG_ECC_SRAM_ADDR_SHIFT,
743 ECC_SRAM_ADDR >> 3);
744
745 /* Enable ECC status in SRAM */
746 vf610_nfc_set(nfc, NFC_FLASH_CONFIG, CONFIG_ECC_SRAM_REQ_BIT);
747 }
748 }
749
vf610_nfc_attach_chip(struct nand_chip * chip)750 static int vf610_nfc_attach_chip(struct nand_chip *chip)
751 {
752 struct mtd_info *mtd = nand_to_mtd(chip);
753 struct vf610_nfc *nfc = mtd_to_nfc(mtd);
754
755 vf610_nfc_init_controller(nfc);
756
757 /* Bad block options. */
758 if (chip->bbt_options & NAND_BBT_USE_FLASH)
759 chip->bbt_options |= NAND_BBT_NO_OOB;
760
761 /* Single buffer only, max 256 OOB minus ECC status */
762 if (mtd->writesize + mtd->oobsize > PAGE_2K + OOB_MAX - 8) {
763 dev_err(nfc->dev, "Unsupported flash page size\n");
764 return -ENXIO;
765 }
766
767 if (chip->ecc.mode != NAND_ECC_HW)
768 return 0;
769
770 if (mtd->writesize != PAGE_2K && mtd->oobsize < 64) {
771 dev_err(nfc->dev, "Unsupported flash with hwecc\n");
772 return -ENXIO;
773 }
774
775 if (chip->ecc.size != mtd->writesize) {
776 dev_err(nfc->dev, "Step size needs to be page size\n");
777 return -ENXIO;
778 }
779
780 /* Only 64 byte ECC layouts known */
781 if (mtd->oobsize > 64)
782 mtd->oobsize = 64;
783
784 /* Use default large page ECC layout defined in NAND core */
785 mtd_set_ooblayout(mtd, &nand_ooblayout_lp_ops);
786 if (chip->ecc.strength == 32) {
787 nfc->ecc_mode = ECC_60_BYTE;
788 chip->ecc.bytes = 60;
789 } else if (chip->ecc.strength == 24) {
790 nfc->ecc_mode = ECC_45_BYTE;
791 chip->ecc.bytes = 45;
792 } else {
793 dev_err(nfc->dev, "Unsupported ECC strength\n");
794 return -ENXIO;
795 }
796
797 chip->ecc.read_page = vf610_nfc_read_page;
798 chip->ecc.write_page = vf610_nfc_write_page;
799 chip->ecc.read_page_raw = vf610_nfc_read_page_raw;
800 chip->ecc.write_page_raw = vf610_nfc_write_page_raw;
801 chip->ecc.read_oob = vf610_nfc_read_oob;
802 chip->ecc.write_oob = vf610_nfc_write_oob;
803
804 chip->ecc.size = PAGE_2K;
805
806 return 0;
807 }
808
809 static const struct nand_controller_ops vf610_nfc_controller_ops = {
810 .attach_chip = vf610_nfc_attach_chip,
811 };
812
vf610_nfc_probe(struct platform_device * pdev)813 static int vf610_nfc_probe(struct platform_device *pdev)
814 {
815 struct vf610_nfc *nfc;
816 struct resource *res;
817 struct mtd_info *mtd;
818 struct nand_chip *chip;
819 struct device_node *child;
820 const struct of_device_id *of_id;
821 int err;
822 int irq;
823
824 nfc = devm_kzalloc(&pdev->dev, sizeof(*nfc), GFP_KERNEL);
825 if (!nfc)
826 return -ENOMEM;
827
828 nfc->dev = &pdev->dev;
829 chip = &nfc->chip;
830 mtd = nand_to_mtd(chip);
831
832 mtd->owner = THIS_MODULE;
833 mtd->dev.parent = nfc->dev;
834 mtd->name = DRV_NAME;
835
836 irq = platform_get_irq(pdev, 0);
837 if (irq <= 0)
838 return -EINVAL;
839
840 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
841 nfc->regs = devm_ioremap_resource(nfc->dev, res);
842 if (IS_ERR(nfc->regs))
843 return PTR_ERR(nfc->regs);
844
845 nfc->clk = devm_clk_get(&pdev->dev, NULL);
846 if (IS_ERR(nfc->clk))
847 return PTR_ERR(nfc->clk);
848
849 err = clk_prepare_enable(nfc->clk);
850 if (err) {
851 dev_err(nfc->dev, "Unable to enable clock!\n");
852 return err;
853 }
854
855 of_id = of_match_device(vf610_nfc_dt_ids, &pdev->dev);
856 nfc->variant = (enum vf610_nfc_variant)of_id->data;
857
858 for_each_available_child_of_node(nfc->dev->of_node, child) {
859 if (of_device_is_compatible(child, "fsl,vf610-nfc-nandcs")) {
860
861 if (nand_get_flash_node(chip)) {
862 dev_err(nfc->dev,
863 "Only one NAND chip supported!\n");
864 err = -EINVAL;
865 goto err_disable_clk;
866 }
867
868 nand_set_flash_node(chip, child);
869 }
870 }
871
872 if (!nand_get_flash_node(chip)) {
873 dev_err(nfc->dev, "NAND chip sub-node missing!\n");
874 err = -ENODEV;
875 goto err_disable_clk;
876 }
877
878 chip->exec_op = vf610_nfc_exec_op;
879 chip->select_chip = vf610_nfc_select_chip;
880
881 chip->options |= NAND_NO_SUBPAGE_WRITE;
882
883 init_completion(&nfc->cmd_done);
884
885 err = devm_request_irq(nfc->dev, irq, vf610_nfc_irq, 0, DRV_NAME, mtd);
886 if (err) {
887 dev_err(nfc->dev, "Error requesting IRQ!\n");
888 goto err_disable_clk;
889 }
890
891 vf610_nfc_preinit_controller(nfc);
892
893 /* Scan the NAND chip */
894 chip->dummy_controller.ops = &vf610_nfc_controller_ops;
895 err = nand_scan(mtd, 1);
896 if (err)
897 goto err_disable_clk;
898
899 platform_set_drvdata(pdev, mtd);
900
901 /* Register device in MTD */
902 err = mtd_device_register(mtd, NULL, 0);
903 if (err)
904 goto err_cleanup_nand;
905 return 0;
906
907 err_cleanup_nand:
908 nand_cleanup(chip);
909 err_disable_clk:
910 clk_disable_unprepare(nfc->clk);
911 return err;
912 }
913
vf610_nfc_remove(struct platform_device * pdev)914 static int vf610_nfc_remove(struct platform_device *pdev)
915 {
916 struct mtd_info *mtd = platform_get_drvdata(pdev);
917 struct vf610_nfc *nfc = mtd_to_nfc(mtd);
918
919 nand_release(mtd);
920 clk_disable_unprepare(nfc->clk);
921 return 0;
922 }
923
924 #ifdef CONFIG_PM_SLEEP
vf610_nfc_suspend(struct device * dev)925 static int vf610_nfc_suspend(struct device *dev)
926 {
927 struct mtd_info *mtd = dev_get_drvdata(dev);
928 struct vf610_nfc *nfc = mtd_to_nfc(mtd);
929
930 clk_disable_unprepare(nfc->clk);
931 return 0;
932 }
933
vf610_nfc_resume(struct device * dev)934 static int vf610_nfc_resume(struct device *dev)
935 {
936 int err;
937
938 struct mtd_info *mtd = dev_get_drvdata(dev);
939 struct vf610_nfc *nfc = mtd_to_nfc(mtd);
940
941 err = clk_prepare_enable(nfc->clk);
942 if (err)
943 return err;
944
945 vf610_nfc_preinit_controller(nfc);
946 vf610_nfc_init_controller(nfc);
947 return 0;
948 }
949 #endif
950
951 static SIMPLE_DEV_PM_OPS(vf610_nfc_pm_ops, vf610_nfc_suspend, vf610_nfc_resume);
952
953 static struct platform_driver vf610_nfc_driver = {
954 .driver = {
955 .name = DRV_NAME,
956 .of_match_table = vf610_nfc_dt_ids,
957 .pm = &vf610_nfc_pm_ops,
958 },
959 .probe = vf610_nfc_probe,
960 .remove = vf610_nfc_remove,
961 };
962
963 module_platform_driver(vf610_nfc_driver);
964
965 MODULE_AUTHOR("Stefan Agner <stefan.agner@toradex.com>");
966 MODULE_DESCRIPTION("Freescale VF610/MPC5125 NFC MTD NAND driver");
967 MODULE_LICENSE("GPL");
968
