1 /*
2 * drivers/mmc/host/via-sdmmc.c - VIA SD/MMC Card Reader driver
3 * Copyright (c) 2008, VIA Technologies Inc. All Rights Reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or (at
8 * your option) any later version.
9 */
10
11 #include <linux/pci.h>
12 #include <linux/module.h>
13 #include <linux/dma-mapping.h>
14 #include <linux/highmem.h>
15 #include <linux/delay.h>
16 #include <linux/interrupt.h>
17
18 #include <linux/mmc/host.h>
19
20 #define DRV_NAME "via_sdmmc"
21
22 #define PCI_DEVICE_ID_VIA_9530 0x9530
23
24 #define VIA_CRDR_SDC_OFF 0x200
25 #define VIA_CRDR_DDMA_OFF 0x400
26 #define VIA_CRDR_PCICTRL_OFF 0x600
27
28 #define VIA_CRDR_MIN_CLOCK 375000
29 #define VIA_CRDR_MAX_CLOCK 48000000
30
31 /*
32 * PCI registers
33 */
34
35 #define VIA_CRDR_PCI_WORK_MODE 0x40
36 #define VIA_CRDR_PCI_DBG_MODE 0x41
37
38 /*
39 * SDC MMIO Registers
40 */
41
42 #define VIA_CRDR_SDCTRL 0x0
43 #define VIA_CRDR_SDCTRL_START 0x01
44 #define VIA_CRDR_SDCTRL_WRITE 0x04
45 #define VIA_CRDR_SDCTRL_SINGLE_WR 0x10
46 #define VIA_CRDR_SDCTRL_SINGLE_RD 0x20
47 #define VIA_CRDR_SDCTRL_MULTI_WR 0x30
48 #define VIA_CRDR_SDCTRL_MULTI_RD 0x40
49 #define VIA_CRDR_SDCTRL_STOP 0x70
50
51 #define VIA_CRDR_SDCTRL_RSP_NONE 0x0
52 #define VIA_CRDR_SDCTRL_RSP_R1 0x10000
53 #define VIA_CRDR_SDCTRL_RSP_R2 0x20000
54 #define VIA_CRDR_SDCTRL_RSP_R3 0x30000
55 #define VIA_CRDR_SDCTRL_RSP_R1B 0x90000
56
57 #define VIA_CRDR_SDCARG 0x4
58
59 #define VIA_CRDR_SDBUSMODE 0x8
60 #define VIA_CRDR_SDMODE_4BIT 0x02
61 #define VIA_CRDR_SDMODE_CLK_ON 0x40
62
63 #define VIA_CRDR_SDBLKLEN 0xc
64 /*
65 * Bit 0 -Bit 10 : Block length. So, the maximum block length should be 2048.
66 * Bit 11 - Bit 13 : Reserved.
67 * GPIDET : Select GPI pin to detect card, GPI means CR_CD# in top design.
68 * INTEN : Enable SD host interrupt.
69 * Bit 16 - Bit 31 : Block count. So, the maximun block count should be 65536.
70 */
71 #define VIA_CRDR_SDBLKLEN_GPIDET 0x2000
72 #define VIA_CRDR_SDBLKLEN_INTEN 0x8000
73 #define VIA_CRDR_MAX_BLOCK_COUNT 65536
74 #define VIA_CRDR_MAX_BLOCK_LENGTH 2048
75
76 #define VIA_CRDR_SDRESP0 0x10
77 #define VIA_CRDR_SDRESP1 0x14
78 #define VIA_CRDR_SDRESP2 0x18
79 #define VIA_CRDR_SDRESP3 0x1c
80
81 #define VIA_CRDR_SDCURBLKCNT 0x20
82
83 #define VIA_CRDR_SDINTMASK 0x24
84 /*
85 * MBDIE : Multiple Blocks transfer Done Interrupt Enable
86 * BDDIE : Block Data transfer Done Interrupt Enable
87 * CIRIE : Card Insertion or Removal Interrupt Enable
88 * CRDIE : Command-Response transfer Done Interrupt Enable
89 * CRTOIE : Command-Response response TimeOut Interrupt Enable
90 * ASCRDIE : Auto Stop Command-Response transfer Done Interrupt Enable
91 * DTIE : Data access Timeout Interrupt Enable
92 * SCIE : reSponse CRC error Interrupt Enable
93 * RCIE : Read data CRC error Interrupt Enable
94 * WCIE : Write data CRC error Interrupt Enable
95 */
96 #define VIA_CRDR_SDINTMASK_MBDIE 0x10
97 #define VIA_CRDR_SDINTMASK_BDDIE 0x20
98 #define VIA_CRDR_SDINTMASK_CIRIE 0x80
99 #define VIA_CRDR_SDINTMASK_CRDIE 0x200
100 #define VIA_CRDR_SDINTMASK_CRTOIE 0x400
101 #define VIA_CRDR_SDINTMASK_ASCRDIE 0x800
102 #define VIA_CRDR_SDINTMASK_DTIE 0x1000
103 #define VIA_CRDR_SDINTMASK_SCIE 0x2000
104 #define VIA_CRDR_SDINTMASK_RCIE 0x4000
105 #define VIA_CRDR_SDINTMASK_WCIE 0x8000
106
107 #define VIA_CRDR_SDACTIVE_INTMASK \
108 (VIA_CRDR_SDINTMASK_MBDIE | VIA_CRDR_SDINTMASK_CIRIE \
109 | VIA_CRDR_SDINTMASK_CRDIE | VIA_CRDR_SDINTMASK_CRTOIE \
110 | VIA_CRDR_SDINTMASK_DTIE | VIA_CRDR_SDINTMASK_SCIE \
111 | VIA_CRDR_SDINTMASK_RCIE | VIA_CRDR_SDINTMASK_WCIE)
112
113 #define VIA_CRDR_SDSTATUS 0x28
114 /*
115 * CECC : Reserved
116 * WP : SD card Write Protect status
117 * SLOTD : Reserved
118 * SLOTG : SD SLOT status(Gpi pin status)
119 * MBD : Multiple Blocks transfer Done interrupt status
120 * BDD : Block Data transfer Done interrupt status
121 * CD : Reserved
122 * CIR : Card Insertion or Removal interrupt detected on GPI pin
123 * IO : Reserved
124 * CRD : Command-Response transfer Done interrupt status
125 * CRTO : Command-Response response TimeOut interrupt status
126 * ASCRDIE : Auto Stop Command-Response transfer Done interrupt status
127 * DT : Data access Timeout interrupt status
128 * SC : reSponse CRC error interrupt status
129 * RC : Read data CRC error interrupt status
130 * WC : Write data CRC error interrupt status
131 */
132 #define VIA_CRDR_SDSTS_CECC 0x01
133 #define VIA_CRDR_SDSTS_WP 0x02
134 #define VIA_CRDR_SDSTS_SLOTD 0x04
135 #define VIA_CRDR_SDSTS_SLOTG 0x08
136 #define VIA_CRDR_SDSTS_MBD 0x10
137 #define VIA_CRDR_SDSTS_BDD 0x20
138 #define VIA_CRDR_SDSTS_CD 0x40
139 #define VIA_CRDR_SDSTS_CIR 0x80
140 #define VIA_CRDR_SDSTS_IO 0x100
141 #define VIA_CRDR_SDSTS_CRD 0x200
142 #define VIA_CRDR_SDSTS_CRTO 0x400
143 #define VIA_CRDR_SDSTS_ASCRDIE 0x800
144 #define VIA_CRDR_SDSTS_DT 0x1000
145 #define VIA_CRDR_SDSTS_SC 0x2000
146 #define VIA_CRDR_SDSTS_RC 0x4000
147 #define VIA_CRDR_SDSTS_WC 0x8000
148
149 #define VIA_CRDR_SDSTS_IGN_MASK\
150 (VIA_CRDR_SDSTS_BDD | VIA_CRDR_SDSTS_ASCRDIE | VIA_CRDR_SDSTS_IO)
151 #define VIA_CRDR_SDSTS_INT_MASK \
152 (VIA_CRDR_SDSTS_MBD | VIA_CRDR_SDSTS_BDD | VIA_CRDR_SDSTS_CD \
153 | VIA_CRDR_SDSTS_CIR | VIA_CRDR_SDSTS_IO | VIA_CRDR_SDSTS_CRD \
154 | VIA_CRDR_SDSTS_CRTO | VIA_CRDR_SDSTS_ASCRDIE | VIA_CRDR_SDSTS_DT \
155 | VIA_CRDR_SDSTS_SC | VIA_CRDR_SDSTS_RC | VIA_CRDR_SDSTS_WC)
156 #define VIA_CRDR_SDSTS_W1C_MASK \
157 (VIA_CRDR_SDSTS_CECC | VIA_CRDR_SDSTS_MBD | VIA_CRDR_SDSTS_BDD \
158 | VIA_CRDR_SDSTS_CD | VIA_CRDR_SDSTS_CIR | VIA_CRDR_SDSTS_CRD \
159 | VIA_CRDR_SDSTS_CRTO | VIA_CRDR_SDSTS_ASCRDIE | VIA_CRDR_SDSTS_DT \
160 | VIA_CRDR_SDSTS_SC | VIA_CRDR_SDSTS_RC | VIA_CRDR_SDSTS_WC)
161 #define VIA_CRDR_SDSTS_CMD_MASK \
162 (VIA_CRDR_SDSTS_CRD | VIA_CRDR_SDSTS_CRTO | VIA_CRDR_SDSTS_SC)
163 #define VIA_CRDR_SDSTS_DATA_MASK\
164 (VIA_CRDR_SDSTS_MBD | VIA_CRDR_SDSTS_DT \
165 | VIA_CRDR_SDSTS_RC | VIA_CRDR_SDSTS_WC)
166
167 #define VIA_CRDR_SDSTATUS2 0x2a
168 /*
169 * CFE : Enable SD host automatic Clock FReezing
170 */
171 #define VIA_CRDR_SDSTS_CFE 0x80
172
173 #define VIA_CRDR_SDRSPTMO 0x2C
174
175 #define VIA_CRDR_SDCLKSEL 0x30
176
177 #define VIA_CRDR_SDEXTCTRL 0x34
178 #define VIS_CRDR_SDEXTCTRL_AUTOSTOP_SD 0x01
179 #define VIS_CRDR_SDEXTCTRL_SHIFT_9 0x02
180 #define VIS_CRDR_SDEXTCTRL_MMC_8BIT 0x04
181 #define VIS_CRDR_SDEXTCTRL_RELD_BLK 0x08
182 #define VIS_CRDR_SDEXTCTRL_BAD_CMDA 0x10
183 #define VIS_CRDR_SDEXTCTRL_BAD_DATA 0x20
184 #define VIS_CRDR_SDEXTCTRL_AUTOSTOP_SPI 0x40
185 #define VIA_CRDR_SDEXTCTRL_HISPD 0x80
186 /* 0x38-0xFF reserved */
187
188 /*
189 * Data DMA Control Registers
190 */
191
192 #define VIA_CRDR_DMABASEADD 0x0
193 #define VIA_CRDR_DMACOUNTER 0x4
194
195 #define VIA_CRDR_DMACTRL 0x8
196 /*
197 * DIR :Transaction Direction
198 * 0 : From card to memory
199 * 1 : From memory to card
200 */
201 #define VIA_CRDR_DMACTRL_DIR 0x100
202 #define VIA_CRDR_DMACTRL_ENIRQ 0x10000
203 #define VIA_CRDR_DMACTRL_SFTRST 0x1000000
204
205 #define VIA_CRDR_DMASTS 0xc
206
207 #define VIA_CRDR_DMASTART 0x10
208 /*0x14-0xFF reserved*/
209
210 /*
211 * PCI Control Registers
212 */
213
214 /*0x0 - 0x1 reserved*/
215 #define VIA_CRDR_PCICLKGATT 0x2
216 /*
217 * SFTRST :
218 * 0 : Soft reset all the controller and it will be de-asserted automatically
219 * 1 : Soft reset is de-asserted
220 */
221 #define VIA_CRDR_PCICLKGATT_SFTRST 0x01
222 /*
223 * 3V3 : Pad power select
224 * 0 : 1.8V
225 * 1 : 3.3V
226 * NOTE : No mater what the actual value should be, this bit always
227 * read as 0. This is a hardware bug.
228 */
229 #define VIA_CRDR_PCICLKGATT_3V3 0x10
230 /*
231 * PAD_PWRON : Pad Power on/off select
232 * 0 : Power off
233 * 1 : Power on
234 * NOTE : No mater what the actual value should be, this bit always
235 * read as 0. This is a hardware bug.
236 */
237 #define VIA_CRDR_PCICLKGATT_PAD_PWRON 0x20
238
239 #define VIA_CRDR_PCISDCCLK 0x5
240
241 #define VIA_CRDR_PCIDMACLK 0x7
242 #define VIA_CRDR_PCIDMACLK_SDC 0x2
243
244 #define VIA_CRDR_PCIINTCTRL 0x8
245 #define VIA_CRDR_PCIINTCTRL_SDCIRQEN 0x04
246
247 #define VIA_CRDR_PCIINTSTATUS 0x9
248 #define VIA_CRDR_PCIINTSTATUS_SDC 0x04
249
250 #define VIA_CRDR_PCITMOCTRL 0xa
251 #define VIA_CRDR_PCITMOCTRL_NO 0x0
252 #define VIA_CRDR_PCITMOCTRL_32US 0x1
253 #define VIA_CRDR_PCITMOCTRL_256US 0x2
254 #define VIA_CRDR_PCITMOCTRL_1024US 0x3
255 #define VIA_CRDR_PCITMOCTRL_256MS 0x4
256 #define VIA_CRDR_PCITMOCTRL_512MS 0x5
257 #define VIA_CRDR_PCITMOCTRL_1024MS 0x6
258
259 /*0xB-0xFF reserved*/
260
261 enum PCI_HOST_CLK_CONTROL {
262 PCI_CLK_375K = 0x03,
263 PCI_CLK_8M = 0x04,
264 PCI_CLK_12M = 0x00,
265 PCI_CLK_16M = 0x05,
266 PCI_CLK_24M = 0x01,
267 PCI_CLK_33M = 0x06,
268 PCI_CLK_48M = 0x02
269 };
270
271 struct sdhcreg {
272 u32 sdcontrol_reg;
273 u32 sdcmdarg_reg;
274 u32 sdbusmode_reg;
275 u32 sdblklen_reg;
276 u32 sdresp_reg[4];
277 u32 sdcurblkcnt_reg;
278 u32 sdintmask_reg;
279 u32 sdstatus_reg;
280 u32 sdrsptmo_reg;
281 u32 sdclksel_reg;
282 u32 sdextctrl_reg;
283 };
284
285 struct pcictrlreg {
286 u8 reserve[2];
287 u8 pciclkgat_reg;
288 u8 pcinfcclk_reg;
289 u8 pcimscclk_reg;
290 u8 pcisdclk_reg;
291 u8 pcicaclk_reg;
292 u8 pcidmaclk_reg;
293 u8 pciintctrl_reg;
294 u8 pciintstatus_reg;
295 u8 pcitmoctrl_reg;
296 u8 Resv;
297 };
298
299 struct via_crdr_mmc_host {
300 struct mmc_host *mmc;
301 struct mmc_request *mrq;
302 struct mmc_command *cmd;
303 struct mmc_data *data;
304
305 void __iomem *mmiobase;
306 void __iomem *sdhc_mmiobase;
307 void __iomem *ddma_mmiobase;
308 void __iomem *pcictrl_mmiobase;
309
310 struct pcictrlreg pm_pcictrl_reg;
311 struct sdhcreg pm_sdhc_reg;
312
313 struct work_struct carddet_work;
314 struct tasklet_struct finish_tasklet;
315
316 struct timer_list timer;
317 spinlock_t lock;
318 u8 power;
319 int reject;
320 unsigned int quirks;
321 };
322
323 /* some devices need a very long delay for power to stabilize */
324 #define VIA_CRDR_QUIRK_300MS_PWRDELAY 0x0001
325
326 static const struct pci_device_id via_ids[] = {
327 {PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_9530,
328 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0,},
329 {0,}
330 };
331
332 MODULE_DEVICE_TABLE(pci, via_ids);
333
via_print_sdchc(struct via_crdr_mmc_host * host)334 static void via_print_sdchc(struct via_crdr_mmc_host *host)
335 {
336 void __iomem *addrbase = host->sdhc_mmiobase;
337
338 pr_debug("SDC MMIO Registers:\n");
339 pr_debug("SDCONTROL=%08x, SDCMDARG=%08x, SDBUSMODE=%08x\n",
340 readl(addrbase + VIA_CRDR_SDCTRL),
341 readl(addrbase + VIA_CRDR_SDCARG),
342 readl(addrbase + VIA_CRDR_SDBUSMODE));
343 pr_debug("SDBLKLEN=%08x, SDCURBLKCNT=%08x, SDINTMASK=%08x\n",
344 readl(addrbase + VIA_CRDR_SDBLKLEN),
345 readl(addrbase + VIA_CRDR_SDCURBLKCNT),
346 readl(addrbase + VIA_CRDR_SDINTMASK));
347 pr_debug("SDSTATUS=%08x, SDCLKSEL=%08x, SDEXTCTRL=%08x\n",
348 readl(addrbase + VIA_CRDR_SDSTATUS),
349 readl(addrbase + VIA_CRDR_SDCLKSEL),
350 readl(addrbase + VIA_CRDR_SDEXTCTRL));
351 }
352
via_print_pcictrl(struct via_crdr_mmc_host * host)353 static void via_print_pcictrl(struct via_crdr_mmc_host *host)
354 {
355 void __iomem *addrbase = host->pcictrl_mmiobase;
356
357 pr_debug("PCI Control Registers:\n");
358 pr_debug("PCICLKGATT=%02x, PCISDCCLK=%02x, PCIDMACLK=%02x\n",
359 readb(addrbase + VIA_CRDR_PCICLKGATT),
360 readb(addrbase + VIA_CRDR_PCISDCCLK),
361 readb(addrbase + VIA_CRDR_PCIDMACLK));
362 pr_debug("PCIINTCTRL=%02x, PCIINTSTATUS=%02x\n",
363 readb(addrbase + VIA_CRDR_PCIINTCTRL),
364 readb(addrbase + VIA_CRDR_PCIINTSTATUS));
365 }
366
via_save_pcictrlreg(struct via_crdr_mmc_host * host)367 static void via_save_pcictrlreg(struct via_crdr_mmc_host *host)
368 {
369 struct pcictrlreg *pm_pcictrl_reg;
370 void __iomem *addrbase;
371
372 pm_pcictrl_reg = &(host->pm_pcictrl_reg);
373 addrbase = host->pcictrl_mmiobase;
374
375 pm_pcictrl_reg->pciclkgat_reg = readb(addrbase + VIA_CRDR_PCICLKGATT);
376 pm_pcictrl_reg->pciclkgat_reg |=
377 VIA_CRDR_PCICLKGATT_3V3 | VIA_CRDR_PCICLKGATT_PAD_PWRON;
378 pm_pcictrl_reg->pcisdclk_reg = readb(addrbase + VIA_CRDR_PCISDCCLK);
379 pm_pcictrl_reg->pcidmaclk_reg = readb(addrbase + VIA_CRDR_PCIDMACLK);
380 pm_pcictrl_reg->pciintctrl_reg = readb(addrbase + VIA_CRDR_PCIINTCTRL);
381 pm_pcictrl_reg->pciintstatus_reg =
382 readb(addrbase + VIA_CRDR_PCIINTSTATUS);
383 pm_pcictrl_reg->pcitmoctrl_reg = readb(addrbase + VIA_CRDR_PCITMOCTRL);
384 }
385
via_restore_pcictrlreg(struct via_crdr_mmc_host * host)386 static void via_restore_pcictrlreg(struct via_crdr_mmc_host *host)
387 {
388 struct pcictrlreg *pm_pcictrl_reg;
389 void __iomem *addrbase;
390
391 pm_pcictrl_reg = &(host->pm_pcictrl_reg);
392 addrbase = host->pcictrl_mmiobase;
393
394 writeb(pm_pcictrl_reg->pciclkgat_reg, addrbase + VIA_CRDR_PCICLKGATT);
395 writeb(pm_pcictrl_reg->pcisdclk_reg, addrbase + VIA_CRDR_PCISDCCLK);
396 writeb(pm_pcictrl_reg->pcidmaclk_reg, addrbase + VIA_CRDR_PCIDMACLK);
397 writeb(pm_pcictrl_reg->pciintctrl_reg, addrbase + VIA_CRDR_PCIINTCTRL);
398 writeb(pm_pcictrl_reg->pciintstatus_reg,
399 addrbase + VIA_CRDR_PCIINTSTATUS);
400 writeb(pm_pcictrl_reg->pcitmoctrl_reg, addrbase + VIA_CRDR_PCITMOCTRL);
401 }
402
via_save_sdcreg(struct via_crdr_mmc_host * host)403 static void via_save_sdcreg(struct via_crdr_mmc_host *host)
404 {
405 struct sdhcreg *pm_sdhc_reg;
406 void __iomem *addrbase;
407
408 pm_sdhc_reg = &(host->pm_sdhc_reg);
409 addrbase = host->sdhc_mmiobase;
410
411 pm_sdhc_reg->sdcontrol_reg = readl(addrbase + VIA_CRDR_SDCTRL);
412 pm_sdhc_reg->sdcmdarg_reg = readl(addrbase + VIA_CRDR_SDCARG);
413 pm_sdhc_reg->sdbusmode_reg = readl(addrbase + VIA_CRDR_SDBUSMODE);
414 pm_sdhc_reg->sdblklen_reg = readl(addrbase + VIA_CRDR_SDBLKLEN);
415 pm_sdhc_reg->sdcurblkcnt_reg = readl(addrbase + VIA_CRDR_SDCURBLKCNT);
416 pm_sdhc_reg->sdintmask_reg = readl(addrbase + VIA_CRDR_SDINTMASK);
417 pm_sdhc_reg->sdstatus_reg = readl(addrbase + VIA_CRDR_SDSTATUS);
418 pm_sdhc_reg->sdrsptmo_reg = readl(addrbase + VIA_CRDR_SDRSPTMO);
419 pm_sdhc_reg->sdclksel_reg = readl(addrbase + VIA_CRDR_SDCLKSEL);
420 pm_sdhc_reg->sdextctrl_reg = readl(addrbase + VIA_CRDR_SDEXTCTRL);
421 }
422
via_restore_sdcreg(struct via_crdr_mmc_host * host)423 static void via_restore_sdcreg(struct via_crdr_mmc_host *host)
424 {
425 struct sdhcreg *pm_sdhc_reg;
426 void __iomem *addrbase;
427
428 pm_sdhc_reg = &(host->pm_sdhc_reg);
429 addrbase = host->sdhc_mmiobase;
430
431 writel(pm_sdhc_reg->sdcontrol_reg, addrbase + VIA_CRDR_SDCTRL);
432 writel(pm_sdhc_reg->sdcmdarg_reg, addrbase + VIA_CRDR_SDCARG);
433 writel(pm_sdhc_reg->sdbusmode_reg, addrbase + VIA_CRDR_SDBUSMODE);
434 writel(pm_sdhc_reg->sdblklen_reg, addrbase + VIA_CRDR_SDBLKLEN);
435 writel(pm_sdhc_reg->sdcurblkcnt_reg, addrbase + VIA_CRDR_SDCURBLKCNT);
436 writel(pm_sdhc_reg->sdintmask_reg, addrbase + VIA_CRDR_SDINTMASK);
437 writel(pm_sdhc_reg->sdstatus_reg, addrbase + VIA_CRDR_SDSTATUS);
438 writel(pm_sdhc_reg->sdrsptmo_reg, addrbase + VIA_CRDR_SDRSPTMO);
439 writel(pm_sdhc_reg->sdclksel_reg, addrbase + VIA_CRDR_SDCLKSEL);
440 writel(pm_sdhc_reg->sdextctrl_reg, addrbase + VIA_CRDR_SDEXTCTRL);
441 }
442
via_pwron_sleep(struct via_crdr_mmc_host * sdhost)443 static void via_pwron_sleep(struct via_crdr_mmc_host *sdhost)
444 {
445 if (sdhost->quirks & VIA_CRDR_QUIRK_300MS_PWRDELAY)
446 msleep(300);
447 else
448 msleep(3);
449 }
450
via_set_ddma(struct via_crdr_mmc_host * host,dma_addr_t dmaaddr,u32 count,int dir,int enirq)451 static void via_set_ddma(struct via_crdr_mmc_host *host,
452 dma_addr_t dmaaddr, u32 count, int dir, int enirq)
453 {
454 void __iomem *addrbase;
455 u32 ctrl_data = 0;
456
457 if (enirq)
458 ctrl_data |= VIA_CRDR_DMACTRL_ENIRQ;
459
460 if (dir)
461 ctrl_data |= VIA_CRDR_DMACTRL_DIR;
462
463 addrbase = host->ddma_mmiobase;
464
465 writel(dmaaddr, addrbase + VIA_CRDR_DMABASEADD);
466 writel(count, addrbase + VIA_CRDR_DMACOUNTER);
467 writel(ctrl_data, addrbase + VIA_CRDR_DMACTRL);
468 writel(0x01, addrbase + VIA_CRDR_DMASTART);
469
470 /* It seems that our DMA can not work normally with 375kHz clock */
471 /* FIXME: don't brute-force 8MHz but use PIO at 375kHz !! */
472 addrbase = host->pcictrl_mmiobase;
473 if (readb(addrbase + VIA_CRDR_PCISDCCLK) == PCI_CLK_375K) {
474 dev_info(host->mmc->parent, "forcing card speed to 8MHz\n");
475 writeb(PCI_CLK_8M, addrbase + VIA_CRDR_PCISDCCLK);
476 }
477 }
478
via_sdc_preparedata(struct via_crdr_mmc_host * host,struct mmc_data * data)479 static void via_sdc_preparedata(struct via_crdr_mmc_host *host,
480 struct mmc_data *data)
481 {
482 void __iomem *addrbase;
483 u32 blk_reg;
484 int count;
485
486 WARN_ON(host->data);
487
488 /* Sanity checks */
489 BUG_ON(data->blksz > host->mmc->max_blk_size);
490 BUG_ON(data->blocks > host->mmc->max_blk_count);
491
492 host->data = data;
493
494 count = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
495 ((data->flags & MMC_DATA_READ) ?
496 PCI_DMA_FROMDEVICE : PCI_DMA_TODEVICE));
497 BUG_ON(count != 1);
498
499 via_set_ddma(host, sg_dma_address(data->sg), sg_dma_len(data->sg),
500 (data->flags & MMC_DATA_WRITE) ? 1 : 0, 1);
501
502 addrbase = host->sdhc_mmiobase;
503
504 blk_reg = data->blksz - 1;
505 blk_reg |= VIA_CRDR_SDBLKLEN_GPIDET | VIA_CRDR_SDBLKLEN_INTEN;
506 blk_reg |= (data->blocks) << 16;
507
508 writel(blk_reg, addrbase + VIA_CRDR_SDBLKLEN);
509 }
510
via_sdc_get_response(struct via_crdr_mmc_host * host,struct mmc_command * cmd)511 static void via_sdc_get_response(struct via_crdr_mmc_host *host,
512 struct mmc_command *cmd)
513 {
514 void __iomem *addrbase = host->sdhc_mmiobase;
515 u32 dwdata0 = readl(addrbase + VIA_CRDR_SDRESP0);
516 u32 dwdata1 = readl(addrbase + VIA_CRDR_SDRESP1);
517 u32 dwdata2 = readl(addrbase + VIA_CRDR_SDRESP2);
518 u32 dwdata3 = readl(addrbase + VIA_CRDR_SDRESP3);
519
520 if (cmd->flags & MMC_RSP_136) {
521 cmd->resp[0] = ((u8) (dwdata1)) |
522 (((u8) (dwdata0 >> 24)) << 8) |
523 (((u8) (dwdata0 >> 16)) << 16) |
524 (((u8) (dwdata0 >> 8)) << 24);
525
526 cmd->resp[1] = ((u8) (dwdata2)) |
527 (((u8) (dwdata1 >> 24)) << 8) |
528 (((u8) (dwdata1 >> 16)) << 16) |
529 (((u8) (dwdata1 >> 8)) << 24);
530
531 cmd->resp[2] = ((u8) (dwdata3)) |
532 (((u8) (dwdata2 >> 24)) << 8) |
533 (((u8) (dwdata2 >> 16)) << 16) |
534 (((u8) (dwdata2 >> 8)) << 24);
535
536 cmd->resp[3] = 0xff |
537 ((((u8) (dwdata3 >> 24))) << 8) |
538 (((u8) (dwdata3 >> 16)) << 16) |
539 (((u8) (dwdata3 >> 8)) << 24);
540 } else {
541 dwdata0 >>= 8;
542 cmd->resp[0] = ((dwdata0 & 0xff) << 24) |
543 (((dwdata0 >> 8) & 0xff) << 16) |
544 (((dwdata0 >> 16) & 0xff) << 8) | (dwdata1 & 0xff);
545
546 dwdata1 >>= 8;
547 cmd->resp[1] = ((dwdata1 & 0xff) << 24) |
548 (((dwdata1 >> 8) & 0xff) << 16) |
549 (((dwdata1 >> 16) & 0xff) << 8);
550 }
551 }
552
via_sdc_send_command(struct via_crdr_mmc_host * host,struct mmc_command * cmd)553 static void via_sdc_send_command(struct via_crdr_mmc_host *host,
554 struct mmc_command *cmd)
555 {
556 void __iomem *addrbase;
557 struct mmc_data *data;
558 u32 cmdctrl = 0;
559
560 WARN_ON(host->cmd);
561
562 data = cmd->data;
563 mod_timer(&host->timer, jiffies + HZ);
564 host->cmd = cmd;
565
566 /*Command index*/
567 cmdctrl = cmd->opcode << 8;
568
569 /*Response type*/
570 switch (mmc_resp_type(cmd)) {
571 case MMC_RSP_NONE:
572 cmdctrl |= VIA_CRDR_SDCTRL_RSP_NONE;
573 break;
574 case MMC_RSP_R1:
575 cmdctrl |= VIA_CRDR_SDCTRL_RSP_R1;
576 break;
577 case MMC_RSP_R1B:
578 cmdctrl |= VIA_CRDR_SDCTRL_RSP_R1B;
579 break;
580 case MMC_RSP_R2:
581 cmdctrl |= VIA_CRDR_SDCTRL_RSP_R2;
582 break;
583 case MMC_RSP_R3:
584 cmdctrl |= VIA_CRDR_SDCTRL_RSP_R3;
585 break;
586 default:
587 pr_err("%s: cmd->flag is not valid\n", mmc_hostname(host->mmc));
588 break;
589 }
590
591 if (!(cmd->data))
592 goto nodata;
593
594 via_sdc_preparedata(host, data);
595
596 /*Command control*/
597 if (data->blocks > 1) {
598 if (data->flags & MMC_DATA_WRITE) {
599 cmdctrl |= VIA_CRDR_SDCTRL_WRITE;
600 cmdctrl |= VIA_CRDR_SDCTRL_MULTI_WR;
601 } else {
602 cmdctrl |= VIA_CRDR_SDCTRL_MULTI_RD;
603 }
604 } else {
605 if (data->flags & MMC_DATA_WRITE) {
606 cmdctrl |= VIA_CRDR_SDCTRL_WRITE;
607 cmdctrl |= VIA_CRDR_SDCTRL_SINGLE_WR;
608 } else {
609 cmdctrl |= VIA_CRDR_SDCTRL_SINGLE_RD;
610 }
611 }
612
613 nodata:
614 if (cmd == host->mrq->stop)
615 cmdctrl |= VIA_CRDR_SDCTRL_STOP;
616
617 cmdctrl |= VIA_CRDR_SDCTRL_START;
618
619 addrbase = host->sdhc_mmiobase;
620 writel(cmd->arg, addrbase + VIA_CRDR_SDCARG);
621 writel(cmdctrl, addrbase + VIA_CRDR_SDCTRL);
622 }
623
via_sdc_finish_data(struct via_crdr_mmc_host * host)624 static void via_sdc_finish_data(struct via_crdr_mmc_host *host)
625 {
626 struct mmc_data *data;
627
628 BUG_ON(!host->data);
629
630 data = host->data;
631 host->data = NULL;
632
633 if (data->error)
634 data->bytes_xfered = 0;
635 else
636 data->bytes_xfered = data->blocks * data->blksz;
637
638 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
639 ((data->flags & MMC_DATA_READ) ?
640 PCI_DMA_FROMDEVICE : PCI_DMA_TODEVICE));
641
642 if (data->stop)
643 via_sdc_send_command(host, data->stop);
644 else
645 tasklet_schedule(&host->finish_tasklet);
646 }
647
via_sdc_finish_command(struct via_crdr_mmc_host * host)648 static void via_sdc_finish_command(struct via_crdr_mmc_host *host)
649 {
650 via_sdc_get_response(host, host->cmd);
651
652 host->cmd->error = 0;
653
654 if (!host->cmd->data)
655 tasklet_schedule(&host->finish_tasklet);
656
657 host->cmd = NULL;
658 }
659
via_sdc_request(struct mmc_host * mmc,struct mmc_request * mrq)660 static void via_sdc_request(struct mmc_host *mmc, struct mmc_request *mrq)
661 {
662 void __iomem *addrbase;
663 struct via_crdr_mmc_host *host;
664 unsigned long flags;
665 u16 status;
666
667 host = mmc_priv(mmc);
668
669 spin_lock_irqsave(&host->lock, flags);
670
671 addrbase = host->pcictrl_mmiobase;
672 writeb(VIA_CRDR_PCIDMACLK_SDC, addrbase + VIA_CRDR_PCIDMACLK);
673
674 status = readw(host->sdhc_mmiobase + VIA_CRDR_SDSTATUS);
675 status &= VIA_CRDR_SDSTS_W1C_MASK;
676 writew(status, host->sdhc_mmiobase + VIA_CRDR_SDSTATUS);
677
678 WARN_ON(host->mrq != NULL);
679 host->mrq = mrq;
680
681 status = readw(host->sdhc_mmiobase + VIA_CRDR_SDSTATUS);
682 if (!(status & VIA_CRDR_SDSTS_SLOTG) || host->reject) {
683 host->mrq->cmd->error = -ENOMEDIUM;
684 tasklet_schedule(&host->finish_tasklet);
685 } else {
686 via_sdc_send_command(host, mrq->cmd);
687 }
688
689 mmiowb();
690 spin_unlock_irqrestore(&host->lock, flags);
691 }
692
via_sdc_set_power(struct via_crdr_mmc_host * host,unsigned short power,unsigned int on)693 static void via_sdc_set_power(struct via_crdr_mmc_host *host,
694 unsigned short power, unsigned int on)
695 {
696 unsigned long flags;
697 u8 gatt;
698
699 spin_lock_irqsave(&host->lock, flags);
700
701 host->power = (1 << power);
702
703 gatt = readb(host->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT);
704 if (host->power == MMC_VDD_165_195)
705 gatt &= ~VIA_CRDR_PCICLKGATT_3V3;
706 else
707 gatt |= VIA_CRDR_PCICLKGATT_3V3;
708 if (on)
709 gatt |= VIA_CRDR_PCICLKGATT_PAD_PWRON;
710 else
711 gatt &= ~VIA_CRDR_PCICLKGATT_PAD_PWRON;
712 writeb(gatt, host->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT);
713
714 mmiowb();
715 spin_unlock_irqrestore(&host->lock, flags);
716
717 via_pwron_sleep(host);
718 }
719
via_sdc_set_ios(struct mmc_host * mmc,struct mmc_ios * ios)720 static void via_sdc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
721 {
722 struct via_crdr_mmc_host *host;
723 unsigned long flags;
724 void __iomem *addrbase;
725 u32 org_data, sdextctrl;
726 u8 clock;
727
728 host = mmc_priv(mmc);
729
730 spin_lock_irqsave(&host->lock, flags);
731
732 addrbase = host->sdhc_mmiobase;
733 org_data = readl(addrbase + VIA_CRDR_SDBUSMODE);
734 sdextctrl = readl(addrbase + VIA_CRDR_SDEXTCTRL);
735
736 if (ios->bus_width == MMC_BUS_WIDTH_1)
737 org_data &= ~VIA_CRDR_SDMODE_4BIT;
738 else
739 org_data |= VIA_CRDR_SDMODE_4BIT;
740
741 if (ios->power_mode == MMC_POWER_OFF)
742 org_data &= ~VIA_CRDR_SDMODE_CLK_ON;
743 else
744 org_data |= VIA_CRDR_SDMODE_CLK_ON;
745
746 if (ios->timing == MMC_TIMING_SD_HS)
747 sdextctrl |= VIA_CRDR_SDEXTCTRL_HISPD;
748 else
749 sdextctrl &= ~VIA_CRDR_SDEXTCTRL_HISPD;
750
751 writel(org_data, addrbase + VIA_CRDR_SDBUSMODE);
752 writel(sdextctrl, addrbase + VIA_CRDR_SDEXTCTRL);
753
754 if (ios->clock >= 48000000)
755 clock = PCI_CLK_48M;
756 else if (ios->clock >= 33000000)
757 clock = PCI_CLK_33M;
758 else if (ios->clock >= 24000000)
759 clock = PCI_CLK_24M;
760 else if (ios->clock >= 16000000)
761 clock = PCI_CLK_16M;
762 else if (ios->clock >= 12000000)
763 clock = PCI_CLK_12M;
764 else if (ios->clock >= 8000000)
765 clock = PCI_CLK_8M;
766 else
767 clock = PCI_CLK_375K;
768
769 addrbase = host->pcictrl_mmiobase;
770 if (readb(addrbase + VIA_CRDR_PCISDCCLK) != clock)
771 writeb(clock, addrbase + VIA_CRDR_PCISDCCLK);
772
773 mmiowb();
774 spin_unlock_irqrestore(&host->lock, flags);
775
776 if (ios->power_mode != MMC_POWER_OFF)
777 via_sdc_set_power(host, ios->vdd, 1);
778 else
779 via_sdc_set_power(host, ios->vdd, 0);
780 }
781
via_sdc_get_ro(struct mmc_host * mmc)782 static int via_sdc_get_ro(struct mmc_host *mmc)
783 {
784 struct via_crdr_mmc_host *host;
785 unsigned long flags;
786 u16 status;
787
788 host = mmc_priv(mmc);
789
790 spin_lock_irqsave(&host->lock, flags);
791
792 status = readw(host->sdhc_mmiobase + VIA_CRDR_SDSTATUS);
793
794 spin_unlock_irqrestore(&host->lock, flags);
795
796 return !(status & VIA_CRDR_SDSTS_WP);
797 }
798
799 static const struct mmc_host_ops via_sdc_ops = {
800 .request = via_sdc_request,
801 .set_ios = via_sdc_set_ios,
802 .get_ro = via_sdc_get_ro,
803 };
804
via_reset_pcictrl(struct via_crdr_mmc_host * host)805 static void via_reset_pcictrl(struct via_crdr_mmc_host *host)
806 {
807 unsigned long flags;
808 u8 gatt;
809
810 spin_lock_irqsave(&host->lock, flags);
811
812 via_save_pcictrlreg(host);
813 via_save_sdcreg(host);
814
815 spin_unlock_irqrestore(&host->lock, flags);
816
817 gatt = VIA_CRDR_PCICLKGATT_PAD_PWRON;
818 if (host->power == MMC_VDD_165_195)
819 gatt &= VIA_CRDR_PCICLKGATT_3V3;
820 else
821 gatt |= VIA_CRDR_PCICLKGATT_3V3;
822 writeb(gatt, host->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT);
823 via_pwron_sleep(host);
824 gatt |= VIA_CRDR_PCICLKGATT_SFTRST;
825 writeb(gatt, host->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT);
826 msleep(3);
827
828 spin_lock_irqsave(&host->lock, flags);
829
830 via_restore_pcictrlreg(host);
831 via_restore_sdcreg(host);
832
833 mmiowb();
834 spin_unlock_irqrestore(&host->lock, flags);
835 }
836
via_sdc_cmd_isr(struct via_crdr_mmc_host * host,u16 intmask)837 static void via_sdc_cmd_isr(struct via_crdr_mmc_host *host, u16 intmask)
838 {
839 BUG_ON(intmask == 0);
840
841 if (!host->cmd) {
842 pr_err("%s: Got command interrupt 0x%x even "
843 "though no command operation was in progress.\n",
844 mmc_hostname(host->mmc), intmask);
845 return;
846 }
847
848 if (intmask & VIA_CRDR_SDSTS_CRTO)
849 host->cmd->error = -ETIMEDOUT;
850 else if (intmask & VIA_CRDR_SDSTS_SC)
851 host->cmd->error = -EILSEQ;
852
853 if (host->cmd->error)
854 tasklet_schedule(&host->finish_tasklet);
855 else if (intmask & VIA_CRDR_SDSTS_CRD)
856 via_sdc_finish_command(host);
857 }
858
via_sdc_data_isr(struct via_crdr_mmc_host * host,u16 intmask)859 static void via_sdc_data_isr(struct via_crdr_mmc_host *host, u16 intmask)
860 {
861 BUG_ON(intmask == 0);
862
863 if (intmask & VIA_CRDR_SDSTS_DT)
864 host->data->error = -ETIMEDOUT;
865 else if (intmask & (VIA_CRDR_SDSTS_RC | VIA_CRDR_SDSTS_WC))
866 host->data->error = -EILSEQ;
867
868 via_sdc_finish_data(host);
869 }
870
via_sdc_isr(int irq,void * dev_id)871 static irqreturn_t via_sdc_isr(int irq, void *dev_id)
872 {
873 struct via_crdr_mmc_host *sdhost = dev_id;
874 void __iomem *addrbase;
875 u8 pci_status;
876 u16 sd_status;
877 irqreturn_t result;
878
879 if (!sdhost)
880 return IRQ_NONE;
881
882 spin_lock(&sdhost->lock);
883
884 addrbase = sdhost->pcictrl_mmiobase;
885 pci_status = readb(addrbase + VIA_CRDR_PCIINTSTATUS);
886 if (!(pci_status & VIA_CRDR_PCIINTSTATUS_SDC)) {
887 result = IRQ_NONE;
888 goto out;
889 }
890
891 addrbase = sdhost->sdhc_mmiobase;
892 sd_status = readw(addrbase + VIA_CRDR_SDSTATUS);
893 sd_status &= VIA_CRDR_SDSTS_INT_MASK;
894 sd_status &= ~VIA_CRDR_SDSTS_IGN_MASK;
895 if (!sd_status) {
896 result = IRQ_NONE;
897 goto out;
898 }
899
900 if (sd_status & VIA_CRDR_SDSTS_CIR) {
901 writew(sd_status & VIA_CRDR_SDSTS_CIR,
902 addrbase + VIA_CRDR_SDSTATUS);
903
904 schedule_work(&sdhost->carddet_work);
905 }
906
907 sd_status &= ~VIA_CRDR_SDSTS_CIR;
908 if (sd_status & VIA_CRDR_SDSTS_CMD_MASK) {
909 writew(sd_status & VIA_CRDR_SDSTS_CMD_MASK,
910 addrbase + VIA_CRDR_SDSTATUS);
911 via_sdc_cmd_isr(sdhost, sd_status & VIA_CRDR_SDSTS_CMD_MASK);
912 }
913 if (sd_status & VIA_CRDR_SDSTS_DATA_MASK) {
914 writew(sd_status & VIA_CRDR_SDSTS_DATA_MASK,
915 addrbase + VIA_CRDR_SDSTATUS);
916 via_sdc_data_isr(sdhost, sd_status & VIA_CRDR_SDSTS_DATA_MASK);
917 }
918
919 sd_status &= ~(VIA_CRDR_SDSTS_CMD_MASK | VIA_CRDR_SDSTS_DATA_MASK);
920 if (sd_status) {
921 pr_err("%s: Unexpected interrupt 0x%x\n",
922 mmc_hostname(sdhost->mmc), sd_status);
923 writew(sd_status, addrbase + VIA_CRDR_SDSTATUS);
924 }
925
926 result = IRQ_HANDLED;
927
928 mmiowb();
929 out:
930 spin_unlock(&sdhost->lock);
931
932 return result;
933 }
934
via_sdc_timeout(struct timer_list * t)935 static void via_sdc_timeout(struct timer_list *t)
936 {
937 struct via_crdr_mmc_host *sdhost;
938 unsigned long flags;
939
940 sdhost = from_timer(sdhost, t, timer);
941
942 spin_lock_irqsave(&sdhost->lock, flags);
943
944 if (sdhost->mrq) {
945 pr_err("%s: Timeout waiting for hardware interrupt."
946 "cmd:0x%x\n", mmc_hostname(sdhost->mmc),
947 sdhost->mrq->cmd->opcode);
948
949 if (sdhost->data) {
950 writel(VIA_CRDR_DMACTRL_SFTRST,
951 sdhost->ddma_mmiobase + VIA_CRDR_DMACTRL);
952 sdhost->data->error = -ETIMEDOUT;
953 via_sdc_finish_data(sdhost);
954 } else {
955 if (sdhost->cmd)
956 sdhost->cmd->error = -ETIMEDOUT;
957 else
958 sdhost->mrq->cmd->error = -ETIMEDOUT;
959 tasklet_schedule(&sdhost->finish_tasklet);
960 }
961 }
962
963 mmiowb();
964 spin_unlock_irqrestore(&sdhost->lock, flags);
965 }
966
via_sdc_tasklet_finish(unsigned long param)967 static void via_sdc_tasklet_finish(unsigned long param)
968 {
969 struct via_crdr_mmc_host *host;
970 unsigned long flags;
971 struct mmc_request *mrq;
972
973 host = (struct via_crdr_mmc_host *)param;
974
975 spin_lock_irqsave(&host->lock, flags);
976
977 del_timer(&host->timer);
978 mrq = host->mrq;
979 host->mrq = NULL;
980 host->cmd = NULL;
981 host->data = NULL;
982
983 spin_unlock_irqrestore(&host->lock, flags);
984
985 mmc_request_done(host->mmc, mrq);
986 }
987
via_sdc_card_detect(struct work_struct * work)988 static void via_sdc_card_detect(struct work_struct *work)
989 {
990 struct via_crdr_mmc_host *host;
991 void __iomem *addrbase;
992 unsigned long flags;
993 u16 status;
994
995 host = container_of(work, struct via_crdr_mmc_host, carddet_work);
996
997 addrbase = host->ddma_mmiobase;
998 writel(VIA_CRDR_DMACTRL_SFTRST, addrbase + VIA_CRDR_DMACTRL);
999
1000 spin_lock_irqsave(&host->lock, flags);
1001
1002 addrbase = host->pcictrl_mmiobase;
1003 writeb(VIA_CRDR_PCIDMACLK_SDC, addrbase + VIA_CRDR_PCIDMACLK);
1004
1005 addrbase = host->sdhc_mmiobase;
1006 status = readw(addrbase + VIA_CRDR_SDSTATUS);
1007 if (!(status & VIA_CRDR_SDSTS_SLOTG)) {
1008 if (host->mrq) {
1009 pr_err("%s: Card removed during transfer!\n",
1010 mmc_hostname(host->mmc));
1011 host->mrq->cmd->error = -ENOMEDIUM;
1012 tasklet_schedule(&host->finish_tasklet);
1013 }
1014
1015 mmiowb();
1016 spin_unlock_irqrestore(&host->lock, flags);
1017
1018 via_reset_pcictrl(host);
1019
1020 spin_lock_irqsave(&host->lock, flags);
1021 }
1022
1023 mmiowb();
1024 spin_unlock_irqrestore(&host->lock, flags);
1025
1026 via_print_pcictrl(host);
1027 via_print_sdchc(host);
1028
1029 mmc_detect_change(host->mmc, msecs_to_jiffies(500));
1030 }
1031
via_init_mmc_host(struct via_crdr_mmc_host * host)1032 static void via_init_mmc_host(struct via_crdr_mmc_host *host)
1033 {
1034 struct mmc_host *mmc = host->mmc;
1035 void __iomem *addrbase;
1036 u32 lenreg;
1037 u32 status;
1038
1039 timer_setup(&host->timer, via_sdc_timeout, 0);
1040
1041 spin_lock_init(&host->lock);
1042
1043 mmc->f_min = VIA_CRDR_MIN_CLOCK;
1044 mmc->f_max = VIA_CRDR_MAX_CLOCK;
1045 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
1046 mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SD_HIGHSPEED;
1047 mmc->ops = &via_sdc_ops;
1048
1049 /*Hardware cannot do scatter lists*/
1050 mmc->max_segs = 1;
1051
1052 mmc->max_blk_size = VIA_CRDR_MAX_BLOCK_LENGTH;
1053 mmc->max_blk_count = VIA_CRDR_MAX_BLOCK_COUNT;
1054
1055 mmc->max_seg_size = mmc->max_blk_size * mmc->max_blk_count;
1056 mmc->max_req_size = mmc->max_seg_size;
1057
1058 INIT_WORK(&host->carddet_work, via_sdc_card_detect);
1059
1060 tasklet_init(&host->finish_tasklet, via_sdc_tasklet_finish,
1061 (unsigned long)host);
1062
1063 addrbase = host->sdhc_mmiobase;
1064 writel(0x0, addrbase + VIA_CRDR_SDINTMASK);
1065 msleep(1);
1066
1067 lenreg = VIA_CRDR_SDBLKLEN_GPIDET | VIA_CRDR_SDBLKLEN_INTEN;
1068 writel(lenreg, addrbase + VIA_CRDR_SDBLKLEN);
1069
1070 status = readw(addrbase + VIA_CRDR_SDSTATUS);
1071 status &= VIA_CRDR_SDSTS_W1C_MASK;
1072 writew(status, addrbase + VIA_CRDR_SDSTATUS);
1073
1074 status = readw(addrbase + VIA_CRDR_SDSTATUS2);
1075 status |= VIA_CRDR_SDSTS_CFE;
1076 writew(status, addrbase + VIA_CRDR_SDSTATUS2);
1077
1078 writeb(0x0, addrbase + VIA_CRDR_SDEXTCTRL);
1079
1080 writel(VIA_CRDR_SDACTIVE_INTMASK, addrbase + VIA_CRDR_SDINTMASK);
1081 msleep(1);
1082 }
1083
via_sd_probe(struct pci_dev * pcidev,const struct pci_device_id * id)1084 static int via_sd_probe(struct pci_dev *pcidev,
1085 const struct pci_device_id *id)
1086 {
1087 struct mmc_host *mmc;
1088 struct via_crdr_mmc_host *sdhost;
1089 u32 base, len;
1090 u8 gatt;
1091 int ret;
1092
1093 pr_info(DRV_NAME
1094 ": VIA SDMMC controller found at %s [%04x:%04x] (rev %x)\n",
1095 pci_name(pcidev), (int)pcidev->vendor, (int)pcidev->device,
1096 (int)pcidev->revision);
1097
1098 ret = pci_enable_device(pcidev);
1099 if (ret)
1100 return ret;
1101
1102 ret = pci_request_regions(pcidev, DRV_NAME);
1103 if (ret)
1104 goto disable;
1105
1106 pci_write_config_byte(pcidev, VIA_CRDR_PCI_WORK_MODE, 0);
1107 pci_write_config_byte(pcidev, VIA_CRDR_PCI_DBG_MODE, 0);
1108
1109 mmc = mmc_alloc_host(sizeof(struct via_crdr_mmc_host), &pcidev->dev);
1110 if (!mmc) {
1111 ret = -ENOMEM;
1112 goto release;
1113 }
1114
1115 sdhost = mmc_priv(mmc);
1116 sdhost->mmc = mmc;
1117 dev_set_drvdata(&pcidev->dev, sdhost);
1118
1119 len = pci_resource_len(pcidev, 0);
1120 base = pci_resource_start(pcidev, 0);
1121 sdhost->mmiobase = ioremap_nocache(base, len);
1122 if (!sdhost->mmiobase) {
1123 ret = -ENOMEM;
1124 goto free_mmc_host;
1125 }
1126
1127 sdhost->sdhc_mmiobase =
1128 sdhost->mmiobase + VIA_CRDR_SDC_OFF;
1129 sdhost->ddma_mmiobase =
1130 sdhost->mmiobase + VIA_CRDR_DDMA_OFF;
1131 sdhost->pcictrl_mmiobase =
1132 sdhost->mmiobase + VIA_CRDR_PCICTRL_OFF;
1133
1134 sdhost->power = MMC_VDD_165_195;
1135
1136 gatt = VIA_CRDR_PCICLKGATT_3V3 | VIA_CRDR_PCICLKGATT_PAD_PWRON;
1137 writeb(gatt, sdhost->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT);
1138 via_pwron_sleep(sdhost);
1139 gatt |= VIA_CRDR_PCICLKGATT_SFTRST;
1140 writeb(gatt, sdhost->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT);
1141 msleep(3);
1142
1143 via_init_mmc_host(sdhost);
1144
1145 ret =
1146 request_irq(pcidev->irq, via_sdc_isr, IRQF_SHARED, DRV_NAME,
1147 sdhost);
1148 if (ret)
1149 goto unmap;
1150
1151 writeb(VIA_CRDR_PCIINTCTRL_SDCIRQEN,
1152 sdhost->pcictrl_mmiobase + VIA_CRDR_PCIINTCTRL);
1153 writeb(VIA_CRDR_PCITMOCTRL_1024MS,
1154 sdhost->pcictrl_mmiobase + VIA_CRDR_PCITMOCTRL);
1155
1156 /* device-specific quirks */
1157 if (pcidev->subsystem_vendor == PCI_VENDOR_ID_LENOVO &&
1158 pcidev->subsystem_device == 0x3891)
1159 sdhost->quirks = VIA_CRDR_QUIRK_300MS_PWRDELAY;
1160
1161 mmc_add_host(mmc);
1162
1163 return 0;
1164
1165 unmap:
1166 iounmap(sdhost->mmiobase);
1167 free_mmc_host:
1168 dev_set_drvdata(&pcidev->dev, NULL);
1169 mmc_free_host(mmc);
1170 release:
1171 pci_release_regions(pcidev);
1172 disable:
1173 pci_disable_device(pcidev);
1174
1175 return ret;
1176 }
1177
via_sd_remove(struct pci_dev * pcidev)1178 static void via_sd_remove(struct pci_dev *pcidev)
1179 {
1180 struct via_crdr_mmc_host *sdhost = pci_get_drvdata(pcidev);
1181 unsigned long flags;
1182 u8 gatt;
1183
1184 spin_lock_irqsave(&sdhost->lock, flags);
1185
1186 /* Ensure we don't accept more commands from mmc layer */
1187 sdhost->reject = 1;
1188
1189 /* Disable generating further interrupts */
1190 writeb(0x0, sdhost->pcictrl_mmiobase + VIA_CRDR_PCIINTCTRL);
1191 mmiowb();
1192
1193 if (sdhost->mrq) {
1194 pr_err("%s: Controller removed during "
1195 "transfer\n", mmc_hostname(sdhost->mmc));
1196
1197 /* make sure all DMA is stopped */
1198 writel(VIA_CRDR_DMACTRL_SFTRST,
1199 sdhost->ddma_mmiobase + VIA_CRDR_DMACTRL);
1200 mmiowb();
1201 sdhost->mrq->cmd->error = -ENOMEDIUM;
1202 if (sdhost->mrq->stop)
1203 sdhost->mrq->stop->error = -ENOMEDIUM;
1204 tasklet_schedule(&sdhost->finish_tasklet);
1205 }
1206 spin_unlock_irqrestore(&sdhost->lock, flags);
1207
1208 mmc_remove_host(sdhost->mmc);
1209
1210 free_irq(pcidev->irq, sdhost);
1211
1212 del_timer_sync(&sdhost->timer);
1213
1214 tasklet_kill(&sdhost->finish_tasklet);
1215
1216 /* switch off power */
1217 gatt = readb(sdhost->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT);
1218 gatt &= ~VIA_CRDR_PCICLKGATT_PAD_PWRON;
1219 writeb(gatt, sdhost->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT);
1220
1221 iounmap(sdhost->mmiobase);
1222 dev_set_drvdata(&pcidev->dev, NULL);
1223 mmc_free_host(sdhost->mmc);
1224 pci_release_regions(pcidev);
1225 pci_disable_device(pcidev);
1226
1227 pr_info(DRV_NAME
1228 ": VIA SDMMC controller at %s [%04x:%04x] has been removed\n",
1229 pci_name(pcidev), (int)pcidev->vendor, (int)pcidev->device);
1230 }
1231
1232 #ifdef CONFIG_PM
1233
via_init_sdc_pm(struct via_crdr_mmc_host * host)1234 static void via_init_sdc_pm(struct via_crdr_mmc_host *host)
1235 {
1236 struct sdhcreg *pm_sdhcreg;
1237 void __iomem *addrbase;
1238 u32 lenreg;
1239 u16 status;
1240
1241 pm_sdhcreg = &(host->pm_sdhc_reg);
1242 addrbase = host->sdhc_mmiobase;
1243
1244 writel(0x0, addrbase + VIA_CRDR_SDINTMASK);
1245
1246 lenreg = VIA_CRDR_SDBLKLEN_GPIDET | VIA_CRDR_SDBLKLEN_INTEN;
1247 writel(lenreg, addrbase + VIA_CRDR_SDBLKLEN);
1248
1249 status = readw(addrbase + VIA_CRDR_SDSTATUS);
1250 status &= VIA_CRDR_SDSTS_W1C_MASK;
1251 writew(status, addrbase + VIA_CRDR_SDSTATUS);
1252
1253 status = readw(addrbase + VIA_CRDR_SDSTATUS2);
1254 status |= VIA_CRDR_SDSTS_CFE;
1255 writew(status, addrbase + VIA_CRDR_SDSTATUS2);
1256
1257 writel(pm_sdhcreg->sdcontrol_reg, addrbase + VIA_CRDR_SDCTRL);
1258 writel(pm_sdhcreg->sdcmdarg_reg, addrbase + VIA_CRDR_SDCARG);
1259 writel(pm_sdhcreg->sdintmask_reg, addrbase + VIA_CRDR_SDINTMASK);
1260 writel(pm_sdhcreg->sdrsptmo_reg, addrbase + VIA_CRDR_SDRSPTMO);
1261 writel(pm_sdhcreg->sdclksel_reg, addrbase + VIA_CRDR_SDCLKSEL);
1262 writel(pm_sdhcreg->sdextctrl_reg, addrbase + VIA_CRDR_SDEXTCTRL);
1263
1264 via_print_pcictrl(host);
1265 via_print_sdchc(host);
1266 }
1267
via_sd_suspend(struct pci_dev * pcidev,pm_message_t state)1268 static int via_sd_suspend(struct pci_dev *pcidev, pm_message_t state)
1269 {
1270 struct via_crdr_mmc_host *host;
1271
1272 host = pci_get_drvdata(pcidev);
1273
1274 via_save_pcictrlreg(host);
1275 via_save_sdcreg(host);
1276
1277 pci_save_state(pcidev);
1278 pci_enable_wake(pcidev, pci_choose_state(pcidev, state), 0);
1279 pci_disable_device(pcidev);
1280 pci_set_power_state(pcidev, pci_choose_state(pcidev, state));
1281
1282 return 0;
1283 }
1284
via_sd_resume(struct pci_dev * pcidev)1285 static int via_sd_resume(struct pci_dev *pcidev)
1286 {
1287 struct via_crdr_mmc_host *sdhost;
1288 int ret = 0;
1289 u8 gatt;
1290
1291 sdhost = pci_get_drvdata(pcidev);
1292
1293 gatt = VIA_CRDR_PCICLKGATT_PAD_PWRON;
1294 if (sdhost->power == MMC_VDD_165_195)
1295 gatt &= ~VIA_CRDR_PCICLKGATT_3V3;
1296 else
1297 gatt |= VIA_CRDR_PCICLKGATT_3V3;
1298 writeb(gatt, sdhost->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT);
1299 via_pwron_sleep(sdhost);
1300 gatt |= VIA_CRDR_PCICLKGATT_SFTRST;
1301 writeb(gatt, sdhost->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT);
1302 msleep(3);
1303
1304 msleep(100);
1305
1306 pci_set_power_state(pcidev, PCI_D0);
1307 pci_restore_state(pcidev);
1308 ret = pci_enable_device(pcidev);
1309 if (ret)
1310 return ret;
1311
1312 via_restore_pcictrlreg(sdhost);
1313 via_init_sdc_pm(sdhost);
1314
1315 return ret;
1316 }
1317
1318 #else /* CONFIG_PM */
1319
1320 #define via_sd_suspend NULL
1321 #define via_sd_resume NULL
1322
1323 #endif /* CONFIG_PM */
1324
1325 static struct pci_driver via_sd_driver = {
1326 .name = DRV_NAME,
1327 .id_table = via_ids,
1328 .probe = via_sd_probe,
1329 .remove = via_sd_remove,
1330 .suspend = via_sd_suspend,
1331 .resume = via_sd_resume,
1332 };
1333
1334 module_pci_driver(via_sd_driver);
1335
1336 MODULE_LICENSE("GPL");
1337 MODULE_AUTHOR("VIA Technologies Inc.");
1338 MODULE_DESCRIPTION("VIA SD/MMC Card Interface driver");
1339
