1 /* linux/drivers/mmc/host/sdhci-s3c.c
2 *
3 * Copyright 2008 Openmoko Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * SDHCI (HSMMC) support for Samsung SoC
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15 #include <linux/spinlock.h>
16 #include <linux/delay.h>
17 #include <linux/dma-mapping.h>
18 #include <linux/platform_device.h>
19 #include <linux/platform_data/mmc-sdhci-s3c.h>
20 #include <linux/slab.h>
21 #include <linux/clk.h>
22 #include <linux/io.h>
23 #include <linux/gpio.h>
24 #include <linux/module.h>
25 #include <linux/of.h>
26 #include <linux/of_gpio.h>
27 #include <linux/pm.h>
28 #include <linux/pm_runtime.h>
29
30 #include <linux/mmc/host.h>
31
32 #include "sdhci.h"
33
34 #define MAX_BUS_CLK (4)
35
36 #define S3C_SDHCI_CONTROL2 (0x80)
37 #define S3C_SDHCI_CONTROL3 (0x84)
38 #define S3C64XX_SDHCI_CONTROL4 (0x8C)
39
40 #define S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR BIT(31)
41 #define S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK BIT(30)
42 #define S3C_SDHCI_CTRL2_CDINVRXD3 BIT(29)
43 #define S3C_SDHCI_CTRL2_SLCARDOUT BIT(28)
44
45 #define S3C_SDHCI_CTRL2_FLTCLKSEL_MASK (0xf << 24)
46 #define S3C_SDHCI_CTRL2_FLTCLKSEL_SHIFT (24)
47 #define S3C_SDHCI_CTRL2_FLTCLKSEL(_x) ((_x) << 24)
48
49 #define S3C_SDHCI_CTRL2_LVLDAT_MASK (0xff << 16)
50 #define S3C_SDHCI_CTRL2_LVLDAT_SHIFT (16)
51 #define S3C_SDHCI_CTRL2_LVLDAT(_x) ((_x) << 16)
52
53 #define S3C_SDHCI_CTRL2_ENFBCLKTX BIT(15)
54 #define S3C_SDHCI_CTRL2_ENFBCLKRX BIT(14)
55 #define S3C_SDHCI_CTRL2_SDCDSEL BIT(13)
56 #define S3C_SDHCI_CTRL2_SDSIGPC BIT(12)
57 #define S3C_SDHCI_CTRL2_ENBUSYCHKTXSTART BIT(11)
58
59 #define S3C_SDHCI_CTRL2_DFCNT_MASK (0x3 << 9)
60 #define S3C_SDHCI_CTRL2_DFCNT_SHIFT (9)
61 #define S3C_SDHCI_CTRL2_DFCNT_NONE (0x0 << 9)
62 #define S3C_SDHCI_CTRL2_DFCNT_4SDCLK (0x1 << 9)
63 #define S3C_SDHCI_CTRL2_DFCNT_16SDCLK (0x2 << 9)
64 #define S3C_SDHCI_CTRL2_DFCNT_64SDCLK (0x3 << 9)
65
66 #define S3C_SDHCI_CTRL2_ENCLKOUTHOLD BIT(8)
67 #define S3C_SDHCI_CTRL2_RWAITMODE BIT(7)
68 #define S3C_SDHCI_CTRL2_DISBUFRD BIT(6)
69
70 #define S3C_SDHCI_CTRL2_SELBASECLK_MASK (0x3 << 4)
71 #define S3C_SDHCI_CTRL2_SELBASECLK_SHIFT (4)
72 #define S3C_SDHCI_CTRL2_PWRSYNC BIT(3)
73 #define S3C_SDHCI_CTRL2_ENCLKOUTMSKCON BIT(1)
74 #define S3C_SDHCI_CTRL2_HWINITFIN BIT(0)
75
76 #define S3C_SDHCI_CTRL3_FCSEL3 BIT(31)
77 #define S3C_SDHCI_CTRL3_FCSEL2 BIT(23)
78 #define S3C_SDHCI_CTRL3_FCSEL1 BIT(15)
79 #define S3C_SDHCI_CTRL3_FCSEL0 BIT(7)
80
81 #define S3C_SDHCI_CTRL3_FIA3_MASK (0x7f << 24)
82 #define S3C_SDHCI_CTRL3_FIA3_SHIFT (24)
83 #define S3C_SDHCI_CTRL3_FIA3(_x) ((_x) << 24)
84
85 #define S3C_SDHCI_CTRL3_FIA2_MASK (0x7f << 16)
86 #define S3C_SDHCI_CTRL3_FIA2_SHIFT (16)
87 #define S3C_SDHCI_CTRL3_FIA2(_x) ((_x) << 16)
88
89 #define S3C_SDHCI_CTRL3_FIA1_MASK (0x7f << 8)
90 #define S3C_SDHCI_CTRL3_FIA1_SHIFT (8)
91 #define S3C_SDHCI_CTRL3_FIA1(_x) ((_x) << 8)
92
93 #define S3C_SDHCI_CTRL3_FIA0_MASK (0x7f << 0)
94 #define S3C_SDHCI_CTRL3_FIA0_SHIFT (0)
95 #define S3C_SDHCI_CTRL3_FIA0(_x) ((_x) << 0)
96
97 #define S3C64XX_SDHCI_CONTROL4_DRIVE_MASK (0x3 << 16)
98 #define S3C64XX_SDHCI_CONTROL4_DRIVE_SHIFT (16)
99 #define S3C64XX_SDHCI_CONTROL4_DRIVE_2mA (0x0 << 16)
100 #define S3C64XX_SDHCI_CONTROL4_DRIVE_4mA (0x1 << 16)
101 #define S3C64XX_SDHCI_CONTROL4_DRIVE_7mA (0x2 << 16)
102 #define S3C64XX_SDHCI_CONTROL4_DRIVE_9mA (0x3 << 16)
103
104 #define S3C64XX_SDHCI_CONTROL4_BUSY (1)
105
106 /**
107 * struct sdhci_s3c - S3C SDHCI instance
108 * @host: The SDHCI host created
109 * @pdev: The platform device we where created from.
110 * @ioarea: The resource created when we claimed the IO area.
111 * @pdata: The platform data for this controller.
112 * @cur_clk: The index of the current bus clock.
113 * @clk_io: The clock for the internal bus interface.
114 * @clk_bus: The clocks that are available for the SD/MMC bus clock.
115 */
116 struct sdhci_s3c {
117 struct sdhci_host *host;
118 struct platform_device *pdev;
119 struct resource *ioarea;
120 struct s3c_sdhci_platdata *pdata;
121 int cur_clk;
122 int ext_cd_irq;
123 int ext_cd_gpio;
124
125 struct clk *clk_io;
126 struct clk *clk_bus[MAX_BUS_CLK];
127 unsigned long clk_rates[MAX_BUS_CLK];
128
129 bool no_divider;
130 };
131
132 /**
133 * struct sdhci_s3c_driver_data - S3C SDHCI platform specific driver data
134 * @sdhci_quirks: sdhci host specific quirks.
135 *
136 * Specifies platform specific configuration of sdhci controller.
137 * Note: A structure for driver specific platform data is used for future
138 * expansion of its usage.
139 */
140 struct sdhci_s3c_drv_data {
141 unsigned int sdhci_quirks;
142 bool no_divider;
143 };
144
to_s3c(struct sdhci_host * host)145 static inline struct sdhci_s3c *to_s3c(struct sdhci_host *host)
146 {
147 return sdhci_priv(host);
148 }
149
150 /**
151 * sdhci_s3c_get_max_clk - callback to get maximum clock frequency.
152 * @host: The SDHCI host instance.
153 *
154 * Callback to return the maximum clock rate acheivable by the controller.
155 */
sdhci_s3c_get_max_clk(struct sdhci_host * host)156 static unsigned int sdhci_s3c_get_max_clk(struct sdhci_host *host)
157 {
158 struct sdhci_s3c *ourhost = to_s3c(host);
159 unsigned long rate, max = 0;
160 int src;
161
162 for (src = 0; src < MAX_BUS_CLK; src++) {
163 rate = ourhost->clk_rates[src];
164 if (rate > max)
165 max = rate;
166 }
167
168 return max;
169 }
170
171 /**
172 * sdhci_s3c_consider_clock - consider one the bus clocks for current setting
173 * @ourhost: Our SDHCI instance.
174 * @src: The source clock index.
175 * @wanted: The clock frequency wanted.
176 */
sdhci_s3c_consider_clock(struct sdhci_s3c * ourhost,unsigned int src,unsigned int wanted)177 static unsigned int sdhci_s3c_consider_clock(struct sdhci_s3c *ourhost,
178 unsigned int src,
179 unsigned int wanted)
180 {
181 unsigned long rate;
182 struct clk *clksrc = ourhost->clk_bus[src];
183 int shift;
184
185 if (IS_ERR(clksrc))
186 return UINT_MAX;
187
188 /*
189 * If controller uses a non-standard clock division, find the best clock
190 * speed possible with selected clock source and skip the division.
191 */
192 if (ourhost->no_divider) {
193 rate = clk_round_rate(clksrc, wanted);
194 return wanted - rate;
195 }
196
197 rate = ourhost->clk_rates[src];
198
199 for (shift = 0; shift <= 8; ++shift) {
200 if ((rate >> shift) <= wanted)
201 break;
202 }
203
204 if (shift > 8) {
205 dev_dbg(&ourhost->pdev->dev,
206 "clk %d: rate %ld, min rate %lu > wanted %u\n",
207 src, rate, rate / 256, wanted);
208 return UINT_MAX;
209 }
210
211 dev_dbg(&ourhost->pdev->dev, "clk %d: rate %ld, want %d, got %ld\n",
212 src, rate, wanted, rate >> shift);
213
214 return wanted - (rate >> shift);
215 }
216
217 /**
218 * sdhci_s3c_set_clock - callback on clock change
219 * @host: The SDHCI host being changed
220 * @clock: The clock rate being requested.
221 *
222 * When the card's clock is going to be changed, look at the new frequency
223 * and find the best clock source to go with it.
224 */
sdhci_s3c_set_clock(struct sdhci_host * host,unsigned int clock)225 static void sdhci_s3c_set_clock(struct sdhci_host *host, unsigned int clock)
226 {
227 struct sdhci_s3c *ourhost = to_s3c(host);
228 unsigned int best = UINT_MAX;
229 unsigned int delta;
230 int best_src = 0;
231 int src;
232 u32 ctrl;
233
234 host->mmc->actual_clock = 0;
235
236 /* don't bother if the clock is going off. */
237 if (clock == 0) {
238 sdhci_set_clock(host, clock);
239 return;
240 }
241
242 for (src = 0; src < MAX_BUS_CLK; src++) {
243 delta = sdhci_s3c_consider_clock(ourhost, src, clock);
244 if (delta < best) {
245 best = delta;
246 best_src = src;
247 }
248 }
249
250 dev_dbg(&ourhost->pdev->dev,
251 "selected source %d, clock %d, delta %d\n",
252 best_src, clock, best);
253
254 /* select the new clock source */
255 if (ourhost->cur_clk != best_src) {
256 struct clk *clk = ourhost->clk_bus[best_src];
257
258 clk_prepare_enable(clk);
259 if (ourhost->cur_clk >= 0)
260 clk_disable_unprepare(
261 ourhost->clk_bus[ourhost->cur_clk]);
262
263 ourhost->cur_clk = best_src;
264 host->max_clk = ourhost->clk_rates[best_src];
265 }
266
267 /* turn clock off to card before changing clock source */
268 writew(0, host->ioaddr + SDHCI_CLOCK_CONTROL);
269
270 ctrl = readl(host->ioaddr + S3C_SDHCI_CONTROL2);
271 ctrl &= ~S3C_SDHCI_CTRL2_SELBASECLK_MASK;
272 ctrl |= best_src << S3C_SDHCI_CTRL2_SELBASECLK_SHIFT;
273 writel(ctrl, host->ioaddr + S3C_SDHCI_CONTROL2);
274
275 /* reprogram default hardware configuration */
276 writel(S3C64XX_SDHCI_CONTROL4_DRIVE_9mA,
277 host->ioaddr + S3C64XX_SDHCI_CONTROL4);
278
279 ctrl = readl(host->ioaddr + S3C_SDHCI_CONTROL2);
280 ctrl |= (S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR |
281 S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK |
282 S3C_SDHCI_CTRL2_ENFBCLKRX |
283 S3C_SDHCI_CTRL2_DFCNT_NONE |
284 S3C_SDHCI_CTRL2_ENCLKOUTHOLD);
285 writel(ctrl, host->ioaddr + S3C_SDHCI_CONTROL2);
286
287 /* reconfigure the controller for new clock rate */
288 ctrl = (S3C_SDHCI_CTRL3_FCSEL1 | S3C_SDHCI_CTRL3_FCSEL0);
289 if (clock < 25 * 1000000)
290 ctrl |= (S3C_SDHCI_CTRL3_FCSEL3 | S3C_SDHCI_CTRL3_FCSEL2);
291 writel(ctrl, host->ioaddr + S3C_SDHCI_CONTROL3);
292
293 sdhci_set_clock(host, clock);
294 }
295
296 /**
297 * sdhci_s3c_get_min_clock - callback to get minimal supported clock value
298 * @host: The SDHCI host being queried
299 *
300 * To init mmc host properly a minimal clock value is needed. For high system
301 * bus clock's values the standard formula gives values out of allowed range.
302 * The clock still can be set to lower values, if clock source other then
303 * system bus is selected.
304 */
sdhci_s3c_get_min_clock(struct sdhci_host * host)305 static unsigned int sdhci_s3c_get_min_clock(struct sdhci_host *host)
306 {
307 struct sdhci_s3c *ourhost = to_s3c(host);
308 unsigned long rate, min = ULONG_MAX;
309 int src;
310
311 for (src = 0; src < MAX_BUS_CLK; src++) {
312 rate = ourhost->clk_rates[src] / 256;
313 if (!rate)
314 continue;
315 if (rate < min)
316 min = rate;
317 }
318
319 return min;
320 }
321
322 /* sdhci_cmu_get_max_clk - callback to get maximum clock frequency.*/
sdhci_cmu_get_max_clock(struct sdhci_host * host)323 static unsigned int sdhci_cmu_get_max_clock(struct sdhci_host *host)
324 {
325 struct sdhci_s3c *ourhost = to_s3c(host);
326 unsigned long rate, max = 0;
327 int src;
328
329 for (src = 0; src < MAX_BUS_CLK; src++) {
330 struct clk *clk;
331
332 clk = ourhost->clk_bus[src];
333 if (IS_ERR(clk))
334 continue;
335
336 rate = clk_round_rate(clk, ULONG_MAX);
337 if (rate > max)
338 max = rate;
339 }
340
341 return max;
342 }
343
344 /* sdhci_cmu_get_min_clock - callback to get minimal supported clock value. */
sdhci_cmu_get_min_clock(struct sdhci_host * host)345 static unsigned int sdhci_cmu_get_min_clock(struct sdhci_host *host)
346 {
347 struct sdhci_s3c *ourhost = to_s3c(host);
348 unsigned long rate, min = ULONG_MAX;
349 int src;
350
351 for (src = 0; src < MAX_BUS_CLK; src++) {
352 struct clk *clk;
353
354 clk = ourhost->clk_bus[src];
355 if (IS_ERR(clk))
356 continue;
357
358 rate = clk_round_rate(clk, 0);
359 if (rate < min)
360 min = rate;
361 }
362
363 return min;
364 }
365
366 /* sdhci_cmu_set_clock - callback on clock change.*/
sdhci_cmu_set_clock(struct sdhci_host * host,unsigned int clock)367 static void sdhci_cmu_set_clock(struct sdhci_host *host, unsigned int clock)
368 {
369 struct sdhci_s3c *ourhost = to_s3c(host);
370 struct device *dev = &ourhost->pdev->dev;
371 unsigned long timeout;
372 u16 clk = 0;
373 int ret;
374
375 host->mmc->actual_clock = 0;
376
377 /* If the clock is going off, set to 0 at clock control register */
378 if (clock == 0) {
379 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
380 return;
381 }
382
383 sdhci_s3c_set_clock(host, clock);
384
385 /* Reset SD Clock Enable */
386 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
387 clk &= ~SDHCI_CLOCK_CARD_EN;
388 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
389
390 ret = clk_set_rate(ourhost->clk_bus[ourhost->cur_clk], clock);
391 if (ret != 0) {
392 dev_err(dev, "%s: failed to set clock rate %uHz\n",
393 mmc_hostname(host->mmc), clock);
394 return;
395 }
396
397 clk = SDHCI_CLOCK_INT_EN;
398 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
399
400 /* Wait max 20 ms */
401 timeout = 20;
402 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
403 & SDHCI_CLOCK_INT_STABLE)) {
404 if (timeout == 0) {
405 dev_err(dev, "%s: Internal clock never stabilised.\n",
406 mmc_hostname(host->mmc));
407 return;
408 }
409 timeout--;
410 mdelay(1);
411 }
412
413 clk |= SDHCI_CLOCK_CARD_EN;
414 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
415 }
416
417 static struct sdhci_ops sdhci_s3c_ops = {
418 .get_max_clock = sdhci_s3c_get_max_clk,
419 .set_clock = sdhci_s3c_set_clock,
420 .get_min_clock = sdhci_s3c_get_min_clock,
421 .set_bus_width = sdhci_set_bus_width,
422 .reset = sdhci_reset,
423 .set_uhs_signaling = sdhci_set_uhs_signaling,
424 };
425
426 #ifdef CONFIG_OF
sdhci_s3c_parse_dt(struct device * dev,struct sdhci_host * host,struct s3c_sdhci_platdata * pdata)427 static int sdhci_s3c_parse_dt(struct device *dev,
428 struct sdhci_host *host, struct s3c_sdhci_platdata *pdata)
429 {
430 struct device_node *node = dev->of_node;
431 u32 max_width;
432
433 /* if the bus-width property is not specified, assume width as 1 */
434 if (of_property_read_u32(node, "bus-width", &max_width))
435 max_width = 1;
436 pdata->max_width = max_width;
437
438 /* get the card detection method */
439 if (of_get_property(node, "broken-cd", NULL)) {
440 pdata->cd_type = S3C_SDHCI_CD_NONE;
441 return 0;
442 }
443
444 if (of_get_property(node, "non-removable", NULL)) {
445 pdata->cd_type = S3C_SDHCI_CD_PERMANENT;
446 return 0;
447 }
448
449 if (of_get_named_gpio(node, "cd-gpios", 0))
450 return 0;
451
452 /* assuming internal card detect that will be configured by pinctrl */
453 pdata->cd_type = S3C_SDHCI_CD_INTERNAL;
454 return 0;
455 }
456 #else
sdhci_s3c_parse_dt(struct device * dev,struct sdhci_host * host,struct s3c_sdhci_platdata * pdata)457 static int sdhci_s3c_parse_dt(struct device *dev,
458 struct sdhci_host *host, struct s3c_sdhci_platdata *pdata)
459 {
460 return -EINVAL;
461 }
462 #endif
463
464 static const struct of_device_id sdhci_s3c_dt_match[];
465
sdhci_s3c_get_driver_data(struct platform_device * pdev)466 static inline struct sdhci_s3c_drv_data *sdhci_s3c_get_driver_data(
467 struct platform_device *pdev)
468 {
469 #ifdef CONFIG_OF
470 if (pdev->dev.of_node) {
471 const struct of_device_id *match;
472 match = of_match_node(sdhci_s3c_dt_match, pdev->dev.of_node);
473 return (struct sdhci_s3c_drv_data *)match->data;
474 }
475 #endif
476 return (struct sdhci_s3c_drv_data *)
477 platform_get_device_id(pdev)->driver_data;
478 }
479
sdhci_s3c_probe(struct platform_device * pdev)480 static int sdhci_s3c_probe(struct platform_device *pdev)
481 {
482 struct s3c_sdhci_platdata *pdata;
483 struct sdhci_s3c_drv_data *drv_data;
484 struct device *dev = &pdev->dev;
485 struct sdhci_host *host;
486 struct sdhci_s3c *sc;
487 struct resource *res;
488 int ret, irq, ptr, clks;
489
490 if (!pdev->dev.platform_data && !pdev->dev.of_node) {
491 dev_err(dev, "no device data specified\n");
492 return -ENOENT;
493 }
494
495 irq = platform_get_irq(pdev, 0);
496 if (irq < 0) {
497 dev_err(dev, "no irq specified\n");
498 return irq;
499 }
500
501 host = sdhci_alloc_host(dev, sizeof(struct sdhci_s3c));
502 if (IS_ERR(host)) {
503 dev_err(dev, "sdhci_alloc_host() failed\n");
504 return PTR_ERR(host);
505 }
506 sc = sdhci_priv(host);
507
508 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
509 if (!pdata) {
510 ret = -ENOMEM;
511 goto err_pdata_io_clk;
512 }
513
514 if (pdev->dev.of_node) {
515 ret = sdhci_s3c_parse_dt(&pdev->dev, host, pdata);
516 if (ret)
517 goto err_pdata_io_clk;
518 } else {
519 memcpy(pdata, pdev->dev.platform_data, sizeof(*pdata));
520 sc->ext_cd_gpio = -1; /* invalid gpio number */
521 }
522
523 drv_data = sdhci_s3c_get_driver_data(pdev);
524
525 sc->host = host;
526 sc->pdev = pdev;
527 sc->pdata = pdata;
528 sc->cur_clk = -1;
529
530 platform_set_drvdata(pdev, host);
531
532 sc->clk_io = devm_clk_get(dev, "hsmmc");
533 if (IS_ERR(sc->clk_io)) {
534 dev_err(dev, "failed to get io clock\n");
535 ret = PTR_ERR(sc->clk_io);
536 goto err_pdata_io_clk;
537 }
538
539 /* enable the local io clock and keep it running for the moment. */
540 clk_prepare_enable(sc->clk_io);
541
542 for (clks = 0, ptr = 0; ptr < MAX_BUS_CLK; ptr++) {
543 char name[14];
544
545 snprintf(name, 14, "mmc_busclk.%d", ptr);
546 sc->clk_bus[ptr] = devm_clk_get(dev, name);
547 if (IS_ERR(sc->clk_bus[ptr]))
548 continue;
549
550 clks++;
551 sc->clk_rates[ptr] = clk_get_rate(sc->clk_bus[ptr]);
552
553 dev_info(dev, "clock source %d: %s (%ld Hz)\n",
554 ptr, name, sc->clk_rates[ptr]);
555 }
556
557 if (clks == 0) {
558 dev_err(dev, "failed to find any bus clocks\n");
559 ret = -ENOENT;
560 goto err_no_busclks;
561 }
562
563 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
564 host->ioaddr = devm_ioremap_resource(&pdev->dev, res);
565 if (IS_ERR(host->ioaddr)) {
566 ret = PTR_ERR(host->ioaddr);
567 goto err_req_regs;
568 }
569
570 /* Ensure we have minimal gpio selected CMD/CLK/Detect */
571 if (pdata->cfg_gpio)
572 pdata->cfg_gpio(pdev, pdata->max_width);
573
574 host->hw_name = "samsung-hsmmc";
575 host->ops = &sdhci_s3c_ops;
576 host->quirks = 0;
577 host->quirks2 = 0;
578 host->irq = irq;
579
580 /* Setup quirks for the controller */
581 host->quirks |= SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC;
582 host->quirks |= SDHCI_QUIRK_NO_HISPD_BIT;
583 if (drv_data) {
584 host->quirks |= drv_data->sdhci_quirks;
585 sc->no_divider = drv_data->no_divider;
586 }
587
588 #ifndef CONFIG_MMC_SDHCI_S3C_DMA
589
590 /* we currently see overruns on errors, so disable the SDMA
591 * support as well. */
592 host->quirks |= SDHCI_QUIRK_BROKEN_DMA;
593
594 #endif /* CONFIG_MMC_SDHCI_S3C_DMA */
595
596 /* It seems we do not get an DATA transfer complete on non-busy
597 * transfers, not sure if this is a problem with this specific
598 * SDHCI block, or a missing configuration that needs to be set. */
599 host->quirks |= SDHCI_QUIRK_NO_BUSY_IRQ;
600
601 /* This host supports the Auto CMD12 */
602 host->quirks |= SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12;
603
604 /* Samsung SoCs need BROKEN_ADMA_ZEROLEN_DESC */
605 host->quirks |= SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC;
606
607 if (pdata->cd_type == S3C_SDHCI_CD_NONE ||
608 pdata->cd_type == S3C_SDHCI_CD_PERMANENT)
609 host->quirks |= SDHCI_QUIRK_BROKEN_CARD_DETECTION;
610
611 if (pdata->cd_type == S3C_SDHCI_CD_PERMANENT)
612 host->mmc->caps = MMC_CAP_NONREMOVABLE;
613
614 switch (pdata->max_width) {
615 case 8:
616 host->mmc->caps |= MMC_CAP_8_BIT_DATA;
617 case 4:
618 host->mmc->caps |= MMC_CAP_4_BIT_DATA;
619 break;
620 }
621
622 if (pdata->pm_caps)
623 host->mmc->pm_caps |= pdata->pm_caps;
624
625 host->quirks |= (SDHCI_QUIRK_32BIT_DMA_ADDR |
626 SDHCI_QUIRK_32BIT_DMA_SIZE);
627
628 /* HSMMC on Samsung SoCs uses SDCLK as timeout clock */
629 host->quirks |= SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK;
630
631 /*
632 * If controller does not have internal clock divider,
633 * we can use overriding functions instead of default.
634 */
635 if (sc->no_divider) {
636 sdhci_s3c_ops.set_clock = sdhci_cmu_set_clock;
637 sdhci_s3c_ops.get_min_clock = sdhci_cmu_get_min_clock;
638 sdhci_s3c_ops.get_max_clock = sdhci_cmu_get_max_clock;
639 }
640
641 /* It supports additional host capabilities if needed */
642 if (pdata->host_caps)
643 host->mmc->caps |= pdata->host_caps;
644
645 if (pdata->host_caps2)
646 host->mmc->caps2 |= pdata->host_caps2;
647
648 pm_runtime_enable(&pdev->dev);
649 pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
650 pm_runtime_use_autosuspend(&pdev->dev);
651 pm_suspend_ignore_children(&pdev->dev, 1);
652
653 ret = mmc_of_parse(host->mmc);
654 if (ret)
655 goto err_req_regs;
656
657 ret = sdhci_add_host(host);
658 if (ret)
659 goto err_req_regs;
660
661 #ifdef CONFIG_PM
662 if (pdata->cd_type != S3C_SDHCI_CD_INTERNAL)
663 clk_disable_unprepare(sc->clk_io);
664 #endif
665 return 0;
666
667 err_req_regs:
668 pm_runtime_disable(&pdev->dev);
669
670 err_no_busclks:
671 clk_disable_unprepare(sc->clk_io);
672
673 err_pdata_io_clk:
674 sdhci_free_host(host);
675
676 return ret;
677 }
678
sdhci_s3c_remove(struct platform_device * pdev)679 static int sdhci_s3c_remove(struct platform_device *pdev)
680 {
681 struct sdhci_host *host = platform_get_drvdata(pdev);
682 struct sdhci_s3c *sc = sdhci_priv(host);
683
684 if (sc->ext_cd_irq)
685 free_irq(sc->ext_cd_irq, sc);
686
687 #ifdef CONFIG_PM
688 if (sc->pdata->cd_type != S3C_SDHCI_CD_INTERNAL)
689 clk_prepare_enable(sc->clk_io);
690 #endif
691 sdhci_remove_host(host, 1);
692
693 pm_runtime_dont_use_autosuspend(&pdev->dev);
694 pm_runtime_disable(&pdev->dev);
695
696 clk_disable_unprepare(sc->clk_io);
697
698 sdhci_free_host(host);
699
700 return 0;
701 }
702
703 #ifdef CONFIG_PM_SLEEP
sdhci_s3c_suspend(struct device * dev)704 static int sdhci_s3c_suspend(struct device *dev)
705 {
706 struct sdhci_host *host = dev_get_drvdata(dev);
707
708 if (host->tuning_mode != SDHCI_TUNING_MODE_3)
709 mmc_retune_needed(host->mmc);
710
711 return sdhci_suspend_host(host);
712 }
713
sdhci_s3c_resume(struct device * dev)714 static int sdhci_s3c_resume(struct device *dev)
715 {
716 struct sdhci_host *host = dev_get_drvdata(dev);
717
718 return sdhci_resume_host(host);
719 }
720 #endif
721
722 #ifdef CONFIG_PM
sdhci_s3c_runtime_suspend(struct device * dev)723 static int sdhci_s3c_runtime_suspend(struct device *dev)
724 {
725 struct sdhci_host *host = dev_get_drvdata(dev);
726 struct sdhci_s3c *ourhost = to_s3c(host);
727 struct clk *busclk = ourhost->clk_io;
728 int ret;
729
730 ret = sdhci_runtime_suspend_host(host);
731
732 if (host->tuning_mode != SDHCI_TUNING_MODE_3)
733 mmc_retune_needed(host->mmc);
734
735 if (ourhost->cur_clk >= 0)
736 clk_disable_unprepare(ourhost->clk_bus[ourhost->cur_clk]);
737 clk_disable_unprepare(busclk);
738 return ret;
739 }
740
sdhci_s3c_runtime_resume(struct device * dev)741 static int sdhci_s3c_runtime_resume(struct device *dev)
742 {
743 struct sdhci_host *host = dev_get_drvdata(dev);
744 struct sdhci_s3c *ourhost = to_s3c(host);
745 struct clk *busclk = ourhost->clk_io;
746 int ret;
747
748 clk_prepare_enable(busclk);
749 if (ourhost->cur_clk >= 0)
750 clk_prepare_enable(ourhost->clk_bus[ourhost->cur_clk]);
751 ret = sdhci_runtime_resume_host(host);
752 return ret;
753 }
754 #endif
755
756 static const struct dev_pm_ops sdhci_s3c_pmops = {
757 SET_SYSTEM_SLEEP_PM_OPS(sdhci_s3c_suspend, sdhci_s3c_resume)
758 SET_RUNTIME_PM_OPS(sdhci_s3c_runtime_suspend, sdhci_s3c_runtime_resume,
759 NULL)
760 };
761
762 static const struct platform_device_id sdhci_s3c_driver_ids[] = {
763 {
764 .name = "s3c-sdhci",
765 .driver_data = (kernel_ulong_t)NULL,
766 },
767 { }
768 };
769 MODULE_DEVICE_TABLE(platform, sdhci_s3c_driver_ids);
770
771 #ifdef CONFIG_OF
772 static struct sdhci_s3c_drv_data exynos4_sdhci_drv_data = {
773 .no_divider = true,
774 };
775
776 static const struct of_device_id sdhci_s3c_dt_match[] = {
777 { .compatible = "samsung,s3c6410-sdhci", },
778 { .compatible = "samsung,exynos4210-sdhci",
779 .data = &exynos4_sdhci_drv_data },
780 {},
781 };
782 MODULE_DEVICE_TABLE(of, sdhci_s3c_dt_match);
783 #endif
784
785 static struct platform_driver sdhci_s3c_driver = {
786 .probe = sdhci_s3c_probe,
787 .remove = sdhci_s3c_remove,
788 .id_table = sdhci_s3c_driver_ids,
789 .driver = {
790 .name = "s3c-sdhci",
791 .of_match_table = of_match_ptr(sdhci_s3c_dt_match),
792 .pm = &sdhci_s3c_pmops,
793 },
794 };
795
796 module_platform_driver(sdhci_s3c_driver);
797
798 MODULE_DESCRIPTION("Samsung SDHCI (HSMMC) glue");
799 MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>");
800 MODULE_LICENSE("GPL v2");
801 MODULE_ALIAS("platform:s3c-sdhci");
802
