1 // SPDX-License-Identifier: GPL-2.0-only
2 /**
3 * SDHCI Controller driver for TI's OMAP SoCs
4 *
5 * Copyright (C) 2017 Texas Instruments
6 * Author: Kishon Vijay Abraham I <kishon@ti.com>
7 */
8
9 #include <linux/delay.h>
10 #include <linux/mmc/mmc.h>
11 #include <linux/mmc/slot-gpio.h>
12 #include <linux/module.h>
13 #include <linux/of.h>
14 #include <linux/of_irq.h>
15 #include <linux/platform_device.h>
16 #include <linux/pm_runtime.h>
17 #include <linux/pm_wakeirq.h>
18 #include <linux/regulator/consumer.h>
19 #include <linux/pinctrl/consumer.h>
20 #include <linux/sys_soc.h>
21 #include <linux/thermal.h>
22
23 #include "sdhci-pltfm.h"
24
25 /*
26 * Note that the register offsets used here are from omap_regs
27 * base which is 0x100 for omap4 and later, and 0 for omap3 and
28 * earlier.
29 */
30 #define SDHCI_OMAP_SYSCONFIG 0x10
31
32 #define SDHCI_OMAP_CON 0x2c
33 #define CON_DW8 BIT(5)
34 #define CON_DMA_MASTER BIT(20)
35 #define CON_DDR BIT(19)
36 #define CON_CLKEXTFREE BIT(16)
37 #define CON_PADEN BIT(15)
38 #define CON_CTPL BIT(11)
39 #define CON_INIT BIT(1)
40 #define CON_OD BIT(0)
41
42 #define SDHCI_OMAP_DLL 0x34
43 #define DLL_SWT BIT(20)
44 #define DLL_FORCE_SR_C_SHIFT 13
45 #define DLL_FORCE_SR_C_MASK (0x7f << DLL_FORCE_SR_C_SHIFT)
46 #define DLL_FORCE_VALUE BIT(12)
47 #define DLL_CALIB BIT(1)
48
49 #define SDHCI_OMAP_CMD 0x10c
50
51 #define SDHCI_OMAP_PSTATE 0x124
52 #define PSTATE_DLEV_DAT0 BIT(20)
53 #define PSTATE_DATI BIT(1)
54
55 #define SDHCI_OMAP_HCTL 0x128
56 #define HCTL_SDBP BIT(8)
57 #define HCTL_SDVS_SHIFT 9
58 #define HCTL_SDVS_MASK (0x7 << HCTL_SDVS_SHIFT)
59 #define HCTL_SDVS_33 (0x7 << HCTL_SDVS_SHIFT)
60 #define HCTL_SDVS_30 (0x6 << HCTL_SDVS_SHIFT)
61 #define HCTL_SDVS_18 (0x5 << HCTL_SDVS_SHIFT)
62
63 #define SDHCI_OMAP_SYSCTL 0x12c
64 #define SYSCTL_CEN BIT(2)
65 #define SYSCTL_CLKD_SHIFT 6
66 #define SYSCTL_CLKD_MASK 0x3ff
67
68 #define SDHCI_OMAP_STAT 0x130
69
70 #define SDHCI_OMAP_IE 0x134
71 #define INT_CC_EN BIT(0)
72
73 #define SDHCI_OMAP_ISE 0x138
74
75 #define SDHCI_OMAP_AC12 0x13c
76 #define AC12_V1V8_SIGEN BIT(19)
77 #define AC12_SCLK_SEL BIT(23)
78
79 #define SDHCI_OMAP_CAPA 0x140
80 #define CAPA_VS33 BIT(24)
81 #define CAPA_VS30 BIT(25)
82 #define CAPA_VS18 BIT(26)
83
84 #define SDHCI_OMAP_CAPA2 0x144
85 #define CAPA2_TSDR50 BIT(13)
86
87 #define SDHCI_OMAP_TIMEOUT 1 /* 1 msec */
88
89 #define SYSCTL_CLKD_MAX 0x3FF
90
91 #define IOV_1V8 1800000 /* 180000 uV */
92 #define IOV_3V0 3000000 /* 300000 uV */
93 #define IOV_3V3 3300000 /* 330000 uV */
94
95 #define MAX_PHASE_DELAY 0x7C
96
97 /* sdhci-omap controller flags */
98 #define SDHCI_OMAP_REQUIRE_IODELAY BIT(0)
99 #define SDHCI_OMAP_SPECIAL_RESET BIT(1)
100
101 struct sdhci_omap_data {
102 int omap_offset; /* Offset for omap regs from base */
103 u32 offset; /* Offset for SDHCI regs from base */
104 u8 flags;
105 };
106
107 struct sdhci_omap_host {
108 char *version;
109 void __iomem *base;
110 struct device *dev;
111 struct regulator *pbias;
112 bool pbias_enabled;
113 struct sdhci_host *host;
114 u8 bus_mode;
115 u8 power_mode;
116 u8 timing;
117 u8 flags;
118
119 struct pinctrl *pinctrl;
120 struct pinctrl_state **pinctrl_state;
121 int wakeirq;
122 bool is_tuning;
123
124 /* Offset for omap specific registers from base */
125 int omap_offset;
126
127 /* Omap specific context save */
128 u32 con;
129 u32 hctl;
130 u32 sysctl;
131 u32 capa;
132 u32 ie;
133 u32 ise;
134 };
135
136 static void sdhci_omap_start_clock(struct sdhci_omap_host *omap_host);
137 static void sdhci_omap_stop_clock(struct sdhci_omap_host *omap_host);
138
sdhci_omap_readl(struct sdhci_omap_host * host,unsigned int offset)139 static inline u32 sdhci_omap_readl(struct sdhci_omap_host *host,
140 unsigned int offset)
141 {
142 return readl(host->base + host->omap_offset + offset);
143 }
144
sdhci_omap_writel(struct sdhci_omap_host * host,unsigned int offset,u32 data)145 static inline void sdhci_omap_writel(struct sdhci_omap_host *host,
146 unsigned int offset, u32 data)
147 {
148 writel(data, host->base + host->omap_offset + offset);
149 }
150
sdhci_omap_set_pbias(struct sdhci_omap_host * omap_host,bool power_on,unsigned int iov)151 static int sdhci_omap_set_pbias(struct sdhci_omap_host *omap_host,
152 bool power_on, unsigned int iov)
153 {
154 int ret;
155 struct device *dev = omap_host->dev;
156
157 if (IS_ERR(omap_host->pbias))
158 return 0;
159
160 if (power_on) {
161 ret = regulator_set_voltage(omap_host->pbias, iov, iov);
162 if (ret) {
163 dev_err(dev, "pbias set voltage failed\n");
164 return ret;
165 }
166
167 if (omap_host->pbias_enabled)
168 return 0;
169
170 ret = regulator_enable(omap_host->pbias);
171 if (ret) {
172 dev_err(dev, "pbias reg enable fail\n");
173 return ret;
174 }
175
176 omap_host->pbias_enabled = true;
177 } else {
178 if (!omap_host->pbias_enabled)
179 return 0;
180
181 ret = regulator_disable(omap_host->pbias);
182 if (ret) {
183 dev_err(dev, "pbias reg disable fail\n");
184 return ret;
185 }
186 omap_host->pbias_enabled = false;
187 }
188
189 return 0;
190 }
191
sdhci_omap_enable_iov(struct sdhci_omap_host * omap_host,unsigned int iov_pbias)192 static int sdhci_omap_enable_iov(struct sdhci_omap_host *omap_host,
193 unsigned int iov_pbias)
194 {
195 int ret;
196 struct sdhci_host *host = omap_host->host;
197 struct mmc_host *mmc = host->mmc;
198
199 ret = sdhci_omap_set_pbias(omap_host, false, 0);
200 if (ret)
201 return ret;
202
203 if (!IS_ERR(mmc->supply.vqmmc)) {
204 /* Pick the right voltage to allow 3.0V for 3.3V nominal PBIAS */
205 ret = mmc_regulator_set_vqmmc(mmc, &mmc->ios);
206 if (ret < 0) {
207 dev_err(mmc_dev(mmc), "vqmmc set voltage failed\n");
208 return ret;
209 }
210 }
211
212 ret = sdhci_omap_set_pbias(omap_host, true, iov_pbias);
213 if (ret)
214 return ret;
215
216 return 0;
217 }
218
sdhci_omap_conf_bus_power(struct sdhci_omap_host * omap_host,unsigned char signal_voltage)219 static void sdhci_omap_conf_bus_power(struct sdhci_omap_host *omap_host,
220 unsigned char signal_voltage)
221 {
222 u32 reg, capa;
223 ktime_t timeout;
224
225 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_HCTL);
226 reg &= ~HCTL_SDVS_MASK;
227
228 switch (signal_voltage) {
229 case MMC_SIGNAL_VOLTAGE_330:
230 capa = sdhci_omap_readl(omap_host, SDHCI_OMAP_CAPA);
231 if (capa & CAPA_VS33)
232 reg |= HCTL_SDVS_33;
233 else if (capa & CAPA_VS30)
234 reg |= HCTL_SDVS_30;
235 else
236 dev_warn(omap_host->dev, "misconfigured CAPA: %08x\n",
237 capa);
238 break;
239 case MMC_SIGNAL_VOLTAGE_180:
240 default:
241 reg |= HCTL_SDVS_18;
242 break;
243 }
244
245 sdhci_omap_writel(omap_host, SDHCI_OMAP_HCTL, reg);
246
247 reg |= HCTL_SDBP;
248 sdhci_omap_writel(omap_host, SDHCI_OMAP_HCTL, reg);
249
250 /* wait 1ms */
251 timeout = ktime_add_ms(ktime_get(), SDHCI_OMAP_TIMEOUT);
252 while (1) {
253 bool timedout = ktime_after(ktime_get(), timeout);
254
255 if (sdhci_omap_readl(omap_host, SDHCI_OMAP_HCTL) & HCTL_SDBP)
256 break;
257 if (WARN_ON(timedout))
258 return;
259 usleep_range(5, 10);
260 }
261 }
262
sdhci_omap_enable_sdio_irq(struct mmc_host * mmc,int enable)263 static void sdhci_omap_enable_sdio_irq(struct mmc_host *mmc, int enable)
264 {
265 struct sdhci_host *host = mmc_priv(mmc);
266 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
267 struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
268 u32 reg;
269
270 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
271 if (enable)
272 reg |= (CON_CTPL | CON_CLKEXTFREE);
273 else
274 reg &= ~(CON_CTPL | CON_CLKEXTFREE);
275 sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
276
277 sdhci_enable_sdio_irq(mmc, enable);
278 }
279
sdhci_omap_set_dll(struct sdhci_omap_host * omap_host,int count)280 static inline void sdhci_omap_set_dll(struct sdhci_omap_host *omap_host,
281 int count)
282 {
283 int i;
284 u32 reg;
285
286 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_DLL);
287 reg |= DLL_FORCE_VALUE;
288 reg &= ~DLL_FORCE_SR_C_MASK;
289 reg |= (count << DLL_FORCE_SR_C_SHIFT);
290 sdhci_omap_writel(omap_host, SDHCI_OMAP_DLL, reg);
291
292 reg |= DLL_CALIB;
293 sdhci_omap_writel(omap_host, SDHCI_OMAP_DLL, reg);
294 for (i = 0; i < 1000; i++) {
295 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_DLL);
296 if (reg & DLL_CALIB)
297 break;
298 }
299 reg &= ~DLL_CALIB;
300 sdhci_omap_writel(omap_host, SDHCI_OMAP_DLL, reg);
301 }
302
sdhci_omap_disable_tuning(struct sdhci_omap_host * omap_host)303 static void sdhci_omap_disable_tuning(struct sdhci_omap_host *omap_host)
304 {
305 u32 reg;
306
307 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_AC12);
308 reg &= ~AC12_SCLK_SEL;
309 sdhci_omap_writel(omap_host, SDHCI_OMAP_AC12, reg);
310
311 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_DLL);
312 reg &= ~(DLL_FORCE_VALUE | DLL_SWT);
313 sdhci_omap_writel(omap_host, SDHCI_OMAP_DLL, reg);
314 }
315
sdhci_omap_execute_tuning(struct mmc_host * mmc,u32 opcode)316 static int sdhci_omap_execute_tuning(struct mmc_host *mmc, u32 opcode)
317 {
318 struct sdhci_host *host = mmc_priv(mmc);
319 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
320 struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
321 struct thermal_zone_device *thermal_dev;
322 struct device *dev = omap_host->dev;
323 struct mmc_ios *ios = &mmc->ios;
324 u32 start_window = 0, max_window = 0;
325 bool single_point_failure = false;
326 bool dcrc_was_enabled = false;
327 u8 cur_match, prev_match = 0;
328 u32 length = 0, max_len = 0;
329 u32 phase_delay = 0;
330 int temperature;
331 int ret = 0;
332 u32 reg;
333 int i;
334
335 /* clock tuning is not needed for upto 52MHz */
336 if (ios->clock <= 52000000)
337 return 0;
338
339 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CAPA2);
340 if (ios->timing == MMC_TIMING_UHS_SDR50 && !(reg & CAPA2_TSDR50))
341 return 0;
342
343 thermal_dev = thermal_zone_get_zone_by_name("cpu_thermal");
344 if (IS_ERR(thermal_dev)) {
345 dev_err(dev, "Unable to get thermal zone for tuning\n");
346 return PTR_ERR(thermal_dev);
347 }
348
349 ret = thermal_zone_get_temp(thermal_dev, &temperature);
350 if (ret)
351 return ret;
352
353 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_DLL);
354 reg |= DLL_SWT;
355 sdhci_omap_writel(omap_host, SDHCI_OMAP_DLL, reg);
356
357 /*
358 * OMAP5/DRA74X/DRA72x Errata i802:
359 * DCRC error interrupts (MMCHS_STAT[21] DCRC=0x1) can occur
360 * during the tuning procedure. So disable it during the
361 * tuning procedure.
362 */
363 if (host->ier & SDHCI_INT_DATA_CRC) {
364 host->ier &= ~SDHCI_INT_DATA_CRC;
365 dcrc_was_enabled = true;
366 }
367
368 omap_host->is_tuning = true;
369
370 /*
371 * Stage 1: Search for a maximum pass window ignoring any
372 * single point failures. If the tuning value ends up
373 * near it, move away from it in stage 2 below
374 */
375 while (phase_delay <= MAX_PHASE_DELAY) {
376 sdhci_omap_set_dll(omap_host, phase_delay);
377
378 cur_match = !mmc_send_tuning(mmc, opcode, NULL);
379 if (cur_match) {
380 if (prev_match) {
381 length++;
382 } else if (single_point_failure) {
383 /* ignore single point failure */
384 length++;
385 } else {
386 start_window = phase_delay;
387 length = 1;
388 }
389 } else {
390 single_point_failure = prev_match;
391 }
392
393 if (length > max_len) {
394 max_window = start_window;
395 max_len = length;
396 }
397
398 prev_match = cur_match;
399 phase_delay += 4;
400 }
401
402 if (!max_len) {
403 dev_err(dev, "Unable to find match\n");
404 ret = -EIO;
405 goto tuning_error;
406 }
407
408 /*
409 * Assign tuning value as a ratio of maximum pass window based
410 * on temperature
411 */
412 if (temperature < -20000)
413 phase_delay = min(max_window + 4 * (max_len - 1) - 24,
414 max_window +
415 DIV_ROUND_UP(13 * max_len, 16) * 4);
416 else if (temperature < 20000)
417 phase_delay = max_window + DIV_ROUND_UP(9 * max_len, 16) * 4;
418 else if (temperature < 40000)
419 phase_delay = max_window + DIV_ROUND_UP(8 * max_len, 16) * 4;
420 else if (temperature < 70000)
421 phase_delay = max_window + DIV_ROUND_UP(7 * max_len, 16) * 4;
422 else if (temperature < 90000)
423 phase_delay = max_window + DIV_ROUND_UP(5 * max_len, 16) * 4;
424 else if (temperature < 120000)
425 phase_delay = max_window + DIV_ROUND_UP(4 * max_len, 16) * 4;
426 else
427 phase_delay = max_window + DIV_ROUND_UP(3 * max_len, 16) * 4;
428
429 /*
430 * Stage 2: Search for a single point failure near the chosen tuning
431 * value in two steps. First in the +3 to +10 range and then in the
432 * +2 to -10 range. If found, move away from it in the appropriate
433 * direction by the appropriate amount depending on the temperature.
434 */
435 for (i = 3; i <= 10; i++) {
436 sdhci_omap_set_dll(omap_host, phase_delay + i);
437
438 if (mmc_send_tuning(mmc, opcode, NULL)) {
439 if (temperature < 10000)
440 phase_delay += i + 6;
441 else if (temperature < 20000)
442 phase_delay += i - 12;
443 else if (temperature < 70000)
444 phase_delay += i - 8;
445 else
446 phase_delay += i - 6;
447
448 goto single_failure_found;
449 }
450 }
451
452 for (i = 2; i >= -10; i--) {
453 sdhci_omap_set_dll(omap_host, phase_delay + i);
454
455 if (mmc_send_tuning(mmc, opcode, NULL)) {
456 if (temperature < 10000)
457 phase_delay += i + 12;
458 else if (temperature < 20000)
459 phase_delay += i + 8;
460 else if (temperature < 70000)
461 phase_delay += i + 8;
462 else if (temperature < 90000)
463 phase_delay += i + 10;
464 else
465 phase_delay += i + 12;
466
467 goto single_failure_found;
468 }
469 }
470
471 single_failure_found:
472 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_AC12);
473 if (!(reg & AC12_SCLK_SEL)) {
474 ret = -EIO;
475 goto tuning_error;
476 }
477
478 sdhci_omap_set_dll(omap_host, phase_delay);
479
480 omap_host->is_tuning = false;
481
482 goto ret;
483
484 tuning_error:
485 omap_host->is_tuning = false;
486 dev_err(dev, "Tuning failed\n");
487 sdhci_omap_disable_tuning(omap_host);
488
489 ret:
490 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
491 /* Reenable forbidden interrupt */
492 if (dcrc_was_enabled)
493 host->ier |= SDHCI_INT_DATA_CRC;
494 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
495 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
496 return ret;
497 }
498
sdhci_omap_card_busy(struct mmc_host * mmc)499 static int sdhci_omap_card_busy(struct mmc_host *mmc)
500 {
501 u32 reg, ac12;
502 int ret = false;
503 struct sdhci_host *host = mmc_priv(mmc);
504 struct sdhci_pltfm_host *pltfm_host;
505 struct sdhci_omap_host *omap_host;
506 u32 ier = host->ier;
507
508 pltfm_host = sdhci_priv(host);
509 omap_host = sdhci_pltfm_priv(pltfm_host);
510
511 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
512 ac12 = sdhci_omap_readl(omap_host, SDHCI_OMAP_AC12);
513 reg &= ~CON_CLKEXTFREE;
514 if (ac12 & AC12_V1V8_SIGEN)
515 reg |= CON_CLKEXTFREE;
516 reg |= CON_PADEN;
517 sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
518
519 disable_irq(host->irq);
520 ier |= SDHCI_INT_CARD_INT;
521 sdhci_writel(host, ier, SDHCI_INT_ENABLE);
522 sdhci_writel(host, ier, SDHCI_SIGNAL_ENABLE);
523
524 /*
525 * Delay is required for PSTATE to correctly reflect
526 * DLEV/CLEV values after PADEN is set.
527 */
528 usleep_range(50, 100);
529 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_PSTATE);
530 if ((reg & PSTATE_DATI) || !(reg & PSTATE_DLEV_DAT0))
531 ret = true;
532
533 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
534 reg &= ~(CON_CLKEXTFREE | CON_PADEN);
535 sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
536
537 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
538 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
539 enable_irq(host->irq);
540
541 return ret;
542 }
543
sdhci_omap_start_signal_voltage_switch(struct mmc_host * mmc,struct mmc_ios * ios)544 static int sdhci_omap_start_signal_voltage_switch(struct mmc_host *mmc,
545 struct mmc_ios *ios)
546 {
547 u32 reg;
548 int ret;
549 unsigned int iov;
550 struct sdhci_host *host = mmc_priv(mmc);
551 struct sdhci_pltfm_host *pltfm_host;
552 struct sdhci_omap_host *omap_host;
553 struct device *dev;
554
555 pltfm_host = sdhci_priv(host);
556 omap_host = sdhci_pltfm_priv(pltfm_host);
557 dev = omap_host->dev;
558
559 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) {
560 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CAPA);
561 if (!(reg & (CAPA_VS30 | CAPA_VS33)))
562 return -EOPNOTSUPP;
563
564 if (reg & CAPA_VS30)
565 iov = IOV_3V0;
566 else
567 iov = IOV_3V3;
568
569 sdhci_omap_conf_bus_power(omap_host, ios->signal_voltage);
570
571 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_AC12);
572 reg &= ~AC12_V1V8_SIGEN;
573 sdhci_omap_writel(omap_host, SDHCI_OMAP_AC12, reg);
574
575 } else if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) {
576 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CAPA);
577 if (!(reg & CAPA_VS18))
578 return -EOPNOTSUPP;
579
580 iov = IOV_1V8;
581
582 sdhci_omap_conf_bus_power(omap_host, ios->signal_voltage);
583
584 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_AC12);
585 reg |= AC12_V1V8_SIGEN;
586 sdhci_omap_writel(omap_host, SDHCI_OMAP_AC12, reg);
587 } else {
588 return -EOPNOTSUPP;
589 }
590
591 ret = sdhci_omap_enable_iov(omap_host, iov);
592 if (ret) {
593 dev_err(dev, "failed to switch IO voltage to %dmV\n", iov);
594 return ret;
595 }
596
597 dev_dbg(dev, "IO voltage switched to %dmV\n", iov);
598 return 0;
599 }
600
sdhci_omap_set_timing(struct sdhci_omap_host * omap_host,u8 timing)601 static void sdhci_omap_set_timing(struct sdhci_omap_host *omap_host, u8 timing)
602 {
603 int ret;
604 struct pinctrl_state *pinctrl_state;
605 struct device *dev = omap_host->dev;
606
607 if (!(omap_host->flags & SDHCI_OMAP_REQUIRE_IODELAY))
608 return;
609
610 if (omap_host->timing == timing)
611 return;
612
613 sdhci_omap_stop_clock(omap_host);
614
615 pinctrl_state = omap_host->pinctrl_state[timing];
616 ret = pinctrl_select_state(omap_host->pinctrl, pinctrl_state);
617 if (ret) {
618 dev_err(dev, "failed to select pinctrl state\n");
619 return;
620 }
621
622 sdhci_omap_start_clock(omap_host);
623 omap_host->timing = timing;
624 }
625
sdhci_omap_set_power_mode(struct sdhci_omap_host * omap_host,u8 power_mode)626 static void sdhci_omap_set_power_mode(struct sdhci_omap_host *omap_host,
627 u8 power_mode)
628 {
629 if (omap_host->bus_mode == MMC_POWER_OFF)
630 sdhci_omap_disable_tuning(omap_host);
631 omap_host->power_mode = power_mode;
632 }
633
sdhci_omap_set_bus_mode(struct sdhci_omap_host * omap_host,unsigned int mode)634 static void sdhci_omap_set_bus_mode(struct sdhci_omap_host *omap_host,
635 unsigned int mode)
636 {
637 u32 reg;
638
639 if (omap_host->bus_mode == mode)
640 return;
641
642 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
643 if (mode == MMC_BUSMODE_OPENDRAIN)
644 reg |= CON_OD;
645 else
646 reg &= ~CON_OD;
647 sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
648
649 omap_host->bus_mode = mode;
650 }
651
sdhci_omap_set_ios(struct mmc_host * mmc,struct mmc_ios * ios)652 static void sdhci_omap_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
653 {
654 struct sdhci_host *host = mmc_priv(mmc);
655 struct sdhci_pltfm_host *pltfm_host;
656 struct sdhci_omap_host *omap_host;
657
658 pltfm_host = sdhci_priv(host);
659 omap_host = sdhci_pltfm_priv(pltfm_host);
660
661 sdhci_omap_set_bus_mode(omap_host, ios->bus_mode);
662 sdhci_omap_set_timing(omap_host, ios->timing);
663 sdhci_set_ios(mmc, ios);
664 sdhci_omap_set_power_mode(omap_host, ios->power_mode);
665 }
666
sdhci_omap_calc_divisor(struct sdhci_pltfm_host * host,unsigned int clock)667 static u16 sdhci_omap_calc_divisor(struct sdhci_pltfm_host *host,
668 unsigned int clock)
669 {
670 u16 dsor;
671
672 dsor = DIV_ROUND_UP(clk_get_rate(host->clk), clock);
673 if (dsor > SYSCTL_CLKD_MAX)
674 dsor = SYSCTL_CLKD_MAX;
675
676 return dsor;
677 }
678
sdhci_omap_start_clock(struct sdhci_omap_host * omap_host)679 static void sdhci_omap_start_clock(struct sdhci_omap_host *omap_host)
680 {
681 u32 reg;
682
683 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_SYSCTL);
684 reg |= SYSCTL_CEN;
685 sdhci_omap_writel(omap_host, SDHCI_OMAP_SYSCTL, reg);
686 }
687
sdhci_omap_stop_clock(struct sdhci_omap_host * omap_host)688 static void sdhci_omap_stop_clock(struct sdhci_omap_host *omap_host)
689 {
690 u32 reg;
691
692 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_SYSCTL);
693 reg &= ~SYSCTL_CEN;
694 sdhci_omap_writel(omap_host, SDHCI_OMAP_SYSCTL, reg);
695 }
696
sdhci_omap_set_clock(struct sdhci_host * host,unsigned int clock)697 static void sdhci_omap_set_clock(struct sdhci_host *host, unsigned int clock)
698 {
699 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
700 struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
701 unsigned long clkdiv;
702
703 sdhci_omap_stop_clock(omap_host);
704
705 if (!clock)
706 return;
707
708 clkdiv = sdhci_omap_calc_divisor(pltfm_host, clock);
709 clkdiv = (clkdiv & SYSCTL_CLKD_MASK) << SYSCTL_CLKD_SHIFT;
710 sdhci_enable_clk(host, clkdiv);
711
712 sdhci_omap_start_clock(omap_host);
713 }
714
sdhci_omap_set_power(struct sdhci_host * host,unsigned char mode,unsigned short vdd)715 static void sdhci_omap_set_power(struct sdhci_host *host, unsigned char mode,
716 unsigned short vdd)
717 {
718 struct mmc_host *mmc = host->mmc;
719
720 if (!IS_ERR(mmc->supply.vmmc))
721 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
722 }
723
724 /*
725 * MMCHS_HL_HWINFO has the MADMA_EN bit set if the controller instance
726 * is connected to L3 interconnect and is bus master capable. Note that
727 * the MMCHS_HL_HWINFO register is in the module registers before the
728 * omap registers and sdhci registers. The offset can vary for omap
729 * registers depending on the SoC. Do not use sdhci_omap_readl() here.
730 */
sdhci_omap_has_adma(struct sdhci_omap_host * omap_host,int offset)731 static bool sdhci_omap_has_adma(struct sdhci_omap_host *omap_host, int offset)
732 {
733 /* MMCHS_HL_HWINFO register is only available on omap4 and later */
734 if (offset < 0x200)
735 return false;
736
737 return readl(omap_host->base + 4) & 1;
738 }
739
sdhci_omap_enable_dma(struct sdhci_host * host)740 static int sdhci_omap_enable_dma(struct sdhci_host *host)
741 {
742 u32 reg;
743 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
744 struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
745
746 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
747 reg &= ~CON_DMA_MASTER;
748 /* Switch to DMA slave mode when using external DMA */
749 if (!host->use_external_dma)
750 reg |= CON_DMA_MASTER;
751
752 sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
753
754 return 0;
755 }
756
sdhci_omap_get_min_clock(struct sdhci_host * host)757 static unsigned int sdhci_omap_get_min_clock(struct sdhci_host *host)
758 {
759 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
760
761 return clk_get_rate(pltfm_host->clk) / SYSCTL_CLKD_MAX;
762 }
763
sdhci_omap_set_bus_width(struct sdhci_host * host,int width)764 static void sdhci_omap_set_bus_width(struct sdhci_host *host, int width)
765 {
766 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
767 struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
768 u32 reg;
769
770 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
771 if (width == MMC_BUS_WIDTH_8)
772 reg |= CON_DW8;
773 else
774 reg &= ~CON_DW8;
775 sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
776
777 sdhci_set_bus_width(host, width);
778 }
779
sdhci_omap_init_74_clocks(struct sdhci_host * host,u8 power_mode)780 static void sdhci_omap_init_74_clocks(struct sdhci_host *host, u8 power_mode)
781 {
782 u32 reg;
783 ktime_t timeout;
784 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
785 struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
786
787 if (omap_host->power_mode == power_mode)
788 return;
789
790 if (power_mode != MMC_POWER_ON)
791 return;
792
793 disable_irq(host->irq);
794
795 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
796 reg |= CON_INIT;
797 sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
798 sdhci_omap_writel(omap_host, SDHCI_OMAP_CMD, 0x0);
799
800 /* wait 1ms */
801 timeout = ktime_add_ms(ktime_get(), SDHCI_OMAP_TIMEOUT);
802 while (1) {
803 bool timedout = ktime_after(ktime_get(), timeout);
804
805 if (sdhci_omap_readl(omap_host, SDHCI_OMAP_STAT) & INT_CC_EN)
806 break;
807 if (WARN_ON(timedout))
808 return;
809 usleep_range(5, 10);
810 }
811
812 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
813 reg &= ~CON_INIT;
814 sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
815 sdhci_omap_writel(omap_host, SDHCI_OMAP_STAT, INT_CC_EN);
816
817 enable_irq(host->irq);
818 }
819
sdhci_omap_set_uhs_signaling(struct sdhci_host * host,unsigned int timing)820 static void sdhci_omap_set_uhs_signaling(struct sdhci_host *host,
821 unsigned int timing)
822 {
823 u32 reg;
824 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
825 struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
826
827 sdhci_omap_stop_clock(omap_host);
828
829 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
830 if (timing == MMC_TIMING_UHS_DDR50 || timing == MMC_TIMING_MMC_DDR52)
831 reg |= CON_DDR;
832 else
833 reg &= ~CON_DDR;
834 sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
835
836 sdhci_set_uhs_signaling(host, timing);
837 sdhci_omap_start_clock(omap_host);
838 }
839
840 #define MMC_TIMEOUT_US 20000 /* 20000 micro Sec */
sdhci_omap_reset(struct sdhci_host * host,u8 mask)841 static void sdhci_omap_reset(struct sdhci_host *host, u8 mask)
842 {
843 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
844 struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
845 unsigned long limit = MMC_TIMEOUT_US;
846 unsigned long i = 0;
847 u32 sysc;
848
849 /* Save target module sysconfig configured by SoC PM layer */
850 if (mask & SDHCI_RESET_ALL)
851 sysc = sdhci_omap_readl(omap_host, SDHCI_OMAP_SYSCONFIG);
852
853 /* Don't reset data lines during tuning operation */
854 if (omap_host->is_tuning)
855 mask &= ~SDHCI_RESET_DATA;
856
857 if (omap_host->flags & SDHCI_OMAP_SPECIAL_RESET) {
858 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
859 while ((!(sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask)) &&
860 (i++ < limit))
861 udelay(1);
862 i = 0;
863 while ((sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) &&
864 (i++ < limit))
865 udelay(1);
866
867 if (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask)
868 dev_err(mmc_dev(host->mmc),
869 "Timeout waiting on controller reset in %s\n",
870 __func__);
871
872 goto restore_sysc;
873 }
874
875 sdhci_reset(host, mask);
876
877 restore_sysc:
878 if (mask & SDHCI_RESET_ALL)
879 sdhci_omap_writel(omap_host, SDHCI_OMAP_SYSCONFIG, sysc);
880 }
881
882 #define CMD_ERR_MASK (SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX |\
883 SDHCI_INT_TIMEOUT)
884 #define CMD_MASK (CMD_ERR_MASK | SDHCI_INT_RESPONSE)
885
sdhci_omap_irq(struct sdhci_host * host,u32 intmask)886 static u32 sdhci_omap_irq(struct sdhci_host *host, u32 intmask)
887 {
888 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
889 struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
890
891 if (omap_host->is_tuning && host->cmd && !host->data_early &&
892 (intmask & CMD_ERR_MASK)) {
893
894 /*
895 * Since we are not resetting data lines during tuning
896 * operation, data error or data complete interrupts
897 * might still arrive. Mark this request as a failure
898 * but still wait for the data interrupt
899 */
900 if (intmask & SDHCI_INT_TIMEOUT)
901 host->cmd->error = -ETIMEDOUT;
902 else
903 host->cmd->error = -EILSEQ;
904
905 host->cmd = NULL;
906
907 /*
908 * Sometimes command error interrupts and command complete
909 * interrupt will arrive together. Clear all command related
910 * interrupts here.
911 */
912 sdhci_writel(host, intmask & CMD_MASK, SDHCI_INT_STATUS);
913 intmask &= ~CMD_MASK;
914 }
915
916 return intmask;
917 }
918
sdhci_omap_set_timeout(struct sdhci_host * host,struct mmc_command * cmd)919 static void sdhci_omap_set_timeout(struct sdhci_host *host,
920 struct mmc_command *cmd)
921 {
922 if (cmd->opcode == MMC_ERASE)
923 sdhci_set_data_timeout_irq(host, false);
924
925 __sdhci_set_timeout(host, cmd);
926 }
927
928 static struct sdhci_ops sdhci_omap_ops = {
929 .set_clock = sdhci_omap_set_clock,
930 .set_power = sdhci_omap_set_power,
931 .enable_dma = sdhci_omap_enable_dma,
932 .get_max_clock = sdhci_pltfm_clk_get_max_clock,
933 .get_min_clock = sdhci_omap_get_min_clock,
934 .set_bus_width = sdhci_omap_set_bus_width,
935 .platform_send_init_74_clocks = sdhci_omap_init_74_clocks,
936 .reset = sdhci_omap_reset,
937 .set_uhs_signaling = sdhci_omap_set_uhs_signaling,
938 .irq = sdhci_omap_irq,
939 .set_timeout = sdhci_omap_set_timeout,
940 };
941
sdhci_omap_regulator_get_caps(struct device * dev,const char * name)942 static unsigned int sdhci_omap_regulator_get_caps(struct device *dev,
943 const char *name)
944 {
945 struct regulator *reg;
946 unsigned int caps = 0;
947
948 reg = regulator_get(dev, name);
949 if (IS_ERR(reg))
950 return ~0U;
951
952 if (regulator_is_supported_voltage(reg, 1700000, 1950000))
953 caps |= SDHCI_CAN_VDD_180;
954 if (regulator_is_supported_voltage(reg, 2700000, 3150000))
955 caps |= SDHCI_CAN_VDD_300;
956 if (regulator_is_supported_voltage(reg, 3150000, 3600000))
957 caps |= SDHCI_CAN_VDD_330;
958
959 regulator_put(reg);
960
961 return caps;
962 }
963
sdhci_omap_set_capabilities(struct sdhci_host * host)964 static int sdhci_omap_set_capabilities(struct sdhci_host *host)
965 {
966 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
967 struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
968 struct device *dev = omap_host->dev;
969 const u32 mask = SDHCI_CAN_VDD_180 | SDHCI_CAN_VDD_300 | SDHCI_CAN_VDD_330;
970 unsigned int pbias, vqmmc, caps = 0;
971 u32 reg;
972
973 pbias = sdhci_omap_regulator_get_caps(dev, "pbias");
974 vqmmc = sdhci_omap_regulator_get_caps(dev, "vqmmc");
975 caps = pbias & vqmmc;
976
977 if (pbias != ~0U && vqmmc == ~0U)
978 dev_warn(dev, "vqmmc regulator missing for pbias\n");
979 else if (caps == ~0U)
980 return 0;
981
982 /*
983 * Quirk handling to allow 3.0V vqmmc with a valid 3.3V PBIAS. This is
984 * needed for 3.0V ldo9_reg on omap5 at least.
985 */
986 if (pbias != ~0U && (pbias & SDHCI_CAN_VDD_330) &&
987 (vqmmc & SDHCI_CAN_VDD_300))
988 caps |= SDHCI_CAN_VDD_330;
989
990 /* voltage capabilities might be set by boot loader, clear it */
991 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CAPA);
992 reg &= ~(CAPA_VS18 | CAPA_VS30 | CAPA_VS33);
993
994 if (caps & SDHCI_CAN_VDD_180)
995 reg |= CAPA_VS18;
996
997 if (caps & SDHCI_CAN_VDD_300)
998 reg |= CAPA_VS30;
999
1000 if (caps & SDHCI_CAN_VDD_330)
1001 reg |= CAPA_VS33;
1002
1003 sdhci_omap_writel(omap_host, SDHCI_OMAP_CAPA, reg);
1004
1005 host->caps &= ~mask;
1006 host->caps |= caps;
1007
1008 return 0;
1009 }
1010
1011 static const struct sdhci_pltfm_data sdhci_omap_pdata = {
1012 .quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION |
1013 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
1014 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN |
1015 SDHCI_QUIRK_NO_HISPD_BIT |
1016 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC,
1017 .quirks2 = SDHCI_QUIRK2_ACMD23_BROKEN |
1018 SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
1019 SDHCI_QUIRK2_RSP_136_HAS_CRC |
1020 SDHCI_QUIRK2_DISABLE_HW_TIMEOUT,
1021 .ops = &sdhci_omap_ops,
1022 };
1023
1024 static const struct sdhci_omap_data omap2430_data = {
1025 .omap_offset = 0,
1026 .offset = 0x100,
1027 };
1028
1029 static const struct sdhci_omap_data omap3_data = {
1030 .omap_offset = 0,
1031 .offset = 0x100,
1032 };
1033
1034 static const struct sdhci_omap_data omap4_data = {
1035 .omap_offset = 0x100,
1036 .offset = 0x200,
1037 .flags = SDHCI_OMAP_SPECIAL_RESET,
1038 };
1039
1040 static const struct sdhci_omap_data omap5_data = {
1041 .omap_offset = 0x100,
1042 .offset = 0x200,
1043 .flags = SDHCI_OMAP_SPECIAL_RESET,
1044 };
1045
1046 static const struct sdhci_omap_data k2g_data = {
1047 .omap_offset = 0x100,
1048 .offset = 0x200,
1049 };
1050
1051 static const struct sdhci_omap_data am335_data = {
1052 .omap_offset = 0x100,
1053 .offset = 0x200,
1054 .flags = SDHCI_OMAP_SPECIAL_RESET,
1055 };
1056
1057 static const struct sdhci_omap_data am437_data = {
1058 .omap_offset = 0x100,
1059 .offset = 0x200,
1060 .flags = SDHCI_OMAP_SPECIAL_RESET,
1061 };
1062
1063 static const struct sdhci_omap_data dra7_data = {
1064 .omap_offset = 0x100,
1065 .offset = 0x200,
1066 .flags = SDHCI_OMAP_REQUIRE_IODELAY,
1067 };
1068
1069 static const struct of_device_id omap_sdhci_match[] = {
1070 { .compatible = "ti,omap2430-sdhci", .data = &omap2430_data },
1071 { .compatible = "ti,omap3-sdhci", .data = &omap3_data },
1072 { .compatible = "ti,omap4-sdhci", .data = &omap4_data },
1073 { .compatible = "ti,omap5-sdhci", .data = &omap5_data },
1074 { .compatible = "ti,dra7-sdhci", .data = &dra7_data },
1075 { .compatible = "ti,k2g-sdhci", .data = &k2g_data },
1076 { .compatible = "ti,am335-sdhci", .data = &am335_data },
1077 { .compatible = "ti,am437-sdhci", .data = &am437_data },
1078 {},
1079 };
1080 MODULE_DEVICE_TABLE(of, omap_sdhci_match);
1081
1082 static struct pinctrl_state
sdhci_omap_iodelay_pinctrl_state(struct sdhci_omap_host * omap_host,char * mode,u32 * caps,u32 capmask)1083 *sdhci_omap_iodelay_pinctrl_state(struct sdhci_omap_host *omap_host, char *mode,
1084 u32 *caps, u32 capmask)
1085 {
1086 struct device *dev = omap_host->dev;
1087 char *version = omap_host->version;
1088 struct pinctrl_state *pinctrl_state = ERR_PTR(-ENODEV);
1089 char str[20];
1090
1091 if (!(*caps & capmask))
1092 goto ret;
1093
1094 if (version) {
1095 snprintf(str, 20, "%s-%s", mode, version);
1096 pinctrl_state = pinctrl_lookup_state(omap_host->pinctrl, str);
1097 }
1098
1099 if (IS_ERR(pinctrl_state))
1100 pinctrl_state = pinctrl_lookup_state(omap_host->pinctrl, mode);
1101
1102 if (IS_ERR(pinctrl_state)) {
1103 dev_err(dev, "no pinctrl state for %s mode", mode);
1104 *caps &= ~capmask;
1105 }
1106
1107 ret:
1108 return pinctrl_state;
1109 }
1110
sdhci_omap_config_iodelay_pinctrl_state(struct sdhci_omap_host * omap_host)1111 static int sdhci_omap_config_iodelay_pinctrl_state(struct sdhci_omap_host
1112 *omap_host)
1113 {
1114 struct device *dev = omap_host->dev;
1115 struct sdhci_host *host = omap_host->host;
1116 struct mmc_host *mmc = host->mmc;
1117 u32 *caps = &mmc->caps;
1118 u32 *caps2 = &mmc->caps2;
1119 struct pinctrl_state *state;
1120 struct pinctrl_state **pinctrl_state;
1121
1122 if (!(omap_host->flags & SDHCI_OMAP_REQUIRE_IODELAY))
1123 return 0;
1124
1125 pinctrl_state = devm_kcalloc(dev,
1126 MMC_TIMING_MMC_HS200 + 1,
1127 sizeof(*pinctrl_state),
1128 GFP_KERNEL);
1129 if (!pinctrl_state)
1130 return -ENOMEM;
1131
1132 omap_host->pinctrl = devm_pinctrl_get(omap_host->dev);
1133 if (IS_ERR(omap_host->pinctrl)) {
1134 dev_err(dev, "Cannot get pinctrl\n");
1135 return PTR_ERR(omap_host->pinctrl);
1136 }
1137
1138 state = pinctrl_lookup_state(omap_host->pinctrl, "default");
1139 if (IS_ERR(state)) {
1140 dev_err(dev, "no pinctrl state for default mode\n");
1141 return PTR_ERR(state);
1142 }
1143 pinctrl_state[MMC_TIMING_LEGACY] = state;
1144
1145 state = sdhci_omap_iodelay_pinctrl_state(omap_host, "sdr104", caps,
1146 MMC_CAP_UHS_SDR104);
1147 if (!IS_ERR(state))
1148 pinctrl_state[MMC_TIMING_UHS_SDR104] = state;
1149
1150 state = sdhci_omap_iodelay_pinctrl_state(omap_host, "ddr50", caps,
1151 MMC_CAP_UHS_DDR50);
1152 if (!IS_ERR(state))
1153 pinctrl_state[MMC_TIMING_UHS_DDR50] = state;
1154
1155 state = sdhci_omap_iodelay_pinctrl_state(omap_host, "sdr50", caps,
1156 MMC_CAP_UHS_SDR50);
1157 if (!IS_ERR(state))
1158 pinctrl_state[MMC_TIMING_UHS_SDR50] = state;
1159
1160 state = sdhci_omap_iodelay_pinctrl_state(omap_host, "sdr25", caps,
1161 MMC_CAP_UHS_SDR25);
1162 if (!IS_ERR(state))
1163 pinctrl_state[MMC_TIMING_UHS_SDR25] = state;
1164
1165 state = sdhci_omap_iodelay_pinctrl_state(omap_host, "sdr12", caps,
1166 MMC_CAP_UHS_SDR12);
1167 if (!IS_ERR(state))
1168 pinctrl_state[MMC_TIMING_UHS_SDR12] = state;
1169
1170 state = sdhci_omap_iodelay_pinctrl_state(omap_host, "ddr_1_8v", caps,
1171 MMC_CAP_1_8V_DDR);
1172 if (!IS_ERR(state)) {
1173 pinctrl_state[MMC_TIMING_MMC_DDR52] = state;
1174 } else {
1175 state = sdhci_omap_iodelay_pinctrl_state(omap_host, "ddr_3_3v",
1176 caps,
1177 MMC_CAP_3_3V_DDR);
1178 if (!IS_ERR(state))
1179 pinctrl_state[MMC_TIMING_MMC_DDR52] = state;
1180 }
1181
1182 state = sdhci_omap_iodelay_pinctrl_state(omap_host, "hs", caps,
1183 MMC_CAP_SD_HIGHSPEED);
1184 if (!IS_ERR(state))
1185 pinctrl_state[MMC_TIMING_SD_HS] = state;
1186
1187 state = sdhci_omap_iodelay_pinctrl_state(omap_host, "hs", caps,
1188 MMC_CAP_MMC_HIGHSPEED);
1189 if (!IS_ERR(state))
1190 pinctrl_state[MMC_TIMING_MMC_HS] = state;
1191
1192 state = sdhci_omap_iodelay_pinctrl_state(omap_host, "hs200_1_8v", caps2,
1193 MMC_CAP2_HS200_1_8V_SDR);
1194 if (!IS_ERR(state))
1195 pinctrl_state[MMC_TIMING_MMC_HS200] = state;
1196
1197 omap_host->pinctrl_state = pinctrl_state;
1198
1199 return 0;
1200 }
1201
1202 static const struct soc_device_attribute sdhci_omap_soc_devices[] = {
1203 {
1204 .machine = "DRA7[45]*",
1205 .revision = "ES1.[01]",
1206 },
1207 {
1208 /* sentinel */
1209 }
1210 };
1211
sdhci_omap_probe(struct platform_device * pdev)1212 static int sdhci_omap_probe(struct platform_device *pdev)
1213 {
1214 int ret;
1215 u32 offset;
1216 struct device *dev = &pdev->dev;
1217 struct sdhci_host *host;
1218 struct sdhci_pltfm_host *pltfm_host;
1219 struct sdhci_omap_host *omap_host;
1220 struct mmc_host *mmc;
1221 const struct sdhci_omap_data *data;
1222 const struct soc_device_attribute *soc;
1223 struct resource *regs;
1224
1225 data = of_device_get_match_data(&pdev->dev);
1226 if (!data) {
1227 dev_err(dev, "no sdhci omap data\n");
1228 return -EINVAL;
1229 }
1230 offset = data->offset;
1231
1232 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1233 if (!regs)
1234 return -ENXIO;
1235
1236 host = sdhci_pltfm_init(pdev, &sdhci_omap_pdata,
1237 sizeof(*omap_host));
1238 if (IS_ERR(host)) {
1239 dev_err(dev, "Failed sdhci_pltfm_init\n");
1240 return PTR_ERR(host);
1241 }
1242
1243 pltfm_host = sdhci_priv(host);
1244 omap_host = sdhci_pltfm_priv(pltfm_host);
1245 omap_host->host = host;
1246 omap_host->base = host->ioaddr;
1247 omap_host->dev = dev;
1248 omap_host->power_mode = MMC_POWER_UNDEFINED;
1249 omap_host->timing = MMC_TIMING_LEGACY;
1250 omap_host->flags = data->flags;
1251 omap_host->omap_offset = data->omap_offset;
1252 omap_host->con = -EINVAL; /* Prevent invalid restore on first resume */
1253 host->ioaddr += offset;
1254 host->mapbase = regs->start + offset;
1255
1256 mmc = host->mmc;
1257 sdhci_get_of_property(pdev);
1258 ret = mmc_of_parse(mmc);
1259 if (ret)
1260 goto err_pltfm_free;
1261
1262 soc = soc_device_match(sdhci_omap_soc_devices);
1263 if (soc) {
1264 omap_host->version = "rev11";
1265 if (!strcmp(dev_name(dev), "4809c000.mmc"))
1266 mmc->f_max = 96000000;
1267 if (!strcmp(dev_name(dev), "480b4000.mmc"))
1268 mmc->f_max = 48000000;
1269 if (!strcmp(dev_name(dev), "480ad000.mmc"))
1270 mmc->f_max = 48000000;
1271 }
1272
1273 if (!mmc_can_gpio_ro(mmc))
1274 mmc->caps2 |= MMC_CAP2_NO_WRITE_PROTECT;
1275
1276 pltfm_host->clk = devm_clk_get(dev, "fck");
1277 if (IS_ERR(pltfm_host->clk)) {
1278 ret = PTR_ERR(pltfm_host->clk);
1279 goto err_pltfm_free;
1280 }
1281
1282 ret = clk_set_rate(pltfm_host->clk, mmc->f_max);
1283 if (ret) {
1284 dev_err(dev, "failed to set clock to %d\n", mmc->f_max);
1285 goto err_pltfm_free;
1286 }
1287
1288 omap_host->pbias = devm_regulator_get_optional(dev, "pbias");
1289 if (IS_ERR(omap_host->pbias)) {
1290 ret = PTR_ERR(omap_host->pbias);
1291 if (ret != -ENODEV)
1292 goto err_pltfm_free;
1293 dev_dbg(dev, "unable to get pbias regulator %d\n", ret);
1294 }
1295 omap_host->pbias_enabled = false;
1296
1297 /*
1298 * omap_device_pm_domain has callbacks to enable the main
1299 * functional clock, interface clock and also configure the
1300 * SYSCONFIG register to clear any boot loader set voltage
1301 * capabilities before calling sdhci_setup_host(). The
1302 * callback will be invoked as part of pm_runtime_get_sync.
1303 */
1304 pm_runtime_use_autosuspend(dev);
1305 pm_runtime_set_autosuspend_delay(dev, 50);
1306 pm_runtime_enable(dev);
1307 ret = pm_runtime_resume_and_get(dev);
1308 if (ret) {
1309 dev_err(dev, "pm_runtime_get_sync failed\n");
1310 goto err_rpm_disable;
1311 }
1312
1313 ret = sdhci_omap_set_capabilities(host);
1314 if (ret) {
1315 dev_err(dev, "failed to set system capabilities\n");
1316 goto err_rpm_put;
1317 }
1318
1319 host->mmc_host_ops.start_signal_voltage_switch =
1320 sdhci_omap_start_signal_voltage_switch;
1321 host->mmc_host_ops.set_ios = sdhci_omap_set_ios;
1322 host->mmc_host_ops.card_busy = sdhci_omap_card_busy;
1323 host->mmc_host_ops.execute_tuning = sdhci_omap_execute_tuning;
1324 host->mmc_host_ops.enable_sdio_irq = sdhci_omap_enable_sdio_irq;
1325
1326 /*
1327 * Switch to external DMA only if there is the "dmas" property and
1328 * ADMA is not available on the controller instance.
1329 */
1330 if (device_property_present(dev, "dmas") &&
1331 !sdhci_omap_has_adma(omap_host, offset))
1332 sdhci_switch_external_dma(host, true);
1333
1334 if (device_property_read_bool(dev, "ti,non-removable")) {
1335 dev_warn_once(dev, "using old ti,non-removable property\n");
1336 mmc->caps |= MMC_CAP_NONREMOVABLE;
1337 }
1338
1339 /* R1B responses is required to properly manage HW busy detection. */
1340 mmc->caps |= MMC_CAP_NEED_RSP_BUSY;
1341
1342 /* Allow card power off and runtime PM for eMMC/SD card devices */
1343 mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_AGGRESSIVE_PM;
1344
1345 ret = sdhci_setup_host(host);
1346 if (ret)
1347 goto err_rpm_put;
1348
1349 ret = sdhci_omap_config_iodelay_pinctrl_state(omap_host);
1350 if (ret)
1351 goto err_cleanup_host;
1352
1353 ret = __sdhci_add_host(host);
1354 if (ret)
1355 goto err_cleanup_host;
1356
1357 /*
1358 * SDIO devices can use the dat1 pin as a wake-up interrupt. Some
1359 * devices like wl1xxx, use an out-of-band GPIO interrupt instead.
1360 */
1361 omap_host->wakeirq = of_irq_get_byname(dev->of_node, "wakeup");
1362 if (omap_host->wakeirq == -EPROBE_DEFER) {
1363 ret = -EPROBE_DEFER;
1364 goto err_cleanup_host;
1365 }
1366 if (omap_host->wakeirq > 0) {
1367 device_init_wakeup(dev, true);
1368 ret = dev_pm_set_dedicated_wake_irq(dev, omap_host->wakeirq);
1369 if (ret) {
1370 device_init_wakeup(dev, false);
1371 goto err_cleanup_host;
1372 }
1373 host->mmc->pm_caps |= MMC_PM_KEEP_POWER | MMC_PM_WAKE_SDIO_IRQ;
1374 }
1375
1376 pm_runtime_mark_last_busy(dev);
1377 pm_runtime_put_autosuspend(dev);
1378
1379 return 0;
1380
1381 err_cleanup_host:
1382 sdhci_cleanup_host(host);
1383
1384 err_rpm_put:
1385 pm_runtime_mark_last_busy(dev);
1386 pm_runtime_put_autosuspend(dev);
1387 err_rpm_disable:
1388 pm_runtime_dont_use_autosuspend(dev);
1389 pm_runtime_disable(dev);
1390
1391 err_pltfm_free:
1392 sdhci_pltfm_free(pdev);
1393 return ret;
1394 }
1395
sdhci_omap_remove(struct platform_device * pdev)1396 static void sdhci_omap_remove(struct platform_device *pdev)
1397 {
1398 struct device *dev = &pdev->dev;
1399 struct sdhci_host *host = platform_get_drvdata(pdev);
1400
1401 pm_runtime_get_sync(dev);
1402 sdhci_remove_host(host, true);
1403 device_init_wakeup(dev, false);
1404 dev_pm_clear_wake_irq(dev);
1405 pm_runtime_dont_use_autosuspend(dev);
1406 pm_runtime_put_sync(dev);
1407 /* Ensure device gets disabled despite userspace sysfs config */
1408 pm_runtime_force_suspend(dev);
1409 sdhci_pltfm_free(pdev);
1410 }
1411
1412 #ifdef CONFIG_PM
sdhci_omap_context_save(struct sdhci_omap_host * omap_host)1413 static void __maybe_unused sdhci_omap_context_save(struct sdhci_omap_host *omap_host)
1414 {
1415 omap_host->con = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
1416 omap_host->hctl = sdhci_omap_readl(omap_host, SDHCI_OMAP_HCTL);
1417 omap_host->sysctl = sdhci_omap_readl(omap_host, SDHCI_OMAP_SYSCTL);
1418 omap_host->capa = sdhci_omap_readl(omap_host, SDHCI_OMAP_CAPA);
1419 omap_host->ie = sdhci_omap_readl(omap_host, SDHCI_OMAP_IE);
1420 omap_host->ise = sdhci_omap_readl(omap_host, SDHCI_OMAP_ISE);
1421 }
1422
1423 /* Order matters here, HCTL must be restored in two phases */
sdhci_omap_context_restore(struct sdhci_omap_host * omap_host)1424 static void __maybe_unused sdhci_omap_context_restore(struct sdhci_omap_host *omap_host)
1425 {
1426 sdhci_omap_writel(omap_host, SDHCI_OMAP_HCTL, omap_host->hctl);
1427 sdhci_omap_writel(omap_host, SDHCI_OMAP_CAPA, omap_host->capa);
1428 sdhci_omap_writel(omap_host, SDHCI_OMAP_HCTL, omap_host->hctl);
1429
1430 sdhci_omap_writel(omap_host, SDHCI_OMAP_SYSCTL, omap_host->sysctl);
1431 sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, omap_host->con);
1432 sdhci_omap_writel(omap_host, SDHCI_OMAP_IE, omap_host->ie);
1433 sdhci_omap_writel(omap_host, SDHCI_OMAP_ISE, omap_host->ise);
1434 }
1435
sdhci_omap_runtime_suspend(struct device * dev)1436 static int __maybe_unused sdhci_omap_runtime_suspend(struct device *dev)
1437 {
1438 struct sdhci_host *host = dev_get_drvdata(dev);
1439 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1440 struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
1441
1442 if (omap_host->con != -EINVAL)
1443 sdhci_runtime_suspend_host(host);
1444
1445 sdhci_omap_context_save(omap_host);
1446
1447 pinctrl_pm_select_idle_state(dev);
1448
1449 return 0;
1450 }
1451
sdhci_omap_runtime_resume(struct device * dev)1452 static int __maybe_unused sdhci_omap_runtime_resume(struct device *dev)
1453 {
1454 struct sdhci_host *host = dev_get_drvdata(dev);
1455 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1456 struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
1457
1458 pinctrl_pm_select_default_state(dev);
1459
1460 if (omap_host->con != -EINVAL) {
1461 sdhci_omap_context_restore(omap_host);
1462 sdhci_runtime_resume_host(host, 0);
1463 }
1464
1465 return 0;
1466 }
1467 #endif
1468
1469 static const struct dev_pm_ops sdhci_omap_dev_pm_ops = {
1470 SET_RUNTIME_PM_OPS(sdhci_omap_runtime_suspend,
1471 sdhci_omap_runtime_resume, NULL)
1472 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1473 pm_runtime_force_resume)
1474 };
1475
1476 static struct platform_driver sdhci_omap_driver = {
1477 .probe = sdhci_omap_probe,
1478 .remove_new = sdhci_omap_remove,
1479 .driver = {
1480 .name = "sdhci-omap",
1481 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
1482 .pm = &sdhci_omap_dev_pm_ops,
1483 .of_match_table = omap_sdhci_match,
1484 },
1485 };
1486
1487 module_platform_driver(sdhci_omap_driver);
1488
1489 MODULE_DESCRIPTION("SDHCI driver for OMAP SoCs");
1490 MODULE_AUTHOR("Texas Instruments Inc.");
1491 MODULE_LICENSE("GPL v2");
1492 MODULE_ALIAS("platform:sdhci_omap");
1493
