1 /*
2 * drivers/mmc/host/omap_hsmmc.c
3 *
4 * Driver for OMAP2430/3430 MMC controller.
5 *
6 * Copyright (C) 2007 Texas Instruments.
7 *
8 * Authors:
9 * Syed Mohammed Khasim <x0khasim@ti.com>
10 * Madhusudhan <madhu.cr@ti.com>
11 * Mohit Jalori <mjalori@ti.com>
12 *
13 * This file is licensed under the terms of the GNU General Public License
14 * version 2. This program is licensed "as is" without any warranty of any
15 * kind, whether express or implied.
16 */
17
18 #include <linux/module.h>
19 #include <linux/init.h>
20 #include <linux/kernel.h>
21 #include <linux/debugfs.h>
22 #include <linux/dmaengine.h>
23 #include <linux/seq_file.h>
24 #include <linux/sizes.h>
25 #include <linux/interrupt.h>
26 #include <linux/delay.h>
27 #include <linux/dma-mapping.h>
28 #include <linux/platform_device.h>
29 #include <linux/timer.h>
30 #include <linux/clk.h>
31 #include <linux/of.h>
32 #include <linux/of_irq.h>
33 #include <linux/of_device.h>
34 #include <linux/mmc/host.h>
35 #include <linux/mmc/core.h>
36 #include <linux/mmc/mmc.h>
37 #include <linux/mmc/slot-gpio.h>
38 #include <linux/io.h>
39 #include <linux/irq.h>
40 #include <linux/regulator/consumer.h>
41 #include <linux/pinctrl/consumer.h>
42 #include <linux/pm_runtime.h>
43 #include <linux/pm_wakeirq.h>
44 #include <linux/platform_data/hsmmc-omap.h>
45
46 /* OMAP HSMMC Host Controller Registers */
47 #define OMAP_HSMMC_SYSSTATUS 0x0014
48 #define OMAP_HSMMC_CON 0x002C
49 #define OMAP_HSMMC_SDMASA 0x0100
50 #define OMAP_HSMMC_BLK 0x0104
51 #define OMAP_HSMMC_ARG 0x0108
52 #define OMAP_HSMMC_CMD 0x010C
53 #define OMAP_HSMMC_RSP10 0x0110
54 #define OMAP_HSMMC_RSP32 0x0114
55 #define OMAP_HSMMC_RSP54 0x0118
56 #define OMAP_HSMMC_RSP76 0x011C
57 #define OMAP_HSMMC_DATA 0x0120
58 #define OMAP_HSMMC_PSTATE 0x0124
59 #define OMAP_HSMMC_HCTL 0x0128
60 #define OMAP_HSMMC_SYSCTL 0x012C
61 #define OMAP_HSMMC_STAT 0x0130
62 #define OMAP_HSMMC_IE 0x0134
63 #define OMAP_HSMMC_ISE 0x0138
64 #define OMAP_HSMMC_AC12 0x013C
65 #define OMAP_HSMMC_CAPA 0x0140
66
67 #define VS18 (1 << 26)
68 #define VS30 (1 << 25)
69 #define HSS (1 << 21)
70 #define SDVS18 (0x5 << 9)
71 #define SDVS30 (0x6 << 9)
72 #define SDVS33 (0x7 << 9)
73 #define SDVS_MASK 0x00000E00
74 #define SDVSCLR 0xFFFFF1FF
75 #define SDVSDET 0x00000400
76 #define AUTOIDLE 0x1
77 #define SDBP (1 << 8)
78 #define DTO 0xe
79 #define ICE 0x1
80 #define ICS 0x2
81 #define CEN (1 << 2)
82 #define CLKD_MAX 0x3FF /* max clock divisor: 1023 */
83 #define CLKD_MASK 0x0000FFC0
84 #define CLKD_SHIFT 6
85 #define DTO_MASK 0x000F0000
86 #define DTO_SHIFT 16
87 #define INIT_STREAM (1 << 1)
88 #define ACEN_ACMD23 (2 << 2)
89 #define DP_SELECT (1 << 21)
90 #define DDIR (1 << 4)
91 #define DMAE 0x1
92 #define MSBS (1 << 5)
93 #define BCE (1 << 1)
94 #define FOUR_BIT (1 << 1)
95 #define HSPE (1 << 2)
96 #define IWE (1 << 24)
97 #define DDR (1 << 19)
98 #define CLKEXTFREE (1 << 16)
99 #define CTPL (1 << 11)
100 #define DW8 (1 << 5)
101 #define OD 0x1
102 #define STAT_CLEAR 0xFFFFFFFF
103 #define INIT_STREAM_CMD 0x00000000
104 #define DUAL_VOLT_OCR_BIT 7
105 #define SRC (1 << 25)
106 #define SRD (1 << 26)
107 #define SOFTRESET (1 << 1)
108
109 /* PSTATE */
110 #define DLEV_DAT(x) (1 << (20 + (x)))
111
112 /* Interrupt masks for IE and ISE register */
113 #define CC_EN (1 << 0)
114 #define TC_EN (1 << 1)
115 #define BWR_EN (1 << 4)
116 #define BRR_EN (1 << 5)
117 #define CIRQ_EN (1 << 8)
118 #define ERR_EN (1 << 15)
119 #define CTO_EN (1 << 16)
120 #define CCRC_EN (1 << 17)
121 #define CEB_EN (1 << 18)
122 #define CIE_EN (1 << 19)
123 #define DTO_EN (1 << 20)
124 #define DCRC_EN (1 << 21)
125 #define DEB_EN (1 << 22)
126 #define ACE_EN (1 << 24)
127 #define CERR_EN (1 << 28)
128 #define BADA_EN (1 << 29)
129
130 #define INT_EN_MASK (BADA_EN | CERR_EN | ACE_EN | DEB_EN | DCRC_EN |\
131 DTO_EN | CIE_EN | CEB_EN | CCRC_EN | CTO_EN | \
132 BRR_EN | BWR_EN | TC_EN | CC_EN)
133
134 #define CNI (1 << 7)
135 #define ACIE (1 << 4)
136 #define ACEB (1 << 3)
137 #define ACCE (1 << 2)
138 #define ACTO (1 << 1)
139 #define ACNE (1 << 0)
140
141 #define MMC_AUTOSUSPEND_DELAY 100
142 #define MMC_TIMEOUT_MS 20 /* 20 mSec */
143 #define MMC_TIMEOUT_US 20000 /* 20000 micro Sec */
144 #define OMAP_MMC_MIN_CLOCK 400000
145 #define OMAP_MMC_MAX_CLOCK 52000000
146 #define DRIVER_NAME "omap_hsmmc"
147
148 /*
149 * One controller can have multiple slots, like on some omap boards using
150 * omap.c controller driver. Luckily this is not currently done on any known
151 * omap_hsmmc.c device.
152 */
153 #define mmc_pdata(host) host->pdata
154
155 /*
156 * MMC Host controller read/write API's
157 */
158 #define OMAP_HSMMC_READ(base, reg) \
159 __raw_readl((base) + OMAP_HSMMC_##reg)
160
161 #define OMAP_HSMMC_WRITE(base, reg, val) \
162 __raw_writel((val), (base) + OMAP_HSMMC_##reg)
163
164 struct omap_hsmmc_next {
165 unsigned int dma_len;
166 s32 cookie;
167 };
168
169 struct omap_hsmmc_host {
170 struct device *dev;
171 struct mmc_host *mmc;
172 struct mmc_request *mrq;
173 struct mmc_command *cmd;
174 struct mmc_data *data;
175 struct clk *fclk;
176 struct clk *dbclk;
177 struct regulator *pbias;
178 bool pbias_enabled;
179 void __iomem *base;
180 bool vqmmc_enabled;
181 resource_size_t mapbase;
182 spinlock_t irq_lock; /* Prevent races with irq handler */
183 unsigned int dma_len;
184 unsigned int dma_sg_idx;
185 unsigned char bus_mode;
186 unsigned char power_mode;
187 int suspended;
188 u32 con;
189 u32 hctl;
190 u32 sysctl;
191 u32 capa;
192 int irq;
193 int wake_irq;
194 int use_dma, dma_ch;
195 struct dma_chan *tx_chan;
196 struct dma_chan *rx_chan;
197 int response_busy;
198 int context_loss;
199 int reqs_blocked;
200 int req_in_progress;
201 unsigned long clk_rate;
202 unsigned int flags;
203 #define AUTO_CMD23 (1 << 0) /* Auto CMD23 support */
204 #define HSMMC_SDIO_IRQ_ENABLED (1 << 1) /* SDIO irq enabled */
205 struct omap_hsmmc_next next_data;
206 struct omap_hsmmc_platform_data *pdata;
207 };
208
209 struct omap_mmc_of_data {
210 u32 reg_offset;
211 u8 controller_flags;
212 };
213
214 static void omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host);
215
omap_hsmmc_enable_supply(struct mmc_host * mmc)216 static int omap_hsmmc_enable_supply(struct mmc_host *mmc)
217 {
218 int ret;
219 struct omap_hsmmc_host *host = mmc_priv(mmc);
220 struct mmc_ios *ios = &mmc->ios;
221
222 if (!IS_ERR(mmc->supply.vmmc)) {
223 ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd);
224 if (ret)
225 return ret;
226 }
227
228 /* Enable interface voltage rail, if needed */
229 if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) {
230 ret = regulator_enable(mmc->supply.vqmmc);
231 if (ret) {
232 dev_err(mmc_dev(mmc), "vmmc_aux reg enable failed\n");
233 goto err_vqmmc;
234 }
235 host->vqmmc_enabled = true;
236 }
237
238 return 0;
239
240 err_vqmmc:
241 if (!IS_ERR(mmc->supply.vmmc))
242 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
243
244 return ret;
245 }
246
omap_hsmmc_disable_supply(struct mmc_host * mmc)247 static int omap_hsmmc_disable_supply(struct mmc_host *mmc)
248 {
249 int ret;
250 int status;
251 struct omap_hsmmc_host *host = mmc_priv(mmc);
252
253 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) {
254 ret = regulator_disable(mmc->supply.vqmmc);
255 if (ret) {
256 dev_err(mmc_dev(mmc), "vmmc_aux reg disable failed\n");
257 return ret;
258 }
259 host->vqmmc_enabled = false;
260 }
261
262 if (!IS_ERR(mmc->supply.vmmc)) {
263 ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
264 if (ret)
265 goto err_set_ocr;
266 }
267
268 return 0;
269
270 err_set_ocr:
271 if (!IS_ERR(mmc->supply.vqmmc)) {
272 status = regulator_enable(mmc->supply.vqmmc);
273 if (status)
274 dev_err(mmc_dev(mmc), "vmmc_aux re-enable failed\n");
275 }
276
277 return ret;
278 }
279
omap_hsmmc_set_pbias(struct omap_hsmmc_host * host,bool power_on)280 static int omap_hsmmc_set_pbias(struct omap_hsmmc_host *host, bool power_on)
281 {
282 int ret;
283
284 if (IS_ERR(host->pbias))
285 return 0;
286
287 if (power_on) {
288 if (!host->pbias_enabled) {
289 ret = regulator_enable(host->pbias);
290 if (ret) {
291 dev_err(host->dev, "pbias reg enable fail\n");
292 return ret;
293 }
294 host->pbias_enabled = true;
295 }
296 } else {
297 if (host->pbias_enabled) {
298 ret = regulator_disable(host->pbias);
299 if (ret) {
300 dev_err(host->dev, "pbias reg disable fail\n");
301 return ret;
302 }
303 host->pbias_enabled = false;
304 }
305 }
306
307 return 0;
308 }
309
omap_hsmmc_set_power(struct omap_hsmmc_host * host,int power_on)310 static int omap_hsmmc_set_power(struct omap_hsmmc_host *host, int power_on)
311 {
312 struct mmc_host *mmc = host->mmc;
313 int ret = 0;
314
315 /*
316 * If we don't see a Vcc regulator, assume it's a fixed
317 * voltage always-on regulator.
318 */
319 if (IS_ERR(mmc->supply.vmmc))
320 return 0;
321
322 ret = omap_hsmmc_set_pbias(host, false);
323 if (ret)
324 return ret;
325
326 /*
327 * Assume Vcc regulator is used only to power the card ... OMAP
328 * VDDS is used to power the pins, optionally with a transceiver to
329 * support cards using voltages other than VDDS (1.8V nominal). When a
330 * transceiver is used, DAT3..7 are muxed as transceiver control pins.
331 *
332 * In some cases this regulator won't support enable/disable;
333 * e.g. it's a fixed rail for a WLAN chip.
334 *
335 * In other cases vcc_aux switches interface power. Example, for
336 * eMMC cards it represents VccQ. Sometimes transceivers or SDIO
337 * chips/cards need an interface voltage rail too.
338 */
339 if (power_on) {
340 ret = omap_hsmmc_enable_supply(mmc);
341 if (ret)
342 return ret;
343
344 ret = omap_hsmmc_set_pbias(host, true);
345 if (ret)
346 goto err_set_voltage;
347 } else {
348 ret = omap_hsmmc_disable_supply(mmc);
349 if (ret)
350 return ret;
351 }
352
353 return 0;
354
355 err_set_voltage:
356 omap_hsmmc_disable_supply(mmc);
357
358 return ret;
359 }
360
omap_hsmmc_disable_boot_regulator(struct regulator * reg)361 static int omap_hsmmc_disable_boot_regulator(struct regulator *reg)
362 {
363 int ret;
364
365 if (IS_ERR(reg))
366 return 0;
367
368 if (regulator_is_enabled(reg)) {
369 ret = regulator_enable(reg);
370 if (ret)
371 return ret;
372
373 ret = regulator_disable(reg);
374 if (ret)
375 return ret;
376 }
377
378 return 0;
379 }
380
omap_hsmmc_disable_boot_regulators(struct omap_hsmmc_host * host)381 static int omap_hsmmc_disable_boot_regulators(struct omap_hsmmc_host *host)
382 {
383 struct mmc_host *mmc = host->mmc;
384 int ret;
385
386 /*
387 * disable regulators enabled during boot and get the usecount
388 * right so that regulators can be enabled/disabled by checking
389 * the return value of regulator_is_enabled
390 */
391 ret = omap_hsmmc_disable_boot_regulator(mmc->supply.vmmc);
392 if (ret) {
393 dev_err(host->dev, "fail to disable boot enabled vmmc reg\n");
394 return ret;
395 }
396
397 ret = omap_hsmmc_disable_boot_regulator(mmc->supply.vqmmc);
398 if (ret) {
399 dev_err(host->dev,
400 "fail to disable boot enabled vmmc_aux reg\n");
401 return ret;
402 }
403
404 ret = omap_hsmmc_disable_boot_regulator(host->pbias);
405 if (ret) {
406 dev_err(host->dev,
407 "failed to disable boot enabled pbias reg\n");
408 return ret;
409 }
410
411 return 0;
412 }
413
omap_hsmmc_reg_get(struct omap_hsmmc_host * host)414 static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
415 {
416 int ret;
417 struct mmc_host *mmc = host->mmc;
418
419
420 ret = mmc_regulator_get_supply(mmc);
421 if (ret)
422 return ret;
423
424 /* Allow an aux regulator */
425 if (IS_ERR(mmc->supply.vqmmc)) {
426 mmc->supply.vqmmc = devm_regulator_get_optional(host->dev,
427 "vmmc_aux");
428 if (IS_ERR(mmc->supply.vqmmc)) {
429 ret = PTR_ERR(mmc->supply.vqmmc);
430 if ((ret != -ENODEV) && host->dev->of_node)
431 return ret;
432 dev_dbg(host->dev, "unable to get vmmc_aux regulator %ld\n",
433 PTR_ERR(mmc->supply.vqmmc));
434 }
435 }
436
437 host->pbias = devm_regulator_get_optional(host->dev, "pbias");
438 if (IS_ERR(host->pbias)) {
439 ret = PTR_ERR(host->pbias);
440 if ((ret != -ENODEV) && host->dev->of_node) {
441 dev_err(host->dev,
442 "SD card detect fail? enable CONFIG_REGULATOR_PBIAS\n");
443 return ret;
444 }
445 dev_dbg(host->dev, "unable to get pbias regulator %ld\n",
446 PTR_ERR(host->pbias));
447 }
448
449 /* For eMMC do not power off when not in sleep state */
450 if (mmc_pdata(host)->no_regulator_off_init)
451 return 0;
452
453 ret = omap_hsmmc_disable_boot_regulators(host);
454 if (ret)
455 return ret;
456
457 return 0;
458 }
459
460 /*
461 * Start clock to the card
462 */
omap_hsmmc_start_clock(struct omap_hsmmc_host * host)463 static void omap_hsmmc_start_clock(struct omap_hsmmc_host *host)
464 {
465 OMAP_HSMMC_WRITE(host->base, SYSCTL,
466 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
467 }
468
469 /*
470 * Stop clock to the card
471 */
omap_hsmmc_stop_clock(struct omap_hsmmc_host * host)472 static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host)
473 {
474 OMAP_HSMMC_WRITE(host->base, SYSCTL,
475 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
476 if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0)
477 dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stopped\n");
478 }
479
omap_hsmmc_enable_irq(struct omap_hsmmc_host * host,struct mmc_command * cmd)480 static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host,
481 struct mmc_command *cmd)
482 {
483 u32 irq_mask = INT_EN_MASK;
484 unsigned long flags;
485
486 if (host->use_dma)
487 irq_mask &= ~(BRR_EN | BWR_EN);
488
489 /* Disable timeout for erases */
490 if (cmd->opcode == MMC_ERASE)
491 irq_mask &= ~DTO_EN;
492
493 spin_lock_irqsave(&host->irq_lock, flags);
494 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
495 OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
496
497 /* latch pending CIRQ, but don't signal MMC core */
498 if (host->flags & HSMMC_SDIO_IRQ_ENABLED)
499 irq_mask |= CIRQ_EN;
500 OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
501 spin_unlock_irqrestore(&host->irq_lock, flags);
502 }
503
omap_hsmmc_disable_irq(struct omap_hsmmc_host * host)504 static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host)
505 {
506 u32 irq_mask = 0;
507 unsigned long flags;
508
509 spin_lock_irqsave(&host->irq_lock, flags);
510 /* no transfer running but need to keep cirq if enabled */
511 if (host->flags & HSMMC_SDIO_IRQ_ENABLED)
512 irq_mask |= CIRQ_EN;
513 OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
514 OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
515 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
516 spin_unlock_irqrestore(&host->irq_lock, flags);
517 }
518
519 /* Calculate divisor for the given clock frequency */
calc_divisor(struct omap_hsmmc_host * host,struct mmc_ios * ios)520 static u16 calc_divisor(struct omap_hsmmc_host *host, struct mmc_ios *ios)
521 {
522 u16 dsor = 0;
523
524 if (ios->clock) {
525 dsor = DIV_ROUND_UP(clk_get_rate(host->fclk), ios->clock);
526 if (dsor > CLKD_MAX)
527 dsor = CLKD_MAX;
528 }
529
530 return dsor;
531 }
532
omap_hsmmc_set_clock(struct omap_hsmmc_host * host)533 static void omap_hsmmc_set_clock(struct omap_hsmmc_host *host)
534 {
535 struct mmc_ios *ios = &host->mmc->ios;
536 unsigned long regval;
537 unsigned long timeout;
538 unsigned long clkdiv;
539
540 dev_vdbg(mmc_dev(host->mmc), "Set clock to %uHz\n", ios->clock);
541
542 omap_hsmmc_stop_clock(host);
543
544 regval = OMAP_HSMMC_READ(host->base, SYSCTL);
545 regval = regval & ~(CLKD_MASK | DTO_MASK);
546 clkdiv = calc_divisor(host, ios);
547 regval = regval | (clkdiv << 6) | (DTO << 16);
548 OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
549 OMAP_HSMMC_WRITE(host->base, SYSCTL,
550 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
551
552 /* Wait till the ICS bit is set */
553 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
554 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS
555 && time_before(jiffies, timeout))
556 cpu_relax();
557
558 /*
559 * Enable High-Speed Support
560 * Pre-Requisites
561 * - Controller should support High-Speed-Enable Bit
562 * - Controller should not be using DDR Mode
563 * - Controller should advertise that it supports High Speed
564 * in capabilities register
565 * - MMC/SD clock coming out of controller > 25MHz
566 */
567 if ((mmc_pdata(host)->features & HSMMC_HAS_HSPE_SUPPORT) &&
568 (ios->timing != MMC_TIMING_MMC_DDR52) &&
569 (ios->timing != MMC_TIMING_UHS_DDR50) &&
570 ((OMAP_HSMMC_READ(host->base, CAPA) & HSS) == HSS)) {
571 regval = OMAP_HSMMC_READ(host->base, HCTL);
572 if (clkdiv && (clk_get_rate(host->fclk)/clkdiv) > 25000000)
573 regval |= HSPE;
574 else
575 regval &= ~HSPE;
576
577 OMAP_HSMMC_WRITE(host->base, HCTL, regval);
578 }
579
580 omap_hsmmc_start_clock(host);
581 }
582
omap_hsmmc_set_bus_width(struct omap_hsmmc_host * host)583 static void omap_hsmmc_set_bus_width(struct omap_hsmmc_host *host)
584 {
585 struct mmc_ios *ios = &host->mmc->ios;
586 u32 con;
587
588 con = OMAP_HSMMC_READ(host->base, CON);
589 if (ios->timing == MMC_TIMING_MMC_DDR52 ||
590 ios->timing == MMC_TIMING_UHS_DDR50)
591 con |= DDR; /* configure in DDR mode */
592 else
593 con &= ~DDR;
594 switch (ios->bus_width) {
595 case MMC_BUS_WIDTH_8:
596 OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
597 break;
598 case MMC_BUS_WIDTH_4:
599 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
600 OMAP_HSMMC_WRITE(host->base, HCTL,
601 OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
602 break;
603 case MMC_BUS_WIDTH_1:
604 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
605 OMAP_HSMMC_WRITE(host->base, HCTL,
606 OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
607 break;
608 }
609 }
610
omap_hsmmc_set_bus_mode(struct omap_hsmmc_host * host)611 static void omap_hsmmc_set_bus_mode(struct omap_hsmmc_host *host)
612 {
613 struct mmc_ios *ios = &host->mmc->ios;
614 u32 con;
615
616 con = OMAP_HSMMC_READ(host->base, CON);
617 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
618 OMAP_HSMMC_WRITE(host->base, CON, con | OD);
619 else
620 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD);
621 }
622
623 #ifdef CONFIG_PM
624
625 /*
626 * Restore the MMC host context, if it was lost as result of a
627 * power state change.
628 */
omap_hsmmc_context_restore(struct omap_hsmmc_host * host)629 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
630 {
631 struct mmc_ios *ios = &host->mmc->ios;
632 u32 hctl, capa;
633 unsigned long timeout;
634
635 if (host->con == OMAP_HSMMC_READ(host->base, CON) &&
636 host->hctl == OMAP_HSMMC_READ(host->base, HCTL) &&
637 host->sysctl == OMAP_HSMMC_READ(host->base, SYSCTL) &&
638 host->capa == OMAP_HSMMC_READ(host->base, CAPA))
639 return 0;
640
641 host->context_loss++;
642
643 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
644 if (host->power_mode != MMC_POWER_OFF &&
645 (1 << ios->vdd) <= MMC_VDD_23_24)
646 hctl = SDVS18;
647 else
648 hctl = SDVS30;
649 capa = VS30 | VS18;
650 } else {
651 hctl = SDVS18;
652 capa = VS18;
653 }
654
655 if (host->mmc->caps & MMC_CAP_SDIO_IRQ)
656 hctl |= IWE;
657
658 OMAP_HSMMC_WRITE(host->base, HCTL,
659 OMAP_HSMMC_READ(host->base, HCTL) | hctl);
660
661 OMAP_HSMMC_WRITE(host->base, CAPA,
662 OMAP_HSMMC_READ(host->base, CAPA) | capa);
663
664 OMAP_HSMMC_WRITE(host->base, HCTL,
665 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
666
667 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
668 while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP
669 && time_before(jiffies, timeout))
670 ;
671
672 OMAP_HSMMC_WRITE(host->base, ISE, 0);
673 OMAP_HSMMC_WRITE(host->base, IE, 0);
674 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
675
676 /* Do not initialize card-specific things if the power is off */
677 if (host->power_mode == MMC_POWER_OFF)
678 goto out;
679
680 omap_hsmmc_set_bus_width(host);
681
682 omap_hsmmc_set_clock(host);
683
684 omap_hsmmc_set_bus_mode(host);
685
686 out:
687 dev_dbg(mmc_dev(host->mmc), "context is restored: restore count %d\n",
688 host->context_loss);
689 return 0;
690 }
691
692 /*
693 * Save the MMC host context (store the number of power state changes so far).
694 */
omap_hsmmc_context_save(struct omap_hsmmc_host * host)695 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
696 {
697 host->con = OMAP_HSMMC_READ(host->base, CON);
698 host->hctl = OMAP_HSMMC_READ(host->base, HCTL);
699 host->sysctl = OMAP_HSMMC_READ(host->base, SYSCTL);
700 host->capa = OMAP_HSMMC_READ(host->base, CAPA);
701 }
702
703 #else
704
omap_hsmmc_context_save(struct omap_hsmmc_host * host)705 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
706 {
707 }
708
709 #endif
710
711 /*
712 * Send init stream sequence to card
713 * before sending IDLE command
714 */
send_init_stream(struct omap_hsmmc_host * host)715 static void send_init_stream(struct omap_hsmmc_host *host)
716 {
717 int reg = 0;
718 unsigned long timeout;
719
720 disable_irq(host->irq);
721
722 OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
723 OMAP_HSMMC_WRITE(host->base, CON,
724 OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM);
725 OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD);
726
727 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
728 while ((reg != CC_EN) && time_before(jiffies, timeout))
729 reg = OMAP_HSMMC_READ(host->base, STAT) & CC_EN;
730
731 OMAP_HSMMC_WRITE(host->base, CON,
732 OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM);
733
734 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
735 OMAP_HSMMC_READ(host->base, STAT);
736
737 enable_irq(host->irq);
738 }
739
740 static ssize_t
omap_hsmmc_show_slot_name(struct device * dev,struct device_attribute * attr,char * buf)741 omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr,
742 char *buf)
743 {
744 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
745 struct omap_hsmmc_host *host = mmc_priv(mmc);
746
747 return sprintf(buf, "%s\n", mmc_pdata(host)->name);
748 }
749
750 static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL);
751
752 /*
753 * Configure the response type and send the cmd.
754 */
755 static void
omap_hsmmc_start_command(struct omap_hsmmc_host * host,struct mmc_command * cmd,struct mmc_data * data)756 omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd,
757 struct mmc_data *data)
758 {
759 int cmdreg = 0, resptype = 0, cmdtype = 0;
760
761 dev_vdbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",
762 mmc_hostname(host->mmc), cmd->opcode, cmd->arg);
763 host->cmd = cmd;
764
765 omap_hsmmc_enable_irq(host, cmd);
766
767 host->response_busy = 0;
768 if (cmd->flags & MMC_RSP_PRESENT) {
769 if (cmd->flags & MMC_RSP_136)
770 resptype = 1;
771 else if (cmd->flags & MMC_RSP_BUSY) {
772 resptype = 3;
773 host->response_busy = 1;
774 } else
775 resptype = 2;
776 }
777
778 /*
779 * Unlike OMAP1 controller, the cmdtype does not seem to be based on
780 * ac, bc, adtc, bcr. Only commands ending an open ended transfer need
781 * a val of 0x3, rest 0x0.
782 */
783 if (cmd == host->mrq->stop)
784 cmdtype = 0x3;
785
786 cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22);
787
788 if ((host->flags & AUTO_CMD23) && mmc_op_multi(cmd->opcode) &&
789 host->mrq->sbc) {
790 cmdreg |= ACEN_ACMD23;
791 OMAP_HSMMC_WRITE(host->base, SDMASA, host->mrq->sbc->arg);
792 }
793 if (data) {
794 cmdreg |= DP_SELECT | MSBS | BCE;
795 if (data->flags & MMC_DATA_READ)
796 cmdreg |= DDIR;
797 else
798 cmdreg &= ~(DDIR);
799 }
800
801 if (host->use_dma)
802 cmdreg |= DMAE;
803
804 host->req_in_progress = 1;
805
806 OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg);
807 OMAP_HSMMC_WRITE(host->base, CMD, cmdreg);
808 }
809
omap_hsmmc_get_dma_chan(struct omap_hsmmc_host * host,struct mmc_data * data)810 static struct dma_chan *omap_hsmmc_get_dma_chan(struct omap_hsmmc_host *host,
811 struct mmc_data *data)
812 {
813 return data->flags & MMC_DATA_WRITE ? host->tx_chan : host->rx_chan;
814 }
815
omap_hsmmc_request_done(struct omap_hsmmc_host * host,struct mmc_request * mrq)816 static void omap_hsmmc_request_done(struct omap_hsmmc_host *host, struct mmc_request *mrq)
817 {
818 int dma_ch;
819 unsigned long flags;
820
821 spin_lock_irqsave(&host->irq_lock, flags);
822 host->req_in_progress = 0;
823 dma_ch = host->dma_ch;
824 spin_unlock_irqrestore(&host->irq_lock, flags);
825
826 omap_hsmmc_disable_irq(host);
827 /* Do not complete the request if DMA is still in progress */
828 if (mrq->data && host->use_dma && dma_ch != -1)
829 return;
830 host->mrq = NULL;
831 mmc_request_done(host->mmc, mrq);
832 }
833
834 /*
835 * Notify the transfer complete to MMC core
836 */
837 static void
omap_hsmmc_xfer_done(struct omap_hsmmc_host * host,struct mmc_data * data)838 omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data)
839 {
840 if (!data) {
841 struct mmc_request *mrq = host->mrq;
842
843 /* TC before CC from CMD6 - don't know why, but it happens */
844 if (host->cmd && host->cmd->opcode == 6 &&
845 host->response_busy) {
846 host->response_busy = 0;
847 return;
848 }
849
850 omap_hsmmc_request_done(host, mrq);
851 return;
852 }
853
854 host->data = NULL;
855
856 if (!data->error)
857 data->bytes_xfered += data->blocks * (data->blksz);
858 else
859 data->bytes_xfered = 0;
860
861 if (data->stop && (data->error || !host->mrq->sbc))
862 omap_hsmmc_start_command(host, data->stop, NULL);
863 else
864 omap_hsmmc_request_done(host, data->mrq);
865 }
866
867 /*
868 * Notify the core about command completion
869 */
870 static void
omap_hsmmc_cmd_done(struct omap_hsmmc_host * host,struct mmc_command * cmd)871 omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd)
872 {
873 if (host->mrq->sbc && (host->cmd == host->mrq->sbc) &&
874 !host->mrq->sbc->error && !(host->flags & AUTO_CMD23)) {
875 host->cmd = NULL;
876 omap_hsmmc_start_dma_transfer(host);
877 omap_hsmmc_start_command(host, host->mrq->cmd,
878 host->mrq->data);
879 return;
880 }
881
882 host->cmd = NULL;
883
884 if (cmd->flags & MMC_RSP_PRESENT) {
885 if (cmd->flags & MMC_RSP_136) {
886 /* response type 2 */
887 cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10);
888 cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32);
889 cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54);
890 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76);
891 } else {
892 /* response types 1, 1b, 3, 4, 5, 6 */
893 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10);
894 }
895 }
896 if ((host->data == NULL && !host->response_busy) || cmd->error)
897 omap_hsmmc_request_done(host, host->mrq);
898 }
899
900 /*
901 * DMA clean up for command errors
902 */
omap_hsmmc_dma_cleanup(struct omap_hsmmc_host * host,int errno)903 static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno)
904 {
905 int dma_ch;
906 unsigned long flags;
907
908 host->data->error = errno;
909
910 spin_lock_irqsave(&host->irq_lock, flags);
911 dma_ch = host->dma_ch;
912 host->dma_ch = -1;
913 spin_unlock_irqrestore(&host->irq_lock, flags);
914
915 if (host->use_dma && dma_ch != -1) {
916 struct dma_chan *chan = omap_hsmmc_get_dma_chan(host, host->data);
917
918 dmaengine_terminate_all(chan);
919 dma_unmap_sg(chan->device->dev,
920 host->data->sg, host->data->sg_len,
921 mmc_get_dma_dir(host->data));
922
923 host->data->host_cookie = 0;
924 }
925 host->data = NULL;
926 }
927
928 /*
929 * Readable error output
930 */
931 #ifdef CONFIG_MMC_DEBUG
omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host * host,u32 status)932 static void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, u32 status)
933 {
934 /* --- means reserved bit without definition at documentation */
935 static const char *omap_hsmmc_status_bits[] = {
936 "CC" , "TC" , "BGE", "---", "BWR" , "BRR" , "---" , "---" ,
937 "CIRQ", "OBI" , "---", "---", "---" , "---" , "---" , "ERRI",
938 "CTO" , "CCRC", "CEB", "CIE", "DTO" , "DCRC", "DEB" , "---" ,
939 "ACE" , "---" , "---", "---", "CERR", "BADA", "---" , "---"
940 };
941 char res[256];
942 char *buf = res;
943 int len, i;
944
945 len = sprintf(buf, "MMC IRQ 0x%x :", status);
946 buf += len;
947
948 for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++)
949 if (status & (1 << i)) {
950 len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]);
951 buf += len;
952 }
953
954 dev_vdbg(mmc_dev(host->mmc), "%s\n", res);
955 }
956 #else
omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host * host,u32 status)957 static inline void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host,
958 u32 status)
959 {
960 }
961 #endif /* CONFIG_MMC_DEBUG */
962
963 /*
964 * MMC controller internal state machines reset
965 *
966 * Used to reset command or data internal state machines, using respectively
967 * SRC or SRD bit of SYSCTL register
968 * Can be called from interrupt context
969 */
omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host * host,unsigned long bit)970 static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host,
971 unsigned long bit)
972 {
973 unsigned long i = 0;
974 unsigned long limit = MMC_TIMEOUT_US;
975
976 OMAP_HSMMC_WRITE(host->base, SYSCTL,
977 OMAP_HSMMC_READ(host->base, SYSCTL) | bit);
978
979 /*
980 * OMAP4 ES2 and greater has an updated reset logic.
981 * Monitor a 0->1 transition first
982 */
983 if (mmc_pdata(host)->features & HSMMC_HAS_UPDATED_RESET) {
984 while ((!(OMAP_HSMMC_READ(host->base, SYSCTL) & bit))
985 && (i++ < limit))
986 udelay(1);
987 }
988 i = 0;
989
990 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) &&
991 (i++ < limit))
992 udelay(1);
993
994 if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit)
995 dev_err(mmc_dev(host->mmc),
996 "Timeout waiting on controller reset in %s\n",
997 __func__);
998 }
999
hsmmc_command_incomplete(struct omap_hsmmc_host * host,int err,int end_cmd)1000 static void hsmmc_command_incomplete(struct omap_hsmmc_host *host,
1001 int err, int end_cmd)
1002 {
1003 if (end_cmd) {
1004 omap_hsmmc_reset_controller_fsm(host, SRC);
1005 if (host->cmd)
1006 host->cmd->error = err;
1007 }
1008
1009 if (host->data) {
1010 omap_hsmmc_reset_controller_fsm(host, SRD);
1011 omap_hsmmc_dma_cleanup(host, err);
1012 } else if (host->mrq && host->mrq->cmd)
1013 host->mrq->cmd->error = err;
1014 }
1015
omap_hsmmc_do_irq(struct omap_hsmmc_host * host,int status)1016 static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status)
1017 {
1018 struct mmc_data *data;
1019 int end_cmd = 0, end_trans = 0;
1020 int error = 0;
1021
1022 data = host->data;
1023 dev_vdbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status);
1024
1025 if (status & ERR_EN) {
1026 omap_hsmmc_dbg_report_irq(host, status);
1027
1028 if (status & (CTO_EN | CCRC_EN | CEB_EN))
1029 end_cmd = 1;
1030 if (host->data || host->response_busy) {
1031 end_trans = !end_cmd;
1032 host->response_busy = 0;
1033 }
1034 if (status & (CTO_EN | DTO_EN))
1035 hsmmc_command_incomplete(host, -ETIMEDOUT, end_cmd);
1036 else if (status & (CCRC_EN | DCRC_EN | DEB_EN | CEB_EN |
1037 BADA_EN))
1038 hsmmc_command_incomplete(host, -EILSEQ, end_cmd);
1039
1040 if (status & ACE_EN) {
1041 u32 ac12;
1042 ac12 = OMAP_HSMMC_READ(host->base, AC12);
1043 if (!(ac12 & ACNE) && host->mrq->sbc) {
1044 end_cmd = 1;
1045 if (ac12 & ACTO)
1046 error = -ETIMEDOUT;
1047 else if (ac12 & (ACCE | ACEB | ACIE))
1048 error = -EILSEQ;
1049 host->mrq->sbc->error = error;
1050 hsmmc_command_incomplete(host, error, end_cmd);
1051 }
1052 dev_dbg(mmc_dev(host->mmc), "AC12 err: 0x%x\n", ac12);
1053 }
1054 }
1055
1056 OMAP_HSMMC_WRITE(host->base, STAT, status);
1057 if (end_cmd || ((status & CC_EN) && host->cmd))
1058 omap_hsmmc_cmd_done(host, host->cmd);
1059 if ((end_trans || (status & TC_EN)) && host->mrq)
1060 omap_hsmmc_xfer_done(host, data);
1061 }
1062
1063 /*
1064 * MMC controller IRQ handler
1065 */
omap_hsmmc_irq(int irq,void * dev_id)1066 static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id)
1067 {
1068 struct omap_hsmmc_host *host = dev_id;
1069 int status;
1070
1071 status = OMAP_HSMMC_READ(host->base, STAT);
1072 while (status & (INT_EN_MASK | CIRQ_EN)) {
1073 if (host->req_in_progress)
1074 omap_hsmmc_do_irq(host, status);
1075
1076 if (status & CIRQ_EN)
1077 mmc_signal_sdio_irq(host->mmc);
1078
1079 /* Flush posted write */
1080 status = OMAP_HSMMC_READ(host->base, STAT);
1081 }
1082
1083 return IRQ_HANDLED;
1084 }
1085
set_sd_bus_power(struct omap_hsmmc_host * host)1086 static void set_sd_bus_power(struct omap_hsmmc_host *host)
1087 {
1088 unsigned long i;
1089
1090 OMAP_HSMMC_WRITE(host->base, HCTL,
1091 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
1092 for (i = 0; i < loops_per_jiffy; i++) {
1093 if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP)
1094 break;
1095 cpu_relax();
1096 }
1097 }
1098
1099 /*
1100 * Switch MMC interface voltage ... only relevant for MMC1.
1101 *
1102 * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver.
1103 * The MMC2 transceiver controls are used instead of DAT4..DAT7.
1104 * Some chips, like eMMC ones, use internal transceivers.
1105 */
omap_hsmmc_switch_opcond(struct omap_hsmmc_host * host,int vdd)1106 static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd)
1107 {
1108 u32 reg_val = 0;
1109 int ret;
1110
1111 /* Disable the clocks */
1112 clk_disable_unprepare(host->dbclk);
1113
1114 /* Turn the power off */
1115 ret = omap_hsmmc_set_power(host, 0);
1116
1117 /* Turn the power ON with given VDD 1.8 or 3.0v */
1118 if (!ret)
1119 ret = omap_hsmmc_set_power(host, 1);
1120 clk_prepare_enable(host->dbclk);
1121
1122 if (ret != 0)
1123 goto err;
1124
1125 OMAP_HSMMC_WRITE(host->base, HCTL,
1126 OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR);
1127 reg_val = OMAP_HSMMC_READ(host->base, HCTL);
1128
1129 /*
1130 * If a MMC dual voltage card is detected, the set_ios fn calls
1131 * this fn with VDD bit set for 1.8V. Upon card removal from the
1132 * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF.
1133 *
1134 * Cope with a bit of slop in the range ... per data sheets:
1135 * - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max,
1136 * but recommended values are 1.71V to 1.89V
1137 * - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max,
1138 * but recommended values are 2.7V to 3.3V
1139 *
1140 * Board setup code shouldn't permit anything very out-of-range.
1141 * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the
1142 * middle range) but VSIM can't power DAT4..DAT7 at more than 3V.
1143 */
1144 if ((1 << vdd) <= MMC_VDD_23_24)
1145 reg_val |= SDVS18;
1146 else
1147 reg_val |= SDVS30;
1148
1149 OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);
1150 set_sd_bus_power(host);
1151
1152 return 0;
1153 err:
1154 dev_err(mmc_dev(host->mmc), "Unable to switch operating voltage\n");
1155 return ret;
1156 }
1157
omap_hsmmc_dma_callback(void * param)1158 static void omap_hsmmc_dma_callback(void *param)
1159 {
1160 struct omap_hsmmc_host *host = param;
1161 struct dma_chan *chan;
1162 struct mmc_data *data;
1163 int req_in_progress;
1164
1165 spin_lock_irq(&host->irq_lock);
1166 if (host->dma_ch < 0) {
1167 spin_unlock_irq(&host->irq_lock);
1168 return;
1169 }
1170
1171 data = host->mrq->data;
1172 chan = omap_hsmmc_get_dma_chan(host, data);
1173 if (!data->host_cookie)
1174 dma_unmap_sg(chan->device->dev,
1175 data->sg, data->sg_len,
1176 mmc_get_dma_dir(data));
1177
1178 req_in_progress = host->req_in_progress;
1179 host->dma_ch = -1;
1180 spin_unlock_irq(&host->irq_lock);
1181
1182 /* If DMA has finished after TC, complete the request */
1183 if (!req_in_progress) {
1184 struct mmc_request *mrq = host->mrq;
1185
1186 host->mrq = NULL;
1187 mmc_request_done(host->mmc, mrq);
1188 }
1189 }
1190
omap_hsmmc_pre_dma_transfer(struct omap_hsmmc_host * host,struct mmc_data * data,struct omap_hsmmc_next * next,struct dma_chan * chan)1191 static int omap_hsmmc_pre_dma_transfer(struct omap_hsmmc_host *host,
1192 struct mmc_data *data,
1193 struct omap_hsmmc_next *next,
1194 struct dma_chan *chan)
1195 {
1196 int dma_len;
1197
1198 if (!next && data->host_cookie &&
1199 data->host_cookie != host->next_data.cookie) {
1200 dev_warn(host->dev, "[%s] invalid cookie: data->host_cookie %d"
1201 " host->next_data.cookie %d\n",
1202 __func__, data->host_cookie, host->next_data.cookie);
1203 data->host_cookie = 0;
1204 }
1205
1206 /* Check if next job is already prepared */
1207 if (next || data->host_cookie != host->next_data.cookie) {
1208 dma_len = dma_map_sg(chan->device->dev, data->sg, data->sg_len,
1209 mmc_get_dma_dir(data));
1210
1211 } else {
1212 dma_len = host->next_data.dma_len;
1213 host->next_data.dma_len = 0;
1214 }
1215
1216
1217 if (dma_len == 0)
1218 return -EINVAL;
1219
1220 if (next) {
1221 next->dma_len = dma_len;
1222 data->host_cookie = ++next->cookie < 0 ? 1 : next->cookie;
1223 } else
1224 host->dma_len = dma_len;
1225
1226 return 0;
1227 }
1228
1229 /*
1230 * Routine to configure and start DMA for the MMC card
1231 */
omap_hsmmc_setup_dma_transfer(struct omap_hsmmc_host * host,struct mmc_request * req)1232 static int omap_hsmmc_setup_dma_transfer(struct omap_hsmmc_host *host,
1233 struct mmc_request *req)
1234 {
1235 struct dma_async_tx_descriptor *tx;
1236 int ret = 0, i;
1237 struct mmc_data *data = req->data;
1238 struct dma_chan *chan;
1239 struct dma_slave_config cfg = {
1240 .src_addr = host->mapbase + OMAP_HSMMC_DATA,
1241 .dst_addr = host->mapbase + OMAP_HSMMC_DATA,
1242 .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
1243 .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
1244 .src_maxburst = data->blksz / 4,
1245 .dst_maxburst = data->blksz / 4,
1246 };
1247
1248 /* Sanity check: all the SG entries must be aligned by block size. */
1249 for (i = 0; i < data->sg_len; i++) {
1250 struct scatterlist *sgl;
1251
1252 sgl = data->sg + i;
1253 if (sgl->length % data->blksz)
1254 return -EINVAL;
1255 }
1256 if ((data->blksz % 4) != 0)
1257 /* REVISIT: The MMC buffer increments only when MSB is written.
1258 * Return error for blksz which is non multiple of four.
1259 */
1260 return -EINVAL;
1261
1262 BUG_ON(host->dma_ch != -1);
1263
1264 chan = omap_hsmmc_get_dma_chan(host, data);
1265
1266 ret = dmaengine_slave_config(chan, &cfg);
1267 if (ret)
1268 return ret;
1269
1270 ret = omap_hsmmc_pre_dma_transfer(host, data, NULL, chan);
1271 if (ret)
1272 return ret;
1273
1274 tx = dmaengine_prep_slave_sg(chan, data->sg, data->sg_len,
1275 data->flags & MMC_DATA_WRITE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM,
1276 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1277 if (!tx) {
1278 dev_err(mmc_dev(host->mmc), "prep_slave_sg() failed\n");
1279 /* FIXME: cleanup */
1280 return -1;
1281 }
1282
1283 tx->callback = omap_hsmmc_dma_callback;
1284 tx->callback_param = host;
1285
1286 /* Does not fail */
1287 dmaengine_submit(tx);
1288
1289 host->dma_ch = 1;
1290
1291 return 0;
1292 }
1293
set_data_timeout(struct omap_hsmmc_host * host,unsigned long long timeout_ns,unsigned int timeout_clks)1294 static void set_data_timeout(struct omap_hsmmc_host *host,
1295 unsigned long long timeout_ns,
1296 unsigned int timeout_clks)
1297 {
1298 unsigned long long timeout = timeout_ns;
1299 unsigned int cycle_ns;
1300 uint32_t reg, clkd, dto = 0;
1301
1302 reg = OMAP_HSMMC_READ(host->base, SYSCTL);
1303 clkd = (reg & CLKD_MASK) >> CLKD_SHIFT;
1304 if (clkd == 0)
1305 clkd = 1;
1306
1307 cycle_ns = 1000000000 / (host->clk_rate / clkd);
1308 do_div(timeout, cycle_ns);
1309 timeout += timeout_clks;
1310 if (timeout) {
1311 while ((timeout & 0x80000000) == 0) {
1312 dto += 1;
1313 timeout <<= 1;
1314 }
1315 dto = 31 - dto;
1316 timeout <<= 1;
1317 if (timeout && dto)
1318 dto += 1;
1319 if (dto >= 13)
1320 dto -= 13;
1321 else
1322 dto = 0;
1323 if (dto > 14)
1324 dto = 14;
1325 }
1326
1327 reg &= ~DTO_MASK;
1328 reg |= dto << DTO_SHIFT;
1329 OMAP_HSMMC_WRITE(host->base, SYSCTL, reg);
1330 }
1331
omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host * host)1332 static void omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host)
1333 {
1334 struct mmc_request *req = host->mrq;
1335 struct dma_chan *chan;
1336
1337 if (!req->data)
1338 return;
1339 OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
1340 | (req->data->blocks << 16));
1341 set_data_timeout(host, req->data->timeout_ns,
1342 req->data->timeout_clks);
1343 chan = omap_hsmmc_get_dma_chan(host, req->data);
1344 dma_async_issue_pending(chan);
1345 }
1346
1347 /*
1348 * Configure block length for MMC/SD cards and initiate the transfer.
1349 */
1350 static int
omap_hsmmc_prepare_data(struct omap_hsmmc_host * host,struct mmc_request * req)1351 omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req)
1352 {
1353 int ret;
1354 unsigned long long timeout;
1355
1356 host->data = req->data;
1357
1358 if (req->data == NULL) {
1359 OMAP_HSMMC_WRITE(host->base, BLK, 0);
1360 if (req->cmd->flags & MMC_RSP_BUSY) {
1361 timeout = req->cmd->busy_timeout * NSEC_PER_MSEC;
1362
1363 /*
1364 * Set an arbitrary 100ms data timeout for commands with
1365 * busy signal and no indication of busy_timeout.
1366 */
1367 if (!timeout)
1368 timeout = 100000000U;
1369
1370 set_data_timeout(host, timeout, 0);
1371 }
1372 return 0;
1373 }
1374
1375 if (host->use_dma) {
1376 ret = omap_hsmmc_setup_dma_transfer(host, req);
1377 if (ret != 0) {
1378 dev_err(mmc_dev(host->mmc), "MMC start dma failure\n");
1379 return ret;
1380 }
1381 }
1382 return 0;
1383 }
1384
omap_hsmmc_post_req(struct mmc_host * mmc,struct mmc_request * mrq,int err)1385 static void omap_hsmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
1386 int err)
1387 {
1388 struct omap_hsmmc_host *host = mmc_priv(mmc);
1389 struct mmc_data *data = mrq->data;
1390
1391 if (host->use_dma && data->host_cookie) {
1392 struct dma_chan *c = omap_hsmmc_get_dma_chan(host, data);
1393
1394 dma_unmap_sg(c->device->dev, data->sg, data->sg_len,
1395 mmc_get_dma_dir(data));
1396 data->host_cookie = 0;
1397 }
1398 }
1399
omap_hsmmc_pre_req(struct mmc_host * mmc,struct mmc_request * mrq)1400 static void omap_hsmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq)
1401 {
1402 struct omap_hsmmc_host *host = mmc_priv(mmc);
1403
1404 if (mrq->data->host_cookie) {
1405 mrq->data->host_cookie = 0;
1406 return ;
1407 }
1408
1409 if (host->use_dma) {
1410 struct dma_chan *c = omap_hsmmc_get_dma_chan(host, mrq->data);
1411
1412 if (omap_hsmmc_pre_dma_transfer(host, mrq->data,
1413 &host->next_data, c))
1414 mrq->data->host_cookie = 0;
1415 }
1416 }
1417
1418 /*
1419 * Request function. for read/write operation
1420 */
omap_hsmmc_request(struct mmc_host * mmc,struct mmc_request * req)1421 static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req)
1422 {
1423 struct omap_hsmmc_host *host = mmc_priv(mmc);
1424 int err;
1425
1426 BUG_ON(host->req_in_progress);
1427 BUG_ON(host->dma_ch != -1);
1428 if (host->reqs_blocked)
1429 host->reqs_blocked = 0;
1430 WARN_ON(host->mrq != NULL);
1431 host->mrq = req;
1432 host->clk_rate = clk_get_rate(host->fclk);
1433 err = omap_hsmmc_prepare_data(host, req);
1434 if (err) {
1435 req->cmd->error = err;
1436 if (req->data)
1437 req->data->error = err;
1438 host->mrq = NULL;
1439 mmc_request_done(mmc, req);
1440 return;
1441 }
1442 if (req->sbc && !(host->flags & AUTO_CMD23)) {
1443 omap_hsmmc_start_command(host, req->sbc, NULL);
1444 return;
1445 }
1446
1447 omap_hsmmc_start_dma_transfer(host);
1448 omap_hsmmc_start_command(host, req->cmd, req->data);
1449 }
1450
1451 /* Routine to configure clock values. Exposed API to core */
omap_hsmmc_set_ios(struct mmc_host * mmc,struct mmc_ios * ios)1452 static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1453 {
1454 struct omap_hsmmc_host *host = mmc_priv(mmc);
1455 int do_send_init_stream = 0;
1456
1457 if (ios->power_mode != host->power_mode) {
1458 switch (ios->power_mode) {
1459 case MMC_POWER_OFF:
1460 omap_hsmmc_set_power(host, 0);
1461 break;
1462 case MMC_POWER_UP:
1463 omap_hsmmc_set_power(host, 1);
1464 break;
1465 case MMC_POWER_ON:
1466 do_send_init_stream = 1;
1467 break;
1468 }
1469 host->power_mode = ios->power_mode;
1470 }
1471
1472 /* FIXME: set registers based only on changes to ios */
1473
1474 omap_hsmmc_set_bus_width(host);
1475
1476 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
1477 /* Only MMC1 can interface at 3V without some flavor
1478 * of external transceiver; but they all handle 1.8V.
1479 */
1480 if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
1481 (ios->vdd == DUAL_VOLT_OCR_BIT)) {
1482 /*
1483 * The mmc_select_voltage fn of the core does
1484 * not seem to set the power_mode to
1485 * MMC_POWER_UP upon recalculating the voltage.
1486 * vdd 1.8v.
1487 */
1488 if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0)
1489 dev_dbg(mmc_dev(host->mmc),
1490 "Switch operation failed\n");
1491 }
1492 }
1493
1494 omap_hsmmc_set_clock(host);
1495
1496 if (do_send_init_stream)
1497 send_init_stream(host);
1498
1499 omap_hsmmc_set_bus_mode(host);
1500 }
1501
omap_hsmmc_enable_sdio_irq(struct mmc_host * mmc,int enable)1502 static void omap_hsmmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
1503 {
1504 struct omap_hsmmc_host *host = mmc_priv(mmc);
1505 u32 irq_mask, con;
1506 unsigned long flags;
1507
1508 spin_lock_irqsave(&host->irq_lock, flags);
1509
1510 con = OMAP_HSMMC_READ(host->base, CON);
1511 irq_mask = OMAP_HSMMC_READ(host->base, ISE);
1512 if (enable) {
1513 host->flags |= HSMMC_SDIO_IRQ_ENABLED;
1514 irq_mask |= CIRQ_EN;
1515 con |= CTPL | CLKEXTFREE;
1516 } else {
1517 host->flags &= ~HSMMC_SDIO_IRQ_ENABLED;
1518 irq_mask &= ~CIRQ_EN;
1519 con &= ~(CTPL | CLKEXTFREE);
1520 }
1521 OMAP_HSMMC_WRITE(host->base, CON, con);
1522 OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
1523
1524 /*
1525 * if enable, piggy back detection on current request
1526 * but always disable immediately
1527 */
1528 if (!host->req_in_progress || !enable)
1529 OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
1530
1531 /* flush posted write */
1532 OMAP_HSMMC_READ(host->base, IE);
1533
1534 spin_unlock_irqrestore(&host->irq_lock, flags);
1535 }
1536
omap_hsmmc_configure_wake_irq(struct omap_hsmmc_host * host)1537 static int omap_hsmmc_configure_wake_irq(struct omap_hsmmc_host *host)
1538 {
1539 int ret;
1540
1541 /*
1542 * For omaps with wake-up path, wakeirq will be irq from pinctrl and
1543 * for other omaps, wakeirq will be from GPIO (dat line remuxed to
1544 * gpio). wakeirq is needed to detect sdio irq in runtime suspend state
1545 * with functional clock disabled.
1546 */
1547 if (!host->dev->of_node || !host->wake_irq)
1548 return -ENODEV;
1549
1550 ret = dev_pm_set_dedicated_wake_irq(host->dev, host->wake_irq);
1551 if (ret) {
1552 dev_err(mmc_dev(host->mmc), "Unable to request wake IRQ\n");
1553 goto err;
1554 }
1555
1556 /*
1557 * Some omaps don't have wake-up path from deeper idle states
1558 * and need to remux SDIO DAT1 to GPIO for wake-up from idle.
1559 */
1560 if (host->pdata->controller_flags & OMAP_HSMMC_SWAKEUP_MISSING) {
1561 struct pinctrl *p = devm_pinctrl_get(host->dev);
1562 if (IS_ERR(p)) {
1563 ret = PTR_ERR(p);
1564 goto err_free_irq;
1565 }
1566
1567 if (IS_ERR(pinctrl_lookup_state(p, PINCTRL_STATE_IDLE))) {
1568 dev_info(host->dev, "missing idle pinctrl state\n");
1569 devm_pinctrl_put(p);
1570 ret = -EINVAL;
1571 goto err_free_irq;
1572 }
1573 devm_pinctrl_put(p);
1574 }
1575
1576 OMAP_HSMMC_WRITE(host->base, HCTL,
1577 OMAP_HSMMC_READ(host->base, HCTL) | IWE);
1578 return 0;
1579
1580 err_free_irq:
1581 dev_pm_clear_wake_irq(host->dev);
1582 err:
1583 dev_warn(host->dev, "no SDIO IRQ support, falling back to polling\n");
1584 host->wake_irq = 0;
1585 return ret;
1586 }
1587
omap_hsmmc_conf_bus_power(struct omap_hsmmc_host * host)1588 static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host)
1589 {
1590 u32 hctl, capa, value;
1591
1592 /* Only MMC1 supports 3.0V */
1593 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
1594 hctl = SDVS30;
1595 capa = VS30 | VS18;
1596 } else {
1597 hctl = SDVS18;
1598 capa = VS18;
1599 }
1600
1601 value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK;
1602 OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl);
1603
1604 value = OMAP_HSMMC_READ(host->base, CAPA);
1605 OMAP_HSMMC_WRITE(host->base, CAPA, value | capa);
1606
1607 /* Set SD bus power bit */
1608 set_sd_bus_power(host);
1609 }
1610
omap_hsmmc_multi_io_quirk(struct mmc_card * card,unsigned int direction,int blk_size)1611 static int omap_hsmmc_multi_io_quirk(struct mmc_card *card,
1612 unsigned int direction, int blk_size)
1613 {
1614 /* This controller can't do multiblock reads due to hw bugs */
1615 if (direction == MMC_DATA_READ)
1616 return 1;
1617
1618 return blk_size;
1619 }
1620
1621 static struct mmc_host_ops omap_hsmmc_ops = {
1622 .post_req = omap_hsmmc_post_req,
1623 .pre_req = omap_hsmmc_pre_req,
1624 .request = omap_hsmmc_request,
1625 .set_ios = omap_hsmmc_set_ios,
1626 .get_cd = mmc_gpio_get_cd,
1627 .get_ro = mmc_gpio_get_ro,
1628 .enable_sdio_irq = omap_hsmmc_enable_sdio_irq,
1629 };
1630
1631 #ifdef CONFIG_DEBUG_FS
1632
mmc_regs_show(struct seq_file * s,void * data)1633 static int mmc_regs_show(struct seq_file *s, void *data)
1634 {
1635 struct mmc_host *mmc = s->private;
1636 struct omap_hsmmc_host *host = mmc_priv(mmc);
1637
1638 seq_printf(s, "mmc%d:\n", mmc->index);
1639 seq_printf(s, "sdio irq mode\t%s\n",
1640 (mmc->caps & MMC_CAP_SDIO_IRQ) ? "interrupt" : "polling");
1641
1642 if (mmc->caps & MMC_CAP_SDIO_IRQ) {
1643 seq_printf(s, "sdio irq \t%s\n",
1644 (host->flags & HSMMC_SDIO_IRQ_ENABLED) ? "enabled"
1645 : "disabled");
1646 }
1647 seq_printf(s, "ctx_loss:\t%d\n", host->context_loss);
1648
1649 pm_runtime_get_sync(host->dev);
1650 seq_puts(s, "\nregs:\n");
1651 seq_printf(s, "CON:\t\t0x%08x\n",
1652 OMAP_HSMMC_READ(host->base, CON));
1653 seq_printf(s, "PSTATE:\t\t0x%08x\n",
1654 OMAP_HSMMC_READ(host->base, PSTATE));
1655 seq_printf(s, "HCTL:\t\t0x%08x\n",
1656 OMAP_HSMMC_READ(host->base, HCTL));
1657 seq_printf(s, "SYSCTL:\t\t0x%08x\n",
1658 OMAP_HSMMC_READ(host->base, SYSCTL));
1659 seq_printf(s, "IE:\t\t0x%08x\n",
1660 OMAP_HSMMC_READ(host->base, IE));
1661 seq_printf(s, "ISE:\t\t0x%08x\n",
1662 OMAP_HSMMC_READ(host->base, ISE));
1663 seq_printf(s, "CAPA:\t\t0x%08x\n",
1664 OMAP_HSMMC_READ(host->base, CAPA));
1665
1666 pm_runtime_mark_last_busy(host->dev);
1667 pm_runtime_put_autosuspend(host->dev);
1668
1669 return 0;
1670 }
1671
1672 DEFINE_SHOW_ATTRIBUTE(mmc_regs);
1673
omap_hsmmc_debugfs(struct mmc_host * mmc)1674 static void omap_hsmmc_debugfs(struct mmc_host *mmc)
1675 {
1676 if (mmc->debugfs_root)
1677 debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root,
1678 mmc, &mmc_regs_fops);
1679 }
1680
1681 #else
1682
omap_hsmmc_debugfs(struct mmc_host * mmc)1683 static void omap_hsmmc_debugfs(struct mmc_host *mmc)
1684 {
1685 }
1686
1687 #endif
1688
1689 #ifdef CONFIG_OF
1690 static const struct omap_mmc_of_data omap3_pre_es3_mmc_of_data = {
1691 /* See 35xx errata 2.1.1.128 in SPRZ278F */
1692 .controller_flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ,
1693 };
1694
1695 static const struct omap_mmc_of_data omap4_mmc_of_data = {
1696 .reg_offset = 0x100,
1697 };
1698 static const struct omap_mmc_of_data am33xx_mmc_of_data = {
1699 .reg_offset = 0x100,
1700 .controller_flags = OMAP_HSMMC_SWAKEUP_MISSING,
1701 };
1702
1703 static const struct of_device_id omap_mmc_of_match[] = {
1704 {
1705 .compatible = "ti,omap2-hsmmc",
1706 },
1707 {
1708 .compatible = "ti,omap3-pre-es3-hsmmc",
1709 .data = &omap3_pre_es3_mmc_of_data,
1710 },
1711 {
1712 .compatible = "ti,omap3-hsmmc",
1713 },
1714 {
1715 .compatible = "ti,omap4-hsmmc",
1716 .data = &omap4_mmc_of_data,
1717 },
1718 {
1719 .compatible = "ti,am33xx-hsmmc",
1720 .data = &am33xx_mmc_of_data,
1721 },
1722 {},
1723 };
1724 MODULE_DEVICE_TABLE(of, omap_mmc_of_match);
1725
of_get_hsmmc_pdata(struct device * dev)1726 static struct omap_hsmmc_platform_data *of_get_hsmmc_pdata(struct device *dev)
1727 {
1728 struct omap_hsmmc_platform_data *pdata, *legacy;
1729 struct device_node *np = dev->of_node;
1730
1731 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
1732 if (!pdata)
1733 return ERR_PTR(-ENOMEM); /* out of memory */
1734
1735 legacy = dev_get_platdata(dev);
1736 if (legacy && legacy->name)
1737 pdata->name = legacy->name;
1738
1739 if (of_property_read_bool(np, "ti,dual-volt"))
1740 pdata->controller_flags |= OMAP_HSMMC_SUPPORTS_DUAL_VOLT;
1741
1742 if (of_property_read_bool(np, "ti,non-removable")) {
1743 pdata->nonremovable = true;
1744 pdata->no_regulator_off_init = true;
1745 }
1746
1747 if (of_property_read_bool(np, "ti,needs-special-reset"))
1748 pdata->features |= HSMMC_HAS_UPDATED_RESET;
1749
1750 if (of_property_read_bool(np, "ti,needs-special-hs-handling"))
1751 pdata->features |= HSMMC_HAS_HSPE_SUPPORT;
1752
1753 return pdata;
1754 }
1755 #else
1756 static inline struct omap_hsmmc_platform_data
of_get_hsmmc_pdata(struct device * dev)1757 *of_get_hsmmc_pdata(struct device *dev)
1758 {
1759 return ERR_PTR(-EINVAL);
1760 }
1761 #endif
1762
omap_hsmmc_probe(struct platform_device * pdev)1763 static int omap_hsmmc_probe(struct platform_device *pdev)
1764 {
1765 struct omap_hsmmc_platform_data *pdata = pdev->dev.platform_data;
1766 struct mmc_host *mmc;
1767 struct omap_hsmmc_host *host = NULL;
1768 struct resource *res;
1769 int ret, irq;
1770 const struct of_device_id *match;
1771 const struct omap_mmc_of_data *data;
1772 void __iomem *base;
1773
1774 match = of_match_device(of_match_ptr(omap_mmc_of_match), &pdev->dev);
1775 if (match) {
1776 pdata = of_get_hsmmc_pdata(&pdev->dev);
1777
1778 if (IS_ERR(pdata))
1779 return PTR_ERR(pdata);
1780
1781 if (match->data) {
1782 data = match->data;
1783 pdata->reg_offset = data->reg_offset;
1784 pdata->controller_flags |= data->controller_flags;
1785 }
1786 }
1787
1788 if (pdata == NULL) {
1789 dev_err(&pdev->dev, "Platform Data is missing\n");
1790 return -ENXIO;
1791 }
1792
1793 irq = platform_get_irq(pdev, 0);
1794 if (irq < 0)
1795 return irq;
1796
1797 base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1798 if (IS_ERR(base))
1799 return PTR_ERR(base);
1800
1801 mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev);
1802 if (!mmc) {
1803 ret = -ENOMEM;
1804 goto err;
1805 }
1806
1807 ret = mmc_of_parse(mmc);
1808 if (ret)
1809 goto err1;
1810
1811 host = mmc_priv(mmc);
1812 host->mmc = mmc;
1813 host->pdata = pdata;
1814 host->dev = &pdev->dev;
1815 host->use_dma = 1;
1816 host->dma_ch = -1;
1817 host->irq = irq;
1818 host->mapbase = res->start + pdata->reg_offset;
1819 host->base = base + pdata->reg_offset;
1820 host->power_mode = MMC_POWER_OFF;
1821 host->next_data.cookie = 1;
1822 host->pbias_enabled = false;
1823 host->vqmmc_enabled = false;
1824
1825 platform_set_drvdata(pdev, host);
1826
1827 if (pdev->dev.of_node)
1828 host->wake_irq = irq_of_parse_and_map(pdev->dev.of_node, 1);
1829
1830 mmc->ops = &omap_hsmmc_ops;
1831
1832 mmc->f_min = OMAP_MMC_MIN_CLOCK;
1833
1834 if (pdata->max_freq > 0)
1835 mmc->f_max = pdata->max_freq;
1836 else if (mmc->f_max == 0)
1837 mmc->f_max = OMAP_MMC_MAX_CLOCK;
1838
1839 spin_lock_init(&host->irq_lock);
1840
1841 host->fclk = devm_clk_get(&pdev->dev, "fck");
1842 if (IS_ERR(host->fclk)) {
1843 ret = PTR_ERR(host->fclk);
1844 host->fclk = NULL;
1845 goto err1;
1846 }
1847
1848 if (host->pdata->controller_flags & OMAP_HSMMC_BROKEN_MULTIBLOCK_READ) {
1849 dev_info(&pdev->dev, "multiblock reads disabled due to 35xx erratum 2.1.1.128; MMC read performance may suffer\n");
1850 omap_hsmmc_ops.multi_io_quirk = omap_hsmmc_multi_io_quirk;
1851 }
1852
1853 device_init_wakeup(&pdev->dev, true);
1854 pm_runtime_enable(host->dev);
1855 pm_runtime_get_sync(host->dev);
1856 pm_runtime_set_autosuspend_delay(host->dev, MMC_AUTOSUSPEND_DELAY);
1857 pm_runtime_use_autosuspend(host->dev);
1858
1859 omap_hsmmc_context_save(host);
1860
1861 host->dbclk = devm_clk_get(&pdev->dev, "mmchsdb_fck");
1862 /*
1863 * MMC can still work without debounce clock.
1864 */
1865 if (IS_ERR(host->dbclk)) {
1866 host->dbclk = NULL;
1867 } else if (clk_prepare_enable(host->dbclk) != 0) {
1868 dev_warn(mmc_dev(host->mmc), "Failed to enable debounce clk\n");
1869 host->dbclk = NULL;
1870 }
1871
1872 /* Set this to a value that allows allocating an entire descriptor
1873 * list within a page (zero order allocation). */
1874 mmc->max_segs = 64;
1875
1876 mmc->max_blk_size = 512; /* Block Length at max can be 1024 */
1877 mmc->max_blk_count = 0xFFFF; /* No. of Blocks is 16 bits */
1878 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1879
1880 mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
1881 MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_CMD23;
1882
1883 mmc->caps |= mmc_pdata(host)->caps;
1884 if (mmc->caps & MMC_CAP_8_BIT_DATA)
1885 mmc->caps |= MMC_CAP_4_BIT_DATA;
1886
1887 if (mmc_pdata(host)->nonremovable)
1888 mmc->caps |= MMC_CAP_NONREMOVABLE;
1889
1890 mmc->pm_caps |= mmc_pdata(host)->pm_caps;
1891
1892 omap_hsmmc_conf_bus_power(host);
1893
1894 host->rx_chan = dma_request_chan(&pdev->dev, "rx");
1895 if (IS_ERR(host->rx_chan)) {
1896 dev_err(mmc_dev(host->mmc), "RX DMA channel request failed\n");
1897 ret = PTR_ERR(host->rx_chan);
1898 goto err_irq;
1899 }
1900
1901 host->tx_chan = dma_request_chan(&pdev->dev, "tx");
1902 if (IS_ERR(host->tx_chan)) {
1903 dev_err(mmc_dev(host->mmc), "TX DMA channel request failed\n");
1904 ret = PTR_ERR(host->tx_chan);
1905 goto err_irq;
1906 }
1907
1908 /*
1909 * Limit the maximum segment size to the lower of the request size
1910 * and the DMA engine device segment size limits. In reality, with
1911 * 32-bit transfers, the DMA engine can do longer segments than this
1912 * but there is no way to represent that in the DMA model - if we
1913 * increase this figure here, we get warnings from the DMA API debug.
1914 */
1915 mmc->max_seg_size = min3(mmc->max_req_size,
1916 dma_get_max_seg_size(host->rx_chan->device->dev),
1917 dma_get_max_seg_size(host->tx_chan->device->dev));
1918
1919 /* Request IRQ for MMC operations */
1920 ret = devm_request_irq(&pdev->dev, host->irq, omap_hsmmc_irq, 0,
1921 mmc_hostname(mmc), host);
1922 if (ret) {
1923 dev_err(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n");
1924 goto err_irq;
1925 }
1926
1927 ret = omap_hsmmc_reg_get(host);
1928 if (ret)
1929 goto err_irq;
1930
1931 if (!mmc->ocr_avail)
1932 mmc->ocr_avail = mmc_pdata(host)->ocr_mask;
1933
1934 omap_hsmmc_disable_irq(host);
1935
1936 /*
1937 * For now, only support SDIO interrupt if we have a separate
1938 * wake-up interrupt configured from device tree. This is because
1939 * the wake-up interrupt is needed for idle state and some
1940 * platforms need special quirks. And we don't want to add new
1941 * legacy mux platform init code callbacks any longer as we
1942 * are moving to DT based booting anyways.
1943 */
1944 ret = omap_hsmmc_configure_wake_irq(host);
1945 if (!ret)
1946 mmc->caps |= MMC_CAP_SDIO_IRQ;
1947
1948 ret = mmc_add_host(mmc);
1949 if (ret)
1950 goto err_irq;
1951
1952 if (mmc_pdata(host)->name != NULL) {
1953 ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name);
1954 if (ret < 0)
1955 goto err_slot_name;
1956 }
1957
1958 omap_hsmmc_debugfs(mmc);
1959 pm_runtime_mark_last_busy(host->dev);
1960 pm_runtime_put_autosuspend(host->dev);
1961
1962 return 0;
1963
1964 err_slot_name:
1965 mmc_remove_host(mmc);
1966 err_irq:
1967 device_init_wakeup(&pdev->dev, false);
1968 if (!IS_ERR_OR_NULL(host->tx_chan))
1969 dma_release_channel(host->tx_chan);
1970 if (!IS_ERR_OR_NULL(host->rx_chan))
1971 dma_release_channel(host->rx_chan);
1972 pm_runtime_dont_use_autosuspend(host->dev);
1973 pm_runtime_put_sync(host->dev);
1974 pm_runtime_disable(host->dev);
1975 clk_disable_unprepare(host->dbclk);
1976 err1:
1977 mmc_free_host(mmc);
1978 err:
1979 return ret;
1980 }
1981
omap_hsmmc_remove(struct platform_device * pdev)1982 static void omap_hsmmc_remove(struct platform_device *pdev)
1983 {
1984 struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
1985
1986 pm_runtime_get_sync(host->dev);
1987 mmc_remove_host(host->mmc);
1988
1989 dma_release_channel(host->tx_chan);
1990 dma_release_channel(host->rx_chan);
1991
1992 dev_pm_clear_wake_irq(host->dev);
1993 pm_runtime_dont_use_autosuspend(host->dev);
1994 pm_runtime_put_sync(host->dev);
1995 pm_runtime_disable(host->dev);
1996 device_init_wakeup(&pdev->dev, false);
1997 clk_disable_unprepare(host->dbclk);
1998
1999 mmc_free_host(host->mmc);
2000 }
2001
2002 #ifdef CONFIG_PM_SLEEP
omap_hsmmc_suspend(struct device * dev)2003 static int omap_hsmmc_suspend(struct device *dev)
2004 {
2005 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
2006
2007 if (!host)
2008 return 0;
2009
2010 pm_runtime_get_sync(host->dev);
2011
2012 if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER)) {
2013 OMAP_HSMMC_WRITE(host->base, ISE, 0);
2014 OMAP_HSMMC_WRITE(host->base, IE, 0);
2015 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
2016 OMAP_HSMMC_WRITE(host->base, HCTL,
2017 OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP);
2018 }
2019
2020 clk_disable_unprepare(host->dbclk);
2021
2022 pm_runtime_put_sync(host->dev);
2023 return 0;
2024 }
2025
2026 /* Routine to resume the MMC device */
omap_hsmmc_resume(struct device * dev)2027 static int omap_hsmmc_resume(struct device *dev)
2028 {
2029 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
2030
2031 if (!host)
2032 return 0;
2033
2034 pm_runtime_get_sync(host->dev);
2035
2036 clk_prepare_enable(host->dbclk);
2037
2038 if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER))
2039 omap_hsmmc_conf_bus_power(host);
2040
2041 pm_runtime_mark_last_busy(host->dev);
2042 pm_runtime_put_autosuspend(host->dev);
2043 return 0;
2044 }
2045 #endif
2046
2047 #ifdef CONFIG_PM
omap_hsmmc_runtime_suspend(struct device * dev)2048 static int omap_hsmmc_runtime_suspend(struct device *dev)
2049 {
2050 struct omap_hsmmc_host *host;
2051 unsigned long flags;
2052 int ret = 0;
2053
2054 host = dev_get_drvdata(dev);
2055 omap_hsmmc_context_save(host);
2056 dev_dbg(dev, "disabled\n");
2057
2058 spin_lock_irqsave(&host->irq_lock, flags);
2059 if ((host->mmc->caps & MMC_CAP_SDIO_IRQ) &&
2060 (host->flags & HSMMC_SDIO_IRQ_ENABLED)) {
2061 /* disable sdio irq handling to prevent race */
2062 OMAP_HSMMC_WRITE(host->base, ISE, 0);
2063 OMAP_HSMMC_WRITE(host->base, IE, 0);
2064
2065 if (!(OMAP_HSMMC_READ(host->base, PSTATE) & DLEV_DAT(1))) {
2066 /*
2067 * dat1 line low, pending sdio irq
2068 * race condition: possible irq handler running on
2069 * multi-core, abort
2070 */
2071 dev_dbg(dev, "pending sdio irq, abort suspend\n");
2072 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
2073 OMAP_HSMMC_WRITE(host->base, ISE, CIRQ_EN);
2074 OMAP_HSMMC_WRITE(host->base, IE, CIRQ_EN);
2075 pm_runtime_mark_last_busy(dev);
2076 ret = -EBUSY;
2077 goto abort;
2078 }
2079
2080 pinctrl_pm_select_idle_state(dev);
2081 } else {
2082 pinctrl_pm_select_idle_state(dev);
2083 }
2084
2085 abort:
2086 spin_unlock_irqrestore(&host->irq_lock, flags);
2087 return ret;
2088 }
2089
omap_hsmmc_runtime_resume(struct device * dev)2090 static int omap_hsmmc_runtime_resume(struct device *dev)
2091 {
2092 struct omap_hsmmc_host *host;
2093 unsigned long flags;
2094
2095 host = dev_get_drvdata(dev);
2096 omap_hsmmc_context_restore(host);
2097 dev_dbg(dev, "enabled\n");
2098
2099 spin_lock_irqsave(&host->irq_lock, flags);
2100 if ((host->mmc->caps & MMC_CAP_SDIO_IRQ) &&
2101 (host->flags & HSMMC_SDIO_IRQ_ENABLED)) {
2102
2103 pinctrl_select_default_state(host->dev);
2104
2105 /* irq lost, if pinmux incorrect */
2106 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
2107 OMAP_HSMMC_WRITE(host->base, ISE, CIRQ_EN);
2108 OMAP_HSMMC_WRITE(host->base, IE, CIRQ_EN);
2109 } else {
2110 pinctrl_select_default_state(host->dev);
2111 }
2112 spin_unlock_irqrestore(&host->irq_lock, flags);
2113 return 0;
2114 }
2115 #endif
2116
2117 static const struct dev_pm_ops omap_hsmmc_dev_pm_ops = {
2118 SET_SYSTEM_SLEEP_PM_OPS(omap_hsmmc_suspend, omap_hsmmc_resume)
2119 SET_RUNTIME_PM_OPS(omap_hsmmc_runtime_suspend, omap_hsmmc_runtime_resume, NULL)
2120 };
2121
2122 static struct platform_driver omap_hsmmc_driver = {
2123 .probe = omap_hsmmc_probe,
2124 .remove_new = omap_hsmmc_remove,
2125 .driver = {
2126 .name = DRIVER_NAME,
2127 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
2128 .pm = &omap_hsmmc_dev_pm_ops,
2129 .of_match_table = of_match_ptr(omap_mmc_of_match),
2130 },
2131 };
2132
2133 module_platform_driver(omap_hsmmc_driver);
2134 MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver");
2135 MODULE_LICENSE("GPL");
2136 MODULE_ALIAS("platform:" DRIVER_NAME);
2137 MODULE_AUTHOR("Texas Instruments Inc");
2138
