1 /*
2 * lpc_ich.c - LPC interface for Intel ICH
3 *
4 * LPC bridge function of the Intel ICH contains many other
5 * functional units, such as Interrupt controllers, Timers,
6 * Power Management, System Management, GPIO, RTC, and LPC
7 * Configuration Registers.
8 *
9 * This driver is derived from lpc_sch.
10
11 * Copyright (c) 2011 Extreme Engineering Solution, Inc.
12 * Author: Aaron Sierra <asierra@xes-inc.com>
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License 2 as published
16 * by the Free Software Foundation.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * This driver supports the following I/O Controller hubs:
24 * (See the intel documentation on http://developer.intel.com.)
25 * document number 290655-003, 290677-014: 82801AA (ICH), 82801AB (ICHO)
26 * document number 290687-002, 298242-027: 82801BA (ICH2)
27 * document number 290733-003, 290739-013: 82801CA (ICH3-S)
28 * document number 290716-001, 290718-007: 82801CAM (ICH3-M)
29 * document number 290744-001, 290745-025: 82801DB (ICH4)
30 * document number 252337-001, 252663-008: 82801DBM (ICH4-M)
31 * document number 273599-001, 273645-002: 82801E (C-ICH)
32 * document number 252516-001, 252517-028: 82801EB (ICH5), 82801ER (ICH5R)
33 * document number 300641-004, 300884-013: 6300ESB
34 * document number 301473-002, 301474-026: 82801F (ICH6)
35 * document number 313082-001, 313075-006: 631xESB, 632xESB
36 * document number 307013-003, 307014-024: 82801G (ICH7)
37 * document number 322896-001, 322897-001: NM10
38 * document number 313056-003, 313057-017: 82801H (ICH8)
39 * document number 316972-004, 316973-012: 82801I (ICH9)
40 * document number 319973-002, 319974-002: 82801J (ICH10)
41 * document number 322169-001, 322170-003: 5 Series, 3400 Series (PCH)
42 * document number 320066-003, 320257-008: EP80597 (IICH)
43 * document number 324645-001, 324646-001: Cougar Point (CPT)
44 */
45
46 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
47
48 #include <linux/kernel.h>
49 #include <linux/module.h>
50 #include <linux/errno.h>
51 #include <linux/acpi.h>
52 #include <linux/pci.h>
53 #include <linux/mfd/core.h>
54 #include <linux/mfd/lpc_ich.h>
55 #include <linux/platform_data/itco_wdt.h>
56
57 #define ACPIBASE 0x40
58 #define ACPIBASE_GPE_OFF 0x28
59 #define ACPIBASE_GPE_END 0x2f
60 #define ACPIBASE_SMI_OFF 0x30
61 #define ACPIBASE_SMI_END 0x33
62 #define ACPIBASE_PMC_OFF 0x08
63 #define ACPIBASE_PMC_END 0x0c
64 #define ACPIBASE_TCO_OFF 0x60
65 #define ACPIBASE_TCO_END 0x7f
66 #define ACPICTRL_PMCBASE 0x44
67
68 #define ACPIBASE_GCS_OFF 0x3410
69 #define ACPIBASE_GCS_END 0x3414
70
71 #define SPIBASE_BYT 0x54
72 #define SPIBASE_BYT_SZ 512
73 #define SPIBASE_BYT_EN BIT(1)
74
75 #define SPIBASE_LPT 0x3800
76 #define SPIBASE_LPT_SZ 512
77 #define BCR 0xdc
78 #define BCR_WPD BIT(0)
79
80 #define SPIBASE_APL_SZ 4096
81
82 #define GPIOBASE_ICH0 0x58
83 #define GPIOCTRL_ICH0 0x5C
84 #define GPIOBASE_ICH6 0x48
85 #define GPIOCTRL_ICH6 0x4C
86
87 #define RCBABASE 0xf0
88
89 #define wdt_io_res(i) wdt_res(0, i)
90 #define wdt_mem_res(i) wdt_res(ICH_RES_MEM_OFF, i)
91 #define wdt_res(b, i) (&wdt_ich_res[(b) + (i)])
92
93 struct lpc_ich_priv {
94 int chipset;
95
96 int abase; /* ACPI base */
97 int actrl_pbase; /* ACPI control or PMC base */
98 int gbase; /* GPIO base */
99 int gctrl; /* GPIO control */
100
101 int abase_save; /* Cached ACPI base value */
102 int actrl_pbase_save; /* Cached ACPI control or PMC base value */
103 int gctrl_save; /* Cached GPIO control value */
104 };
105
106 static struct resource wdt_ich_res[] = {
107 /* ACPI - TCO */
108 {
109 .flags = IORESOURCE_IO,
110 },
111 /* ACPI - SMI */
112 {
113 .flags = IORESOURCE_IO,
114 },
115 /* GCS or PMC */
116 {
117 .flags = IORESOURCE_MEM,
118 },
119 };
120
121 static struct resource gpio_ich_res[] = {
122 /* GPIO */
123 {
124 .flags = IORESOURCE_IO,
125 },
126 /* ACPI - GPE0 */
127 {
128 .flags = IORESOURCE_IO,
129 },
130 };
131
132 static struct resource intel_spi_res[] = {
133 {
134 .flags = IORESOURCE_MEM,
135 }
136 };
137
138 static struct mfd_cell lpc_ich_wdt_cell = {
139 .name = "iTCO_wdt",
140 .num_resources = ARRAY_SIZE(wdt_ich_res),
141 .resources = wdt_ich_res,
142 .ignore_resource_conflicts = true,
143 };
144
145 static struct mfd_cell lpc_ich_gpio_cell = {
146 .name = "gpio_ich",
147 .num_resources = ARRAY_SIZE(gpio_ich_res),
148 .resources = gpio_ich_res,
149 .ignore_resource_conflicts = true,
150 };
151
152
153 static struct mfd_cell lpc_ich_spi_cell = {
154 .name = "intel-spi",
155 .num_resources = ARRAY_SIZE(intel_spi_res),
156 .resources = intel_spi_res,
157 .ignore_resource_conflicts = true,
158 };
159
160 /* chipset related info */
161 enum lpc_chipsets {
162 LPC_ICH = 0, /* ICH */
163 LPC_ICH0, /* ICH0 */
164 LPC_ICH2, /* ICH2 */
165 LPC_ICH2M, /* ICH2-M */
166 LPC_ICH3, /* ICH3-S */
167 LPC_ICH3M, /* ICH3-M */
168 LPC_ICH4, /* ICH4 */
169 LPC_ICH4M, /* ICH4-M */
170 LPC_CICH, /* C-ICH */
171 LPC_ICH5, /* ICH5 & ICH5R */
172 LPC_6300ESB, /* 6300ESB */
173 LPC_ICH6, /* ICH6 & ICH6R */
174 LPC_ICH6M, /* ICH6-M */
175 LPC_ICH6W, /* ICH6W & ICH6RW */
176 LPC_631XESB, /* 631xESB/632xESB */
177 LPC_ICH7, /* ICH7 & ICH7R */
178 LPC_ICH7DH, /* ICH7DH */
179 LPC_ICH7M, /* ICH7-M & ICH7-U */
180 LPC_ICH7MDH, /* ICH7-M DH */
181 LPC_NM10, /* NM10 */
182 LPC_ICH8, /* ICH8 & ICH8R */
183 LPC_ICH8DH, /* ICH8DH */
184 LPC_ICH8DO, /* ICH8DO */
185 LPC_ICH8M, /* ICH8M */
186 LPC_ICH8ME, /* ICH8M-E */
187 LPC_ICH9, /* ICH9 */
188 LPC_ICH9R, /* ICH9R */
189 LPC_ICH9DH, /* ICH9DH */
190 LPC_ICH9DO, /* ICH9DO */
191 LPC_ICH9M, /* ICH9M */
192 LPC_ICH9ME, /* ICH9M-E */
193 LPC_ICH10, /* ICH10 */
194 LPC_ICH10R, /* ICH10R */
195 LPC_ICH10D, /* ICH10D */
196 LPC_ICH10DO, /* ICH10DO */
197 LPC_PCH, /* PCH Desktop Full Featured */
198 LPC_PCHM, /* PCH Mobile Full Featured */
199 LPC_P55, /* P55 */
200 LPC_PM55, /* PM55 */
201 LPC_H55, /* H55 */
202 LPC_QM57, /* QM57 */
203 LPC_H57, /* H57 */
204 LPC_HM55, /* HM55 */
205 LPC_Q57, /* Q57 */
206 LPC_HM57, /* HM57 */
207 LPC_PCHMSFF, /* PCH Mobile SFF Full Featured */
208 LPC_QS57, /* QS57 */
209 LPC_3400, /* 3400 */
210 LPC_3420, /* 3420 */
211 LPC_3450, /* 3450 */
212 LPC_EP80579, /* EP80579 */
213 LPC_CPT, /* Cougar Point */
214 LPC_CPTD, /* Cougar Point Desktop */
215 LPC_CPTM, /* Cougar Point Mobile */
216 LPC_PBG, /* Patsburg */
217 LPC_DH89XXCC, /* DH89xxCC */
218 LPC_PPT, /* Panther Point */
219 LPC_LPT, /* Lynx Point */
220 LPC_LPT_LP, /* Lynx Point-LP */
221 LPC_WBG, /* Wellsburg */
222 LPC_AVN, /* Avoton SoC */
223 LPC_BAYTRAIL, /* Bay Trail SoC */
224 LPC_COLETO, /* Coleto Creek */
225 LPC_WPT_LP, /* Wildcat Point-LP */
226 LPC_BRASWELL, /* Braswell SoC */
227 LPC_LEWISBURG, /* Lewisburg */
228 LPC_9S, /* 9 Series */
229 LPC_APL, /* Apollo Lake SoC */
230 LPC_GLK, /* Gemini Lake SoC */
231 LPC_COUGARMOUNTAIN,/* Cougar Mountain SoC*/
232 };
233
234 static struct lpc_ich_info lpc_chipset_info[] = {
235 [LPC_ICH] = {
236 .name = "ICH",
237 .iTCO_version = 1,
238 },
239 [LPC_ICH0] = {
240 .name = "ICH0",
241 .iTCO_version = 1,
242 },
243 [LPC_ICH2] = {
244 .name = "ICH2",
245 .iTCO_version = 1,
246 },
247 [LPC_ICH2M] = {
248 .name = "ICH2-M",
249 .iTCO_version = 1,
250 },
251 [LPC_ICH3] = {
252 .name = "ICH3-S",
253 .iTCO_version = 1,
254 },
255 [LPC_ICH3M] = {
256 .name = "ICH3-M",
257 .iTCO_version = 1,
258 },
259 [LPC_ICH4] = {
260 .name = "ICH4",
261 .iTCO_version = 1,
262 },
263 [LPC_ICH4M] = {
264 .name = "ICH4-M",
265 .iTCO_version = 1,
266 },
267 [LPC_CICH] = {
268 .name = "C-ICH",
269 .iTCO_version = 1,
270 },
271 [LPC_ICH5] = {
272 .name = "ICH5 or ICH5R",
273 .iTCO_version = 1,
274 },
275 [LPC_6300ESB] = {
276 .name = "6300ESB",
277 .iTCO_version = 1,
278 },
279 [LPC_ICH6] = {
280 .name = "ICH6 or ICH6R",
281 .iTCO_version = 2,
282 .gpio_version = ICH_V6_GPIO,
283 },
284 [LPC_ICH6M] = {
285 .name = "ICH6-M",
286 .iTCO_version = 2,
287 .gpio_version = ICH_V6_GPIO,
288 },
289 [LPC_ICH6W] = {
290 .name = "ICH6W or ICH6RW",
291 .iTCO_version = 2,
292 .gpio_version = ICH_V6_GPIO,
293 },
294 [LPC_631XESB] = {
295 .name = "631xESB/632xESB",
296 .iTCO_version = 2,
297 .gpio_version = ICH_V6_GPIO,
298 },
299 [LPC_ICH7] = {
300 .name = "ICH7 or ICH7R",
301 .iTCO_version = 2,
302 .gpio_version = ICH_V7_GPIO,
303 },
304 [LPC_ICH7DH] = {
305 .name = "ICH7DH",
306 .iTCO_version = 2,
307 .gpio_version = ICH_V7_GPIO,
308 },
309 [LPC_ICH7M] = {
310 .name = "ICH7-M or ICH7-U",
311 .iTCO_version = 2,
312 .gpio_version = ICH_V7_GPIO,
313 },
314 [LPC_ICH7MDH] = {
315 .name = "ICH7-M DH",
316 .iTCO_version = 2,
317 .gpio_version = ICH_V7_GPIO,
318 },
319 [LPC_NM10] = {
320 .name = "NM10",
321 .iTCO_version = 2,
322 .gpio_version = ICH_V7_GPIO,
323 },
324 [LPC_ICH8] = {
325 .name = "ICH8 or ICH8R",
326 .iTCO_version = 2,
327 .gpio_version = ICH_V7_GPIO,
328 },
329 [LPC_ICH8DH] = {
330 .name = "ICH8DH",
331 .iTCO_version = 2,
332 .gpio_version = ICH_V7_GPIO,
333 },
334 [LPC_ICH8DO] = {
335 .name = "ICH8DO",
336 .iTCO_version = 2,
337 .gpio_version = ICH_V7_GPIO,
338 },
339 [LPC_ICH8M] = {
340 .name = "ICH8M",
341 .iTCO_version = 2,
342 .gpio_version = ICH_V7_GPIO,
343 },
344 [LPC_ICH8ME] = {
345 .name = "ICH8M-E",
346 .iTCO_version = 2,
347 .gpio_version = ICH_V7_GPIO,
348 },
349 [LPC_ICH9] = {
350 .name = "ICH9",
351 .iTCO_version = 2,
352 .gpio_version = ICH_V9_GPIO,
353 },
354 [LPC_ICH9R] = {
355 .name = "ICH9R",
356 .iTCO_version = 2,
357 .gpio_version = ICH_V9_GPIO,
358 },
359 [LPC_ICH9DH] = {
360 .name = "ICH9DH",
361 .iTCO_version = 2,
362 .gpio_version = ICH_V9_GPIO,
363 },
364 [LPC_ICH9DO] = {
365 .name = "ICH9DO",
366 .iTCO_version = 2,
367 .gpio_version = ICH_V9_GPIO,
368 },
369 [LPC_ICH9M] = {
370 .name = "ICH9M",
371 .iTCO_version = 2,
372 .gpio_version = ICH_V9_GPIO,
373 },
374 [LPC_ICH9ME] = {
375 .name = "ICH9M-E",
376 .iTCO_version = 2,
377 .gpio_version = ICH_V9_GPIO,
378 },
379 [LPC_ICH10] = {
380 .name = "ICH10",
381 .iTCO_version = 2,
382 .gpio_version = ICH_V10CONS_GPIO,
383 },
384 [LPC_ICH10R] = {
385 .name = "ICH10R",
386 .iTCO_version = 2,
387 .gpio_version = ICH_V10CONS_GPIO,
388 },
389 [LPC_ICH10D] = {
390 .name = "ICH10D",
391 .iTCO_version = 2,
392 .gpio_version = ICH_V10CORP_GPIO,
393 },
394 [LPC_ICH10DO] = {
395 .name = "ICH10DO",
396 .iTCO_version = 2,
397 .gpio_version = ICH_V10CORP_GPIO,
398 },
399 [LPC_PCH] = {
400 .name = "PCH Desktop Full Featured",
401 .iTCO_version = 2,
402 .gpio_version = ICH_V5_GPIO,
403 },
404 [LPC_PCHM] = {
405 .name = "PCH Mobile Full Featured",
406 .iTCO_version = 2,
407 .gpio_version = ICH_V5_GPIO,
408 },
409 [LPC_P55] = {
410 .name = "P55",
411 .iTCO_version = 2,
412 .gpio_version = ICH_V5_GPIO,
413 },
414 [LPC_PM55] = {
415 .name = "PM55",
416 .iTCO_version = 2,
417 .gpio_version = ICH_V5_GPIO,
418 },
419 [LPC_H55] = {
420 .name = "H55",
421 .iTCO_version = 2,
422 .gpio_version = ICH_V5_GPIO,
423 },
424 [LPC_QM57] = {
425 .name = "QM57",
426 .iTCO_version = 2,
427 .gpio_version = ICH_V5_GPIO,
428 },
429 [LPC_H57] = {
430 .name = "H57",
431 .iTCO_version = 2,
432 .gpio_version = ICH_V5_GPIO,
433 },
434 [LPC_HM55] = {
435 .name = "HM55",
436 .iTCO_version = 2,
437 .gpio_version = ICH_V5_GPIO,
438 },
439 [LPC_Q57] = {
440 .name = "Q57",
441 .iTCO_version = 2,
442 .gpio_version = ICH_V5_GPIO,
443 },
444 [LPC_HM57] = {
445 .name = "HM57",
446 .iTCO_version = 2,
447 .gpio_version = ICH_V5_GPIO,
448 },
449 [LPC_PCHMSFF] = {
450 .name = "PCH Mobile SFF Full Featured",
451 .iTCO_version = 2,
452 .gpio_version = ICH_V5_GPIO,
453 },
454 [LPC_QS57] = {
455 .name = "QS57",
456 .iTCO_version = 2,
457 .gpio_version = ICH_V5_GPIO,
458 },
459 [LPC_3400] = {
460 .name = "3400",
461 .iTCO_version = 2,
462 .gpio_version = ICH_V5_GPIO,
463 },
464 [LPC_3420] = {
465 .name = "3420",
466 .iTCO_version = 2,
467 .gpio_version = ICH_V5_GPIO,
468 },
469 [LPC_3450] = {
470 .name = "3450",
471 .iTCO_version = 2,
472 .gpio_version = ICH_V5_GPIO,
473 },
474 [LPC_EP80579] = {
475 .name = "EP80579",
476 .iTCO_version = 2,
477 },
478 [LPC_CPT] = {
479 .name = "Cougar Point",
480 .iTCO_version = 2,
481 .gpio_version = ICH_V5_GPIO,
482 },
483 [LPC_CPTD] = {
484 .name = "Cougar Point Desktop",
485 .iTCO_version = 2,
486 .gpio_version = ICH_V5_GPIO,
487 },
488 [LPC_CPTM] = {
489 .name = "Cougar Point Mobile",
490 .iTCO_version = 2,
491 .gpio_version = ICH_V5_GPIO,
492 },
493 [LPC_PBG] = {
494 .name = "Patsburg",
495 .iTCO_version = 2,
496 },
497 [LPC_DH89XXCC] = {
498 .name = "DH89xxCC",
499 .iTCO_version = 2,
500 },
501 [LPC_PPT] = {
502 .name = "Panther Point",
503 .iTCO_version = 2,
504 .gpio_version = ICH_V5_GPIO,
505 },
506 [LPC_LPT] = {
507 .name = "Lynx Point",
508 .iTCO_version = 2,
509 .gpio_version = ICH_V5_GPIO,
510 .spi_type = INTEL_SPI_LPT,
511 },
512 [LPC_LPT_LP] = {
513 .name = "Lynx Point_LP",
514 .iTCO_version = 2,
515 .spi_type = INTEL_SPI_LPT,
516 },
517 [LPC_WBG] = {
518 .name = "Wellsburg",
519 .iTCO_version = 2,
520 },
521 [LPC_AVN] = {
522 .name = "Avoton SoC",
523 .iTCO_version = 3,
524 .gpio_version = AVOTON_GPIO,
525 .spi_type = INTEL_SPI_BYT,
526 },
527 [LPC_BAYTRAIL] = {
528 .name = "Bay Trail SoC",
529 .iTCO_version = 3,
530 .spi_type = INTEL_SPI_BYT,
531 },
532 [LPC_COLETO] = {
533 .name = "Coleto Creek",
534 .iTCO_version = 2,
535 },
536 [LPC_WPT_LP] = {
537 .name = "Wildcat Point_LP",
538 .iTCO_version = 2,
539 .spi_type = INTEL_SPI_LPT,
540 },
541 [LPC_BRASWELL] = {
542 .name = "Braswell SoC",
543 .iTCO_version = 3,
544 .spi_type = INTEL_SPI_BYT,
545 },
546 [LPC_LEWISBURG] = {
547 .name = "Lewisburg",
548 .iTCO_version = 2,
549 },
550 [LPC_9S] = {
551 .name = "9 Series",
552 .iTCO_version = 2,
553 .gpio_version = ICH_V5_GPIO,
554 },
555 [LPC_APL] = {
556 .name = "Apollo Lake SoC",
557 .iTCO_version = 5,
558 .spi_type = INTEL_SPI_BXT,
559 },
560 [LPC_GLK] = {
561 .name = "Gemini Lake SoC",
562 .spi_type = INTEL_SPI_BXT,
563 },
564 [LPC_COUGARMOUNTAIN] = {
565 .name = "Cougar Mountain SoC",
566 .iTCO_version = 3,
567 },
568 };
569
570 /*
571 * This data only exists for exporting the supported PCI ids
572 * via MODULE_DEVICE_TABLE. We do not actually register a
573 * pci_driver, because the I/O Controller Hub has also other
574 * functions that probably will be registered by other drivers.
575 */
576 static const struct pci_device_id lpc_ich_ids[] = {
577 { PCI_VDEVICE(INTEL, 0x0f1c), LPC_BAYTRAIL},
578 { PCI_VDEVICE(INTEL, 0x1c41), LPC_CPT},
579 { PCI_VDEVICE(INTEL, 0x1c42), LPC_CPTD},
580 { PCI_VDEVICE(INTEL, 0x1c43), LPC_CPTM},
581 { PCI_VDEVICE(INTEL, 0x1c44), LPC_CPT},
582 { PCI_VDEVICE(INTEL, 0x1c45), LPC_CPT},
583 { PCI_VDEVICE(INTEL, 0x1c46), LPC_CPT},
584 { PCI_VDEVICE(INTEL, 0x1c47), LPC_CPT},
585 { PCI_VDEVICE(INTEL, 0x1c48), LPC_CPT},
586 { PCI_VDEVICE(INTEL, 0x1c49), LPC_CPT},
587 { PCI_VDEVICE(INTEL, 0x1c4a), LPC_CPT},
588 { PCI_VDEVICE(INTEL, 0x1c4b), LPC_CPT},
589 { PCI_VDEVICE(INTEL, 0x1c4c), LPC_CPT},
590 { PCI_VDEVICE(INTEL, 0x1c4d), LPC_CPT},
591 { PCI_VDEVICE(INTEL, 0x1c4e), LPC_CPT},
592 { PCI_VDEVICE(INTEL, 0x1c4f), LPC_CPT},
593 { PCI_VDEVICE(INTEL, 0x1c50), LPC_CPT},
594 { PCI_VDEVICE(INTEL, 0x1c51), LPC_CPT},
595 { PCI_VDEVICE(INTEL, 0x1c52), LPC_CPT},
596 { PCI_VDEVICE(INTEL, 0x1c53), LPC_CPT},
597 { PCI_VDEVICE(INTEL, 0x1c54), LPC_CPT},
598 { PCI_VDEVICE(INTEL, 0x1c55), LPC_CPT},
599 { PCI_VDEVICE(INTEL, 0x1c56), LPC_CPT},
600 { PCI_VDEVICE(INTEL, 0x1c57), LPC_CPT},
601 { PCI_VDEVICE(INTEL, 0x1c58), LPC_CPT},
602 { PCI_VDEVICE(INTEL, 0x1c59), LPC_CPT},
603 { PCI_VDEVICE(INTEL, 0x1c5a), LPC_CPT},
604 { PCI_VDEVICE(INTEL, 0x1c5b), LPC_CPT},
605 { PCI_VDEVICE(INTEL, 0x1c5c), LPC_CPT},
606 { PCI_VDEVICE(INTEL, 0x1c5d), LPC_CPT},
607 { PCI_VDEVICE(INTEL, 0x1c5e), LPC_CPT},
608 { PCI_VDEVICE(INTEL, 0x1c5f), LPC_CPT},
609 { PCI_VDEVICE(INTEL, 0x1d40), LPC_PBG},
610 { PCI_VDEVICE(INTEL, 0x1d41), LPC_PBG},
611 { PCI_VDEVICE(INTEL, 0x1e40), LPC_PPT},
612 { PCI_VDEVICE(INTEL, 0x1e41), LPC_PPT},
613 { PCI_VDEVICE(INTEL, 0x1e42), LPC_PPT},
614 { PCI_VDEVICE(INTEL, 0x1e43), LPC_PPT},
615 { PCI_VDEVICE(INTEL, 0x1e44), LPC_PPT},
616 { PCI_VDEVICE(INTEL, 0x1e45), LPC_PPT},
617 { PCI_VDEVICE(INTEL, 0x1e46), LPC_PPT},
618 { PCI_VDEVICE(INTEL, 0x1e47), LPC_PPT},
619 { PCI_VDEVICE(INTEL, 0x1e48), LPC_PPT},
620 { PCI_VDEVICE(INTEL, 0x1e49), LPC_PPT},
621 { PCI_VDEVICE(INTEL, 0x1e4a), LPC_PPT},
622 { PCI_VDEVICE(INTEL, 0x1e4b), LPC_PPT},
623 { PCI_VDEVICE(INTEL, 0x1e4c), LPC_PPT},
624 { PCI_VDEVICE(INTEL, 0x1e4d), LPC_PPT},
625 { PCI_VDEVICE(INTEL, 0x1e4e), LPC_PPT},
626 { PCI_VDEVICE(INTEL, 0x1e4f), LPC_PPT},
627 { PCI_VDEVICE(INTEL, 0x1e50), LPC_PPT},
628 { PCI_VDEVICE(INTEL, 0x1e51), LPC_PPT},
629 { PCI_VDEVICE(INTEL, 0x1e52), LPC_PPT},
630 { PCI_VDEVICE(INTEL, 0x1e53), LPC_PPT},
631 { PCI_VDEVICE(INTEL, 0x1e54), LPC_PPT},
632 { PCI_VDEVICE(INTEL, 0x1e55), LPC_PPT},
633 { PCI_VDEVICE(INTEL, 0x1e56), LPC_PPT},
634 { PCI_VDEVICE(INTEL, 0x1e57), LPC_PPT},
635 { PCI_VDEVICE(INTEL, 0x1e58), LPC_PPT},
636 { PCI_VDEVICE(INTEL, 0x1e59), LPC_PPT},
637 { PCI_VDEVICE(INTEL, 0x1e5a), LPC_PPT},
638 { PCI_VDEVICE(INTEL, 0x1e5b), LPC_PPT},
639 { PCI_VDEVICE(INTEL, 0x1e5c), LPC_PPT},
640 { PCI_VDEVICE(INTEL, 0x1e5d), LPC_PPT},
641 { PCI_VDEVICE(INTEL, 0x1e5e), LPC_PPT},
642 { PCI_VDEVICE(INTEL, 0x1e5f), LPC_PPT},
643 { PCI_VDEVICE(INTEL, 0x1f38), LPC_AVN},
644 { PCI_VDEVICE(INTEL, 0x1f39), LPC_AVN},
645 { PCI_VDEVICE(INTEL, 0x1f3a), LPC_AVN},
646 { PCI_VDEVICE(INTEL, 0x1f3b), LPC_AVN},
647 { PCI_VDEVICE(INTEL, 0x229c), LPC_BRASWELL},
648 { PCI_VDEVICE(INTEL, 0x2310), LPC_DH89XXCC},
649 { PCI_VDEVICE(INTEL, 0x2390), LPC_COLETO},
650 { PCI_VDEVICE(INTEL, 0x2410), LPC_ICH},
651 { PCI_VDEVICE(INTEL, 0x2420), LPC_ICH0},
652 { PCI_VDEVICE(INTEL, 0x2440), LPC_ICH2},
653 { PCI_VDEVICE(INTEL, 0x244c), LPC_ICH2M},
654 { PCI_VDEVICE(INTEL, 0x2450), LPC_CICH},
655 { PCI_VDEVICE(INTEL, 0x2480), LPC_ICH3},
656 { PCI_VDEVICE(INTEL, 0x248c), LPC_ICH3M},
657 { PCI_VDEVICE(INTEL, 0x24c0), LPC_ICH4},
658 { PCI_VDEVICE(INTEL, 0x24cc), LPC_ICH4M},
659 { PCI_VDEVICE(INTEL, 0x24d0), LPC_ICH5},
660 { PCI_VDEVICE(INTEL, 0x25a1), LPC_6300ESB},
661 { PCI_VDEVICE(INTEL, 0x2640), LPC_ICH6},
662 { PCI_VDEVICE(INTEL, 0x2641), LPC_ICH6M},
663 { PCI_VDEVICE(INTEL, 0x2642), LPC_ICH6W},
664 { PCI_VDEVICE(INTEL, 0x2670), LPC_631XESB},
665 { PCI_VDEVICE(INTEL, 0x2671), LPC_631XESB},
666 { PCI_VDEVICE(INTEL, 0x2672), LPC_631XESB},
667 { PCI_VDEVICE(INTEL, 0x2673), LPC_631XESB},
668 { PCI_VDEVICE(INTEL, 0x2674), LPC_631XESB},
669 { PCI_VDEVICE(INTEL, 0x2675), LPC_631XESB},
670 { PCI_VDEVICE(INTEL, 0x2676), LPC_631XESB},
671 { PCI_VDEVICE(INTEL, 0x2677), LPC_631XESB},
672 { PCI_VDEVICE(INTEL, 0x2678), LPC_631XESB},
673 { PCI_VDEVICE(INTEL, 0x2679), LPC_631XESB},
674 { PCI_VDEVICE(INTEL, 0x267a), LPC_631XESB},
675 { PCI_VDEVICE(INTEL, 0x267b), LPC_631XESB},
676 { PCI_VDEVICE(INTEL, 0x267c), LPC_631XESB},
677 { PCI_VDEVICE(INTEL, 0x267d), LPC_631XESB},
678 { PCI_VDEVICE(INTEL, 0x267e), LPC_631XESB},
679 { PCI_VDEVICE(INTEL, 0x267f), LPC_631XESB},
680 { PCI_VDEVICE(INTEL, 0x27b0), LPC_ICH7DH},
681 { PCI_VDEVICE(INTEL, 0x27b8), LPC_ICH7},
682 { PCI_VDEVICE(INTEL, 0x27b9), LPC_ICH7M},
683 { PCI_VDEVICE(INTEL, 0x27bc), LPC_NM10},
684 { PCI_VDEVICE(INTEL, 0x27bd), LPC_ICH7MDH},
685 { PCI_VDEVICE(INTEL, 0x2810), LPC_ICH8},
686 { PCI_VDEVICE(INTEL, 0x2811), LPC_ICH8ME},
687 { PCI_VDEVICE(INTEL, 0x2812), LPC_ICH8DH},
688 { PCI_VDEVICE(INTEL, 0x2814), LPC_ICH8DO},
689 { PCI_VDEVICE(INTEL, 0x2815), LPC_ICH8M},
690 { PCI_VDEVICE(INTEL, 0x2912), LPC_ICH9DH},
691 { PCI_VDEVICE(INTEL, 0x2914), LPC_ICH9DO},
692 { PCI_VDEVICE(INTEL, 0x2916), LPC_ICH9R},
693 { PCI_VDEVICE(INTEL, 0x2917), LPC_ICH9ME},
694 { PCI_VDEVICE(INTEL, 0x2918), LPC_ICH9},
695 { PCI_VDEVICE(INTEL, 0x2919), LPC_ICH9M},
696 { PCI_VDEVICE(INTEL, 0x3197), LPC_GLK},
697 { PCI_VDEVICE(INTEL, 0x2b9c), LPC_COUGARMOUNTAIN},
698 { PCI_VDEVICE(INTEL, 0x3a14), LPC_ICH10DO},
699 { PCI_VDEVICE(INTEL, 0x3a16), LPC_ICH10R},
700 { PCI_VDEVICE(INTEL, 0x3a18), LPC_ICH10},
701 { PCI_VDEVICE(INTEL, 0x3a1a), LPC_ICH10D},
702 { PCI_VDEVICE(INTEL, 0x3b00), LPC_PCH},
703 { PCI_VDEVICE(INTEL, 0x3b01), LPC_PCHM},
704 { PCI_VDEVICE(INTEL, 0x3b02), LPC_P55},
705 { PCI_VDEVICE(INTEL, 0x3b03), LPC_PM55},
706 { PCI_VDEVICE(INTEL, 0x3b06), LPC_H55},
707 { PCI_VDEVICE(INTEL, 0x3b07), LPC_QM57},
708 { PCI_VDEVICE(INTEL, 0x3b08), LPC_H57},
709 { PCI_VDEVICE(INTEL, 0x3b09), LPC_HM55},
710 { PCI_VDEVICE(INTEL, 0x3b0a), LPC_Q57},
711 { PCI_VDEVICE(INTEL, 0x3b0b), LPC_HM57},
712 { PCI_VDEVICE(INTEL, 0x3b0d), LPC_PCHMSFF},
713 { PCI_VDEVICE(INTEL, 0x3b0f), LPC_QS57},
714 { PCI_VDEVICE(INTEL, 0x3b12), LPC_3400},
715 { PCI_VDEVICE(INTEL, 0x3b14), LPC_3420},
716 { PCI_VDEVICE(INTEL, 0x3b16), LPC_3450},
717 { PCI_VDEVICE(INTEL, 0x5031), LPC_EP80579},
718 { PCI_VDEVICE(INTEL, 0x5ae8), LPC_APL},
719 { PCI_VDEVICE(INTEL, 0x8c40), LPC_LPT},
720 { PCI_VDEVICE(INTEL, 0x8c41), LPC_LPT},
721 { PCI_VDEVICE(INTEL, 0x8c42), LPC_LPT},
722 { PCI_VDEVICE(INTEL, 0x8c43), LPC_LPT},
723 { PCI_VDEVICE(INTEL, 0x8c44), LPC_LPT},
724 { PCI_VDEVICE(INTEL, 0x8c45), LPC_LPT},
725 { PCI_VDEVICE(INTEL, 0x8c46), LPC_LPT},
726 { PCI_VDEVICE(INTEL, 0x8c47), LPC_LPT},
727 { PCI_VDEVICE(INTEL, 0x8c48), LPC_LPT},
728 { PCI_VDEVICE(INTEL, 0x8c49), LPC_LPT},
729 { PCI_VDEVICE(INTEL, 0x8c4a), LPC_LPT},
730 { PCI_VDEVICE(INTEL, 0x8c4b), LPC_LPT},
731 { PCI_VDEVICE(INTEL, 0x8c4c), LPC_LPT},
732 { PCI_VDEVICE(INTEL, 0x8c4d), LPC_LPT},
733 { PCI_VDEVICE(INTEL, 0x8c4e), LPC_LPT},
734 { PCI_VDEVICE(INTEL, 0x8c4f), LPC_LPT},
735 { PCI_VDEVICE(INTEL, 0x8c50), LPC_LPT},
736 { PCI_VDEVICE(INTEL, 0x8c51), LPC_LPT},
737 { PCI_VDEVICE(INTEL, 0x8c52), LPC_LPT},
738 { PCI_VDEVICE(INTEL, 0x8c53), LPC_LPT},
739 { PCI_VDEVICE(INTEL, 0x8c54), LPC_LPT},
740 { PCI_VDEVICE(INTEL, 0x8c55), LPC_LPT},
741 { PCI_VDEVICE(INTEL, 0x8c56), LPC_LPT},
742 { PCI_VDEVICE(INTEL, 0x8c57), LPC_LPT},
743 { PCI_VDEVICE(INTEL, 0x8c58), LPC_LPT},
744 { PCI_VDEVICE(INTEL, 0x8c59), LPC_LPT},
745 { PCI_VDEVICE(INTEL, 0x8c5a), LPC_LPT},
746 { PCI_VDEVICE(INTEL, 0x8c5b), LPC_LPT},
747 { PCI_VDEVICE(INTEL, 0x8c5c), LPC_LPT},
748 { PCI_VDEVICE(INTEL, 0x8c5d), LPC_LPT},
749 { PCI_VDEVICE(INTEL, 0x8c5e), LPC_LPT},
750 { PCI_VDEVICE(INTEL, 0x8c5f), LPC_LPT},
751 { PCI_VDEVICE(INTEL, 0x8cc1), LPC_9S},
752 { PCI_VDEVICE(INTEL, 0x8cc2), LPC_9S},
753 { PCI_VDEVICE(INTEL, 0x8cc3), LPC_9S},
754 { PCI_VDEVICE(INTEL, 0x8cc4), LPC_9S},
755 { PCI_VDEVICE(INTEL, 0x8cc6), LPC_9S},
756 { PCI_VDEVICE(INTEL, 0x8d40), LPC_WBG},
757 { PCI_VDEVICE(INTEL, 0x8d41), LPC_WBG},
758 { PCI_VDEVICE(INTEL, 0x8d42), LPC_WBG},
759 { PCI_VDEVICE(INTEL, 0x8d43), LPC_WBG},
760 { PCI_VDEVICE(INTEL, 0x8d44), LPC_WBG},
761 { PCI_VDEVICE(INTEL, 0x8d45), LPC_WBG},
762 { PCI_VDEVICE(INTEL, 0x8d46), LPC_WBG},
763 { PCI_VDEVICE(INTEL, 0x8d47), LPC_WBG},
764 { PCI_VDEVICE(INTEL, 0x8d48), LPC_WBG},
765 { PCI_VDEVICE(INTEL, 0x8d49), LPC_WBG},
766 { PCI_VDEVICE(INTEL, 0x8d4a), LPC_WBG},
767 { PCI_VDEVICE(INTEL, 0x8d4b), LPC_WBG},
768 { PCI_VDEVICE(INTEL, 0x8d4c), LPC_WBG},
769 { PCI_VDEVICE(INTEL, 0x8d4d), LPC_WBG},
770 { PCI_VDEVICE(INTEL, 0x8d4e), LPC_WBG},
771 { PCI_VDEVICE(INTEL, 0x8d4f), LPC_WBG},
772 { PCI_VDEVICE(INTEL, 0x8d50), LPC_WBG},
773 { PCI_VDEVICE(INTEL, 0x8d51), LPC_WBG},
774 { PCI_VDEVICE(INTEL, 0x8d52), LPC_WBG},
775 { PCI_VDEVICE(INTEL, 0x8d53), LPC_WBG},
776 { PCI_VDEVICE(INTEL, 0x8d54), LPC_WBG},
777 { PCI_VDEVICE(INTEL, 0x8d55), LPC_WBG},
778 { PCI_VDEVICE(INTEL, 0x8d56), LPC_WBG},
779 { PCI_VDEVICE(INTEL, 0x8d57), LPC_WBG},
780 { PCI_VDEVICE(INTEL, 0x8d58), LPC_WBG},
781 { PCI_VDEVICE(INTEL, 0x8d59), LPC_WBG},
782 { PCI_VDEVICE(INTEL, 0x8d5a), LPC_WBG},
783 { PCI_VDEVICE(INTEL, 0x8d5b), LPC_WBG},
784 { PCI_VDEVICE(INTEL, 0x8d5c), LPC_WBG},
785 { PCI_VDEVICE(INTEL, 0x8d5d), LPC_WBG},
786 { PCI_VDEVICE(INTEL, 0x8d5e), LPC_WBG},
787 { PCI_VDEVICE(INTEL, 0x8d5f), LPC_WBG},
788 { PCI_VDEVICE(INTEL, 0x9c40), LPC_LPT_LP},
789 { PCI_VDEVICE(INTEL, 0x9c41), LPC_LPT_LP},
790 { PCI_VDEVICE(INTEL, 0x9c42), LPC_LPT_LP},
791 { PCI_VDEVICE(INTEL, 0x9c43), LPC_LPT_LP},
792 { PCI_VDEVICE(INTEL, 0x9c44), LPC_LPT_LP},
793 { PCI_VDEVICE(INTEL, 0x9c45), LPC_LPT_LP},
794 { PCI_VDEVICE(INTEL, 0x9c46), LPC_LPT_LP},
795 { PCI_VDEVICE(INTEL, 0x9c47), LPC_LPT_LP},
796 { PCI_VDEVICE(INTEL, 0x9cc1), LPC_WPT_LP},
797 { PCI_VDEVICE(INTEL, 0x9cc2), LPC_WPT_LP},
798 { PCI_VDEVICE(INTEL, 0x9cc3), LPC_WPT_LP},
799 { PCI_VDEVICE(INTEL, 0x9cc5), LPC_WPT_LP},
800 { PCI_VDEVICE(INTEL, 0x9cc6), LPC_WPT_LP},
801 { PCI_VDEVICE(INTEL, 0x9cc7), LPC_WPT_LP},
802 { PCI_VDEVICE(INTEL, 0x9cc9), LPC_WPT_LP},
803 { PCI_VDEVICE(INTEL, 0xa1c1), LPC_LEWISBURG},
804 { PCI_VDEVICE(INTEL, 0xa1c2), LPC_LEWISBURG},
805 { PCI_VDEVICE(INTEL, 0xa1c3), LPC_LEWISBURG},
806 { PCI_VDEVICE(INTEL, 0xa1c4), LPC_LEWISBURG},
807 { PCI_VDEVICE(INTEL, 0xa1c5), LPC_LEWISBURG},
808 { PCI_VDEVICE(INTEL, 0xa1c6), LPC_LEWISBURG},
809 { PCI_VDEVICE(INTEL, 0xa1c7), LPC_LEWISBURG},
810 { PCI_VDEVICE(INTEL, 0xa242), LPC_LEWISBURG},
811 { PCI_VDEVICE(INTEL, 0xa243), LPC_LEWISBURG},
812 { 0, }, /* End of list */
813 };
814 MODULE_DEVICE_TABLE(pci, lpc_ich_ids);
815
lpc_ich_restore_config_space(struct pci_dev * dev)816 static void lpc_ich_restore_config_space(struct pci_dev *dev)
817 {
818 struct lpc_ich_priv *priv = pci_get_drvdata(dev);
819
820 if (priv->abase_save >= 0) {
821 pci_write_config_byte(dev, priv->abase, priv->abase_save);
822 priv->abase_save = -1;
823 }
824
825 if (priv->actrl_pbase_save >= 0) {
826 pci_write_config_byte(dev, priv->actrl_pbase,
827 priv->actrl_pbase_save);
828 priv->actrl_pbase_save = -1;
829 }
830
831 if (priv->gctrl_save >= 0) {
832 pci_write_config_byte(dev, priv->gctrl, priv->gctrl_save);
833 priv->gctrl_save = -1;
834 }
835 }
836
lpc_ich_enable_acpi_space(struct pci_dev * dev)837 static void lpc_ich_enable_acpi_space(struct pci_dev *dev)
838 {
839 struct lpc_ich_priv *priv = pci_get_drvdata(dev);
840 u8 reg_save;
841
842 switch (lpc_chipset_info[priv->chipset].iTCO_version) {
843 case 3:
844 /*
845 * Some chipsets (eg Avoton) enable the ACPI space in the
846 * ACPI BASE register.
847 */
848 pci_read_config_byte(dev, priv->abase, ®_save);
849 pci_write_config_byte(dev, priv->abase, reg_save | 0x2);
850 priv->abase_save = reg_save;
851 break;
852 default:
853 /*
854 * Most chipsets enable the ACPI space in the ACPI control
855 * register.
856 */
857 pci_read_config_byte(dev, priv->actrl_pbase, ®_save);
858 pci_write_config_byte(dev, priv->actrl_pbase, reg_save | 0x80);
859 priv->actrl_pbase_save = reg_save;
860 break;
861 }
862 }
863
lpc_ich_enable_gpio_space(struct pci_dev * dev)864 static void lpc_ich_enable_gpio_space(struct pci_dev *dev)
865 {
866 struct lpc_ich_priv *priv = pci_get_drvdata(dev);
867 u8 reg_save;
868
869 pci_read_config_byte(dev, priv->gctrl, ®_save);
870 pci_write_config_byte(dev, priv->gctrl, reg_save | 0x10);
871 priv->gctrl_save = reg_save;
872 }
873
lpc_ich_enable_pmc_space(struct pci_dev * dev)874 static void lpc_ich_enable_pmc_space(struct pci_dev *dev)
875 {
876 struct lpc_ich_priv *priv = pci_get_drvdata(dev);
877 u8 reg_save;
878
879 pci_read_config_byte(dev, priv->actrl_pbase, ®_save);
880 pci_write_config_byte(dev, priv->actrl_pbase, reg_save | 0x2);
881
882 priv->actrl_pbase_save = reg_save;
883 }
884
lpc_ich_finalize_wdt_cell(struct pci_dev * dev)885 static int lpc_ich_finalize_wdt_cell(struct pci_dev *dev)
886 {
887 struct itco_wdt_platform_data *pdata;
888 struct lpc_ich_priv *priv = pci_get_drvdata(dev);
889 struct lpc_ich_info *info;
890 struct mfd_cell *cell = &lpc_ich_wdt_cell;
891
892 pdata = devm_kzalloc(&dev->dev, sizeof(*pdata), GFP_KERNEL);
893 if (!pdata)
894 return -ENOMEM;
895
896 info = &lpc_chipset_info[priv->chipset];
897
898 pdata->version = info->iTCO_version;
899 strlcpy(pdata->name, info->name, sizeof(pdata->name));
900
901 cell->platform_data = pdata;
902 cell->pdata_size = sizeof(*pdata);
903 return 0;
904 }
905
lpc_ich_finalize_gpio_cell(struct pci_dev * dev)906 static void lpc_ich_finalize_gpio_cell(struct pci_dev *dev)
907 {
908 struct lpc_ich_priv *priv = pci_get_drvdata(dev);
909 struct mfd_cell *cell = &lpc_ich_gpio_cell;
910
911 cell->platform_data = &lpc_chipset_info[priv->chipset];
912 cell->pdata_size = sizeof(struct lpc_ich_info);
913 }
914
915 /*
916 * We don't check for resource conflict globally. There are 2 or 3 independent
917 * GPIO groups and it's enough to have access to one of these to instantiate
918 * the device.
919 */
lpc_ich_check_conflict_gpio(struct resource * res)920 static int lpc_ich_check_conflict_gpio(struct resource *res)
921 {
922 int ret;
923 u8 use_gpio = 0;
924
925 if (resource_size(res) >= 0x50 &&
926 !acpi_check_region(res->start + 0x40, 0x10, "LPC ICH GPIO3"))
927 use_gpio |= 1 << 2;
928
929 if (!acpi_check_region(res->start + 0x30, 0x10, "LPC ICH GPIO2"))
930 use_gpio |= 1 << 1;
931
932 ret = acpi_check_region(res->start + 0x00, 0x30, "LPC ICH GPIO1");
933 if (!ret)
934 use_gpio |= 1 << 0;
935
936 return use_gpio ? use_gpio : ret;
937 }
938
lpc_ich_init_gpio(struct pci_dev * dev)939 static int lpc_ich_init_gpio(struct pci_dev *dev)
940 {
941 struct lpc_ich_priv *priv = pci_get_drvdata(dev);
942 u32 base_addr_cfg;
943 u32 base_addr;
944 int ret;
945 bool acpi_conflict = false;
946 struct resource *res;
947
948 /* Setup power management base register */
949 pci_read_config_dword(dev, priv->abase, &base_addr_cfg);
950 base_addr = base_addr_cfg & 0x0000ff80;
951 if (!base_addr) {
952 dev_notice(&dev->dev, "I/O space for ACPI uninitialized\n");
953 lpc_ich_gpio_cell.num_resources--;
954 goto gpe0_done;
955 }
956
957 res = &gpio_ich_res[ICH_RES_GPE0];
958 res->start = base_addr + ACPIBASE_GPE_OFF;
959 res->end = base_addr + ACPIBASE_GPE_END;
960 ret = acpi_check_resource_conflict(res);
961 if (ret) {
962 /*
963 * This isn't fatal for the GPIO, but we have to make sure that
964 * the platform_device subsystem doesn't see this resource
965 * or it will register an invalid region.
966 */
967 lpc_ich_gpio_cell.num_resources--;
968 acpi_conflict = true;
969 } else {
970 lpc_ich_enable_acpi_space(dev);
971 }
972
973 gpe0_done:
974 /* Setup GPIO base register */
975 pci_read_config_dword(dev, priv->gbase, &base_addr_cfg);
976 base_addr = base_addr_cfg & 0x0000ff80;
977 if (!base_addr) {
978 dev_notice(&dev->dev, "I/O space for GPIO uninitialized\n");
979 ret = -ENODEV;
980 goto gpio_done;
981 }
982
983 /* Older devices provide fewer GPIO and have a smaller resource size. */
984 res = &gpio_ich_res[ICH_RES_GPIO];
985 res->start = base_addr;
986 switch (lpc_chipset_info[priv->chipset].gpio_version) {
987 case ICH_V5_GPIO:
988 case ICH_V10CORP_GPIO:
989 res->end = res->start + 128 - 1;
990 break;
991 default:
992 res->end = res->start + 64 - 1;
993 break;
994 }
995
996 ret = lpc_ich_check_conflict_gpio(res);
997 if (ret < 0) {
998 /* this isn't necessarily fatal for the GPIO */
999 acpi_conflict = true;
1000 goto gpio_done;
1001 }
1002 lpc_chipset_info[priv->chipset].use_gpio = ret;
1003 lpc_ich_enable_gpio_space(dev);
1004
1005 lpc_ich_finalize_gpio_cell(dev);
1006 ret = mfd_add_devices(&dev->dev, PLATFORM_DEVID_AUTO,
1007 &lpc_ich_gpio_cell, 1, NULL, 0, NULL);
1008
1009 gpio_done:
1010 if (acpi_conflict)
1011 pr_warn("Resource conflict(s) found affecting %s\n",
1012 lpc_ich_gpio_cell.name);
1013 return ret;
1014 }
1015
lpc_ich_init_wdt(struct pci_dev * dev)1016 static int lpc_ich_init_wdt(struct pci_dev *dev)
1017 {
1018 struct lpc_ich_priv *priv = pci_get_drvdata(dev);
1019 u32 base_addr_cfg;
1020 u32 base_addr;
1021 int ret;
1022 struct resource *res;
1023
1024 /* If we have ACPI based watchdog use that instead */
1025 if (acpi_has_watchdog())
1026 return -ENODEV;
1027
1028 /* Setup power management base register */
1029 pci_read_config_dword(dev, priv->abase, &base_addr_cfg);
1030 base_addr = base_addr_cfg & 0x0000ff80;
1031 if (!base_addr) {
1032 dev_notice(&dev->dev, "I/O space for ACPI uninitialized\n");
1033 ret = -ENODEV;
1034 goto wdt_done;
1035 }
1036
1037 res = wdt_io_res(ICH_RES_IO_TCO);
1038 res->start = base_addr + ACPIBASE_TCO_OFF;
1039 res->end = base_addr + ACPIBASE_TCO_END;
1040
1041 res = wdt_io_res(ICH_RES_IO_SMI);
1042 res->start = base_addr + ACPIBASE_SMI_OFF;
1043 res->end = base_addr + ACPIBASE_SMI_END;
1044
1045 lpc_ich_enable_acpi_space(dev);
1046
1047 /*
1048 * iTCO v2:
1049 * Get the Memory-Mapped GCS register. To get access to it
1050 * we have to read RCBA from PCI Config space 0xf0 and use
1051 * it as base. GCS = RCBA + ICH6_GCS(0x3410).
1052 *
1053 * iTCO v3:
1054 * Get the Power Management Configuration register. To get access
1055 * to it we have to read the PMC BASE from config space and address
1056 * the register at offset 0x8.
1057 */
1058 if (lpc_chipset_info[priv->chipset].iTCO_version == 1) {
1059 /* Don't register iomem for TCO ver 1 */
1060 lpc_ich_wdt_cell.num_resources--;
1061 } else if (lpc_chipset_info[priv->chipset].iTCO_version == 2) {
1062 pci_read_config_dword(dev, RCBABASE, &base_addr_cfg);
1063 base_addr = base_addr_cfg & 0xffffc000;
1064 if (!(base_addr_cfg & 1)) {
1065 dev_notice(&dev->dev, "RCBA is disabled by "
1066 "hardware/BIOS, device disabled\n");
1067 ret = -ENODEV;
1068 goto wdt_done;
1069 }
1070 res = wdt_mem_res(ICH_RES_MEM_GCS_PMC);
1071 res->start = base_addr + ACPIBASE_GCS_OFF;
1072 res->end = base_addr + ACPIBASE_GCS_END;
1073 } else if (lpc_chipset_info[priv->chipset].iTCO_version == 3) {
1074 lpc_ich_enable_pmc_space(dev);
1075 pci_read_config_dword(dev, ACPICTRL_PMCBASE, &base_addr_cfg);
1076 base_addr = base_addr_cfg & 0xfffffe00;
1077
1078 res = wdt_mem_res(ICH_RES_MEM_GCS_PMC);
1079 res->start = base_addr + ACPIBASE_PMC_OFF;
1080 res->end = base_addr + ACPIBASE_PMC_END;
1081 }
1082
1083 ret = lpc_ich_finalize_wdt_cell(dev);
1084 if (ret)
1085 goto wdt_done;
1086
1087 ret = mfd_add_devices(&dev->dev, PLATFORM_DEVID_AUTO,
1088 &lpc_ich_wdt_cell, 1, NULL, 0, NULL);
1089
1090 wdt_done:
1091 return ret;
1092 }
1093
lpc_ich_init_spi(struct pci_dev * dev)1094 static int lpc_ich_init_spi(struct pci_dev *dev)
1095 {
1096 struct lpc_ich_priv *priv = pci_get_drvdata(dev);
1097 struct resource *res = &intel_spi_res[0];
1098 struct intel_spi_boardinfo *info;
1099 u32 spi_base, rcba, bcr;
1100
1101 info = devm_kzalloc(&dev->dev, sizeof(*info), GFP_KERNEL);
1102 if (!info)
1103 return -ENOMEM;
1104
1105 info->type = lpc_chipset_info[priv->chipset].spi_type;
1106
1107 switch (info->type) {
1108 case INTEL_SPI_BYT:
1109 pci_read_config_dword(dev, SPIBASE_BYT, &spi_base);
1110 if (spi_base & SPIBASE_BYT_EN) {
1111 res->start = spi_base & ~(SPIBASE_BYT_SZ - 1);
1112 res->end = res->start + SPIBASE_BYT_SZ - 1;
1113 }
1114 break;
1115
1116 case INTEL_SPI_LPT:
1117 pci_read_config_dword(dev, RCBABASE, &rcba);
1118 if (rcba & 1) {
1119 spi_base = round_down(rcba, SPIBASE_LPT_SZ);
1120 res->start = spi_base + SPIBASE_LPT;
1121 res->end = res->start + SPIBASE_LPT_SZ - 1;
1122
1123 pci_read_config_dword(dev, BCR, &bcr);
1124 info->writeable = !!(bcr & BCR_WPD);
1125 }
1126 break;
1127
1128 case INTEL_SPI_BXT: {
1129 unsigned int p2sb = PCI_DEVFN(13, 0);
1130 unsigned int spi = PCI_DEVFN(13, 2);
1131 struct pci_bus *bus = dev->bus;
1132
1133 /*
1134 * The P2SB is hidden by BIOS and we need to unhide it in
1135 * order to read BAR of the SPI flash device. Once that is
1136 * done we hide it again.
1137 */
1138 pci_bus_write_config_byte(bus, p2sb, 0xe1, 0x0);
1139 pci_bus_read_config_dword(bus, spi, PCI_BASE_ADDRESS_0,
1140 &spi_base);
1141 if (spi_base != ~0) {
1142 res->start = spi_base & 0xfffffff0;
1143 res->end = res->start + SPIBASE_APL_SZ - 1;
1144
1145 pci_bus_read_config_dword(bus, spi, BCR, &bcr);
1146 info->writeable = !!(bcr & BCR_WPD);
1147 }
1148
1149 pci_bus_write_config_byte(bus, p2sb, 0xe1, 0x1);
1150 break;
1151 }
1152
1153 default:
1154 return -EINVAL;
1155 }
1156
1157 if (!res->start)
1158 return -ENODEV;
1159
1160 lpc_ich_spi_cell.platform_data = info;
1161 lpc_ich_spi_cell.pdata_size = sizeof(*info);
1162
1163 return mfd_add_devices(&dev->dev, PLATFORM_DEVID_NONE,
1164 &lpc_ich_spi_cell, 1, NULL, 0, NULL);
1165 }
1166
lpc_ich_probe(struct pci_dev * dev,const struct pci_device_id * id)1167 static int lpc_ich_probe(struct pci_dev *dev,
1168 const struct pci_device_id *id)
1169 {
1170 struct lpc_ich_priv *priv;
1171 int ret;
1172 bool cell_added = false;
1173
1174 priv = devm_kzalloc(&dev->dev,
1175 sizeof(struct lpc_ich_priv), GFP_KERNEL);
1176 if (!priv)
1177 return -ENOMEM;
1178
1179 priv->chipset = id->driver_data;
1180
1181 priv->actrl_pbase_save = -1;
1182 priv->abase_save = -1;
1183
1184 priv->abase = ACPIBASE;
1185 priv->actrl_pbase = ACPICTRL_PMCBASE;
1186
1187 priv->gctrl_save = -1;
1188 if (priv->chipset <= LPC_ICH5) {
1189 priv->gbase = GPIOBASE_ICH0;
1190 priv->gctrl = GPIOCTRL_ICH0;
1191 } else {
1192 priv->gbase = GPIOBASE_ICH6;
1193 priv->gctrl = GPIOCTRL_ICH6;
1194 }
1195
1196 pci_set_drvdata(dev, priv);
1197
1198 if (lpc_chipset_info[priv->chipset].iTCO_version) {
1199 ret = lpc_ich_init_wdt(dev);
1200 if (!ret)
1201 cell_added = true;
1202 }
1203
1204 if (lpc_chipset_info[priv->chipset].gpio_version) {
1205 ret = lpc_ich_init_gpio(dev);
1206 if (!ret)
1207 cell_added = true;
1208 }
1209
1210 if (lpc_chipset_info[priv->chipset].spi_type) {
1211 ret = lpc_ich_init_spi(dev);
1212 if (!ret)
1213 cell_added = true;
1214 }
1215
1216 /*
1217 * We only care if at least one or none of the cells registered
1218 * successfully.
1219 */
1220 if (!cell_added) {
1221 dev_warn(&dev->dev, "No MFD cells added\n");
1222 lpc_ich_restore_config_space(dev);
1223 return -ENODEV;
1224 }
1225
1226 return 0;
1227 }
1228
lpc_ich_remove(struct pci_dev * dev)1229 static void lpc_ich_remove(struct pci_dev *dev)
1230 {
1231 mfd_remove_devices(&dev->dev);
1232 lpc_ich_restore_config_space(dev);
1233 }
1234
1235 static struct pci_driver lpc_ich_driver = {
1236 .name = "lpc_ich",
1237 .id_table = lpc_ich_ids,
1238 .probe = lpc_ich_probe,
1239 .remove = lpc_ich_remove,
1240 };
1241
1242 module_pci_driver(lpc_ich_driver);
1243
1244 MODULE_AUTHOR("Aaron Sierra <asierra@xes-inc.com>");
1245 MODULE_DESCRIPTION("LPC interface for Intel ICH");
1246 MODULE_LICENSE("GPL");
1247
