1 /*
2 * Driver for Mediatek IR Receiver Controller
3 *
4 * Copyright (C) 2017 Sean Wang <sean.wang@mediatek.com>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17 #include <linux/clk.h>
18 #include <linux/interrupt.h>
19 #include <linux/module.h>
20 #include <linux/of_platform.h>
21 #include <linux/reset.h>
22 #include <media/rc-core.h>
23
24 #define MTK_IR_DEV KBUILD_MODNAME
25
26 /* Register to enable PWM and IR */
27 #define MTK_CONFIG_HIGH_REG 0x0c
28
29 /* Bit to enable IR pulse width detection */
30 #define MTK_PWM_EN BIT(13)
31
32 /*
33 * Register to setting ok count whose unit based on hardware sampling period
34 * indicating IR receiving completion and then making IRQ fires
35 */
36 #define MTK_OK_COUNT(x) (((x) & GENMASK(23, 16)) << 16)
37
38 /* Bit to enable IR hardware function */
39 #define MTK_IR_EN BIT(0)
40
41 /* Bit to restart IR receiving */
42 #define MTK_IRCLR BIT(0)
43
44 /* Fields containing pulse width data */
45 #define MTK_WIDTH_MASK (GENMASK(7, 0))
46
47 /* Bit to enable interrupt */
48 #define MTK_IRINT_EN BIT(0)
49
50 /* Bit to clear interrupt status */
51 #define MTK_IRINT_CLR BIT(0)
52
53 /* Maximum count of samples */
54 #define MTK_MAX_SAMPLES 0xff
55 /* Indicate the end of IR message */
56 #define MTK_IR_END(v, p) ((v) == MTK_MAX_SAMPLES && (p) == 0)
57 /* Number of registers to record the pulse width */
58 #define MTK_CHKDATA_SZ 17
59 /* Sample period in ns */
60 #define MTK_IR_SAMPLE 46000
61
62 enum mtk_fields {
63 /* Register to setting software sampling period */
64 MTK_CHK_PERIOD,
65 /* Register to setting hardware sampling period */
66 MTK_HW_PERIOD,
67 };
68
69 enum mtk_regs {
70 /* Register to clear state of state machine */
71 MTK_IRCLR_REG,
72 /* Register containing pulse width data */
73 MTK_CHKDATA_REG,
74 /* Register to enable IR interrupt */
75 MTK_IRINT_EN_REG,
76 /* Register to ack IR interrupt */
77 MTK_IRINT_CLR_REG
78 };
79
80 static const u32 mt7623_regs[] = {
81 [MTK_IRCLR_REG] = 0x20,
82 [MTK_CHKDATA_REG] = 0x88,
83 [MTK_IRINT_EN_REG] = 0xcc,
84 [MTK_IRINT_CLR_REG] = 0xd0,
85 };
86
87 static const u32 mt7622_regs[] = {
88 [MTK_IRCLR_REG] = 0x18,
89 [MTK_CHKDATA_REG] = 0x30,
90 [MTK_IRINT_EN_REG] = 0x1c,
91 [MTK_IRINT_CLR_REG] = 0x20,
92 };
93
94 struct mtk_field_type {
95 u32 reg;
96 u8 offset;
97 u32 mask;
98 };
99
100 /*
101 * struct mtk_ir_data - This is the structure holding all differences among
102 various hardwares
103 * @regs: The pointer to the array holding registers offset
104 * @fields: The pointer to the array holding fields location
105 * @div: The internal divisor for the based reference clock
106 * @ok_count: The count indicating the completion of IR data
107 * receiving when count is reached
108 * @hw_period: The value indicating the hardware sampling period
109 */
110 struct mtk_ir_data {
111 const u32 *regs;
112 const struct mtk_field_type *fields;
113 u8 div;
114 u8 ok_count;
115 u32 hw_period;
116 };
117
118 static const struct mtk_field_type mt7623_fields[] = {
119 [MTK_CHK_PERIOD] = {0x10, 8, GENMASK(20, 8)},
120 [MTK_HW_PERIOD] = {0x10, 0, GENMASK(7, 0)},
121 };
122
123 static const struct mtk_field_type mt7622_fields[] = {
124 [MTK_CHK_PERIOD] = {0x24, 0, GENMASK(24, 0)},
125 [MTK_HW_PERIOD] = {0x10, 0, GENMASK(24, 0)},
126 };
127
128 /*
129 * struct mtk_ir - This is the main datasructure for holding the state
130 * of the driver
131 * @dev: The device pointer
132 * @rc: The rc instrance
133 * @base: The mapped register i/o base
134 * @irq: The IRQ that we are using
135 * @clk: The clock that IR internal is using
136 * @bus: The clock that software decoder is using
137 * @data: Holding specific data for vaious platform
138 */
139 struct mtk_ir {
140 struct device *dev;
141 struct rc_dev *rc;
142 void __iomem *base;
143 int irq;
144 struct clk *clk;
145 struct clk *bus;
146 const struct mtk_ir_data *data;
147 };
148
mtk_chkdata_reg(struct mtk_ir * ir,u32 i)149 static inline u32 mtk_chkdata_reg(struct mtk_ir *ir, u32 i)
150 {
151 return ir->data->regs[MTK_CHKDATA_REG] + 4 * i;
152 }
153
mtk_chk_period(struct mtk_ir * ir)154 static inline u32 mtk_chk_period(struct mtk_ir *ir)
155 {
156 u32 val;
157
158 /* Period of raw software sampling in ns */
159 val = DIV_ROUND_CLOSEST(1000000000ul,
160 clk_get_rate(ir->bus) / ir->data->div);
161
162 /*
163 * Period for software decoder used in the
164 * unit of raw software sampling
165 */
166 val = DIV_ROUND_CLOSEST(MTK_IR_SAMPLE, val);
167
168 dev_dbg(ir->dev, "@pwm clk = \t%lu\n",
169 clk_get_rate(ir->bus) / ir->data->div);
170 dev_dbg(ir->dev, "@chkperiod = %08x\n", val);
171
172 return val;
173 }
174
mtk_w32_mask(struct mtk_ir * ir,u32 val,u32 mask,unsigned int reg)175 static void mtk_w32_mask(struct mtk_ir *ir, u32 val, u32 mask, unsigned int reg)
176 {
177 u32 tmp;
178
179 tmp = __raw_readl(ir->base + reg);
180 tmp = (tmp & ~mask) | val;
181 __raw_writel(tmp, ir->base + reg);
182 }
183
mtk_w32(struct mtk_ir * ir,u32 val,unsigned int reg)184 static void mtk_w32(struct mtk_ir *ir, u32 val, unsigned int reg)
185 {
186 __raw_writel(val, ir->base + reg);
187 }
188
mtk_r32(struct mtk_ir * ir,unsigned int reg)189 static u32 mtk_r32(struct mtk_ir *ir, unsigned int reg)
190 {
191 return __raw_readl(ir->base + reg);
192 }
193
mtk_irq_disable(struct mtk_ir * ir,u32 mask)194 static inline void mtk_irq_disable(struct mtk_ir *ir, u32 mask)
195 {
196 u32 val;
197
198 val = mtk_r32(ir, ir->data->regs[MTK_IRINT_EN_REG]);
199 mtk_w32(ir, val & ~mask, ir->data->regs[MTK_IRINT_EN_REG]);
200 }
201
mtk_irq_enable(struct mtk_ir * ir,u32 mask)202 static inline void mtk_irq_enable(struct mtk_ir *ir, u32 mask)
203 {
204 u32 val;
205
206 val = mtk_r32(ir, ir->data->regs[MTK_IRINT_EN_REG]);
207 mtk_w32(ir, val | mask, ir->data->regs[MTK_IRINT_EN_REG]);
208 }
209
mtk_ir_irq(int irqno,void * dev_id)210 static irqreturn_t mtk_ir_irq(int irqno, void *dev_id)
211 {
212 struct mtk_ir *ir = dev_id;
213 u8 wid = 0;
214 u32 i, j, val;
215 DEFINE_IR_RAW_EVENT(rawir);
216
217 /*
218 * Reset decoder state machine explicitly is required
219 * because 1) the longest duration for space MTK IR hardware
220 * could record is not safely long. e.g 12ms if rx resolution
221 * is 46us by default. There is still the risk to satisfying
222 * every decoder to reset themselves through long enough
223 * trailing spaces and 2) the IRQ handler guarantees that
224 * start of IR message is always contained in and starting
225 * from register mtk_chkdata_reg(ir, i).
226 */
227 ir_raw_event_reset(ir->rc);
228
229 /* First message must be pulse */
230 rawir.pulse = false;
231
232 /* Handle all pulse and space IR controller captures */
233 for (i = 0 ; i < MTK_CHKDATA_SZ ; i++) {
234 val = mtk_r32(ir, mtk_chkdata_reg(ir, i));
235 dev_dbg(ir->dev, "@reg%d=0x%08x\n", i, val);
236
237 for (j = 0 ; j < 4 ; j++) {
238 wid = (val & (MTK_WIDTH_MASK << j * 8)) >> j * 8;
239 rawir.pulse = !rawir.pulse;
240 rawir.duration = wid * (MTK_IR_SAMPLE + 1);
241 ir_raw_event_store_with_filter(ir->rc, &rawir);
242 }
243 }
244
245 /*
246 * The maximum number of edges the IR controller can
247 * hold is MTK_CHKDATA_SZ * 4. So if received IR messages
248 * is over the limit, the last incomplete IR message would
249 * be appended trailing space and still would be sent into
250 * ir-rc-raw to decode. That helps it is possible that it
251 * has enough information to decode a scancode even if the
252 * trailing end of the message is missing.
253 */
254 if (!MTK_IR_END(wid, rawir.pulse)) {
255 rawir.pulse = false;
256 rawir.duration = MTK_MAX_SAMPLES * (MTK_IR_SAMPLE + 1);
257 ir_raw_event_store_with_filter(ir->rc, &rawir);
258 }
259
260 ir_raw_event_handle(ir->rc);
261
262 /*
263 * Restart controller for the next receive that would
264 * clear up all CHKDATA registers
265 */
266 mtk_w32_mask(ir, 0x1, MTK_IRCLR, ir->data->regs[MTK_IRCLR_REG]);
267
268 /* Clear interrupt status */
269 mtk_w32_mask(ir, 0x1, MTK_IRINT_CLR,
270 ir->data->regs[MTK_IRINT_CLR_REG]);
271
272 return IRQ_HANDLED;
273 }
274
275 static const struct mtk_ir_data mt7623_data = {
276 .regs = mt7623_regs,
277 .fields = mt7623_fields,
278 .ok_count = 0xf,
279 .hw_period = 0xff,
280 .div = 4,
281 };
282
283 static const struct mtk_ir_data mt7622_data = {
284 .regs = mt7622_regs,
285 .fields = mt7622_fields,
286 .ok_count = 0xf,
287 .hw_period = 0xffff,
288 .div = 32,
289 };
290
291 static const struct of_device_id mtk_ir_match[] = {
292 { .compatible = "mediatek,mt7623-cir", .data = &mt7623_data},
293 { .compatible = "mediatek,mt7622-cir", .data = &mt7622_data},
294 {},
295 };
296 MODULE_DEVICE_TABLE(of, mtk_ir_match);
297
mtk_ir_probe(struct platform_device * pdev)298 static int mtk_ir_probe(struct platform_device *pdev)
299 {
300 struct device *dev = &pdev->dev;
301 struct device_node *dn = dev->of_node;
302 struct resource *res;
303 struct mtk_ir *ir;
304 u32 val;
305 int ret = 0;
306 const char *map_name;
307
308 ir = devm_kzalloc(dev, sizeof(struct mtk_ir), GFP_KERNEL);
309 if (!ir)
310 return -ENOMEM;
311
312 ir->dev = dev;
313 ir->data = of_device_get_match_data(dev);
314
315 ir->clk = devm_clk_get(dev, "clk");
316 if (IS_ERR(ir->clk)) {
317 dev_err(dev, "failed to get a ir clock.\n");
318 return PTR_ERR(ir->clk);
319 }
320
321 ir->bus = devm_clk_get(dev, "bus");
322 if (IS_ERR(ir->bus)) {
323 /*
324 * For compatibility with older device trees try unnamed
325 * ir->bus uses the same clock as ir->clock.
326 */
327 ir->bus = ir->clk;
328 }
329
330 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
331 ir->base = devm_ioremap_resource(dev, res);
332 if (IS_ERR(ir->base)) {
333 dev_err(dev, "failed to map registers\n");
334 return PTR_ERR(ir->base);
335 }
336
337 ir->rc = devm_rc_allocate_device(dev, RC_DRIVER_IR_RAW);
338 if (!ir->rc) {
339 dev_err(dev, "failed to allocate device\n");
340 return -ENOMEM;
341 }
342
343 ir->rc->priv = ir;
344 ir->rc->device_name = MTK_IR_DEV;
345 ir->rc->input_phys = MTK_IR_DEV "/input0";
346 ir->rc->input_id.bustype = BUS_HOST;
347 ir->rc->input_id.vendor = 0x0001;
348 ir->rc->input_id.product = 0x0001;
349 ir->rc->input_id.version = 0x0001;
350 map_name = of_get_property(dn, "linux,rc-map-name", NULL);
351 ir->rc->map_name = map_name ?: RC_MAP_EMPTY;
352 ir->rc->dev.parent = dev;
353 ir->rc->driver_name = MTK_IR_DEV;
354 ir->rc->allowed_protocols = RC_PROTO_BIT_ALL;
355 ir->rc->rx_resolution = MTK_IR_SAMPLE;
356 ir->rc->timeout = MTK_MAX_SAMPLES * (MTK_IR_SAMPLE + 1);
357
358 ret = devm_rc_register_device(dev, ir->rc);
359 if (ret) {
360 dev_err(dev, "failed to register rc device\n");
361 return ret;
362 }
363
364 platform_set_drvdata(pdev, ir);
365
366 ir->irq = platform_get_irq(pdev, 0);
367 if (ir->irq < 0) {
368 dev_err(dev, "no irq resource\n");
369 return -ENODEV;
370 }
371
372 if (clk_prepare_enable(ir->clk)) {
373 dev_err(dev, "try to enable ir_clk failed\n");
374 return -EINVAL;
375 }
376
377 if (clk_prepare_enable(ir->bus)) {
378 dev_err(dev, "try to enable ir_clk failed\n");
379 ret = -EINVAL;
380 goto exit_clkdisable_clk;
381 }
382
383 /*
384 * Enable interrupt after proper hardware
385 * setup and IRQ handler registration
386 */
387 mtk_irq_disable(ir, MTK_IRINT_EN);
388
389 ret = devm_request_irq(dev, ir->irq, mtk_ir_irq, 0, MTK_IR_DEV, ir);
390 if (ret) {
391 dev_err(dev, "failed request irq\n");
392 goto exit_clkdisable_bus;
393 }
394
395 /*
396 * Setup software sample period as the reference of software decoder
397 */
398 val = (mtk_chk_period(ir) << ir->data->fields[MTK_CHK_PERIOD].offset) &
399 ir->data->fields[MTK_CHK_PERIOD].mask;
400 mtk_w32_mask(ir, val, ir->data->fields[MTK_CHK_PERIOD].mask,
401 ir->data->fields[MTK_CHK_PERIOD].reg);
402
403 /*
404 * Setup hardware sampling period used to setup the proper timeout for
405 * indicating end of IR receiving completion
406 */
407 val = (ir->data->hw_period << ir->data->fields[MTK_HW_PERIOD].offset) &
408 ir->data->fields[MTK_HW_PERIOD].mask;
409 mtk_w32_mask(ir, val, ir->data->fields[MTK_HW_PERIOD].mask,
410 ir->data->fields[MTK_HW_PERIOD].reg);
411
412 /* Enable IR and PWM */
413 val = mtk_r32(ir, MTK_CONFIG_HIGH_REG);
414 val |= MTK_OK_COUNT(ir->data->ok_count) | MTK_PWM_EN | MTK_IR_EN;
415 mtk_w32(ir, val, MTK_CONFIG_HIGH_REG);
416
417 mtk_irq_enable(ir, MTK_IRINT_EN);
418
419 dev_info(dev, "Initialized MT7623 IR driver, sample period = %dus\n",
420 DIV_ROUND_CLOSEST(MTK_IR_SAMPLE, 1000));
421
422 return 0;
423
424 exit_clkdisable_bus:
425 clk_disable_unprepare(ir->bus);
426 exit_clkdisable_clk:
427 clk_disable_unprepare(ir->clk);
428
429 return ret;
430 }
431
mtk_ir_remove(struct platform_device * pdev)432 static int mtk_ir_remove(struct platform_device *pdev)
433 {
434 struct mtk_ir *ir = platform_get_drvdata(pdev);
435
436 /*
437 * Avoid contention between remove handler and
438 * IRQ handler so that disabling IR interrupt and
439 * waiting for pending IRQ handler to complete
440 */
441 mtk_irq_disable(ir, MTK_IRINT_EN);
442 synchronize_irq(ir->irq);
443
444 clk_disable_unprepare(ir->bus);
445 clk_disable_unprepare(ir->clk);
446
447 return 0;
448 }
449
450 static struct platform_driver mtk_ir_driver = {
451 .probe = mtk_ir_probe,
452 .remove = mtk_ir_remove,
453 .driver = {
454 .name = MTK_IR_DEV,
455 .of_match_table = mtk_ir_match,
456 },
457 };
458
459 module_platform_driver(mtk_ir_driver);
460
461 MODULE_DESCRIPTION("Mediatek IR Receiver Controller Driver");
462 MODULE_AUTHOR("Sean Wang <sean.wang@mediatek.com>");
463 MODULE_LICENSE("GPL");
464
