1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Microchip Image Sensor Controller (ISC) common driver base
4 *
5 * Copyright (C) 2016-2019 Microchip Technology, Inc.
6 *
7 * Author: Songjun Wu
8 * Author: Eugen Hristev <eugen.hristev@microchip.com>
9 *
10 */
11
12 #include <linux/clk.h>
13 #include <linux/clkdev.h>
14 #include <linux/clk-provider.h>
15 #include <linux/delay.h>
16 #include <linux/interrupt.h>
17 #include <linux/math64.h>
18 #include <linux/module.h>
19 #include <linux/of.h>
20 #include <linux/of_graph.h>
21 #include <linux/platform_device.h>
22 #include <linux/pm_runtime.h>
23 #include <linux/regmap.h>
24 #include <linux/videodev2.h>
25
26 #include <media/v4l2-ctrls.h>
27 #include <media/v4l2-device.h>
28 #include <media/v4l2-event.h>
29 #include <media/v4l2-image-sizes.h>
30 #include <media/v4l2-ioctl.h>
31 #include <media/v4l2-fwnode.h>
32 #include <media/v4l2-subdev.h>
33 #include <media/videobuf2-dma-contig.h>
34
35 #include "atmel-isc-regs.h"
36 #include "atmel-isc.h"
37
38 static unsigned int debug;
39 module_param(debug, int, 0644);
40 MODULE_PARM_DESC(debug, "debug level (0-2)");
41
42 static unsigned int sensor_preferred = 1;
43 module_param(sensor_preferred, uint, 0644);
44 MODULE_PARM_DESC(sensor_preferred,
45 "Sensor is preferred to output the specified format (1-on 0-off), default 1");
46
47 /* This is a list of the formats that the ISC can *output* */
48 const struct isc_format controller_formats[] = {
49 {
50 .fourcc = V4L2_PIX_FMT_ARGB444,
51 },
52 {
53 .fourcc = V4L2_PIX_FMT_ARGB555,
54 },
55 {
56 .fourcc = V4L2_PIX_FMT_RGB565,
57 },
58 {
59 .fourcc = V4L2_PIX_FMT_ABGR32,
60 },
61 {
62 .fourcc = V4L2_PIX_FMT_XBGR32,
63 },
64 {
65 .fourcc = V4L2_PIX_FMT_YUV420,
66 },
67 {
68 .fourcc = V4L2_PIX_FMT_YUYV,
69 },
70 {
71 .fourcc = V4L2_PIX_FMT_YUV422P,
72 },
73 {
74 .fourcc = V4L2_PIX_FMT_GREY,
75 },
76 };
77
78 /* This is a list of formats that the ISC can receive as *input* */
79 struct isc_format formats_list[] = {
80 {
81 .fourcc = V4L2_PIX_FMT_SBGGR8,
82 .mbus_code = MEDIA_BUS_FMT_SBGGR8_1X8,
83 .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT,
84 .cfa_baycfg = ISC_BAY_CFG_BGBG,
85 },
86 {
87 .fourcc = V4L2_PIX_FMT_SGBRG8,
88 .mbus_code = MEDIA_BUS_FMT_SGBRG8_1X8,
89 .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT,
90 .cfa_baycfg = ISC_BAY_CFG_GBGB,
91 },
92 {
93 .fourcc = V4L2_PIX_FMT_SGRBG8,
94 .mbus_code = MEDIA_BUS_FMT_SGRBG8_1X8,
95 .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT,
96 .cfa_baycfg = ISC_BAY_CFG_GRGR,
97 },
98 {
99 .fourcc = V4L2_PIX_FMT_SRGGB8,
100 .mbus_code = MEDIA_BUS_FMT_SRGGB8_1X8,
101 .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT,
102 .cfa_baycfg = ISC_BAY_CFG_RGRG,
103 },
104 {
105 .fourcc = V4L2_PIX_FMT_SBGGR10,
106 .mbus_code = MEDIA_BUS_FMT_SBGGR10_1X10,
107 .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TEN,
108 .cfa_baycfg = ISC_BAY_CFG_RGRG,
109 },
110 {
111 .fourcc = V4L2_PIX_FMT_SGBRG10,
112 .mbus_code = MEDIA_BUS_FMT_SGBRG10_1X10,
113 .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TEN,
114 .cfa_baycfg = ISC_BAY_CFG_GBGB,
115 },
116 {
117 .fourcc = V4L2_PIX_FMT_SGRBG10,
118 .mbus_code = MEDIA_BUS_FMT_SGRBG10_1X10,
119 .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TEN,
120 .cfa_baycfg = ISC_BAY_CFG_GRGR,
121 },
122 {
123 .fourcc = V4L2_PIX_FMT_SRGGB10,
124 .mbus_code = MEDIA_BUS_FMT_SRGGB10_1X10,
125 .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TEN,
126 .cfa_baycfg = ISC_BAY_CFG_RGRG,
127 },
128 {
129 .fourcc = V4L2_PIX_FMT_SBGGR12,
130 .mbus_code = MEDIA_BUS_FMT_SBGGR12_1X12,
131 .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TWELVE,
132 .cfa_baycfg = ISC_BAY_CFG_BGBG,
133 },
134 {
135 .fourcc = V4L2_PIX_FMT_SGBRG12,
136 .mbus_code = MEDIA_BUS_FMT_SGBRG12_1X12,
137 .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TWELVE,
138 .cfa_baycfg = ISC_BAY_CFG_GBGB,
139 },
140 {
141 .fourcc = V4L2_PIX_FMT_SGRBG12,
142 .mbus_code = MEDIA_BUS_FMT_SGRBG12_1X12,
143 .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TWELVE,
144 .cfa_baycfg = ISC_BAY_CFG_GRGR,
145 },
146 {
147 .fourcc = V4L2_PIX_FMT_SRGGB12,
148 .mbus_code = MEDIA_BUS_FMT_SRGGB12_1X12,
149 .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TWELVE,
150 .cfa_baycfg = ISC_BAY_CFG_RGRG,
151 },
152 {
153 .fourcc = V4L2_PIX_FMT_GREY,
154 .mbus_code = MEDIA_BUS_FMT_Y8_1X8,
155 .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT,
156 },
157 {
158 .fourcc = V4L2_PIX_FMT_YUYV,
159 .mbus_code = MEDIA_BUS_FMT_YUYV8_2X8,
160 .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT,
161 },
162 {
163 .fourcc = V4L2_PIX_FMT_RGB565,
164 .mbus_code = MEDIA_BUS_FMT_RGB565_2X8_LE,
165 .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT,
166 },
167 };
168
169 /* Gamma table with gamma 1/2.2 */
170 const u32 isc_gamma_table[GAMMA_MAX + 1][GAMMA_ENTRIES] = {
171 /* 0 --> gamma 1/1.8 */
172 { 0x65, 0x66002F, 0x950025, 0xBB0020, 0xDB001D, 0xF8001A,
173 0x1130018, 0x12B0017, 0x1420016, 0x1580014, 0x16D0013, 0x1810012,
174 0x1940012, 0x1A60012, 0x1B80011, 0x1C90010, 0x1DA0010, 0x1EA000F,
175 0x1FA000F, 0x209000F, 0x218000F, 0x227000E, 0x235000E, 0x243000E,
176 0x251000E, 0x25F000D, 0x26C000D, 0x279000D, 0x286000D, 0x293000C,
177 0x2A0000C, 0x2AC000C, 0x2B8000C, 0x2C4000C, 0x2D0000B, 0x2DC000B,
178 0x2E7000B, 0x2F3000B, 0x2FE000B, 0x309000B, 0x314000B, 0x31F000A,
179 0x32A000A, 0x334000B, 0x33F000A, 0x349000A, 0x354000A, 0x35E000A,
180 0x368000A, 0x372000A, 0x37C000A, 0x386000A, 0x3900009, 0x399000A,
181 0x3A30009, 0x3AD0009, 0x3B60009, 0x3BF000A, 0x3C90009, 0x3D20009,
182 0x3DB0009, 0x3E40009, 0x3ED0009, 0x3F60009 },
183
184 /* 1 --> gamma 1/2 */
185 { 0x7F, 0x800034, 0xB50028, 0xDE0021, 0x100001E, 0x11E001B,
186 0x1390019, 0x1520017, 0x16A0015, 0x1800014, 0x1940014, 0x1A80013,
187 0x1BB0012, 0x1CD0011, 0x1DF0010, 0x1EF0010, 0x200000F, 0x20F000F,
188 0x21F000E, 0x22D000F, 0x23C000E, 0x24A000E, 0x258000D, 0x265000D,
189 0x273000C, 0x27F000D, 0x28C000C, 0x299000C, 0x2A5000C, 0x2B1000B,
190 0x2BC000C, 0x2C8000B, 0x2D3000C, 0x2DF000B, 0x2EA000A, 0x2F5000A,
191 0x2FF000B, 0x30A000A, 0x314000B, 0x31F000A, 0x329000A, 0x333000A,
192 0x33D0009, 0x3470009, 0x350000A, 0x35A0009, 0x363000A, 0x36D0009,
193 0x3760009, 0x37F0009, 0x3880009, 0x3910009, 0x39A0009, 0x3A30009,
194 0x3AC0008, 0x3B40009, 0x3BD0008, 0x3C60008, 0x3CE0008, 0x3D60009,
195 0x3DF0008, 0x3E70008, 0x3EF0008, 0x3F70008 },
196
197 /* 2 --> gamma 1/2.2 */
198 { 0x99, 0x9B0038, 0xD4002A, 0xFF0023, 0x122001F, 0x141001B,
199 0x15D0019, 0x1760017, 0x18E0015, 0x1A30015, 0x1B80013, 0x1CC0012,
200 0x1DE0011, 0x1F00010, 0x2010010, 0x2110010, 0x221000F, 0x230000F,
201 0x23F000E, 0x24D000E, 0x25B000D, 0x269000C, 0x276000C, 0x283000C,
202 0x28F000C, 0x29B000C, 0x2A7000C, 0x2B3000B, 0x2BF000B, 0x2CA000B,
203 0x2D5000B, 0x2E0000A, 0x2EB000A, 0x2F5000A, 0x2FF000A, 0x30A000A,
204 0x3140009, 0x31E0009, 0x327000A, 0x3310009, 0x33A0009, 0x3440009,
205 0x34D0009, 0x3560009, 0x35F0009, 0x3680008, 0x3710008, 0x3790009,
206 0x3820008, 0x38A0008, 0x3930008, 0x39B0008, 0x3A30008, 0x3AB0008,
207 0x3B30008, 0x3BB0008, 0x3C30008, 0x3CB0007, 0x3D20008, 0x3DA0007,
208 0x3E20007, 0x3E90007, 0x3F00008, 0x3F80007 },
209 };
210
211 #define ISC_IS_FORMAT_RAW(mbus_code) \
212 (((mbus_code) & 0xf000) == 0x3000)
213
isc_update_awb_ctrls(struct isc_device * isc)214 static inline void isc_update_awb_ctrls(struct isc_device *isc)
215 {
216 struct isc_ctrls *ctrls = &isc->ctrls;
217
218 regmap_write(isc->regmap, ISC_WB_O_RGR,
219 (ISC_WB_O_ZERO_VAL - (ctrls->offset[ISC_HIS_CFG_MODE_R])) |
220 ((ISC_WB_O_ZERO_VAL - ctrls->offset[ISC_HIS_CFG_MODE_GR]) << 16));
221 regmap_write(isc->regmap, ISC_WB_O_BGB,
222 (ISC_WB_O_ZERO_VAL - (ctrls->offset[ISC_HIS_CFG_MODE_B])) |
223 ((ISC_WB_O_ZERO_VAL - ctrls->offset[ISC_HIS_CFG_MODE_GB]) << 16));
224 regmap_write(isc->regmap, ISC_WB_G_RGR,
225 ctrls->gain[ISC_HIS_CFG_MODE_R] |
226 (ctrls->gain[ISC_HIS_CFG_MODE_GR] << 16));
227 regmap_write(isc->regmap, ISC_WB_G_BGB,
228 ctrls->gain[ISC_HIS_CFG_MODE_B] |
229 (ctrls->gain[ISC_HIS_CFG_MODE_GB] << 16));
230 }
231
isc_reset_awb_ctrls(struct isc_device * isc)232 static inline void isc_reset_awb_ctrls(struct isc_device *isc)
233 {
234 unsigned int c;
235
236 for (c = ISC_HIS_CFG_MODE_GR; c <= ISC_HIS_CFG_MODE_B; c++) {
237 /* gains have a fixed point at 9 decimals */
238 isc->ctrls.gain[c] = 1 << 9;
239 /* offsets are in 2's complements, the value
240 * will be substracted from ISC_WB_O_ZERO_VAL to obtain
241 * 2's complement of a value between 0 and
242 * ISC_WB_O_ZERO_VAL >> 1
243 */
244 isc->ctrls.offset[c] = ISC_WB_O_ZERO_VAL;
245 }
246 }
247
isc_wait_clk_stable(struct clk_hw * hw)248 static int isc_wait_clk_stable(struct clk_hw *hw)
249 {
250 struct isc_clk *isc_clk = to_isc_clk(hw);
251 struct regmap *regmap = isc_clk->regmap;
252 unsigned long timeout = jiffies + usecs_to_jiffies(1000);
253 unsigned int status;
254
255 while (time_before(jiffies, timeout)) {
256 regmap_read(regmap, ISC_CLKSR, &status);
257 if (!(status & ISC_CLKSR_SIP))
258 return 0;
259
260 usleep_range(10, 250);
261 }
262
263 return -ETIMEDOUT;
264 }
265
isc_clk_prepare(struct clk_hw * hw)266 static int isc_clk_prepare(struct clk_hw *hw)
267 {
268 struct isc_clk *isc_clk = to_isc_clk(hw);
269
270 if (isc_clk->id == ISC_ISPCK)
271 pm_runtime_get_sync(isc_clk->dev);
272
273 return isc_wait_clk_stable(hw);
274 }
275
isc_clk_unprepare(struct clk_hw * hw)276 static void isc_clk_unprepare(struct clk_hw *hw)
277 {
278 struct isc_clk *isc_clk = to_isc_clk(hw);
279
280 isc_wait_clk_stable(hw);
281
282 if (isc_clk->id == ISC_ISPCK)
283 pm_runtime_put_sync(isc_clk->dev);
284 }
285
isc_clk_enable(struct clk_hw * hw)286 static int isc_clk_enable(struct clk_hw *hw)
287 {
288 struct isc_clk *isc_clk = to_isc_clk(hw);
289 u32 id = isc_clk->id;
290 struct regmap *regmap = isc_clk->regmap;
291 unsigned long flags;
292 unsigned int status;
293
294 dev_dbg(isc_clk->dev, "ISC CLK: %s, div = %d, parent id = %d\n",
295 __func__, isc_clk->div, isc_clk->parent_id);
296
297 spin_lock_irqsave(&isc_clk->lock, flags);
298 regmap_update_bits(regmap, ISC_CLKCFG,
299 ISC_CLKCFG_DIV_MASK(id) | ISC_CLKCFG_SEL_MASK(id),
300 (isc_clk->div << ISC_CLKCFG_DIV_SHIFT(id)) |
301 (isc_clk->parent_id << ISC_CLKCFG_SEL_SHIFT(id)));
302
303 regmap_write(regmap, ISC_CLKEN, ISC_CLK(id));
304 spin_unlock_irqrestore(&isc_clk->lock, flags);
305
306 regmap_read(regmap, ISC_CLKSR, &status);
307 if (status & ISC_CLK(id))
308 return 0;
309 else
310 return -EINVAL;
311 }
312
isc_clk_disable(struct clk_hw * hw)313 static void isc_clk_disable(struct clk_hw *hw)
314 {
315 struct isc_clk *isc_clk = to_isc_clk(hw);
316 u32 id = isc_clk->id;
317 unsigned long flags;
318
319 spin_lock_irqsave(&isc_clk->lock, flags);
320 regmap_write(isc_clk->regmap, ISC_CLKDIS, ISC_CLK(id));
321 spin_unlock_irqrestore(&isc_clk->lock, flags);
322 }
323
isc_clk_is_enabled(struct clk_hw * hw)324 static int isc_clk_is_enabled(struct clk_hw *hw)
325 {
326 struct isc_clk *isc_clk = to_isc_clk(hw);
327 u32 status;
328
329 if (isc_clk->id == ISC_ISPCK)
330 pm_runtime_get_sync(isc_clk->dev);
331
332 regmap_read(isc_clk->regmap, ISC_CLKSR, &status);
333
334 if (isc_clk->id == ISC_ISPCK)
335 pm_runtime_put_sync(isc_clk->dev);
336
337 return status & ISC_CLK(isc_clk->id) ? 1 : 0;
338 }
339
340 static unsigned long
isc_clk_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)341 isc_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
342 {
343 struct isc_clk *isc_clk = to_isc_clk(hw);
344
345 return DIV_ROUND_CLOSEST(parent_rate, isc_clk->div + 1);
346 }
347
isc_clk_determine_rate(struct clk_hw * hw,struct clk_rate_request * req)348 static int isc_clk_determine_rate(struct clk_hw *hw,
349 struct clk_rate_request *req)
350 {
351 struct isc_clk *isc_clk = to_isc_clk(hw);
352 long best_rate = -EINVAL;
353 int best_diff = -1;
354 unsigned int i, div;
355
356 for (i = 0; i < clk_hw_get_num_parents(hw); i++) {
357 struct clk_hw *parent;
358 unsigned long parent_rate;
359
360 parent = clk_hw_get_parent_by_index(hw, i);
361 if (!parent)
362 continue;
363
364 parent_rate = clk_hw_get_rate(parent);
365 if (!parent_rate)
366 continue;
367
368 for (div = 1; div < ISC_CLK_MAX_DIV + 2; div++) {
369 unsigned long rate;
370 int diff;
371
372 rate = DIV_ROUND_CLOSEST(parent_rate, div);
373 diff = abs(req->rate - rate);
374
375 if (best_diff < 0 || best_diff > diff) {
376 best_rate = rate;
377 best_diff = diff;
378 req->best_parent_rate = parent_rate;
379 req->best_parent_hw = parent;
380 }
381
382 if (!best_diff || rate < req->rate)
383 break;
384 }
385
386 if (!best_diff)
387 break;
388 }
389
390 dev_dbg(isc_clk->dev,
391 "ISC CLK: %s, best_rate = %ld, parent clk: %s @ %ld\n",
392 __func__, best_rate,
393 __clk_get_name((req->best_parent_hw)->clk),
394 req->best_parent_rate);
395
396 if (best_rate < 0)
397 return best_rate;
398
399 req->rate = best_rate;
400
401 return 0;
402 }
403
isc_clk_set_parent(struct clk_hw * hw,u8 index)404 static int isc_clk_set_parent(struct clk_hw *hw, u8 index)
405 {
406 struct isc_clk *isc_clk = to_isc_clk(hw);
407
408 if (index >= clk_hw_get_num_parents(hw))
409 return -EINVAL;
410
411 isc_clk->parent_id = index;
412
413 return 0;
414 }
415
isc_clk_get_parent(struct clk_hw * hw)416 static u8 isc_clk_get_parent(struct clk_hw *hw)
417 {
418 struct isc_clk *isc_clk = to_isc_clk(hw);
419
420 return isc_clk->parent_id;
421 }
422
isc_clk_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)423 static int isc_clk_set_rate(struct clk_hw *hw,
424 unsigned long rate,
425 unsigned long parent_rate)
426 {
427 struct isc_clk *isc_clk = to_isc_clk(hw);
428 u32 div;
429
430 if (!rate)
431 return -EINVAL;
432
433 div = DIV_ROUND_CLOSEST(parent_rate, rate);
434 if (div > (ISC_CLK_MAX_DIV + 1) || !div)
435 return -EINVAL;
436
437 isc_clk->div = div - 1;
438
439 return 0;
440 }
441
442 static const struct clk_ops isc_clk_ops = {
443 .prepare = isc_clk_prepare,
444 .unprepare = isc_clk_unprepare,
445 .enable = isc_clk_enable,
446 .disable = isc_clk_disable,
447 .is_enabled = isc_clk_is_enabled,
448 .recalc_rate = isc_clk_recalc_rate,
449 .determine_rate = isc_clk_determine_rate,
450 .set_parent = isc_clk_set_parent,
451 .get_parent = isc_clk_get_parent,
452 .set_rate = isc_clk_set_rate,
453 };
454
isc_clk_register(struct isc_device * isc,unsigned int id)455 static int isc_clk_register(struct isc_device *isc, unsigned int id)
456 {
457 struct regmap *regmap = isc->regmap;
458 struct device_node *np = isc->dev->of_node;
459 struct isc_clk *isc_clk;
460 struct clk_init_data init;
461 const char *clk_name = np->name;
462 const char *parent_names[3];
463 int num_parents;
464
465 num_parents = of_clk_get_parent_count(np);
466 if (num_parents < 1 || num_parents > 3)
467 return -EINVAL;
468
469 if (num_parents > 2 && id == ISC_ISPCK)
470 num_parents = 2;
471
472 of_clk_parent_fill(np, parent_names, num_parents);
473
474 if (id == ISC_MCK)
475 of_property_read_string(np, "clock-output-names", &clk_name);
476 else
477 clk_name = "isc-ispck";
478
479 init.parent_names = parent_names;
480 init.num_parents = num_parents;
481 init.name = clk_name;
482 init.ops = &isc_clk_ops;
483 init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE;
484
485 isc_clk = &isc->isc_clks[id];
486 isc_clk->hw.init = &init;
487 isc_clk->regmap = regmap;
488 isc_clk->id = id;
489 isc_clk->dev = isc->dev;
490 spin_lock_init(&isc_clk->lock);
491
492 isc_clk->clk = clk_register(isc->dev, &isc_clk->hw);
493 if (IS_ERR(isc_clk->clk)) {
494 dev_err(isc->dev, "%s: clock register fail\n", clk_name);
495 return PTR_ERR(isc_clk->clk);
496 } else if (id == ISC_MCK)
497 of_clk_add_provider(np, of_clk_src_simple_get, isc_clk->clk);
498
499 return 0;
500 }
501
isc_clk_init(struct isc_device * isc)502 int isc_clk_init(struct isc_device *isc)
503 {
504 unsigned int i;
505 int ret;
506
507 for (i = 0; i < ARRAY_SIZE(isc->isc_clks); i++)
508 isc->isc_clks[i].clk = ERR_PTR(-EINVAL);
509
510 for (i = 0; i < ARRAY_SIZE(isc->isc_clks); i++) {
511 ret = isc_clk_register(isc, i);
512 if (ret)
513 return ret;
514 }
515
516 return 0;
517 }
518
isc_clk_cleanup(struct isc_device * isc)519 void isc_clk_cleanup(struct isc_device *isc)
520 {
521 unsigned int i;
522
523 of_clk_del_provider(isc->dev->of_node);
524
525 for (i = 0; i < ARRAY_SIZE(isc->isc_clks); i++) {
526 struct isc_clk *isc_clk = &isc->isc_clks[i];
527
528 if (!IS_ERR(isc_clk->clk))
529 clk_unregister(isc_clk->clk);
530 }
531 }
532
isc_queue_setup(struct vb2_queue * vq,unsigned int * nbuffers,unsigned int * nplanes,unsigned int sizes[],struct device * alloc_devs[])533 static int isc_queue_setup(struct vb2_queue *vq,
534 unsigned int *nbuffers, unsigned int *nplanes,
535 unsigned int sizes[], struct device *alloc_devs[])
536 {
537 struct isc_device *isc = vb2_get_drv_priv(vq);
538 unsigned int size = isc->fmt.fmt.pix.sizeimage;
539
540 if (*nplanes)
541 return sizes[0] < size ? -EINVAL : 0;
542
543 *nplanes = 1;
544 sizes[0] = size;
545
546 return 0;
547 }
548
isc_buffer_prepare(struct vb2_buffer * vb)549 static int isc_buffer_prepare(struct vb2_buffer *vb)
550 {
551 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
552 struct isc_device *isc = vb2_get_drv_priv(vb->vb2_queue);
553 unsigned long size = isc->fmt.fmt.pix.sizeimage;
554
555 if (vb2_plane_size(vb, 0) < size) {
556 v4l2_err(&isc->v4l2_dev, "buffer too small (%lu < %lu)\n",
557 vb2_plane_size(vb, 0), size);
558 return -EINVAL;
559 }
560
561 vb2_set_plane_payload(vb, 0, size);
562
563 vbuf->field = isc->fmt.fmt.pix.field;
564
565 return 0;
566 }
567
isc_start_dma(struct isc_device * isc)568 static void isc_start_dma(struct isc_device *isc)
569 {
570 struct regmap *regmap = isc->regmap;
571 u32 sizeimage = isc->fmt.fmt.pix.sizeimage;
572 u32 dctrl_dview;
573 dma_addr_t addr0;
574 u32 h, w;
575
576 h = isc->fmt.fmt.pix.height;
577 w = isc->fmt.fmt.pix.width;
578
579 /*
580 * In case the sensor is not RAW, it will output a pixel (12-16 bits)
581 * with two samples on the ISC Data bus (which is 8-12)
582 * ISC will count each sample, so, we need to multiply these values
583 * by two, to get the real number of samples for the required pixels.
584 */
585 if (!ISC_IS_FORMAT_RAW(isc->config.sd_format->mbus_code)) {
586 h <<= 1;
587 w <<= 1;
588 }
589
590 /*
591 * We limit the column/row count that the ISC will output according
592 * to the configured resolution that we want.
593 * This will avoid the situation where the sensor is misconfigured,
594 * sending more data, and the ISC will just take it and DMA to memory,
595 * causing corruption.
596 */
597 regmap_write(regmap, ISC_PFE_CFG1,
598 (ISC_PFE_CFG1_COLMIN(0) & ISC_PFE_CFG1_COLMIN_MASK) |
599 (ISC_PFE_CFG1_COLMAX(w - 1) & ISC_PFE_CFG1_COLMAX_MASK));
600
601 regmap_write(regmap, ISC_PFE_CFG2,
602 (ISC_PFE_CFG2_ROWMIN(0) & ISC_PFE_CFG2_ROWMIN_MASK) |
603 (ISC_PFE_CFG2_ROWMAX(h - 1) & ISC_PFE_CFG2_ROWMAX_MASK));
604
605 regmap_update_bits(regmap, ISC_PFE_CFG0,
606 ISC_PFE_CFG0_COLEN | ISC_PFE_CFG0_ROWEN,
607 ISC_PFE_CFG0_COLEN | ISC_PFE_CFG0_ROWEN);
608
609 addr0 = vb2_dma_contig_plane_dma_addr(&isc->cur_frm->vb.vb2_buf, 0);
610 regmap_write(regmap, ISC_DAD0, addr0);
611
612 switch (isc->config.fourcc) {
613 case V4L2_PIX_FMT_YUV420:
614 regmap_write(regmap, ISC_DAD1, addr0 + (sizeimage * 2) / 3);
615 regmap_write(regmap, ISC_DAD2, addr0 + (sizeimage * 5) / 6);
616 break;
617 case V4L2_PIX_FMT_YUV422P:
618 regmap_write(regmap, ISC_DAD1, addr0 + sizeimage / 2);
619 regmap_write(regmap, ISC_DAD2, addr0 + (sizeimage * 3) / 4);
620 break;
621 default:
622 break;
623 }
624
625 dctrl_dview = isc->config.dctrl_dview;
626
627 regmap_write(regmap, ISC_DCTRL, dctrl_dview | ISC_DCTRL_IE_IS);
628 spin_lock(&isc->awb_lock);
629 regmap_write(regmap, ISC_CTRLEN, ISC_CTRL_CAPTURE);
630 spin_unlock(&isc->awb_lock);
631 }
632
isc_set_pipeline(struct isc_device * isc,u32 pipeline)633 static void isc_set_pipeline(struct isc_device *isc, u32 pipeline)
634 {
635 struct regmap *regmap = isc->regmap;
636 struct isc_ctrls *ctrls = &isc->ctrls;
637 u32 val, bay_cfg;
638 const u32 *gamma;
639 unsigned int i;
640
641 /* WB-->CFA-->CC-->GAM-->CSC-->CBC-->SUB422-->SUB420 */
642 for (i = 0; i < ISC_PIPE_LINE_NODE_NUM; i++) {
643 val = pipeline & BIT(i) ? 1 : 0;
644 regmap_field_write(isc->pipeline[i], val);
645 }
646
647 if (!pipeline)
648 return;
649
650 bay_cfg = isc->config.sd_format->cfa_baycfg;
651
652 if (ctrls->awb == ISC_WB_NONE)
653 isc_reset_awb_ctrls(isc);
654
655 regmap_write(regmap, ISC_WB_CFG, bay_cfg);
656 isc_update_awb_ctrls(isc);
657
658 regmap_write(regmap, ISC_CFA_CFG, bay_cfg | ISC_CFA_CFG_EITPOL);
659
660 gamma = &isc_gamma_table[ctrls->gamma_index][0];
661 regmap_bulk_write(regmap, ISC_GAM_BENTRY, gamma, GAMMA_ENTRIES);
662 regmap_bulk_write(regmap, ISC_GAM_GENTRY, gamma, GAMMA_ENTRIES);
663 regmap_bulk_write(regmap, ISC_GAM_RENTRY, gamma, GAMMA_ENTRIES);
664
665 /* Convert RGB to YUV */
666 regmap_write(regmap, ISC_CSC_YR_YG, 0x42 | (0x81 << 16));
667 regmap_write(regmap, ISC_CSC_YB_OY, 0x19 | (0x10 << 16));
668 regmap_write(regmap, ISC_CSC_CBR_CBG, 0xFDA | (0xFB6 << 16));
669 regmap_write(regmap, ISC_CSC_CBB_OCB, 0x70 | (0x80 << 16));
670 regmap_write(regmap, ISC_CSC_CRR_CRG, 0x70 | (0xFA2 << 16));
671 regmap_write(regmap, ISC_CSC_CRB_OCR, 0xFEE | (0x80 << 16));
672
673 regmap_write(regmap, ISC_CBC_BRIGHT, ctrls->brightness);
674 regmap_write(regmap, ISC_CBC_CONTRAST, ctrls->contrast);
675 }
676
isc_update_profile(struct isc_device * isc)677 static int isc_update_profile(struct isc_device *isc)
678 {
679 struct regmap *regmap = isc->regmap;
680 u32 sr;
681 int counter = 100;
682
683 regmap_write(regmap, ISC_CTRLEN, ISC_CTRL_UPPRO);
684
685 regmap_read(regmap, ISC_CTRLSR, &sr);
686 while ((sr & ISC_CTRL_UPPRO) && counter--) {
687 usleep_range(1000, 2000);
688 regmap_read(regmap, ISC_CTRLSR, &sr);
689 }
690
691 if (counter < 0) {
692 v4l2_warn(&isc->v4l2_dev, "Time out to update profile\n");
693 return -ETIMEDOUT;
694 }
695
696 return 0;
697 }
698
isc_set_histogram(struct isc_device * isc,bool enable)699 static void isc_set_histogram(struct isc_device *isc, bool enable)
700 {
701 struct regmap *regmap = isc->regmap;
702 struct isc_ctrls *ctrls = &isc->ctrls;
703
704 if (enable) {
705 regmap_write(regmap, ISC_HIS_CFG,
706 ISC_HIS_CFG_MODE_GR |
707 (isc->config.sd_format->cfa_baycfg
708 << ISC_HIS_CFG_BAYSEL_SHIFT) |
709 ISC_HIS_CFG_RAR);
710 regmap_write(regmap, ISC_HIS_CTRL, ISC_HIS_CTRL_EN);
711 regmap_write(regmap, ISC_INTEN, ISC_INT_HISDONE);
712 ctrls->hist_id = ISC_HIS_CFG_MODE_GR;
713 isc_update_profile(isc);
714 regmap_write(regmap, ISC_CTRLEN, ISC_CTRL_HISREQ);
715
716 ctrls->hist_stat = HIST_ENABLED;
717 } else {
718 regmap_write(regmap, ISC_INTDIS, ISC_INT_HISDONE);
719 regmap_write(regmap, ISC_HIS_CTRL, ISC_HIS_CTRL_DIS);
720
721 ctrls->hist_stat = HIST_DISABLED;
722 }
723 }
724
isc_configure(struct isc_device * isc)725 static int isc_configure(struct isc_device *isc)
726 {
727 struct regmap *regmap = isc->regmap;
728 u32 pfe_cfg0, rlp_mode, dcfg, mask, pipeline;
729 struct isc_subdev_entity *subdev = isc->current_subdev;
730
731 pfe_cfg0 = isc->config.sd_format->pfe_cfg0_bps;
732 rlp_mode = isc->config.rlp_cfg_mode;
733 pipeline = isc->config.bits_pipeline;
734
735 dcfg = isc->config.dcfg_imode |
736 ISC_DCFG_YMBSIZE_BEATS8 | ISC_DCFG_CMBSIZE_BEATS8;
737
738 pfe_cfg0 |= subdev->pfe_cfg0 | ISC_PFE_CFG0_MODE_PROGRESSIVE;
739 mask = ISC_PFE_CFG0_BPS_MASK | ISC_PFE_CFG0_HPOL_LOW |
740 ISC_PFE_CFG0_VPOL_LOW | ISC_PFE_CFG0_PPOL_LOW |
741 ISC_PFE_CFG0_MODE_MASK | ISC_PFE_CFG0_CCIR_CRC |
742 ISC_PFE_CFG0_CCIR656;
743
744 regmap_update_bits(regmap, ISC_PFE_CFG0, mask, pfe_cfg0);
745
746 regmap_update_bits(regmap, ISC_RLP_CFG, ISC_RLP_CFG_MODE_MASK,
747 rlp_mode);
748
749 regmap_write(regmap, ISC_DCFG, dcfg);
750
751 /* Set the pipeline */
752 isc_set_pipeline(isc, pipeline);
753
754 /*
755 * The current implemented histogram is available for RAW R, B, GB, GR
756 * channels. We need to check if sensor is outputting RAW BAYER
757 */
758 if (isc->ctrls.awb &&
759 ISC_IS_FORMAT_RAW(isc->config.sd_format->mbus_code))
760 isc_set_histogram(isc, true);
761 else
762 isc_set_histogram(isc, false);
763
764 /* Update profile */
765 return isc_update_profile(isc);
766 }
767
isc_start_streaming(struct vb2_queue * vq,unsigned int count)768 static int isc_start_streaming(struct vb2_queue *vq, unsigned int count)
769 {
770 struct isc_device *isc = vb2_get_drv_priv(vq);
771 struct regmap *regmap = isc->regmap;
772 struct isc_buffer *buf;
773 unsigned long flags;
774 int ret;
775
776 /* Enable stream on the sub device */
777 ret = v4l2_subdev_call(isc->current_subdev->sd, video, s_stream, 1);
778 if (ret && ret != -ENOIOCTLCMD) {
779 v4l2_err(&isc->v4l2_dev, "stream on failed in subdev %d\n",
780 ret);
781 goto err_start_stream;
782 }
783
784 pm_runtime_get_sync(isc->dev);
785
786 ret = isc_configure(isc);
787 if (unlikely(ret))
788 goto err_configure;
789
790 /* Enable DMA interrupt */
791 regmap_write(regmap, ISC_INTEN, ISC_INT_DDONE);
792
793 spin_lock_irqsave(&isc->dma_queue_lock, flags);
794
795 isc->sequence = 0;
796 isc->stop = false;
797 reinit_completion(&isc->comp);
798
799 isc->cur_frm = list_first_entry(&isc->dma_queue,
800 struct isc_buffer, list);
801 list_del(&isc->cur_frm->list);
802
803 isc_start_dma(isc);
804
805 spin_unlock_irqrestore(&isc->dma_queue_lock, flags);
806
807 /* if we streaming from RAW, we can do one-shot white balance adj */
808 if (ISC_IS_FORMAT_RAW(isc->config.sd_format->mbus_code))
809 v4l2_ctrl_activate(isc->do_wb_ctrl, true);
810
811 return 0;
812
813 err_configure:
814 pm_runtime_put_sync(isc->dev);
815
816 v4l2_subdev_call(isc->current_subdev->sd, video, s_stream, 0);
817
818 err_start_stream:
819 spin_lock_irqsave(&isc->dma_queue_lock, flags);
820 list_for_each_entry(buf, &isc->dma_queue, list)
821 vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_QUEUED);
822 INIT_LIST_HEAD(&isc->dma_queue);
823 spin_unlock_irqrestore(&isc->dma_queue_lock, flags);
824
825 return ret;
826 }
827
isc_stop_streaming(struct vb2_queue * vq)828 static void isc_stop_streaming(struct vb2_queue *vq)
829 {
830 struct isc_device *isc = vb2_get_drv_priv(vq);
831 unsigned long flags;
832 struct isc_buffer *buf;
833 int ret;
834
835 v4l2_ctrl_activate(isc->do_wb_ctrl, false);
836
837 isc->stop = true;
838
839 /* Wait until the end of the current frame */
840 if (isc->cur_frm && !wait_for_completion_timeout(&isc->comp, 5 * HZ))
841 v4l2_err(&isc->v4l2_dev,
842 "Timeout waiting for end of the capture\n");
843
844 /* Disable DMA interrupt */
845 regmap_write(isc->regmap, ISC_INTDIS, ISC_INT_DDONE);
846
847 pm_runtime_put_sync(isc->dev);
848
849 /* Disable stream on the sub device */
850 ret = v4l2_subdev_call(isc->current_subdev->sd, video, s_stream, 0);
851 if (ret && ret != -ENOIOCTLCMD)
852 v4l2_err(&isc->v4l2_dev, "stream off failed in subdev\n");
853
854 /* Release all active buffers */
855 spin_lock_irqsave(&isc->dma_queue_lock, flags);
856 if (unlikely(isc->cur_frm)) {
857 vb2_buffer_done(&isc->cur_frm->vb.vb2_buf,
858 VB2_BUF_STATE_ERROR);
859 isc->cur_frm = NULL;
860 }
861 list_for_each_entry(buf, &isc->dma_queue, list)
862 vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR);
863 INIT_LIST_HEAD(&isc->dma_queue);
864 spin_unlock_irqrestore(&isc->dma_queue_lock, flags);
865 }
866
isc_buffer_queue(struct vb2_buffer * vb)867 static void isc_buffer_queue(struct vb2_buffer *vb)
868 {
869 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
870 struct isc_buffer *buf = container_of(vbuf, struct isc_buffer, vb);
871 struct isc_device *isc = vb2_get_drv_priv(vb->vb2_queue);
872 unsigned long flags;
873
874 spin_lock_irqsave(&isc->dma_queue_lock, flags);
875 if (!isc->cur_frm && list_empty(&isc->dma_queue) &&
876 vb2_is_streaming(vb->vb2_queue)) {
877 isc->cur_frm = buf;
878 isc_start_dma(isc);
879 } else
880 list_add_tail(&buf->list, &isc->dma_queue);
881 spin_unlock_irqrestore(&isc->dma_queue_lock, flags);
882 }
883
find_format_by_fourcc(struct isc_device * isc,unsigned int fourcc)884 static struct isc_format *find_format_by_fourcc(struct isc_device *isc,
885 unsigned int fourcc)
886 {
887 unsigned int num_formats = isc->num_user_formats;
888 struct isc_format *fmt;
889 unsigned int i;
890
891 for (i = 0; i < num_formats; i++) {
892 fmt = isc->user_formats[i];
893 if (fmt->fourcc == fourcc)
894 return fmt;
895 }
896
897 return NULL;
898 }
899
900 static const struct vb2_ops isc_vb2_ops = {
901 .queue_setup = isc_queue_setup,
902 .wait_prepare = vb2_ops_wait_prepare,
903 .wait_finish = vb2_ops_wait_finish,
904 .buf_prepare = isc_buffer_prepare,
905 .start_streaming = isc_start_streaming,
906 .stop_streaming = isc_stop_streaming,
907 .buf_queue = isc_buffer_queue,
908 };
909
isc_querycap(struct file * file,void * priv,struct v4l2_capability * cap)910 static int isc_querycap(struct file *file, void *priv,
911 struct v4l2_capability *cap)
912 {
913 struct isc_device *isc = video_drvdata(file);
914
915 strscpy(cap->driver, ATMEL_ISC_NAME, sizeof(cap->driver));
916 strscpy(cap->card, "Atmel Image Sensor Controller", sizeof(cap->card));
917 snprintf(cap->bus_info, sizeof(cap->bus_info),
918 "platform:%s", isc->v4l2_dev.name);
919
920 return 0;
921 }
922
isc_enum_fmt_vid_cap(struct file * file,void * priv,struct v4l2_fmtdesc * f)923 static int isc_enum_fmt_vid_cap(struct file *file, void *priv,
924 struct v4l2_fmtdesc *f)
925 {
926 u32 index = f->index;
927 u32 i, supported_index;
928
929 if (index < ARRAY_SIZE(controller_formats)) {
930 f->pixelformat = controller_formats[index].fourcc;
931 return 0;
932 }
933
934 index -= ARRAY_SIZE(controller_formats);
935
936 i = 0;
937 supported_index = 0;
938
939 for (i = 0; i < ARRAY_SIZE(formats_list); i++) {
940 if (!ISC_IS_FORMAT_RAW(formats_list[i].mbus_code) ||
941 !formats_list[i].sd_support)
942 continue;
943 if (supported_index == index) {
944 f->pixelformat = formats_list[i].fourcc;
945 return 0;
946 }
947 supported_index++;
948 }
949
950 return -EINVAL;
951 }
952
isc_g_fmt_vid_cap(struct file * file,void * priv,struct v4l2_format * fmt)953 static int isc_g_fmt_vid_cap(struct file *file, void *priv,
954 struct v4l2_format *fmt)
955 {
956 struct isc_device *isc = video_drvdata(file);
957
958 *fmt = isc->fmt;
959
960 return 0;
961 }
962
963 /*
964 * Checks the current configured format, if ISC can output it,
965 * considering which type of format the ISC receives from the sensor
966 */
isc_try_validate_formats(struct isc_device * isc)967 static int isc_try_validate_formats(struct isc_device *isc)
968 {
969 int ret;
970 bool bayer = false, yuv = false, rgb = false, grey = false;
971
972 /* all formats supported by the RLP module are OK */
973 switch (isc->try_config.fourcc) {
974 case V4L2_PIX_FMT_SBGGR8:
975 case V4L2_PIX_FMT_SGBRG8:
976 case V4L2_PIX_FMT_SGRBG8:
977 case V4L2_PIX_FMT_SRGGB8:
978 case V4L2_PIX_FMT_SBGGR10:
979 case V4L2_PIX_FMT_SGBRG10:
980 case V4L2_PIX_FMT_SGRBG10:
981 case V4L2_PIX_FMT_SRGGB10:
982 case V4L2_PIX_FMT_SBGGR12:
983 case V4L2_PIX_FMT_SGBRG12:
984 case V4L2_PIX_FMT_SGRBG12:
985 case V4L2_PIX_FMT_SRGGB12:
986 ret = 0;
987 bayer = true;
988 break;
989
990 case V4L2_PIX_FMT_YUV420:
991 case V4L2_PIX_FMT_YUV422P:
992 case V4L2_PIX_FMT_YUYV:
993 ret = 0;
994 yuv = true;
995 break;
996
997 case V4L2_PIX_FMT_RGB565:
998 case V4L2_PIX_FMT_ABGR32:
999 case V4L2_PIX_FMT_XBGR32:
1000 case V4L2_PIX_FMT_ARGB444:
1001 case V4L2_PIX_FMT_ARGB555:
1002 ret = 0;
1003 rgb = true;
1004 break;
1005 case V4L2_PIX_FMT_GREY:
1006 ret = 0;
1007 grey = true;
1008 break;
1009 default:
1010 /* any other different formats are not supported */
1011 ret = -EINVAL;
1012 }
1013
1014 /* we cannot output RAW/Grey if we do not receive RAW */
1015 if ((bayer || grey) &&
1016 !ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code))
1017 return -EINVAL;
1018
1019 v4l2_dbg(1, debug, &isc->v4l2_dev,
1020 "Format validation, requested rgb=%u, yuv=%u, grey=%u, bayer=%u\n",
1021 rgb, yuv, grey, bayer);
1022
1023 return ret;
1024 }
1025
1026 /*
1027 * Configures the RLP and DMA modules, depending on the output format
1028 * configured for the ISC.
1029 * If direct_dump == true, just dump raw data 8 bits.
1030 */
isc_try_configure_rlp_dma(struct isc_device * isc,bool direct_dump)1031 static int isc_try_configure_rlp_dma(struct isc_device *isc, bool direct_dump)
1032 {
1033 if (direct_dump) {
1034 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_DAT8;
1035 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED8;
1036 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
1037 isc->try_config.bpp = 16;
1038 return 0;
1039 }
1040
1041 switch (isc->try_config.fourcc) {
1042 case V4L2_PIX_FMT_SBGGR8:
1043 case V4L2_PIX_FMT_SGBRG8:
1044 case V4L2_PIX_FMT_SGRBG8:
1045 case V4L2_PIX_FMT_SRGGB8:
1046 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_DAT8;
1047 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED8;
1048 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
1049 isc->try_config.bpp = 8;
1050 break;
1051 case V4L2_PIX_FMT_SBGGR10:
1052 case V4L2_PIX_FMT_SGBRG10:
1053 case V4L2_PIX_FMT_SGRBG10:
1054 case V4L2_PIX_FMT_SRGGB10:
1055 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_DAT10;
1056 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED16;
1057 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
1058 isc->try_config.bpp = 16;
1059 break;
1060 case V4L2_PIX_FMT_SBGGR12:
1061 case V4L2_PIX_FMT_SGBRG12:
1062 case V4L2_PIX_FMT_SGRBG12:
1063 case V4L2_PIX_FMT_SRGGB12:
1064 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_DAT12;
1065 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED16;
1066 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
1067 isc->try_config.bpp = 16;
1068 break;
1069 case V4L2_PIX_FMT_RGB565:
1070 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_RGB565;
1071 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED16;
1072 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
1073 isc->try_config.bpp = 16;
1074 break;
1075 case V4L2_PIX_FMT_ARGB444:
1076 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_ARGB444;
1077 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED16;
1078 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
1079 isc->try_config.bpp = 16;
1080 break;
1081 case V4L2_PIX_FMT_ARGB555:
1082 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_ARGB555;
1083 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED16;
1084 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
1085 isc->try_config.bpp = 16;
1086 break;
1087 case V4L2_PIX_FMT_ABGR32:
1088 case V4L2_PIX_FMT_XBGR32:
1089 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_ARGB32;
1090 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED32;
1091 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
1092 isc->try_config.bpp = 32;
1093 break;
1094 case V4L2_PIX_FMT_YUV420:
1095 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_YYCC;
1096 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_YC420P;
1097 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PLANAR;
1098 isc->try_config.bpp = 12;
1099 break;
1100 case V4L2_PIX_FMT_YUV422P:
1101 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_YYCC;
1102 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_YC422P;
1103 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PLANAR;
1104 isc->try_config.bpp = 16;
1105 break;
1106 case V4L2_PIX_FMT_YUYV:
1107 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_YYCC;
1108 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED32;
1109 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
1110 isc->try_config.bpp = 16;
1111 break;
1112 case V4L2_PIX_FMT_GREY:
1113 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_DATY8;
1114 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED8;
1115 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
1116 isc->try_config.bpp = 8;
1117 break;
1118 default:
1119 return -EINVAL;
1120 }
1121 return 0;
1122 }
1123
1124 /*
1125 * Configuring pipeline modules, depending on which format the ISC outputs
1126 * and considering which format it has as input from the sensor.
1127 */
isc_try_configure_pipeline(struct isc_device * isc)1128 static int isc_try_configure_pipeline(struct isc_device *isc)
1129 {
1130 switch (isc->try_config.fourcc) {
1131 case V4L2_PIX_FMT_RGB565:
1132 case V4L2_PIX_FMT_ARGB555:
1133 case V4L2_PIX_FMT_ARGB444:
1134 case V4L2_PIX_FMT_ABGR32:
1135 case V4L2_PIX_FMT_XBGR32:
1136 /* if sensor format is RAW, we convert inside ISC */
1137 if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) {
1138 isc->try_config.bits_pipeline = CFA_ENABLE |
1139 WB_ENABLE | GAM_ENABLES;
1140 } else {
1141 isc->try_config.bits_pipeline = 0x0;
1142 }
1143 break;
1144 case V4L2_PIX_FMT_YUV420:
1145 /* if sensor format is RAW, we convert inside ISC */
1146 if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) {
1147 isc->try_config.bits_pipeline = CFA_ENABLE |
1148 CSC_ENABLE | WB_ENABLE | GAM_ENABLES |
1149 SUB420_ENABLE | SUB422_ENABLE | CBC_ENABLE;
1150 } else {
1151 isc->try_config.bits_pipeline = 0x0;
1152 }
1153 break;
1154 case V4L2_PIX_FMT_YUV422P:
1155 /* if sensor format is RAW, we convert inside ISC */
1156 if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) {
1157 isc->try_config.bits_pipeline = CFA_ENABLE |
1158 CSC_ENABLE | WB_ENABLE | GAM_ENABLES |
1159 SUB422_ENABLE | CBC_ENABLE;
1160 } else {
1161 isc->try_config.bits_pipeline = 0x0;
1162 }
1163 break;
1164 case V4L2_PIX_FMT_YUYV:
1165 /* if sensor format is RAW, we convert inside ISC */
1166 if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) {
1167 isc->try_config.bits_pipeline = CFA_ENABLE |
1168 CSC_ENABLE | WB_ENABLE | GAM_ENABLES |
1169 SUB422_ENABLE | CBC_ENABLE;
1170 } else {
1171 isc->try_config.bits_pipeline = 0x0;
1172 }
1173 break;
1174 case V4L2_PIX_FMT_GREY:
1175 if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) {
1176 /* if sensor format is RAW, we convert inside ISC */
1177 isc->try_config.bits_pipeline = CFA_ENABLE |
1178 CSC_ENABLE | WB_ENABLE | GAM_ENABLES |
1179 CBC_ENABLE;
1180 } else {
1181 isc->try_config.bits_pipeline = 0x0;
1182 }
1183 break;
1184 default:
1185 isc->try_config.bits_pipeline = 0x0;
1186 }
1187 return 0;
1188 }
1189
isc_try_fmt(struct isc_device * isc,struct v4l2_format * f,u32 * code)1190 static int isc_try_fmt(struct isc_device *isc, struct v4l2_format *f,
1191 u32 *code)
1192 {
1193 int i;
1194 struct isc_format *sd_fmt = NULL, *direct_fmt = NULL;
1195 struct v4l2_pix_format *pixfmt = &f->fmt.pix;
1196 struct v4l2_subdev_pad_config pad_cfg;
1197 struct v4l2_subdev_format format = {
1198 .which = V4L2_SUBDEV_FORMAT_TRY,
1199 };
1200 u32 mbus_code;
1201 int ret;
1202 bool rlp_dma_direct_dump = false;
1203
1204 if (f->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
1205 return -EINVAL;
1206
1207 /* Step 1: find a RAW format that is supported */
1208 for (i = 0; i < isc->num_user_formats; i++) {
1209 if (ISC_IS_FORMAT_RAW(isc->user_formats[i]->mbus_code)) {
1210 sd_fmt = isc->user_formats[i];
1211 break;
1212 }
1213 }
1214 /* Step 2: We can continue with this RAW format, or we can look
1215 * for better: maybe sensor supports directly what we need.
1216 */
1217 direct_fmt = find_format_by_fourcc(isc, pixfmt->pixelformat);
1218
1219 /* Step 3: We have both. We decide given the module parameter which
1220 * one to use.
1221 */
1222 if (direct_fmt && sd_fmt && sensor_preferred)
1223 sd_fmt = direct_fmt;
1224
1225 /* Step 4: we do not have RAW but we have a direct format. Use it. */
1226 if (direct_fmt && !sd_fmt)
1227 sd_fmt = direct_fmt;
1228
1229 /* Step 5: if we are using a direct format, we need to package
1230 * everything as 8 bit data and just dump it
1231 */
1232 if (sd_fmt == direct_fmt)
1233 rlp_dma_direct_dump = true;
1234
1235 /* Step 6: We have no format. This can happen if the userspace
1236 * requests some weird/invalid format.
1237 * In this case, default to whatever we have
1238 */
1239 if (!sd_fmt && !direct_fmt) {
1240 sd_fmt = isc->user_formats[isc->num_user_formats - 1];
1241 v4l2_dbg(1, debug, &isc->v4l2_dev,
1242 "Sensor not supporting %.4s, using %.4s\n",
1243 (char *)&pixfmt->pixelformat, (char *)&sd_fmt->fourcc);
1244 }
1245
1246 if (!sd_fmt) {
1247 ret = -EINVAL;
1248 goto isc_try_fmt_err;
1249 }
1250
1251 /* Step 7: Print out what we decided for debugging */
1252 v4l2_dbg(1, debug, &isc->v4l2_dev,
1253 "Preferring to have sensor using format %.4s\n",
1254 (char *)&sd_fmt->fourcc);
1255
1256 /* Step 8: at this moment we decided which format the subdev will use */
1257 isc->try_config.sd_format = sd_fmt;
1258
1259 /* Limit to Atmel ISC hardware capabilities */
1260 if (pixfmt->width > ISC_MAX_SUPPORT_WIDTH)
1261 pixfmt->width = ISC_MAX_SUPPORT_WIDTH;
1262 if (pixfmt->height > ISC_MAX_SUPPORT_HEIGHT)
1263 pixfmt->height = ISC_MAX_SUPPORT_HEIGHT;
1264
1265 /*
1266 * The mbus format is the one the subdev outputs.
1267 * The pixels will be transferred in this format Sensor -> ISC
1268 */
1269 mbus_code = sd_fmt->mbus_code;
1270
1271 /*
1272 * Validate formats. If the required format is not OK, default to raw.
1273 */
1274
1275 isc->try_config.fourcc = pixfmt->pixelformat;
1276
1277 if (isc_try_validate_formats(isc)) {
1278 pixfmt->pixelformat = isc->try_config.fourcc = sd_fmt->fourcc;
1279 /* Re-try to validate the new format */
1280 ret = isc_try_validate_formats(isc);
1281 if (ret)
1282 goto isc_try_fmt_err;
1283 }
1284
1285 ret = isc_try_configure_rlp_dma(isc, rlp_dma_direct_dump);
1286 if (ret)
1287 goto isc_try_fmt_err;
1288
1289 ret = isc_try_configure_pipeline(isc);
1290 if (ret)
1291 goto isc_try_fmt_err;
1292
1293 v4l2_fill_mbus_format(&format.format, pixfmt, mbus_code);
1294 ret = v4l2_subdev_call(isc->current_subdev->sd, pad, set_fmt,
1295 &pad_cfg, &format);
1296 if (ret < 0)
1297 goto isc_try_fmt_subdev_err;
1298
1299 v4l2_fill_pix_format(pixfmt, &format.format);
1300
1301 pixfmt->field = V4L2_FIELD_NONE;
1302 pixfmt->bytesperline = (pixfmt->width * isc->try_config.bpp) >> 3;
1303 pixfmt->sizeimage = pixfmt->bytesperline * pixfmt->height;
1304
1305 if (code)
1306 *code = mbus_code;
1307
1308 return 0;
1309
1310 isc_try_fmt_err:
1311 v4l2_err(&isc->v4l2_dev, "Could not find any possible format for a working pipeline\n");
1312 isc_try_fmt_subdev_err:
1313 memset(&isc->try_config, 0, sizeof(isc->try_config));
1314
1315 return ret;
1316 }
1317
isc_set_fmt(struct isc_device * isc,struct v4l2_format * f)1318 static int isc_set_fmt(struct isc_device *isc, struct v4l2_format *f)
1319 {
1320 struct v4l2_subdev_format format = {
1321 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
1322 };
1323 u32 mbus_code = 0;
1324 int ret;
1325
1326 ret = isc_try_fmt(isc, f, &mbus_code);
1327 if (ret)
1328 return ret;
1329
1330 v4l2_fill_mbus_format(&format.format, &f->fmt.pix, mbus_code);
1331 ret = v4l2_subdev_call(isc->current_subdev->sd, pad,
1332 set_fmt, NULL, &format);
1333 if (ret < 0)
1334 return ret;
1335
1336 isc->fmt = *f;
1337
1338 if (isc->try_config.sd_format && isc->config.sd_format &&
1339 isc->try_config.sd_format != isc->config.sd_format) {
1340 isc->ctrls.hist_stat = HIST_INIT;
1341 isc_reset_awb_ctrls(isc);
1342 }
1343 /* make the try configuration active */
1344 isc->config = isc->try_config;
1345
1346 v4l2_dbg(1, debug, &isc->v4l2_dev, "New ISC configuration in place\n");
1347
1348 return 0;
1349 }
1350
isc_s_fmt_vid_cap(struct file * file,void * priv,struct v4l2_format * f)1351 static int isc_s_fmt_vid_cap(struct file *file, void *priv,
1352 struct v4l2_format *f)
1353 {
1354 struct isc_device *isc = video_drvdata(file);
1355
1356 if (vb2_is_streaming(&isc->vb2_vidq))
1357 return -EBUSY;
1358
1359 return isc_set_fmt(isc, f);
1360 }
1361
isc_try_fmt_vid_cap(struct file * file,void * priv,struct v4l2_format * f)1362 static int isc_try_fmt_vid_cap(struct file *file, void *priv,
1363 struct v4l2_format *f)
1364 {
1365 struct isc_device *isc = video_drvdata(file);
1366
1367 return isc_try_fmt(isc, f, NULL);
1368 }
1369
isc_enum_input(struct file * file,void * priv,struct v4l2_input * inp)1370 static int isc_enum_input(struct file *file, void *priv,
1371 struct v4l2_input *inp)
1372 {
1373 if (inp->index != 0)
1374 return -EINVAL;
1375
1376 inp->type = V4L2_INPUT_TYPE_CAMERA;
1377 inp->std = 0;
1378 strscpy(inp->name, "Camera", sizeof(inp->name));
1379
1380 return 0;
1381 }
1382
isc_g_input(struct file * file,void * priv,unsigned int * i)1383 static int isc_g_input(struct file *file, void *priv, unsigned int *i)
1384 {
1385 *i = 0;
1386
1387 return 0;
1388 }
1389
isc_s_input(struct file * file,void * priv,unsigned int i)1390 static int isc_s_input(struct file *file, void *priv, unsigned int i)
1391 {
1392 if (i > 0)
1393 return -EINVAL;
1394
1395 return 0;
1396 }
1397
isc_g_parm(struct file * file,void * fh,struct v4l2_streamparm * a)1398 static int isc_g_parm(struct file *file, void *fh, struct v4l2_streamparm *a)
1399 {
1400 struct isc_device *isc = video_drvdata(file);
1401
1402 return v4l2_g_parm_cap(video_devdata(file), isc->current_subdev->sd, a);
1403 }
1404
isc_s_parm(struct file * file,void * fh,struct v4l2_streamparm * a)1405 static int isc_s_parm(struct file *file, void *fh, struct v4l2_streamparm *a)
1406 {
1407 struct isc_device *isc = video_drvdata(file);
1408
1409 return v4l2_s_parm_cap(video_devdata(file), isc->current_subdev->sd, a);
1410 }
1411
isc_enum_framesizes(struct file * file,void * fh,struct v4l2_frmsizeenum * fsize)1412 static int isc_enum_framesizes(struct file *file, void *fh,
1413 struct v4l2_frmsizeenum *fsize)
1414 {
1415 struct isc_device *isc = video_drvdata(file);
1416 struct v4l2_subdev_frame_size_enum fse = {
1417 .index = fsize->index,
1418 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
1419 };
1420 int ret = -EINVAL;
1421 int i;
1422
1423 for (i = 0; i < isc->num_user_formats; i++)
1424 if (isc->user_formats[i]->fourcc == fsize->pixel_format)
1425 ret = 0;
1426
1427 for (i = 0; i < ARRAY_SIZE(controller_formats); i++)
1428 if (controller_formats[i].fourcc == fsize->pixel_format)
1429 ret = 0;
1430
1431 if (ret)
1432 return ret;
1433
1434 ret = v4l2_subdev_call(isc->current_subdev->sd, pad, enum_frame_size,
1435 NULL, &fse);
1436 if (ret)
1437 return ret;
1438
1439 fse.code = isc->config.sd_format->mbus_code;
1440
1441 fsize->type = V4L2_FRMSIZE_TYPE_DISCRETE;
1442 fsize->discrete.width = fse.max_width;
1443 fsize->discrete.height = fse.max_height;
1444
1445 return 0;
1446 }
1447
isc_enum_frameintervals(struct file * file,void * fh,struct v4l2_frmivalenum * fival)1448 static int isc_enum_frameintervals(struct file *file, void *fh,
1449 struct v4l2_frmivalenum *fival)
1450 {
1451 struct isc_device *isc = video_drvdata(file);
1452 struct v4l2_subdev_frame_interval_enum fie = {
1453 .index = fival->index,
1454 .width = fival->width,
1455 .height = fival->height,
1456 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
1457 };
1458 int ret = -EINVAL;
1459 unsigned int i;
1460
1461 for (i = 0; i < isc->num_user_formats; i++)
1462 if (isc->user_formats[i]->fourcc == fival->pixel_format)
1463 ret = 0;
1464
1465 for (i = 0; i < ARRAY_SIZE(controller_formats); i++)
1466 if (controller_formats[i].fourcc == fival->pixel_format)
1467 ret = 0;
1468
1469 if (ret)
1470 return ret;
1471
1472 ret = v4l2_subdev_call(isc->current_subdev->sd, pad,
1473 enum_frame_interval, NULL, &fie);
1474 if (ret)
1475 return ret;
1476
1477 fie.code = isc->config.sd_format->mbus_code;
1478 fival->type = V4L2_FRMIVAL_TYPE_DISCRETE;
1479 fival->discrete = fie.interval;
1480
1481 return 0;
1482 }
1483
1484 static const struct v4l2_ioctl_ops isc_ioctl_ops = {
1485 .vidioc_querycap = isc_querycap,
1486 .vidioc_enum_fmt_vid_cap = isc_enum_fmt_vid_cap,
1487 .vidioc_g_fmt_vid_cap = isc_g_fmt_vid_cap,
1488 .vidioc_s_fmt_vid_cap = isc_s_fmt_vid_cap,
1489 .vidioc_try_fmt_vid_cap = isc_try_fmt_vid_cap,
1490
1491 .vidioc_enum_input = isc_enum_input,
1492 .vidioc_g_input = isc_g_input,
1493 .vidioc_s_input = isc_s_input,
1494
1495 .vidioc_reqbufs = vb2_ioctl_reqbufs,
1496 .vidioc_querybuf = vb2_ioctl_querybuf,
1497 .vidioc_qbuf = vb2_ioctl_qbuf,
1498 .vidioc_expbuf = vb2_ioctl_expbuf,
1499 .vidioc_dqbuf = vb2_ioctl_dqbuf,
1500 .vidioc_create_bufs = vb2_ioctl_create_bufs,
1501 .vidioc_prepare_buf = vb2_ioctl_prepare_buf,
1502 .vidioc_streamon = vb2_ioctl_streamon,
1503 .vidioc_streamoff = vb2_ioctl_streamoff,
1504
1505 .vidioc_g_parm = isc_g_parm,
1506 .vidioc_s_parm = isc_s_parm,
1507 .vidioc_enum_framesizes = isc_enum_framesizes,
1508 .vidioc_enum_frameintervals = isc_enum_frameintervals,
1509
1510 .vidioc_log_status = v4l2_ctrl_log_status,
1511 .vidioc_subscribe_event = v4l2_ctrl_subscribe_event,
1512 .vidioc_unsubscribe_event = v4l2_event_unsubscribe,
1513 };
1514
isc_open(struct file * file)1515 static int isc_open(struct file *file)
1516 {
1517 struct isc_device *isc = video_drvdata(file);
1518 struct v4l2_subdev *sd = isc->current_subdev->sd;
1519 int ret;
1520
1521 if (mutex_lock_interruptible(&isc->lock))
1522 return -ERESTARTSYS;
1523
1524 ret = v4l2_fh_open(file);
1525 if (ret < 0)
1526 goto unlock;
1527
1528 if (!v4l2_fh_is_singular_file(file))
1529 goto unlock;
1530
1531 ret = v4l2_subdev_call(sd, core, s_power, 1);
1532 if (ret < 0 && ret != -ENOIOCTLCMD) {
1533 v4l2_fh_release(file);
1534 goto unlock;
1535 }
1536
1537 ret = isc_set_fmt(isc, &isc->fmt);
1538 if (ret) {
1539 v4l2_subdev_call(sd, core, s_power, 0);
1540 v4l2_fh_release(file);
1541 }
1542
1543 unlock:
1544 mutex_unlock(&isc->lock);
1545 return ret;
1546 }
1547
isc_release(struct file * file)1548 static int isc_release(struct file *file)
1549 {
1550 struct isc_device *isc = video_drvdata(file);
1551 struct v4l2_subdev *sd = isc->current_subdev->sd;
1552 bool fh_singular;
1553 int ret;
1554
1555 mutex_lock(&isc->lock);
1556
1557 fh_singular = v4l2_fh_is_singular_file(file);
1558
1559 ret = _vb2_fop_release(file, NULL);
1560
1561 if (fh_singular)
1562 v4l2_subdev_call(sd, core, s_power, 0);
1563
1564 mutex_unlock(&isc->lock);
1565
1566 return ret;
1567 }
1568
1569 static const struct v4l2_file_operations isc_fops = {
1570 .owner = THIS_MODULE,
1571 .open = isc_open,
1572 .release = isc_release,
1573 .unlocked_ioctl = video_ioctl2,
1574 .read = vb2_fop_read,
1575 .mmap = vb2_fop_mmap,
1576 .poll = vb2_fop_poll,
1577 };
1578
isc_interrupt(int irq,void * dev_id)1579 irqreturn_t isc_interrupt(int irq, void *dev_id)
1580 {
1581 struct isc_device *isc = (struct isc_device *)dev_id;
1582 struct regmap *regmap = isc->regmap;
1583 u32 isc_intsr, isc_intmask, pending;
1584 irqreturn_t ret = IRQ_NONE;
1585
1586 regmap_read(regmap, ISC_INTSR, &isc_intsr);
1587 regmap_read(regmap, ISC_INTMASK, &isc_intmask);
1588
1589 pending = isc_intsr & isc_intmask;
1590
1591 if (likely(pending & ISC_INT_DDONE)) {
1592 spin_lock(&isc->dma_queue_lock);
1593 if (isc->cur_frm) {
1594 struct vb2_v4l2_buffer *vbuf = &isc->cur_frm->vb;
1595 struct vb2_buffer *vb = &vbuf->vb2_buf;
1596
1597 vb->timestamp = ktime_get_ns();
1598 vbuf->sequence = isc->sequence++;
1599 vb2_buffer_done(vb, VB2_BUF_STATE_DONE);
1600 isc->cur_frm = NULL;
1601 }
1602
1603 if (!list_empty(&isc->dma_queue) && !isc->stop) {
1604 isc->cur_frm = list_first_entry(&isc->dma_queue,
1605 struct isc_buffer, list);
1606 list_del(&isc->cur_frm->list);
1607
1608 isc_start_dma(isc);
1609 }
1610
1611 if (isc->stop)
1612 complete(&isc->comp);
1613
1614 ret = IRQ_HANDLED;
1615 spin_unlock(&isc->dma_queue_lock);
1616 }
1617
1618 if (pending & ISC_INT_HISDONE) {
1619 schedule_work(&isc->awb_work);
1620 ret = IRQ_HANDLED;
1621 }
1622
1623 return ret;
1624 }
1625
isc_hist_count(struct isc_device * isc,u32 * min,u32 * max)1626 static void isc_hist_count(struct isc_device *isc, u32 *min, u32 *max)
1627 {
1628 struct regmap *regmap = isc->regmap;
1629 struct isc_ctrls *ctrls = &isc->ctrls;
1630 u32 *hist_count = &ctrls->hist_count[ctrls->hist_id];
1631 u32 *hist_entry = &ctrls->hist_entry[0];
1632 u32 i;
1633
1634 *min = 0;
1635 *max = HIST_ENTRIES;
1636
1637 regmap_bulk_read(regmap, ISC_HIS_ENTRY, hist_entry, HIST_ENTRIES);
1638
1639 *hist_count = 0;
1640 /*
1641 * we deliberately ignore the end of the histogram,
1642 * the most white pixels
1643 */
1644 for (i = 1; i < HIST_ENTRIES; i++) {
1645 if (*hist_entry && !*min)
1646 *min = i;
1647 if (*hist_entry)
1648 *max = i;
1649 *hist_count += i * (*hist_entry++);
1650 }
1651
1652 if (!*min)
1653 *min = 1;
1654 }
1655
isc_wb_update(struct isc_ctrls * ctrls)1656 static void isc_wb_update(struct isc_ctrls *ctrls)
1657 {
1658 u32 *hist_count = &ctrls->hist_count[0];
1659 u32 c, offset[4];
1660 u64 avg = 0;
1661 /* We compute two gains, stretch gain and grey world gain */
1662 u32 s_gain[4], gw_gain[4];
1663
1664 /*
1665 * According to Grey World, we need to set gains for R/B to normalize
1666 * them towards the green channel.
1667 * Thus we want to keep Green as fixed and adjust only Red/Blue
1668 * Compute the average of the both green channels first
1669 */
1670 avg = (u64)hist_count[ISC_HIS_CFG_MODE_GR] +
1671 (u64)hist_count[ISC_HIS_CFG_MODE_GB];
1672 avg >>= 1;
1673
1674 /* Green histogram is null, nothing to do */
1675 if (!avg)
1676 return;
1677
1678 for (c = ISC_HIS_CFG_MODE_GR; c <= ISC_HIS_CFG_MODE_B; c++) {
1679 /*
1680 * the color offset is the minimum value of the histogram.
1681 * we stretch this color to the full range by substracting
1682 * this value from the color component.
1683 */
1684 offset[c] = ctrls->hist_minmax[c][HIST_MIN_INDEX];
1685 /*
1686 * The offset is always at least 1. If the offset is 1, we do
1687 * not need to adjust it, so our result must be zero.
1688 * the offset is computed in a histogram on 9 bits (0..512)
1689 * but the offset in register is based on
1690 * 12 bits pipeline (0..4096).
1691 * we need to shift with the 3 bits that the histogram is
1692 * ignoring
1693 */
1694 ctrls->offset[c] = (offset[c] - 1) << 3;
1695
1696 /* the offset is then taken and converted to 2's complements */
1697 if (!ctrls->offset[c])
1698 ctrls->offset[c] = ISC_WB_O_ZERO_VAL;
1699
1700 /*
1701 * the stretch gain is the total number of histogram bins
1702 * divided by the actual range of color component (Max - Min)
1703 * If we compute gain like this, the actual color component
1704 * will be stretched to the full histogram.
1705 * We need to shift 9 bits for precision, we have 9 bits for
1706 * decimals
1707 */
1708 s_gain[c] = (HIST_ENTRIES << 9) /
1709 (ctrls->hist_minmax[c][HIST_MAX_INDEX] -
1710 ctrls->hist_minmax[c][HIST_MIN_INDEX] + 1);
1711
1712 /*
1713 * Now we have to compute the gain w.r.t. the average.
1714 * Add/lose gain to the component towards the average.
1715 * If it happens that the component is zero, use the
1716 * fixed point value : 1.0 gain.
1717 */
1718 if (hist_count[c])
1719 gw_gain[c] = div_u64(avg << 9, hist_count[c]);
1720 else
1721 gw_gain[c] = 1 << 9;
1722
1723 /* multiply both gains and adjust for decimals */
1724 ctrls->gain[c] = s_gain[c] * gw_gain[c];
1725 ctrls->gain[c] >>= 9;
1726 }
1727 }
1728
isc_awb_work(struct work_struct * w)1729 static void isc_awb_work(struct work_struct *w)
1730 {
1731 struct isc_device *isc =
1732 container_of(w, struct isc_device, awb_work);
1733 struct regmap *regmap = isc->regmap;
1734 struct isc_ctrls *ctrls = &isc->ctrls;
1735 u32 hist_id = ctrls->hist_id;
1736 u32 baysel;
1737 unsigned long flags;
1738 u32 min, max;
1739
1740 /* streaming is not active anymore */
1741 if (isc->stop)
1742 return;
1743
1744 if (ctrls->hist_stat != HIST_ENABLED)
1745 return;
1746
1747 isc_hist_count(isc, &min, &max);
1748 ctrls->hist_minmax[hist_id][HIST_MIN_INDEX] = min;
1749 ctrls->hist_minmax[hist_id][HIST_MAX_INDEX] = max;
1750
1751 if (hist_id != ISC_HIS_CFG_MODE_B) {
1752 hist_id++;
1753 } else {
1754 isc_wb_update(ctrls);
1755 hist_id = ISC_HIS_CFG_MODE_GR;
1756 }
1757
1758 ctrls->hist_id = hist_id;
1759 baysel = isc->config.sd_format->cfa_baycfg << ISC_HIS_CFG_BAYSEL_SHIFT;
1760
1761 /* if no more auto white balance, reset controls. */
1762 if (ctrls->awb == ISC_WB_NONE)
1763 isc_reset_awb_ctrls(isc);
1764
1765 pm_runtime_get_sync(isc->dev);
1766
1767 /*
1768 * only update if we have all the required histograms and controls
1769 * if awb has been disabled, we need to reset registers as well.
1770 */
1771 if (hist_id == ISC_HIS_CFG_MODE_GR || ctrls->awb == ISC_WB_NONE) {
1772 /*
1773 * It may happen that DMA Done IRQ will trigger while we are
1774 * updating white balance registers here.
1775 * In that case, only parts of the controls have been updated.
1776 * We can avoid that by locking the section.
1777 */
1778 spin_lock_irqsave(&isc->awb_lock, flags);
1779 isc_update_awb_ctrls(isc);
1780 spin_unlock_irqrestore(&isc->awb_lock, flags);
1781
1782 /*
1783 * if we are doing just the one time white balance adjustment,
1784 * we are basically done.
1785 */
1786 if (ctrls->awb == ISC_WB_ONETIME) {
1787 v4l2_info(&isc->v4l2_dev,
1788 "Completed one time white-balance adjustment.\n");
1789 ctrls->awb = ISC_WB_NONE;
1790 }
1791 }
1792 regmap_write(regmap, ISC_HIS_CFG, hist_id | baysel | ISC_HIS_CFG_RAR);
1793 isc_update_profile(isc);
1794 /* if awb has been disabled, we don't need to start another histogram */
1795 if (ctrls->awb)
1796 regmap_write(regmap, ISC_CTRLEN, ISC_CTRL_HISREQ);
1797
1798 pm_runtime_put_sync(isc->dev);
1799 }
1800
isc_s_ctrl(struct v4l2_ctrl * ctrl)1801 static int isc_s_ctrl(struct v4l2_ctrl *ctrl)
1802 {
1803 struct isc_device *isc = container_of(ctrl->handler,
1804 struct isc_device, ctrls.handler);
1805 struct isc_ctrls *ctrls = &isc->ctrls;
1806
1807 if (ctrl->flags & V4L2_CTRL_FLAG_INACTIVE)
1808 return 0;
1809
1810 switch (ctrl->id) {
1811 case V4L2_CID_BRIGHTNESS:
1812 ctrls->brightness = ctrl->val & ISC_CBC_BRIGHT_MASK;
1813 break;
1814 case V4L2_CID_CONTRAST:
1815 ctrls->contrast = ctrl->val & ISC_CBC_CONTRAST_MASK;
1816 break;
1817 case V4L2_CID_GAMMA:
1818 ctrls->gamma_index = ctrl->val;
1819 break;
1820 case V4L2_CID_AUTO_WHITE_BALANCE:
1821 if (ctrl->val == 1)
1822 ctrls->awb = ISC_WB_AUTO;
1823 else
1824 ctrls->awb = ISC_WB_NONE;
1825
1826 /* we did not configure ISC yet */
1827 if (!isc->config.sd_format)
1828 break;
1829
1830 if (ctrls->hist_stat != HIST_ENABLED)
1831 isc_reset_awb_ctrls(isc);
1832
1833 if (isc->ctrls.awb == ISC_WB_AUTO &&
1834 vb2_is_streaming(&isc->vb2_vidq) &&
1835 ISC_IS_FORMAT_RAW(isc->config.sd_format->mbus_code))
1836 isc_set_histogram(isc, true);
1837
1838 break;
1839 case V4L2_CID_DO_WHITE_BALANCE:
1840 /* if AWB is enabled, do nothing */
1841 if (ctrls->awb == ISC_WB_AUTO)
1842 return 0;
1843
1844 ctrls->awb = ISC_WB_ONETIME;
1845 isc_set_histogram(isc, true);
1846 v4l2_dbg(1, debug, &isc->v4l2_dev,
1847 "One time white-balance started.\n");
1848 break;
1849 default:
1850 return -EINVAL;
1851 }
1852
1853 return 0;
1854 }
1855
1856 static const struct v4l2_ctrl_ops isc_ctrl_ops = {
1857 .s_ctrl = isc_s_ctrl,
1858 };
1859
isc_ctrl_init(struct isc_device * isc)1860 static int isc_ctrl_init(struct isc_device *isc)
1861 {
1862 const struct v4l2_ctrl_ops *ops = &isc_ctrl_ops;
1863 struct isc_ctrls *ctrls = &isc->ctrls;
1864 struct v4l2_ctrl_handler *hdl = &ctrls->handler;
1865 int ret;
1866
1867 ctrls->hist_stat = HIST_INIT;
1868 isc_reset_awb_ctrls(isc);
1869
1870 ret = v4l2_ctrl_handler_init(hdl, 5);
1871 if (ret < 0)
1872 return ret;
1873
1874 ctrls->brightness = 0;
1875 ctrls->contrast = 256;
1876
1877 v4l2_ctrl_new_std(hdl, ops, V4L2_CID_BRIGHTNESS, -1024, 1023, 1, 0);
1878 v4l2_ctrl_new_std(hdl, ops, V4L2_CID_CONTRAST, -2048, 2047, 1, 256);
1879 v4l2_ctrl_new_std(hdl, ops, V4L2_CID_GAMMA, 0, GAMMA_MAX, 1, 2);
1880 v4l2_ctrl_new_std(hdl, ops, V4L2_CID_AUTO_WHITE_BALANCE, 0, 1, 1, 1);
1881
1882 /* do_white_balance is a button, so min,max,step,default are ignored */
1883 isc->do_wb_ctrl = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_DO_WHITE_BALANCE,
1884 0, 0, 0, 0);
1885
1886 if (!isc->do_wb_ctrl) {
1887 ret = hdl->error;
1888 v4l2_ctrl_handler_free(hdl);
1889 return ret;
1890 }
1891
1892 v4l2_ctrl_activate(isc->do_wb_ctrl, false);
1893
1894 v4l2_ctrl_handler_setup(hdl);
1895
1896 return 0;
1897 }
1898
isc_async_bound(struct v4l2_async_notifier * notifier,struct v4l2_subdev * subdev,struct v4l2_async_subdev * asd)1899 static int isc_async_bound(struct v4l2_async_notifier *notifier,
1900 struct v4l2_subdev *subdev,
1901 struct v4l2_async_subdev *asd)
1902 {
1903 struct isc_device *isc = container_of(notifier->v4l2_dev,
1904 struct isc_device, v4l2_dev);
1905 struct isc_subdev_entity *subdev_entity =
1906 container_of(notifier, struct isc_subdev_entity, notifier);
1907
1908 if (video_is_registered(&isc->video_dev)) {
1909 v4l2_err(&isc->v4l2_dev, "only supports one sub-device.\n");
1910 return -EBUSY;
1911 }
1912
1913 subdev_entity->sd = subdev;
1914
1915 return 0;
1916 }
1917
isc_async_unbind(struct v4l2_async_notifier * notifier,struct v4l2_subdev * subdev,struct v4l2_async_subdev * asd)1918 static void isc_async_unbind(struct v4l2_async_notifier *notifier,
1919 struct v4l2_subdev *subdev,
1920 struct v4l2_async_subdev *asd)
1921 {
1922 struct isc_device *isc = container_of(notifier->v4l2_dev,
1923 struct isc_device, v4l2_dev);
1924 cancel_work_sync(&isc->awb_work);
1925 video_unregister_device(&isc->video_dev);
1926 v4l2_ctrl_handler_free(&isc->ctrls.handler);
1927 }
1928
find_format_by_code(unsigned int code,int * index)1929 static struct isc_format *find_format_by_code(unsigned int code, int *index)
1930 {
1931 struct isc_format *fmt = &formats_list[0];
1932 unsigned int i;
1933
1934 for (i = 0; i < ARRAY_SIZE(formats_list); i++) {
1935 if (fmt->mbus_code == code) {
1936 *index = i;
1937 return fmt;
1938 }
1939
1940 fmt++;
1941 }
1942
1943 return NULL;
1944 }
1945
isc_formats_init(struct isc_device * isc)1946 static int isc_formats_init(struct isc_device *isc)
1947 {
1948 struct isc_format *fmt;
1949 struct v4l2_subdev *subdev = isc->current_subdev->sd;
1950 unsigned int num_fmts, i, j;
1951 u32 list_size = ARRAY_SIZE(formats_list);
1952 struct v4l2_subdev_mbus_code_enum mbus_code = {
1953 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
1954 };
1955
1956 num_fmts = 0;
1957 while (!v4l2_subdev_call(subdev, pad, enum_mbus_code,
1958 NULL, &mbus_code)) {
1959 mbus_code.index++;
1960
1961 fmt = find_format_by_code(mbus_code.code, &i);
1962 if (!fmt) {
1963 v4l2_warn(&isc->v4l2_dev, "Mbus code %x not supported\n",
1964 mbus_code.code);
1965 continue;
1966 }
1967
1968 fmt->sd_support = true;
1969 num_fmts++;
1970 }
1971
1972 if (!num_fmts)
1973 return -ENXIO;
1974
1975 isc->num_user_formats = num_fmts;
1976 isc->user_formats = devm_kcalloc(isc->dev,
1977 num_fmts, sizeof(*isc->user_formats),
1978 GFP_KERNEL);
1979 if (!isc->user_formats)
1980 return -ENOMEM;
1981
1982 fmt = &formats_list[0];
1983 for (i = 0, j = 0; i < list_size; i++) {
1984 if (fmt->sd_support)
1985 isc->user_formats[j++] = fmt;
1986 fmt++;
1987 }
1988
1989 return 0;
1990 }
1991
isc_set_default_fmt(struct isc_device * isc)1992 static int isc_set_default_fmt(struct isc_device *isc)
1993 {
1994 struct v4l2_format f = {
1995 .type = V4L2_BUF_TYPE_VIDEO_CAPTURE,
1996 .fmt.pix = {
1997 .width = VGA_WIDTH,
1998 .height = VGA_HEIGHT,
1999 .field = V4L2_FIELD_NONE,
2000 .pixelformat = isc->user_formats[0]->fourcc,
2001 },
2002 };
2003 int ret;
2004
2005 ret = isc_try_fmt(isc, &f, NULL);
2006 if (ret)
2007 return ret;
2008
2009 isc->fmt = f;
2010 return 0;
2011 }
2012
isc_async_complete(struct v4l2_async_notifier * notifier)2013 static int isc_async_complete(struct v4l2_async_notifier *notifier)
2014 {
2015 struct isc_device *isc = container_of(notifier->v4l2_dev,
2016 struct isc_device, v4l2_dev);
2017 struct video_device *vdev = &isc->video_dev;
2018 struct vb2_queue *q = &isc->vb2_vidq;
2019 int ret = 0;
2020
2021 INIT_WORK(&isc->awb_work, isc_awb_work);
2022
2023 ret = v4l2_device_register_subdev_nodes(&isc->v4l2_dev);
2024 if (ret < 0) {
2025 v4l2_err(&isc->v4l2_dev, "Failed to register subdev nodes\n");
2026 return ret;
2027 }
2028
2029 isc->current_subdev = container_of(notifier,
2030 struct isc_subdev_entity, notifier);
2031 mutex_init(&isc->lock);
2032 init_completion(&isc->comp);
2033
2034 /* Initialize videobuf2 queue */
2035 q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
2036 q->io_modes = VB2_MMAP | VB2_DMABUF | VB2_READ;
2037 q->drv_priv = isc;
2038 q->buf_struct_size = sizeof(struct isc_buffer);
2039 q->ops = &isc_vb2_ops;
2040 q->mem_ops = &vb2_dma_contig_memops;
2041 q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
2042 q->lock = &isc->lock;
2043 q->min_buffers_needed = 1;
2044 q->dev = isc->dev;
2045
2046 ret = vb2_queue_init(q);
2047 if (ret < 0) {
2048 v4l2_err(&isc->v4l2_dev,
2049 "vb2_queue_init() failed: %d\n", ret);
2050 goto isc_async_complete_err;
2051 }
2052
2053 /* Init video dma queues */
2054 INIT_LIST_HEAD(&isc->dma_queue);
2055 spin_lock_init(&isc->dma_queue_lock);
2056 spin_lock_init(&isc->awb_lock);
2057
2058 ret = isc_formats_init(isc);
2059 if (ret < 0) {
2060 v4l2_err(&isc->v4l2_dev,
2061 "Init format failed: %d\n", ret);
2062 goto isc_async_complete_err;
2063 }
2064
2065 ret = isc_set_default_fmt(isc);
2066 if (ret) {
2067 v4l2_err(&isc->v4l2_dev, "Could not set default format\n");
2068 goto isc_async_complete_err;
2069 }
2070
2071 ret = isc_ctrl_init(isc);
2072 if (ret) {
2073 v4l2_err(&isc->v4l2_dev, "Init isc ctrols failed: %d\n", ret);
2074 goto isc_async_complete_err;
2075 }
2076
2077 /* Register video device */
2078 strscpy(vdev->name, ATMEL_ISC_NAME, sizeof(vdev->name));
2079 vdev->release = video_device_release_empty;
2080 vdev->fops = &isc_fops;
2081 vdev->ioctl_ops = &isc_ioctl_ops;
2082 vdev->v4l2_dev = &isc->v4l2_dev;
2083 vdev->vfl_dir = VFL_DIR_RX;
2084 vdev->queue = q;
2085 vdev->lock = &isc->lock;
2086 vdev->ctrl_handler = &isc->ctrls.handler;
2087 vdev->device_caps = V4L2_CAP_STREAMING | V4L2_CAP_VIDEO_CAPTURE;
2088 video_set_drvdata(vdev, isc);
2089
2090 ret = video_register_device(vdev, VFL_TYPE_GRABBER, -1);
2091 if (ret < 0) {
2092 v4l2_err(&isc->v4l2_dev,
2093 "video_register_device failed: %d\n", ret);
2094 goto isc_async_complete_err;
2095 }
2096
2097 return 0;
2098
2099 isc_async_complete_err:
2100 mutex_destroy(&isc->lock);
2101 return ret;
2102 }
2103
2104 const struct v4l2_async_notifier_operations isc_async_ops = {
2105 .bound = isc_async_bound,
2106 .unbind = isc_async_unbind,
2107 .complete = isc_async_complete,
2108 };
2109
isc_subdev_cleanup(struct isc_device * isc)2110 void isc_subdev_cleanup(struct isc_device *isc)
2111 {
2112 struct isc_subdev_entity *subdev_entity;
2113
2114 list_for_each_entry(subdev_entity, &isc->subdev_entities, list) {
2115 v4l2_async_notifier_unregister(&subdev_entity->notifier);
2116 v4l2_async_notifier_cleanup(&subdev_entity->notifier);
2117 }
2118
2119 INIT_LIST_HEAD(&isc->subdev_entities);
2120 }
2121
isc_pipeline_init(struct isc_device * isc)2122 int isc_pipeline_init(struct isc_device *isc)
2123 {
2124 struct device *dev = isc->dev;
2125 struct regmap *regmap = isc->regmap;
2126 struct regmap_field *regs;
2127 unsigned int i;
2128
2129 /* WB-->CFA-->CC-->GAM-->CSC-->CBC-->SUB422-->SUB420 */
2130 const struct reg_field regfields[ISC_PIPE_LINE_NODE_NUM] = {
2131 REG_FIELD(ISC_WB_CTRL, 0, 0),
2132 REG_FIELD(ISC_CFA_CTRL, 0, 0),
2133 REG_FIELD(ISC_CC_CTRL, 0, 0),
2134 REG_FIELD(ISC_GAM_CTRL, 0, 0),
2135 REG_FIELD(ISC_GAM_CTRL, 1, 1),
2136 REG_FIELD(ISC_GAM_CTRL, 2, 2),
2137 REG_FIELD(ISC_GAM_CTRL, 3, 3),
2138 REG_FIELD(ISC_CSC_CTRL, 0, 0),
2139 REG_FIELD(ISC_CBC_CTRL, 0, 0),
2140 REG_FIELD(ISC_SUB422_CTRL, 0, 0),
2141 REG_FIELD(ISC_SUB420_CTRL, 0, 0),
2142 };
2143
2144 for (i = 0; i < ISC_PIPE_LINE_NODE_NUM; i++) {
2145 regs = devm_regmap_field_alloc(dev, regmap, regfields[i]);
2146 if (IS_ERR(regs))
2147 return PTR_ERR(regs);
2148
2149 isc->pipeline[i] = regs;
2150 }
2151
2152 return 0;
2153 }
2154
2155 /* regmap configuration */
2156 #define ATMEL_ISC_REG_MAX 0xbfc
2157 const struct regmap_config isc_regmap_config = {
2158 .reg_bits = 32,
2159 .reg_stride = 4,
2160 .val_bits = 32,
2161 .max_register = ATMEL_ISC_REG_MAX,
2162 };
2163
2164
