1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) 2018 Gateworks Corporation
4 */
5 #include <linux/delay.h>
6 #include <linux/hdmi.h>
7 #include <linux/i2c.h>
8 #include <linux/init.h>
9 #include <linux/interrupt.h>
10 #include <linux/kernel.h>
11 #include <linux/module.h>
12 #include <linux/of_graph.h>
13 #include <linux/platform_device.h>
14 #include <linux/regulator/consumer.h>
15 #include <linux/types.h>
16 #include <linux/v4l2-dv-timings.h>
17 #include <linux/videodev2.h>
18
19 #include <media/v4l2-ctrls.h>
20 #include <media/v4l2-device.h>
21 #include <media/v4l2-dv-timings.h>
22 #include <media/v4l2-event.h>
23 #include <media/v4l2-fwnode.h>
24 #include <media/i2c/tda1997x.h>
25
26 #include <sound/core.h>
27 #include <sound/pcm.h>
28 #include <sound/pcm_params.h>
29 #include <sound/soc.h>
30
31 #include <dt-bindings/media/tda1997x.h>
32
33 #include "tda1997x_regs.h"
34
35 #define TDA1997X_MBUS_CODES 5
36
37 /* debug level */
38 static int debug;
39 module_param(debug, int, 0644);
40 MODULE_PARM_DESC(debug, "debug level (0-2)");
41
42 /* Audio formats */
43 static const char * const audtype_names[] = {
44 "PCM", /* PCM Samples */
45 "HBR", /* High Bit Rate Audio */
46 "OBA", /* One-Bit Audio */
47 "DST" /* Direct Stream Transfer */
48 };
49
50 /* Audio output port formats */
51 enum audfmt_types {
52 AUDFMT_TYPE_DISABLED = 0,
53 AUDFMT_TYPE_I2S,
54 AUDFMT_TYPE_SPDIF,
55 };
56 static const char * const audfmt_names[] = {
57 "Disabled",
58 "I2S",
59 "SPDIF",
60 };
61
62 /* Video input formats */
63 static const char * const hdmi_colorspace_names[] = {
64 "RGB", "YUV422", "YUV444", "YUV420", "", "", "", "",
65 };
66 static const char * const hdmi_colorimetry_names[] = {
67 "", "ITU601", "ITU709", "Extended",
68 };
69 static const char * const v4l2_quantization_names[] = {
70 "Default",
71 "Full Range (0-255)",
72 "Limited Range (16-235)",
73 };
74
75 /* Video output port formats */
76 static const char * const vidfmt_names[] = {
77 "RGB444/YUV444", /* RGB/YUV444 16bit data bus, 8bpp */
78 "YUV422 semi-planar", /* YUV422 16bit data base, 8bpp */
79 "YUV422 CCIR656", /* BT656 (YUV 8bpp 2 clock per pixel) */
80 "Invalid",
81 };
82
83 /*
84 * Colorspace conversion matrices
85 */
86 struct color_matrix_coefs {
87 const char *name;
88 /* Input offsets */
89 s16 offint1;
90 s16 offint2;
91 s16 offint3;
92 /* Coeficients */
93 s16 p11coef;
94 s16 p12coef;
95 s16 p13coef;
96 s16 p21coef;
97 s16 p22coef;
98 s16 p23coef;
99 s16 p31coef;
100 s16 p32coef;
101 s16 p33coef;
102 /* Output offsets */
103 s16 offout1;
104 s16 offout2;
105 s16 offout3;
106 };
107
108 enum {
109 ITU709_RGBFULL,
110 ITU601_RGBFULL,
111 RGBLIMITED_RGBFULL,
112 RGBLIMITED_ITU601,
113 RGBLIMITED_ITU709,
114 RGBFULL_ITU601,
115 RGBFULL_ITU709,
116 };
117
118 /* NB: 4096 is 1.0 using fixed point numbers */
119 static const struct color_matrix_coefs conv_matrix[] = {
120 {
121 "YUV709 -> RGB full",
122 -256, -2048, -2048,
123 4769, -2183, -873,
124 4769, 7343, 0,
125 4769, 0, 8652,
126 0, 0, 0,
127 },
128 {
129 "YUV601 -> RGB full",
130 -256, -2048, -2048,
131 4769, -3330, -1602,
132 4769, 6538, 0,
133 4769, 0, 8264,
134 256, 256, 256,
135 },
136 {
137 "RGB limited -> RGB full",
138 -256, -256, -256,
139 0, 4769, 0,
140 0, 0, 4769,
141 4769, 0, 0,
142 0, 0, 0,
143 },
144 {
145 "RGB limited -> ITU601",
146 -256, -256, -256,
147 2404, 1225, 467,
148 -1754, 2095, -341,
149 -1388, -707, 2095,
150 256, 2048, 2048,
151 },
152 {
153 "RGB limited -> ITU709",
154 -256, -256, -256,
155 2918, 867, 295,
156 -1894, 2087, -190,
157 -1607, -477, 2087,
158 256, 2048, 2048,
159 },
160 {
161 "RGB full -> ITU601",
162 0, 0, 0,
163 2065, 1052, 401,
164 -1506, 1799, -293,
165 -1192, -607, 1799,
166 256, 2048, 2048,
167 },
168 {
169 "RGB full -> ITU709",
170 0, 0, 0,
171 2506, 745, 253,
172 -1627, 1792, -163,
173 -1380, -410, 1792,
174 256, 2048, 2048,
175 },
176 };
177
178 static const struct v4l2_dv_timings_cap tda1997x_dv_timings_cap = {
179 .type = V4L2_DV_BT_656_1120,
180 /* keep this initialization for compatibility with GCC < 4.4.6 */
181 .reserved = { 0 },
182
183 V4L2_INIT_BT_TIMINGS(
184 640, 1920, /* min/max width */
185 350, 1200, /* min/max height */
186 13000000, 165000000, /* min/max pixelclock */
187 /* standards */
188 V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
189 V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT,
190 /* capabilities */
191 V4L2_DV_BT_CAP_INTERLACED | V4L2_DV_BT_CAP_PROGRESSIVE |
192 V4L2_DV_BT_CAP_REDUCED_BLANKING |
193 V4L2_DV_BT_CAP_CUSTOM
194 )
195 };
196
197 /* regulator supplies */
198 static const char * const tda1997x_supply_name[] = {
199 "DOVDD", /* Digital I/O supply */
200 "DVDD", /* Digital Core supply */
201 "AVDD", /* Analog supply */
202 };
203
204 #define TDA1997X_NUM_SUPPLIES ARRAY_SIZE(tda1997x_supply_name)
205
206 enum tda1997x_type {
207 TDA19971,
208 TDA19973,
209 };
210
211 enum tda1997x_hdmi_pads {
212 TDA1997X_PAD_SOURCE,
213 TDA1997X_NUM_PADS,
214 };
215
216 struct tda1997x_chip_info {
217 enum tda1997x_type type;
218 const char *name;
219 };
220
221 struct tda1997x_state {
222 const struct tda1997x_chip_info *info;
223 struct tda1997x_platform_data pdata;
224 struct i2c_client *client;
225 struct i2c_client *client_cec;
226 struct v4l2_subdev sd;
227 struct regulator_bulk_data supplies[TDA1997X_NUM_SUPPLIES];
228 struct media_pad pads[TDA1997X_NUM_PADS];
229 struct mutex lock;
230 struct mutex page_lock;
231 char page;
232
233 /* detected info from chip */
234 int chip_revision;
235 char port_30bit;
236 char output_2p5;
237 char tmdsb_clk;
238 char tmdsb_soc;
239
240 /* status info */
241 char hdmi_status;
242 char mptrw_in_progress;
243 char activity_status;
244 char input_detect[2];
245
246 /* video */
247 struct hdmi_avi_infoframe avi_infoframe;
248 struct v4l2_hdmi_colorimetry colorimetry;
249 u32 rgb_quantization_range;
250 struct v4l2_dv_timings timings;
251 int fps;
252 const struct color_matrix_coefs *conv;
253 u32 mbus_codes[TDA1997X_MBUS_CODES]; /* available modes */
254 u32 mbus_code; /* current mode */
255 u8 vid_fmt;
256
257 /* controls */
258 struct v4l2_ctrl_handler hdl;
259 struct v4l2_ctrl *detect_tx_5v_ctrl;
260 struct v4l2_ctrl *rgb_quantization_range_ctrl;
261
262 /* audio */
263 u8 audio_ch_alloc;
264 int audio_samplerate;
265 int audio_channels;
266 int audio_samplesize;
267 int audio_type;
268 struct mutex audio_lock;
269 struct snd_pcm_substream *audio_stream;
270
271 /* EDID */
272 struct {
273 u8 edid[256];
274 u32 present;
275 unsigned int blocks;
276 } edid;
277 struct delayed_work delayed_work_enable_hpd;
278 };
279
280 static const struct v4l2_event tda1997x_ev_fmt = {
281 .type = V4L2_EVENT_SOURCE_CHANGE,
282 .u.src_change.changes = V4L2_EVENT_SRC_CH_RESOLUTION,
283 };
284
285 static const struct tda1997x_chip_info tda1997x_chip_info[] = {
286 [TDA19971] = {
287 .type = TDA19971,
288 .name = "tda19971",
289 },
290 [TDA19973] = {
291 .type = TDA19973,
292 .name = "tda19973",
293 },
294 };
295
to_state(struct v4l2_subdev * sd)296 static inline struct tda1997x_state *to_state(struct v4l2_subdev *sd)
297 {
298 return container_of(sd, struct tda1997x_state, sd);
299 }
300
to_sd(struct v4l2_ctrl * ctrl)301 static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
302 {
303 return &container_of(ctrl->handler, struct tda1997x_state, hdl)->sd;
304 }
305
tda1997x_cec_read(struct v4l2_subdev * sd,u8 reg)306 static int tda1997x_cec_read(struct v4l2_subdev *sd, u8 reg)
307 {
308 struct tda1997x_state *state = to_state(sd);
309 int val;
310
311 val = i2c_smbus_read_byte_data(state->client_cec, reg);
312 if (val < 0) {
313 v4l_err(state->client, "read reg error: reg=%2x\n", reg);
314 val = -1;
315 }
316
317 return val;
318 }
319
tda1997x_cec_write(struct v4l2_subdev * sd,u8 reg,u8 val)320 static int tda1997x_cec_write(struct v4l2_subdev *sd, u8 reg, u8 val)
321 {
322 struct tda1997x_state *state = to_state(sd);
323 int ret = 0;
324
325 ret = i2c_smbus_write_byte_data(state->client_cec, reg, val);
326 if (ret < 0) {
327 v4l_err(state->client, "write reg error:reg=%2x,val=%2x\n",
328 reg, val);
329 ret = -1;
330 }
331
332 return ret;
333 }
334
335 /* -----------------------------------------------------------------------------
336 * I2C transfer
337 */
338
tda1997x_setpage(struct v4l2_subdev * sd,u8 page)339 static int tda1997x_setpage(struct v4l2_subdev *sd, u8 page)
340 {
341 struct tda1997x_state *state = to_state(sd);
342 int ret;
343
344 if (state->page != page) {
345 ret = i2c_smbus_write_byte_data(state->client,
346 REG_CURPAGE_00H, page);
347 if (ret < 0) {
348 v4l_err(state->client,
349 "write reg error:reg=%2x,val=%2x\n",
350 REG_CURPAGE_00H, page);
351 return ret;
352 }
353 state->page = page;
354 }
355 return 0;
356 }
357
io_read(struct v4l2_subdev * sd,u16 reg)358 static inline int io_read(struct v4l2_subdev *sd, u16 reg)
359 {
360 struct tda1997x_state *state = to_state(sd);
361 int val;
362
363 mutex_lock(&state->page_lock);
364 if (tda1997x_setpage(sd, reg >> 8)) {
365 val = -1;
366 goto out;
367 }
368
369 val = i2c_smbus_read_byte_data(state->client, reg&0xff);
370 if (val < 0) {
371 v4l_err(state->client, "read reg error: reg=%2x\n", reg & 0xff);
372 val = -1;
373 goto out;
374 }
375
376 out:
377 mutex_unlock(&state->page_lock);
378 return val;
379 }
380
io_read16(struct v4l2_subdev * sd,u16 reg)381 static inline long io_read16(struct v4l2_subdev *sd, u16 reg)
382 {
383 int val;
384 long lval = 0;
385
386 val = io_read(sd, reg);
387 if (val < 0)
388 return val;
389 lval |= (val << 8);
390 val = io_read(sd, reg + 1);
391 if (val < 0)
392 return val;
393 lval |= val;
394
395 return lval;
396 }
397
io_read24(struct v4l2_subdev * sd,u16 reg)398 static inline long io_read24(struct v4l2_subdev *sd, u16 reg)
399 {
400 int val;
401 long lval = 0;
402
403 val = io_read(sd, reg);
404 if (val < 0)
405 return val;
406 lval |= (val << 16);
407 val = io_read(sd, reg + 1);
408 if (val < 0)
409 return val;
410 lval |= (val << 8);
411 val = io_read(sd, reg + 2);
412 if (val < 0)
413 return val;
414 lval |= val;
415
416 return lval;
417 }
418
io_readn(struct v4l2_subdev * sd,u16 reg,u8 len,u8 * data)419 static unsigned int io_readn(struct v4l2_subdev *sd, u16 reg, u8 len, u8 *data)
420 {
421 int i;
422 int sz = 0;
423 int val;
424
425 for (i = 0; i < len; i++) {
426 val = io_read(sd, reg + i);
427 if (val < 0)
428 break;
429 data[i] = val;
430 sz++;
431 }
432
433 return sz;
434 }
435
io_write(struct v4l2_subdev * sd,u16 reg,u8 val)436 static int io_write(struct v4l2_subdev *sd, u16 reg, u8 val)
437 {
438 struct tda1997x_state *state = to_state(sd);
439 s32 ret = 0;
440
441 mutex_lock(&state->page_lock);
442 if (tda1997x_setpage(sd, reg >> 8)) {
443 ret = -1;
444 goto out;
445 }
446
447 ret = i2c_smbus_write_byte_data(state->client, reg & 0xff, val);
448 if (ret < 0) {
449 v4l_err(state->client, "write reg error:reg=%2x,val=%2x\n",
450 reg&0xff, val);
451 ret = -1;
452 goto out;
453 }
454
455 out:
456 mutex_unlock(&state->page_lock);
457 return ret;
458 }
459
io_write16(struct v4l2_subdev * sd,u16 reg,u16 val)460 static int io_write16(struct v4l2_subdev *sd, u16 reg, u16 val)
461 {
462 int ret;
463
464 ret = io_write(sd, reg, (val >> 8) & 0xff);
465 if (ret < 0)
466 return ret;
467 ret = io_write(sd, reg + 1, val & 0xff);
468 if (ret < 0)
469 return ret;
470 return 0;
471 }
472
io_write24(struct v4l2_subdev * sd,u16 reg,u32 val)473 static int io_write24(struct v4l2_subdev *sd, u16 reg, u32 val)
474 {
475 int ret;
476
477 ret = io_write(sd, reg, (val >> 16) & 0xff);
478 if (ret < 0)
479 return ret;
480 ret = io_write(sd, reg + 1, (val >> 8) & 0xff);
481 if (ret < 0)
482 return ret;
483 ret = io_write(sd, reg + 2, val & 0xff);
484 if (ret < 0)
485 return ret;
486 return 0;
487 }
488
489 /* -----------------------------------------------------------------------------
490 * Hotplug
491 */
492
493 enum hpd_mode {
494 HPD_LOW_BP, /* HPD low and pulse of at least 100ms */
495 HPD_LOW_OTHER, /* HPD low and pulse of at least 100ms */
496 HPD_HIGH_BP, /* HIGH */
497 HPD_HIGH_OTHER,
498 HPD_PULSE, /* HPD low pulse */
499 };
500
501 /* manual HPD (Hot Plug Detect) control */
tda1997x_manual_hpd(struct v4l2_subdev * sd,enum hpd_mode mode)502 static int tda1997x_manual_hpd(struct v4l2_subdev *sd, enum hpd_mode mode)
503 {
504 u8 hpd_auto, hpd_pwr, hpd_man;
505
506 hpd_auto = io_read(sd, REG_HPD_AUTO_CTRL);
507 hpd_pwr = io_read(sd, REG_HPD_POWER);
508 hpd_man = io_read(sd, REG_HPD_MAN_CTRL);
509
510 /* mask out unused bits */
511 hpd_man &= (HPD_MAN_CTRL_HPD_PULSE |
512 HPD_MAN_CTRL_5VEN |
513 HPD_MAN_CTRL_HPD_B |
514 HPD_MAN_CTRL_HPD_A);
515
516 switch (mode) {
517 /* HPD low and pulse of at least 100ms */
518 case HPD_LOW_BP:
519 /* hpd_bp=0 */
520 hpd_pwr &= ~HPD_POWER_BP_MASK;
521 /* disable HPD_A and HPD_B */
522 hpd_man &= ~(HPD_MAN_CTRL_HPD_A | HPD_MAN_CTRL_HPD_B);
523 io_write(sd, REG_HPD_POWER, hpd_pwr);
524 io_write(sd, REG_HPD_MAN_CTRL, hpd_man);
525 break;
526 /* HPD high */
527 case HPD_HIGH_BP:
528 /* hpd_bp=1 */
529 hpd_pwr &= ~HPD_POWER_BP_MASK;
530 hpd_pwr |= 1 << HPD_POWER_BP_SHIFT;
531 io_write(sd, REG_HPD_POWER, hpd_pwr);
532 break;
533 /* HPD low and pulse of at least 100ms */
534 case HPD_LOW_OTHER:
535 /* disable HPD_A and HPD_B */
536 hpd_man &= ~(HPD_MAN_CTRL_HPD_A | HPD_MAN_CTRL_HPD_B);
537 /* hp_other=0 */
538 hpd_auto &= ~HPD_AUTO_HP_OTHER;
539 io_write(sd, REG_HPD_AUTO_CTRL, hpd_auto);
540 io_write(sd, REG_HPD_MAN_CTRL, hpd_man);
541 break;
542 /* HPD high */
543 case HPD_HIGH_OTHER:
544 hpd_auto |= HPD_AUTO_HP_OTHER;
545 io_write(sd, REG_HPD_AUTO_CTRL, hpd_auto);
546 break;
547 /* HPD low pulse */
548 case HPD_PULSE:
549 /* disable HPD_A and HPD_B */
550 hpd_man &= ~(HPD_MAN_CTRL_HPD_A | HPD_MAN_CTRL_HPD_B);
551 io_write(sd, REG_HPD_MAN_CTRL, hpd_man);
552 break;
553 }
554
555 return 0;
556 }
557
tda1997x_delayed_work_enable_hpd(struct work_struct * work)558 static void tda1997x_delayed_work_enable_hpd(struct work_struct *work)
559 {
560 struct delayed_work *dwork = to_delayed_work(work);
561 struct tda1997x_state *state = container_of(dwork,
562 struct tda1997x_state,
563 delayed_work_enable_hpd);
564 struct v4l2_subdev *sd = &state->sd;
565
566 v4l2_dbg(2, debug, sd, "%s:\n", __func__);
567
568 /* Set HPD high */
569 tda1997x_manual_hpd(sd, HPD_HIGH_OTHER);
570 tda1997x_manual_hpd(sd, HPD_HIGH_BP);
571
572 state->edid.present = 1;
573 }
574
tda1997x_disable_edid(struct v4l2_subdev * sd)575 static void tda1997x_disable_edid(struct v4l2_subdev *sd)
576 {
577 struct tda1997x_state *state = to_state(sd);
578
579 v4l2_dbg(1, debug, sd, "%s\n", __func__);
580 cancel_delayed_work_sync(&state->delayed_work_enable_hpd);
581
582 /* Set HPD low */
583 tda1997x_manual_hpd(sd, HPD_LOW_BP);
584 }
585
tda1997x_enable_edid(struct v4l2_subdev * sd)586 static void tda1997x_enable_edid(struct v4l2_subdev *sd)
587 {
588 struct tda1997x_state *state = to_state(sd);
589
590 v4l2_dbg(1, debug, sd, "%s\n", __func__);
591
592 /* Enable hotplug after 100ms */
593 schedule_delayed_work(&state->delayed_work_enable_hpd, HZ / 10);
594 }
595
596 /* -----------------------------------------------------------------------------
597 * Signal Control
598 */
599
600 /*
601 * configure vid_fmt based on mbus_code
602 */
603 static int
tda1997x_setup_format(struct tda1997x_state * state,u32 code)604 tda1997x_setup_format(struct tda1997x_state *state, u32 code)
605 {
606 v4l_dbg(1, debug, state->client, "%s code=0x%x\n", __func__, code);
607 switch (code) {
608 case MEDIA_BUS_FMT_RGB121212_1X36:
609 case MEDIA_BUS_FMT_RGB888_1X24:
610 case MEDIA_BUS_FMT_YUV12_1X36:
611 case MEDIA_BUS_FMT_YUV8_1X24:
612 state->vid_fmt = OF_FMT_444;
613 break;
614 case MEDIA_BUS_FMT_UYVY12_1X24:
615 case MEDIA_BUS_FMT_UYVY10_1X20:
616 case MEDIA_BUS_FMT_UYVY8_1X16:
617 state->vid_fmt = OF_FMT_422_SMPT;
618 break;
619 case MEDIA_BUS_FMT_UYVY12_2X12:
620 case MEDIA_BUS_FMT_UYVY10_2X10:
621 case MEDIA_BUS_FMT_UYVY8_2X8:
622 state->vid_fmt = OF_FMT_422_CCIR;
623 break;
624 default:
625 v4l_err(state->client, "incompatible format (0x%x)\n", code);
626 return -EINVAL;
627 }
628 v4l_dbg(1, debug, state->client, "%s code=0x%x fmt=%s\n", __func__,
629 code, vidfmt_names[state->vid_fmt]);
630 state->mbus_code = code;
631
632 return 0;
633 }
634
635 /*
636 * The color conversion matrix will convert between the colorimetry of the
637 * HDMI input to the desired output format RGB|YUV. RGB output is to be
638 * full-range and YUV is to be limited range.
639 *
640 * RGB full-range uses values from 0 to 255 which is recommended on a monitor
641 * and RGB Limited uses values from 16 to 236 (16=black, 235=white) which is
642 * typically recommended on a TV.
643 */
644 static void
tda1997x_configure_csc(struct v4l2_subdev * sd)645 tda1997x_configure_csc(struct v4l2_subdev *sd)
646 {
647 struct tda1997x_state *state = to_state(sd);
648 struct hdmi_avi_infoframe *avi = &state->avi_infoframe;
649 struct v4l2_hdmi_colorimetry *c = &state->colorimetry;
650 /* Blanking code values depend on output colorspace (RGB or YUV) */
651 struct blanking_codes {
652 s16 code_gy;
653 s16 code_bu;
654 s16 code_rv;
655 };
656 static const struct blanking_codes rgb_blanking = { 64, 64, 64 };
657 static const struct blanking_codes yuv_blanking = { 64, 512, 512 };
658 const struct blanking_codes *blanking_codes = NULL;
659 u8 reg;
660
661 v4l_dbg(1, debug, state->client, "input:%s quant:%s output:%s\n",
662 hdmi_colorspace_names[avi->colorspace],
663 v4l2_quantization_names[c->quantization],
664 vidfmt_names[state->vid_fmt]);
665 state->conv = NULL;
666 switch (state->vid_fmt) {
667 /* RGB output */
668 case OF_FMT_444:
669 blanking_codes = &rgb_blanking;
670 if (c->colorspace == V4L2_COLORSPACE_SRGB) {
671 if (c->quantization == V4L2_QUANTIZATION_LIM_RANGE)
672 state->conv = &conv_matrix[RGBLIMITED_RGBFULL];
673 } else {
674 if (c->colorspace == V4L2_COLORSPACE_REC709)
675 state->conv = &conv_matrix[ITU709_RGBFULL];
676 else if (c->colorspace == V4L2_COLORSPACE_SMPTE170M)
677 state->conv = &conv_matrix[ITU601_RGBFULL];
678 }
679 break;
680
681 /* YUV output */
682 case OF_FMT_422_SMPT: /* semi-planar */
683 case OF_FMT_422_CCIR: /* CCIR656 */
684 blanking_codes = &yuv_blanking;
685 if ((c->colorspace == V4L2_COLORSPACE_SRGB) &&
686 (c->quantization == V4L2_QUANTIZATION_FULL_RANGE)) {
687 if (state->timings.bt.height <= 576)
688 state->conv = &conv_matrix[RGBFULL_ITU601];
689 else
690 state->conv = &conv_matrix[RGBFULL_ITU709];
691 } else if ((c->colorspace == V4L2_COLORSPACE_SRGB) &&
692 (c->quantization == V4L2_QUANTIZATION_LIM_RANGE)) {
693 if (state->timings.bt.height <= 576)
694 state->conv = &conv_matrix[RGBLIMITED_ITU601];
695 else
696 state->conv = &conv_matrix[RGBLIMITED_ITU709];
697 }
698 break;
699 }
700
701 if (state->conv) {
702 v4l_dbg(1, debug, state->client, "%s\n",
703 state->conv->name);
704 /* enable matrix conversion */
705 reg = io_read(sd, REG_VDP_CTRL);
706 reg &= ~VDP_CTRL_MATRIX_BP;
707 io_write(sd, REG_VDP_CTRL, reg);
708 /* offset inputs */
709 io_write16(sd, REG_VDP_MATRIX + 0, state->conv->offint1);
710 io_write16(sd, REG_VDP_MATRIX + 2, state->conv->offint2);
711 io_write16(sd, REG_VDP_MATRIX + 4, state->conv->offint3);
712 /* coefficients */
713 io_write16(sd, REG_VDP_MATRIX + 6, state->conv->p11coef);
714 io_write16(sd, REG_VDP_MATRIX + 8, state->conv->p12coef);
715 io_write16(sd, REG_VDP_MATRIX + 10, state->conv->p13coef);
716 io_write16(sd, REG_VDP_MATRIX + 12, state->conv->p21coef);
717 io_write16(sd, REG_VDP_MATRIX + 14, state->conv->p22coef);
718 io_write16(sd, REG_VDP_MATRIX + 16, state->conv->p23coef);
719 io_write16(sd, REG_VDP_MATRIX + 18, state->conv->p31coef);
720 io_write16(sd, REG_VDP_MATRIX + 20, state->conv->p32coef);
721 io_write16(sd, REG_VDP_MATRIX + 22, state->conv->p33coef);
722 /* offset outputs */
723 io_write16(sd, REG_VDP_MATRIX + 24, state->conv->offout1);
724 io_write16(sd, REG_VDP_MATRIX + 26, state->conv->offout2);
725 io_write16(sd, REG_VDP_MATRIX + 28, state->conv->offout3);
726 } else {
727 /* disable matrix conversion */
728 reg = io_read(sd, REG_VDP_CTRL);
729 reg |= VDP_CTRL_MATRIX_BP;
730 io_write(sd, REG_VDP_CTRL, reg);
731 }
732
733 /* SetBlankingCodes */
734 if (blanking_codes) {
735 io_write16(sd, REG_BLK_GY, blanking_codes->code_gy);
736 io_write16(sd, REG_BLK_BU, blanking_codes->code_bu);
737 io_write16(sd, REG_BLK_RV, blanking_codes->code_rv);
738 }
739 }
740
741 /* Configure frame detection window and VHREF timing generator */
742 static void
tda1997x_configure_vhref(struct v4l2_subdev * sd)743 tda1997x_configure_vhref(struct v4l2_subdev *sd)
744 {
745 struct tda1997x_state *state = to_state(sd);
746 const struct v4l2_bt_timings *bt = &state->timings.bt;
747 int width, lines;
748 u16 href_start, href_end;
749 u16 vref_f1_start, vref_f2_start;
750 u8 vref_f1_width, vref_f2_width;
751 u8 field_polarity;
752 u16 fieldref_f1_start, fieldref_f2_start;
753 u8 reg;
754
755 href_start = bt->hbackporch + bt->hsync + 1;
756 href_end = href_start + bt->width;
757 vref_f1_start = bt->height + bt->vbackporch + bt->vsync +
758 bt->il_vbackporch + bt->il_vsync +
759 bt->il_vfrontporch;
760 vref_f1_width = bt->vbackporch + bt->vsync + bt->vfrontporch;
761 vref_f2_start = 0;
762 vref_f2_width = 0;
763 fieldref_f1_start = 0;
764 fieldref_f2_start = 0;
765 if (bt->interlaced) {
766 vref_f2_start = (bt->height / 2) +
767 (bt->il_vbackporch + bt->il_vsync - 1);
768 vref_f2_width = bt->il_vbackporch + bt->il_vsync +
769 bt->il_vfrontporch;
770 fieldref_f2_start = vref_f2_start + bt->il_vfrontporch +
771 fieldref_f1_start;
772 }
773 field_polarity = 0;
774
775 width = V4L2_DV_BT_FRAME_WIDTH(bt);
776 lines = V4L2_DV_BT_FRAME_HEIGHT(bt);
777
778 /*
779 * Configure Frame Detection Window:
780 * horiz area where the VHREF module consider a VSYNC a new frame
781 */
782 io_write16(sd, REG_FDW_S, 0x2ef); /* start position */
783 io_write16(sd, REG_FDW_E, 0x141); /* end position */
784
785 /* Set Pixel And Line Counters */
786 if (state->chip_revision == 0)
787 io_write16(sd, REG_PXCNT_PR, 4);
788 else
789 io_write16(sd, REG_PXCNT_PR, 1);
790 io_write16(sd, REG_PXCNT_NPIX, width & MASK_VHREF);
791 io_write16(sd, REG_LCNT_PR, 1);
792 io_write16(sd, REG_LCNT_NLIN, lines & MASK_VHREF);
793
794 /*
795 * Configure the VHRef timing generator responsible for rebuilding all
796 * horiz and vert synch and ref signals from its input allowing auto
797 * detection algorithms and forcing predefined modes (480i & 576i)
798 */
799 reg = VHREF_STD_DET_OFF << VHREF_STD_DET_SHIFT;
800 io_write(sd, REG_VHREF_CTRL, reg);
801
802 /*
803 * Configure the VHRef timing values. In case the VHREF generator has
804 * been configured in manual mode, this will allow to manually set all
805 * horiz and vert ref values (non-active pixel areas) of the generator
806 * and allows setting the frame reference params.
807 */
808 /* horizontal reference start/end */
809 io_write16(sd, REG_HREF_S, href_start & MASK_VHREF);
810 io_write16(sd, REG_HREF_E, href_end & MASK_VHREF);
811 /* vertical reference f1 start/end */
812 io_write16(sd, REG_VREF_F1_S, vref_f1_start & MASK_VHREF);
813 io_write(sd, REG_VREF_F1_WIDTH, vref_f1_width);
814 /* vertical reference f2 start/end */
815 io_write16(sd, REG_VREF_F2_S, vref_f2_start & MASK_VHREF);
816 io_write(sd, REG_VREF_F2_WIDTH, vref_f2_width);
817
818 /* F1/F2 FREF, field polarity */
819 reg = fieldref_f1_start & MASK_VHREF;
820 reg |= field_polarity << 8;
821 io_write16(sd, REG_FREF_F1_S, reg);
822 reg = fieldref_f2_start & MASK_VHREF;
823 io_write16(sd, REG_FREF_F2_S, reg);
824 }
825
826 /* Configure Video Output port signals */
827 static int
tda1997x_configure_vidout(struct tda1997x_state * state)828 tda1997x_configure_vidout(struct tda1997x_state *state)
829 {
830 struct v4l2_subdev *sd = &state->sd;
831 struct tda1997x_platform_data *pdata = &state->pdata;
832 u8 prefilter;
833 u8 reg;
834
835 /* Configure pixel clock generator: delay, polarity, rate */
836 reg = (state->vid_fmt == OF_FMT_422_CCIR) ?
837 PCLK_SEL_X2 : PCLK_SEL_X1;
838 reg |= pdata->vidout_delay_pclk << PCLK_DELAY_SHIFT;
839 reg |= pdata->vidout_inv_pclk << PCLK_INV_SHIFT;
840 io_write(sd, REG_PCLK, reg);
841
842 /* Configure pre-filter */
843 prefilter = 0; /* filters off */
844 /* YUV422 mode requires conversion */
845 if ((state->vid_fmt == OF_FMT_422_SMPT) ||
846 (state->vid_fmt == OF_FMT_422_CCIR)) {
847 /* 2/7 taps for Rv and Bu */
848 prefilter = FILTERS_CTRL_2_7TAP << FILTERS_CTRL_BU_SHIFT |
849 FILTERS_CTRL_2_7TAP << FILTERS_CTRL_RV_SHIFT;
850 }
851 io_write(sd, REG_FILTERS_CTRL, prefilter);
852
853 /* Configure video port */
854 reg = state->vid_fmt & OF_FMT_MASK;
855 if (state->vid_fmt == OF_FMT_422_CCIR)
856 reg |= (OF_BLK | OF_TRC);
857 reg |= OF_VP_ENABLE;
858 io_write(sd, REG_OF, reg);
859
860 /* Configure formatter and conversions */
861 reg = io_read(sd, REG_VDP_CTRL);
862 /* pre-filter is needed unless (REG_FILTERS_CTRL == 0) */
863 if (!prefilter)
864 reg |= VDP_CTRL_PREFILTER_BP;
865 else
866 reg &= ~VDP_CTRL_PREFILTER_BP;
867 /* formatter is needed for YUV422 and for trc/blc codes */
868 if (state->vid_fmt == OF_FMT_444)
869 reg |= VDP_CTRL_FORMATTER_BP;
870 /* formatter and compdel needed for timing/blanking codes */
871 else
872 reg &= ~(VDP_CTRL_FORMATTER_BP | VDP_CTRL_COMPDEL_BP);
873 /* activate compdel for small sync delays */
874 if ((pdata->vidout_delay_vs < 4) || (pdata->vidout_delay_hs < 4))
875 reg &= ~VDP_CTRL_COMPDEL_BP;
876 io_write(sd, REG_VDP_CTRL, reg);
877
878 /* Configure DE output signal: delay, polarity, and source */
879 reg = pdata->vidout_delay_de << DE_FREF_DELAY_SHIFT |
880 pdata->vidout_inv_de << DE_FREF_INV_SHIFT |
881 pdata->vidout_sel_de << DE_FREF_SEL_SHIFT;
882 io_write(sd, REG_DE_FREF, reg);
883
884 /* Configure HS/HREF output signal: delay, polarity, and source */
885 if (state->vid_fmt != OF_FMT_422_CCIR) {
886 reg = pdata->vidout_delay_hs << HS_HREF_DELAY_SHIFT |
887 pdata->vidout_inv_hs << HS_HREF_INV_SHIFT |
888 pdata->vidout_sel_hs << HS_HREF_SEL_SHIFT;
889 } else
890 reg = HS_HREF_SEL_NONE << HS_HREF_SEL_SHIFT;
891 io_write(sd, REG_HS_HREF, reg);
892
893 /* Configure VS/VREF output signal: delay, polarity, and source */
894 if (state->vid_fmt != OF_FMT_422_CCIR) {
895 reg = pdata->vidout_delay_vs << VS_VREF_DELAY_SHIFT |
896 pdata->vidout_inv_vs << VS_VREF_INV_SHIFT |
897 pdata->vidout_sel_vs << VS_VREF_SEL_SHIFT;
898 } else
899 reg = VS_VREF_SEL_NONE << VS_VREF_SEL_SHIFT;
900 io_write(sd, REG_VS_VREF, reg);
901
902 return 0;
903 }
904
905 /* Configure Audio output port signals */
906 static int
tda1997x_configure_audout(struct v4l2_subdev * sd,u8 channel_assignment)907 tda1997x_configure_audout(struct v4l2_subdev *sd, u8 channel_assignment)
908 {
909 struct tda1997x_state *state = to_state(sd);
910 struct tda1997x_platform_data *pdata = &state->pdata;
911 bool sp_used_by_fifo = 1;
912 u8 reg;
913
914 if (!pdata->audout_format)
915 return 0;
916
917 /* channel assignment (CEA-861-D Table 20) */
918 io_write(sd, REG_AUDIO_PATH, channel_assignment);
919
920 /* Audio output configuration */
921 reg = 0;
922 switch (pdata->audout_format) {
923 case AUDFMT_TYPE_I2S:
924 reg |= AUDCFG_BUS_I2S << AUDCFG_BUS_SHIFT;
925 break;
926 case AUDFMT_TYPE_SPDIF:
927 reg |= AUDCFG_BUS_SPDIF << AUDCFG_BUS_SHIFT;
928 break;
929 }
930 switch (state->audio_type) {
931 case AUDCFG_TYPE_PCM:
932 reg |= AUDCFG_TYPE_PCM << AUDCFG_TYPE_SHIFT;
933 break;
934 case AUDCFG_TYPE_OBA:
935 reg |= AUDCFG_TYPE_OBA << AUDCFG_TYPE_SHIFT;
936 break;
937 case AUDCFG_TYPE_DST:
938 reg |= AUDCFG_TYPE_DST << AUDCFG_TYPE_SHIFT;
939 sp_used_by_fifo = 0;
940 break;
941 case AUDCFG_TYPE_HBR:
942 reg |= AUDCFG_TYPE_HBR << AUDCFG_TYPE_SHIFT;
943 if (pdata->audout_layout == 1) {
944 /* demuxed via AP0:AP3 */
945 reg |= AUDCFG_HBR_DEMUX << AUDCFG_HBR_SHIFT;
946 if (pdata->audout_format == AUDFMT_TYPE_SPDIF)
947 sp_used_by_fifo = 0;
948 } else {
949 /* straight via AP0 */
950 reg |= AUDCFG_HBR_STRAIGHT << AUDCFG_HBR_SHIFT;
951 }
952 break;
953 }
954 if (pdata->audout_width == 32)
955 reg |= AUDCFG_I2SW_32 << AUDCFG_I2SW_SHIFT;
956 else
957 reg |= AUDCFG_I2SW_16 << AUDCFG_I2SW_SHIFT;
958
959 /* automatic hardware mute */
960 if (pdata->audio_auto_mute)
961 reg |= AUDCFG_AUTO_MUTE_EN;
962 /* clock polarity */
963 if (pdata->audout_invert_clk)
964 reg |= AUDCFG_CLK_INVERT;
965 io_write(sd, REG_AUDCFG, reg);
966
967 /* audio layout */
968 reg = (pdata->audout_layout) ? AUDIO_LAYOUT_LAYOUT1 : 0;
969 if (!pdata->audout_layoutauto)
970 reg |= AUDIO_LAYOUT_MANUAL;
971 if (sp_used_by_fifo)
972 reg |= AUDIO_LAYOUT_SP_FLAG;
973 io_write(sd, REG_AUDIO_LAYOUT, reg);
974
975 /* FIFO Latency value */
976 io_write(sd, REG_FIFO_LATENCY_VAL, 0x80);
977
978 /* Audio output port config */
979 if (sp_used_by_fifo) {
980 reg = AUDIO_OUT_ENABLE_AP0;
981 if (channel_assignment >= 0x01)
982 reg |= AUDIO_OUT_ENABLE_AP1;
983 if (channel_assignment >= 0x04)
984 reg |= AUDIO_OUT_ENABLE_AP2;
985 if (channel_assignment >= 0x0c)
986 reg |= AUDIO_OUT_ENABLE_AP3;
987 /* specific cases where AP1 is not used */
988 if ((channel_assignment == 0x04)
989 || (channel_assignment == 0x08)
990 || (channel_assignment == 0x0c)
991 || (channel_assignment == 0x10)
992 || (channel_assignment == 0x14)
993 || (channel_assignment == 0x18)
994 || (channel_assignment == 0x1c))
995 reg &= ~AUDIO_OUT_ENABLE_AP1;
996 /* specific cases where AP2 is not used */
997 if ((channel_assignment >= 0x14)
998 && (channel_assignment <= 0x17))
999 reg &= ~AUDIO_OUT_ENABLE_AP2;
1000 } else {
1001 reg = AUDIO_OUT_ENABLE_AP3 |
1002 AUDIO_OUT_ENABLE_AP2 |
1003 AUDIO_OUT_ENABLE_AP1 |
1004 AUDIO_OUT_ENABLE_AP0;
1005 }
1006 if (pdata->audout_format == AUDFMT_TYPE_I2S)
1007 reg |= (AUDIO_OUT_ENABLE_ACLK | AUDIO_OUT_ENABLE_WS);
1008 io_write(sd, REG_AUDIO_OUT_ENABLE, reg);
1009
1010 /* reset test mode to normal audio freq auto selection */
1011 io_write(sd, REG_TEST_MODE, 0x00);
1012
1013 return 0;
1014 }
1015
1016 /* Soft Reset of specific hdmi info */
1017 static int
tda1997x_hdmi_info_reset(struct v4l2_subdev * sd,u8 info_rst,bool reset_sus)1018 tda1997x_hdmi_info_reset(struct v4l2_subdev *sd, u8 info_rst, bool reset_sus)
1019 {
1020 u8 reg;
1021
1022 /* reset infoframe engine packets */
1023 reg = io_read(sd, REG_HDMI_INFO_RST);
1024 io_write(sd, REG_HDMI_INFO_RST, info_rst);
1025
1026 /* if infoframe engine has been reset clear INT_FLG_MODE */
1027 if (reg & RESET_IF) {
1028 reg = io_read(sd, REG_INT_FLG_CLR_MODE);
1029 io_write(sd, REG_INT_FLG_CLR_MODE, reg);
1030 }
1031
1032 /* Disable REFTIM to restart start-up-sequencer (SUS) */
1033 reg = io_read(sd, REG_RATE_CTRL);
1034 reg &= ~RATE_REFTIM_ENABLE;
1035 if (!reset_sus)
1036 reg |= RATE_REFTIM_ENABLE;
1037 reg = io_write(sd, REG_RATE_CTRL, reg);
1038
1039 return 0;
1040 }
1041
1042 static void
tda1997x_power_mode(struct tda1997x_state * state,bool enable)1043 tda1997x_power_mode(struct tda1997x_state *state, bool enable)
1044 {
1045 struct v4l2_subdev *sd = &state->sd;
1046 u8 reg;
1047
1048 if (enable) {
1049 /* Automatic control of TMDS */
1050 io_write(sd, REG_PON_OVR_EN, PON_DIS);
1051 /* Enable current bias unit */
1052 io_write(sd, REG_CFG1, PON_EN);
1053 /* Enable deep color PLL */
1054 io_write(sd, REG_DEEP_PLL7_BYP, PON_DIS);
1055 /* Output buffers active */
1056 reg = io_read(sd, REG_OF);
1057 reg &= ~OF_VP_ENABLE;
1058 io_write(sd, REG_OF, reg);
1059 } else {
1060 /* Power down EDID mode sequence */
1061 /* Output buffers in HiZ */
1062 reg = io_read(sd, REG_OF);
1063 reg |= OF_VP_ENABLE;
1064 io_write(sd, REG_OF, reg);
1065 /* Disable deep color PLL */
1066 io_write(sd, REG_DEEP_PLL7_BYP, PON_EN);
1067 /* Disable current bias unit */
1068 io_write(sd, REG_CFG1, PON_DIS);
1069 /* Manual control of TMDS */
1070 io_write(sd, REG_PON_OVR_EN, PON_EN);
1071 }
1072 }
1073
1074 static bool
tda1997x_detect_tx_5v(struct v4l2_subdev * sd)1075 tda1997x_detect_tx_5v(struct v4l2_subdev *sd)
1076 {
1077 u8 reg = io_read(sd, REG_DETECT_5V);
1078
1079 return ((reg & DETECT_5V_SEL) ? 1 : 0);
1080 }
1081
1082 static bool
tda1997x_detect_tx_hpd(struct v4l2_subdev * sd)1083 tda1997x_detect_tx_hpd(struct v4l2_subdev *sd)
1084 {
1085 u8 reg = io_read(sd, REG_DETECT_5V);
1086
1087 return ((reg & DETECT_HPD) ? 1 : 0);
1088 }
1089
1090 static int
tda1997x_detect_std(struct tda1997x_state * state,struct v4l2_dv_timings * timings)1091 tda1997x_detect_std(struct tda1997x_state *state,
1092 struct v4l2_dv_timings *timings)
1093 {
1094 struct v4l2_subdev *sd = &state->sd;
1095 u32 vper;
1096 u16 hper;
1097 u16 hsper;
1098 int i;
1099
1100 /*
1101 * Read the FMT registers
1102 * REG_V_PER: Period of a frame (or two fields) in MCLK(27MHz) cycles
1103 * REG_H_PER: Period of a line in MCLK(27MHz) cycles
1104 * REG_HS_WIDTH: Period of horiz sync pulse in MCLK(27MHz) cycles
1105 */
1106 vper = io_read24(sd, REG_V_PER) & MASK_VPER;
1107 hper = io_read16(sd, REG_H_PER) & MASK_HPER;
1108 hsper = io_read16(sd, REG_HS_WIDTH) & MASK_HSWIDTH;
1109 v4l2_dbg(1, debug, sd, "Signal Timings: %u/%u/%u\n", vper, hper, hsper);
1110 if (!vper || !hper || !hsper)
1111 return -ENOLINK;
1112
1113 for (i = 0; v4l2_dv_timings_presets[i].bt.width; i++) {
1114 const struct v4l2_bt_timings *bt;
1115 u32 lines, width, _hper, _hsper;
1116 u32 vmin, vmax, hmin, hmax, hsmin, hsmax;
1117 bool vmatch, hmatch, hsmatch;
1118
1119 bt = &v4l2_dv_timings_presets[i].bt;
1120 width = V4L2_DV_BT_FRAME_WIDTH(bt);
1121 lines = V4L2_DV_BT_FRAME_HEIGHT(bt);
1122 _hper = (u32)bt->pixelclock / width;
1123 if (bt->interlaced)
1124 lines /= 2;
1125 /* vper +/- 0.7% */
1126 vmin = ((27000000 / 1000) * 993) / _hper * lines;
1127 vmax = ((27000000 / 1000) * 1007) / _hper * lines;
1128 /* hper +/- 1.0% */
1129 hmin = ((27000000 / 100) * 99) / _hper;
1130 hmax = ((27000000 / 100) * 101) / _hper;
1131 /* hsper +/- 2 (take care to avoid 32bit overflow) */
1132 _hsper = 27000 * bt->hsync / ((u32)bt->pixelclock/1000);
1133 hsmin = _hsper - 2;
1134 hsmax = _hsper + 2;
1135
1136 /* vmatch matches the framerate */
1137 vmatch = ((vper <= vmax) && (vper >= vmin)) ? 1 : 0;
1138 /* hmatch matches the width */
1139 hmatch = ((hper <= hmax) && (hper >= hmin)) ? 1 : 0;
1140 /* hsmatch matches the hswidth */
1141 hsmatch = ((hsper <= hsmax) && (hsper >= hsmin)) ? 1 : 0;
1142 if (hmatch && vmatch && hsmatch) {
1143 v4l2_print_dv_timings(sd->name, "Detected format: ",
1144 &v4l2_dv_timings_presets[i],
1145 false);
1146 if (timings)
1147 *timings = v4l2_dv_timings_presets[i];
1148 return 0;
1149 }
1150 }
1151
1152 v4l_err(state->client, "no resolution match for timings: %d/%d/%d\n",
1153 vper, hper, hsper);
1154 return -ERANGE;
1155 }
1156
1157 /* some sort of errata workaround for chip revision 0 (N1) */
tda1997x_reset_n1(struct tda1997x_state * state)1158 static void tda1997x_reset_n1(struct tda1997x_state *state)
1159 {
1160 struct v4l2_subdev *sd = &state->sd;
1161 u8 reg;
1162
1163 /* clear HDMI mode flag in BCAPS */
1164 io_write(sd, REG_CLK_CFG, CLK_CFG_SEL_ACLK_EN | CLK_CFG_SEL_ACLK);
1165 io_write(sd, REG_PON_OVR_EN, PON_EN);
1166 io_write(sd, REG_PON_CBIAS, PON_EN);
1167 io_write(sd, REG_PON_PLL, PON_EN);
1168
1169 reg = io_read(sd, REG_MODE_REC_CFG1);
1170 reg &= ~0x06;
1171 reg |= 0x02;
1172 io_write(sd, REG_MODE_REC_CFG1, reg);
1173 io_write(sd, REG_CLK_CFG, CLK_CFG_DIS);
1174 io_write(sd, REG_PON_OVR_EN, PON_DIS);
1175 reg = io_read(sd, REG_MODE_REC_CFG1);
1176 reg &= ~0x06;
1177 io_write(sd, REG_MODE_REC_CFG1, reg);
1178 }
1179
1180 /*
1181 * Activity detection must only be notified when stable_clk_x AND active_x
1182 * bits are set to 1. If only stable_clk_x bit is set to 1 but not
1183 * active_x, it means that the TMDS clock is not in the defined range
1184 * and activity detection must not be notified.
1185 */
1186 static u8
tda1997x_read_activity_status_regs(struct v4l2_subdev * sd)1187 tda1997x_read_activity_status_regs(struct v4l2_subdev *sd)
1188 {
1189 u8 reg, status = 0;
1190
1191 /* Read CLK_A_STATUS register */
1192 reg = io_read(sd, REG_CLK_A_STATUS);
1193 /* ignore if not active */
1194 if ((reg & MASK_CLK_STABLE) && !(reg & MASK_CLK_ACTIVE))
1195 reg &= ~MASK_CLK_STABLE;
1196 status |= ((reg & MASK_CLK_STABLE) >> 2);
1197
1198 /* Read CLK_B_STATUS register */
1199 reg = io_read(sd, REG_CLK_B_STATUS);
1200 /* ignore if not active */
1201 if ((reg & MASK_CLK_STABLE) && !(reg & MASK_CLK_ACTIVE))
1202 reg &= ~MASK_CLK_STABLE;
1203 status |= ((reg & MASK_CLK_STABLE) >> 1);
1204
1205 /* Read the SUS_STATUS register */
1206 reg = io_read(sd, REG_SUS_STATUS);
1207
1208 /* If state = 5 => TMDS is locked */
1209 if ((reg & MASK_SUS_STATUS) == LAST_STATE_REACHED)
1210 status |= MASK_SUS_STATE;
1211 else
1212 status &= ~MASK_SUS_STATE;
1213
1214 return status;
1215 }
1216
1217 static void
set_rgb_quantization_range(struct tda1997x_state * state)1218 set_rgb_quantization_range(struct tda1997x_state *state)
1219 {
1220 struct v4l2_hdmi_colorimetry *c = &state->colorimetry;
1221
1222 state->colorimetry = v4l2_hdmi_rx_colorimetry(&state->avi_infoframe,
1223 NULL,
1224 state->timings.bt.height);
1225 /* If ycbcr_enc is V4L2_YCBCR_ENC_DEFAULT, we receive RGB */
1226 if (c->ycbcr_enc == V4L2_YCBCR_ENC_DEFAULT) {
1227 switch (state->rgb_quantization_range) {
1228 case V4L2_DV_RGB_RANGE_LIMITED:
1229 c->quantization = V4L2_QUANTIZATION_FULL_RANGE;
1230 break;
1231 case V4L2_DV_RGB_RANGE_FULL:
1232 c->quantization = V4L2_QUANTIZATION_LIM_RANGE;
1233 break;
1234 }
1235 }
1236 v4l_dbg(1, debug, state->client,
1237 "colorspace=%d/%d colorimetry=%d range=%s content=%d\n",
1238 state->avi_infoframe.colorspace, c->colorspace,
1239 state->avi_infoframe.colorimetry,
1240 v4l2_quantization_names[c->quantization],
1241 state->avi_infoframe.content_type);
1242 }
1243
1244 /* parse an infoframe and do some sanity checks on it */
1245 static unsigned int
tda1997x_parse_infoframe(struct tda1997x_state * state,u16 addr)1246 tda1997x_parse_infoframe(struct tda1997x_state *state, u16 addr)
1247 {
1248 struct v4l2_subdev *sd = &state->sd;
1249 union hdmi_infoframe frame;
1250 u8 buffer[40];
1251 u8 reg;
1252 int len, err;
1253
1254 /* read data */
1255 len = io_readn(sd, addr, sizeof(buffer), buffer);
1256 err = hdmi_infoframe_unpack(&frame, buffer);
1257 if (err) {
1258 v4l_err(state->client,
1259 "failed parsing %d byte infoframe: 0x%04x/0x%02x\n",
1260 len, addr, buffer[0]);
1261 return err;
1262 }
1263 hdmi_infoframe_log(KERN_INFO, &state->client->dev, &frame);
1264 switch (frame.any.type) {
1265 /* Audio InfoFrame: see HDMI spec 8.2.2 */
1266 case HDMI_INFOFRAME_TYPE_AUDIO:
1267 /* sample rate */
1268 switch (frame.audio.sample_frequency) {
1269 case HDMI_AUDIO_SAMPLE_FREQUENCY_32000:
1270 state->audio_samplerate = 32000;
1271 break;
1272 case HDMI_AUDIO_SAMPLE_FREQUENCY_44100:
1273 state->audio_samplerate = 44100;
1274 break;
1275 case HDMI_AUDIO_SAMPLE_FREQUENCY_48000:
1276 state->audio_samplerate = 48000;
1277 break;
1278 case HDMI_AUDIO_SAMPLE_FREQUENCY_88200:
1279 state->audio_samplerate = 88200;
1280 break;
1281 case HDMI_AUDIO_SAMPLE_FREQUENCY_96000:
1282 state->audio_samplerate = 96000;
1283 break;
1284 case HDMI_AUDIO_SAMPLE_FREQUENCY_176400:
1285 state->audio_samplerate = 176400;
1286 break;
1287 case HDMI_AUDIO_SAMPLE_FREQUENCY_192000:
1288 state->audio_samplerate = 192000;
1289 break;
1290 default:
1291 case HDMI_AUDIO_SAMPLE_FREQUENCY_STREAM:
1292 break;
1293 }
1294
1295 /* sample size */
1296 switch (frame.audio.sample_size) {
1297 case HDMI_AUDIO_SAMPLE_SIZE_16:
1298 state->audio_samplesize = 16;
1299 break;
1300 case HDMI_AUDIO_SAMPLE_SIZE_20:
1301 state->audio_samplesize = 20;
1302 break;
1303 case HDMI_AUDIO_SAMPLE_SIZE_24:
1304 state->audio_samplesize = 24;
1305 break;
1306 case HDMI_AUDIO_SAMPLE_SIZE_STREAM:
1307 default:
1308 break;
1309 }
1310
1311 /* Channel Count */
1312 state->audio_channels = frame.audio.channels;
1313 if (frame.audio.channel_allocation &&
1314 frame.audio.channel_allocation != state->audio_ch_alloc) {
1315 /* use the channel assignment from the infoframe */
1316 state->audio_ch_alloc = frame.audio.channel_allocation;
1317 tda1997x_configure_audout(sd, state->audio_ch_alloc);
1318 /* reset the audio FIFO */
1319 tda1997x_hdmi_info_reset(sd, RESET_AUDIO, false);
1320 }
1321 break;
1322
1323 /* Auxiliary Video information (AVI) InfoFrame: see HDMI spec 8.2.1 */
1324 case HDMI_INFOFRAME_TYPE_AVI:
1325 state->avi_infoframe = frame.avi;
1326 set_rgb_quantization_range(state);
1327
1328 /* configure upsampler: 0=bypass 1=repeatchroma 2=interpolate */
1329 reg = io_read(sd, REG_PIX_REPEAT);
1330 reg &= ~PIX_REPEAT_MASK_UP_SEL;
1331 if (frame.avi.colorspace == HDMI_COLORSPACE_YUV422)
1332 reg |= (PIX_REPEAT_CHROMA << PIX_REPEAT_SHIFT);
1333 io_write(sd, REG_PIX_REPEAT, reg);
1334
1335 /* ConfigurePixelRepeater: repeat n-times each pixel */
1336 reg = io_read(sd, REG_PIX_REPEAT);
1337 reg &= ~PIX_REPEAT_MASK_REP;
1338 reg |= frame.avi.pixel_repeat;
1339 io_write(sd, REG_PIX_REPEAT, reg);
1340
1341 /* configure the receiver with the new colorspace */
1342 tda1997x_configure_csc(sd);
1343 break;
1344 default:
1345 break;
1346 }
1347 return 0;
1348 }
1349
tda1997x_irq_sus(struct tda1997x_state * state,u8 * flags)1350 static void tda1997x_irq_sus(struct tda1997x_state *state, u8 *flags)
1351 {
1352 struct v4l2_subdev *sd = &state->sd;
1353 u8 reg, source;
1354
1355 source = io_read(sd, REG_INT_FLG_CLR_SUS);
1356 io_write(sd, REG_INT_FLG_CLR_SUS, source);
1357
1358 if (source & MASK_MPT) {
1359 /* reset MTP in use flag if set */
1360 if (state->mptrw_in_progress)
1361 state->mptrw_in_progress = 0;
1362 }
1363
1364 if (source & MASK_SUS_END) {
1365 /* reset audio FIFO */
1366 reg = io_read(sd, REG_HDMI_INFO_RST);
1367 reg |= MASK_SR_FIFO_FIFO_CTRL;
1368 io_write(sd, REG_HDMI_INFO_RST, reg);
1369 reg &= ~MASK_SR_FIFO_FIFO_CTRL;
1370 io_write(sd, REG_HDMI_INFO_RST, reg);
1371
1372 /* reset HDMI flags */
1373 state->hdmi_status = 0;
1374 }
1375
1376 /* filter FMT interrupt based on SUS state */
1377 reg = io_read(sd, REG_SUS_STATUS);
1378 if (((reg & MASK_SUS_STATUS) != LAST_STATE_REACHED)
1379 || (source & MASK_MPT)) {
1380 source &= ~MASK_FMT;
1381 }
1382
1383 if (source & (MASK_FMT | MASK_SUS_END)) {
1384 reg = io_read(sd, REG_SUS_STATUS);
1385 if ((reg & MASK_SUS_STATUS) != LAST_STATE_REACHED) {
1386 v4l_err(state->client, "BAD SUS STATUS\n");
1387 return;
1388 }
1389 if (debug)
1390 tda1997x_detect_std(state, NULL);
1391 /* notify user of change in resolution */
1392 v4l2_subdev_notify_event(&state->sd, &tda1997x_ev_fmt);
1393 }
1394 }
1395
tda1997x_irq_ddc(struct tda1997x_state * state,u8 * flags)1396 static void tda1997x_irq_ddc(struct tda1997x_state *state, u8 *flags)
1397 {
1398 struct v4l2_subdev *sd = &state->sd;
1399 u8 source;
1400
1401 source = io_read(sd, REG_INT_FLG_CLR_DDC);
1402 io_write(sd, REG_INT_FLG_CLR_DDC, source);
1403 if (source & MASK_EDID_MTP) {
1404 /* reset MTP in use flag if set */
1405 if (state->mptrw_in_progress)
1406 state->mptrw_in_progress = 0;
1407 }
1408
1409 /* Detection of +5V */
1410 if (source & MASK_DET_5V) {
1411 v4l2_ctrl_s_ctrl(state->detect_tx_5v_ctrl,
1412 tda1997x_detect_tx_5v(sd));
1413 }
1414 }
1415
tda1997x_irq_rate(struct tda1997x_state * state,u8 * flags)1416 static void tda1997x_irq_rate(struct tda1997x_state *state, u8 *flags)
1417 {
1418 struct v4l2_subdev *sd = &state->sd;
1419 u8 reg, source;
1420
1421 u8 irq_status;
1422
1423 source = io_read(sd, REG_INT_FLG_CLR_RATE);
1424 io_write(sd, REG_INT_FLG_CLR_RATE, source);
1425
1426 /* read status regs */
1427 irq_status = tda1997x_read_activity_status_regs(sd);
1428
1429 /*
1430 * read clock status reg until INT_FLG_CLR_RATE is still 0
1431 * after the read to make sure its the last one
1432 */
1433 reg = source;
1434 while (reg != 0) {
1435 irq_status = tda1997x_read_activity_status_regs(sd);
1436 reg = io_read(sd, REG_INT_FLG_CLR_RATE);
1437 io_write(sd, REG_INT_FLG_CLR_RATE, reg);
1438 source |= reg;
1439 }
1440
1441 /* we only pay attention to stability change events */
1442 if (source & (MASK_RATE_A_ST | MASK_RATE_B_ST)) {
1443 int input = (source & MASK_RATE_A_ST)?0:1;
1444 u8 mask = 1<<input;
1445
1446 /* state change */
1447 if ((irq_status & mask) != (state->activity_status & mask)) {
1448 /* activity lost */
1449 if ((irq_status & mask) == 0) {
1450 v4l_info(state->client,
1451 "HDMI-%c: Digital Activity Lost\n",
1452 input+'A');
1453
1454 /* bypass up/down sampler and pixel repeater */
1455 reg = io_read(sd, REG_PIX_REPEAT);
1456 reg &= ~PIX_REPEAT_MASK_UP_SEL;
1457 reg &= ~PIX_REPEAT_MASK_REP;
1458 io_write(sd, REG_PIX_REPEAT, reg);
1459
1460 if (state->chip_revision == 0)
1461 tda1997x_reset_n1(state);
1462
1463 state->input_detect[input] = 0;
1464 v4l2_subdev_notify_event(sd, &tda1997x_ev_fmt);
1465 }
1466
1467 /* activity detected */
1468 else {
1469 v4l_info(state->client,
1470 "HDMI-%c: Digital Activity Detected\n",
1471 input+'A');
1472 state->input_detect[input] = 1;
1473 }
1474
1475 /* hold onto current state */
1476 state->activity_status = (irq_status & mask);
1477 }
1478 }
1479 }
1480
tda1997x_irq_info(struct tda1997x_state * state,u8 * flags)1481 static void tda1997x_irq_info(struct tda1997x_state *state, u8 *flags)
1482 {
1483 struct v4l2_subdev *sd = &state->sd;
1484 u8 source;
1485
1486 source = io_read(sd, REG_INT_FLG_CLR_INFO);
1487 io_write(sd, REG_INT_FLG_CLR_INFO, source);
1488
1489 /* Audio infoframe */
1490 if (source & MASK_AUD_IF) {
1491 tda1997x_parse_infoframe(state, AUD_IF);
1492 source &= ~MASK_AUD_IF;
1493 }
1494
1495 /* Source Product Descriptor infoframe change */
1496 if (source & MASK_SPD_IF) {
1497 tda1997x_parse_infoframe(state, SPD_IF);
1498 source &= ~MASK_SPD_IF;
1499 }
1500
1501 /* Auxiliary Video Information infoframe */
1502 if (source & MASK_AVI_IF) {
1503 tda1997x_parse_infoframe(state, AVI_IF);
1504 source &= ~MASK_AVI_IF;
1505 }
1506 }
1507
tda1997x_irq_audio(struct tda1997x_state * state,u8 * flags)1508 static void tda1997x_irq_audio(struct tda1997x_state *state, u8 *flags)
1509 {
1510 struct v4l2_subdev *sd = &state->sd;
1511 u8 reg, source;
1512
1513 source = io_read(sd, REG_INT_FLG_CLR_AUDIO);
1514 io_write(sd, REG_INT_FLG_CLR_AUDIO, source);
1515
1516 /* reset audio FIFO on FIFO pointer error or audio mute */
1517 if (source & MASK_ERROR_FIFO_PT ||
1518 source & MASK_MUTE_FLG) {
1519 /* audio reset audio FIFO */
1520 reg = io_read(sd, REG_SUS_STATUS);
1521 if ((reg & MASK_SUS_STATUS) == LAST_STATE_REACHED) {
1522 reg = io_read(sd, REG_HDMI_INFO_RST);
1523 reg |= MASK_SR_FIFO_FIFO_CTRL;
1524 io_write(sd, REG_HDMI_INFO_RST, reg);
1525 reg &= ~MASK_SR_FIFO_FIFO_CTRL;
1526 io_write(sd, REG_HDMI_INFO_RST, reg);
1527 /* reset channel status IT if present */
1528 source &= ~(MASK_CH_STATE);
1529 }
1530 }
1531 if (source & MASK_AUDIO_FREQ_FLG) {
1532 static const int freq[] = {
1533 0, 32000, 44100, 48000, 88200, 96000, 176400, 192000
1534 };
1535
1536 reg = io_read(sd, REG_AUDIO_FREQ);
1537 state->audio_samplerate = freq[reg & 7];
1538 v4l_info(state->client, "Audio Frequency Change: %dHz\n",
1539 state->audio_samplerate);
1540 }
1541 if (source & MASK_AUDIO_FLG) {
1542 reg = io_read(sd, REG_AUDIO_FLAGS);
1543 if (reg & BIT(AUDCFG_TYPE_DST))
1544 state->audio_type = AUDCFG_TYPE_DST;
1545 if (reg & BIT(AUDCFG_TYPE_OBA))
1546 state->audio_type = AUDCFG_TYPE_OBA;
1547 if (reg & BIT(AUDCFG_TYPE_HBR))
1548 state->audio_type = AUDCFG_TYPE_HBR;
1549 if (reg & BIT(AUDCFG_TYPE_PCM))
1550 state->audio_type = AUDCFG_TYPE_PCM;
1551 v4l_info(state->client, "Audio Type: %s\n",
1552 audtype_names[state->audio_type]);
1553 }
1554 }
1555
tda1997x_irq_hdcp(struct tda1997x_state * state,u8 * flags)1556 static void tda1997x_irq_hdcp(struct tda1997x_state *state, u8 *flags)
1557 {
1558 struct v4l2_subdev *sd = &state->sd;
1559 u8 reg, source;
1560
1561 source = io_read(sd, REG_INT_FLG_CLR_HDCP);
1562 io_write(sd, REG_INT_FLG_CLR_HDCP, source);
1563
1564 /* reset MTP in use flag if set */
1565 if (source & MASK_HDCP_MTP)
1566 state->mptrw_in_progress = 0;
1567 if (source & MASK_STATE_C5) {
1568 /* REPEATER: mask AUDIO and IF irqs to avoid IF during auth */
1569 reg = io_read(sd, REG_INT_MASK_TOP);
1570 reg &= ~(INTERRUPT_AUDIO | INTERRUPT_INFO);
1571 io_write(sd, REG_INT_MASK_TOP, reg);
1572 *flags &= (INTERRUPT_AUDIO | INTERRUPT_INFO);
1573 }
1574 }
1575
tda1997x_isr_thread(int irq,void * d)1576 static irqreturn_t tda1997x_isr_thread(int irq, void *d)
1577 {
1578 struct tda1997x_state *state = d;
1579 struct v4l2_subdev *sd = &state->sd;
1580 u8 flags;
1581
1582 mutex_lock(&state->lock);
1583 do {
1584 /* read interrupt flags */
1585 flags = io_read(sd, REG_INT_FLG_CLR_TOP);
1586 if (flags == 0)
1587 break;
1588
1589 /* SUS interrupt source (Input activity events) */
1590 if (flags & INTERRUPT_SUS)
1591 tda1997x_irq_sus(state, &flags);
1592 /* DDC interrupt source (Display Data Channel) */
1593 else if (flags & INTERRUPT_DDC)
1594 tda1997x_irq_ddc(state, &flags);
1595 /* RATE interrupt source (Digital Input activity) */
1596 else if (flags & INTERRUPT_RATE)
1597 tda1997x_irq_rate(state, &flags);
1598 /* Infoframe change interrupt */
1599 else if (flags & INTERRUPT_INFO)
1600 tda1997x_irq_info(state, &flags);
1601 /* Audio interrupt source:
1602 * freq change, DST,OBA,HBR,ASP flags, mute, FIFO err
1603 */
1604 else if (flags & INTERRUPT_AUDIO)
1605 tda1997x_irq_audio(state, &flags);
1606 /* HDCP interrupt source (content protection) */
1607 if (flags & INTERRUPT_HDCP)
1608 tda1997x_irq_hdcp(state, &flags);
1609 } while (flags != 0);
1610 mutex_unlock(&state->lock);
1611
1612 return IRQ_HANDLED;
1613 }
1614
1615 /* -----------------------------------------------------------------------------
1616 * v4l2_subdev_video_ops
1617 */
1618
1619 static int
tda1997x_g_input_status(struct v4l2_subdev * sd,u32 * status)1620 tda1997x_g_input_status(struct v4l2_subdev *sd, u32 *status)
1621 {
1622 struct tda1997x_state *state = to_state(sd);
1623 u32 vper;
1624 u16 hper;
1625 u16 hsper;
1626
1627 mutex_lock(&state->lock);
1628 vper = io_read24(sd, REG_V_PER) & MASK_VPER;
1629 hper = io_read16(sd, REG_H_PER) & MASK_HPER;
1630 hsper = io_read16(sd, REG_HS_WIDTH) & MASK_HSWIDTH;
1631 /*
1632 * The tda1997x supports A/B inputs but only a single output.
1633 * The irq handler monitors for timing changes on both inputs and
1634 * sets the input_detect array to 0|1 depending on signal presence.
1635 * I believe selection of A vs B is automatic.
1636 *
1637 * The vper/hper/hsper registers provide the frame period, line period
1638 * and horiz sync period (units of MCLK clock cycles (27MHz)) and
1639 * testing shows these values to be random if no signal is present
1640 * or locked.
1641 */
1642 v4l2_dbg(1, debug, sd, "inputs:%d/%d timings:%d/%d/%d\n",
1643 state->input_detect[0], state->input_detect[1],
1644 vper, hper, hsper);
1645 if (!state->input_detect[0] && !state->input_detect[1])
1646 *status = V4L2_IN_ST_NO_SIGNAL;
1647 else if (!vper || !hper || !hsper)
1648 *status = V4L2_IN_ST_NO_SYNC;
1649 else
1650 *status = 0;
1651 mutex_unlock(&state->lock);
1652
1653 return 0;
1654 };
1655
tda1997x_s_dv_timings(struct v4l2_subdev * sd,struct v4l2_dv_timings * timings)1656 static int tda1997x_s_dv_timings(struct v4l2_subdev *sd,
1657 struct v4l2_dv_timings *timings)
1658 {
1659 struct tda1997x_state *state = to_state(sd);
1660
1661 v4l_dbg(1, debug, state->client, "%s\n", __func__);
1662
1663 if (v4l2_match_dv_timings(&state->timings, timings, 0, false))
1664 return 0; /* no changes */
1665
1666 if (!v4l2_valid_dv_timings(timings, &tda1997x_dv_timings_cap,
1667 NULL, NULL))
1668 return -ERANGE;
1669
1670 mutex_lock(&state->lock);
1671 state->timings = *timings;
1672 /* setup frame detection window and VHREF timing generator */
1673 tda1997x_configure_vhref(sd);
1674 /* configure colorspace conversion */
1675 tda1997x_configure_csc(sd);
1676 mutex_unlock(&state->lock);
1677
1678 return 0;
1679 }
1680
tda1997x_g_dv_timings(struct v4l2_subdev * sd,struct v4l2_dv_timings * timings)1681 static int tda1997x_g_dv_timings(struct v4l2_subdev *sd,
1682 struct v4l2_dv_timings *timings)
1683 {
1684 struct tda1997x_state *state = to_state(sd);
1685
1686 v4l_dbg(1, debug, state->client, "%s\n", __func__);
1687 mutex_lock(&state->lock);
1688 *timings = state->timings;
1689 mutex_unlock(&state->lock);
1690
1691 return 0;
1692 }
1693
tda1997x_query_dv_timings(struct v4l2_subdev * sd,struct v4l2_dv_timings * timings)1694 static int tda1997x_query_dv_timings(struct v4l2_subdev *sd,
1695 struct v4l2_dv_timings *timings)
1696 {
1697 struct tda1997x_state *state = to_state(sd);
1698
1699 v4l_dbg(1, debug, state->client, "%s\n", __func__);
1700 memset(timings, 0, sizeof(struct v4l2_dv_timings));
1701 mutex_lock(&state->lock);
1702 tda1997x_detect_std(state, timings);
1703 mutex_unlock(&state->lock);
1704
1705 return 0;
1706 }
1707
1708 static const struct v4l2_subdev_video_ops tda1997x_video_ops = {
1709 .g_input_status = tda1997x_g_input_status,
1710 .s_dv_timings = tda1997x_s_dv_timings,
1711 .g_dv_timings = tda1997x_g_dv_timings,
1712 .query_dv_timings = tda1997x_query_dv_timings,
1713 };
1714
1715
1716 /* -----------------------------------------------------------------------------
1717 * v4l2_subdev_pad_ops
1718 */
1719
tda1997x_init_cfg(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg)1720 static int tda1997x_init_cfg(struct v4l2_subdev *sd,
1721 struct v4l2_subdev_pad_config *cfg)
1722 {
1723 struct tda1997x_state *state = to_state(sd);
1724 struct v4l2_mbus_framefmt *mf;
1725
1726 mf = v4l2_subdev_get_try_format(sd, cfg, 0);
1727 mf->code = state->mbus_codes[0];
1728
1729 return 0;
1730 }
1731
tda1997x_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_mbus_code_enum * code)1732 static int tda1997x_enum_mbus_code(struct v4l2_subdev *sd,
1733 struct v4l2_subdev_pad_config *cfg,
1734 struct v4l2_subdev_mbus_code_enum *code)
1735 {
1736 struct tda1997x_state *state = to_state(sd);
1737
1738 v4l_dbg(1, debug, state->client, "%s %d\n", __func__, code->index);
1739 if (code->index >= ARRAY_SIZE(state->mbus_codes))
1740 return -EINVAL;
1741
1742 if (!state->mbus_codes[code->index])
1743 return -EINVAL;
1744
1745 code->code = state->mbus_codes[code->index];
1746
1747 return 0;
1748 }
1749
tda1997x_fill_format(struct tda1997x_state * state,struct v4l2_mbus_framefmt * format)1750 static void tda1997x_fill_format(struct tda1997x_state *state,
1751 struct v4l2_mbus_framefmt *format)
1752 {
1753 const struct v4l2_bt_timings *bt;
1754
1755 memset(format, 0, sizeof(*format));
1756 bt = &state->timings.bt;
1757 format->width = bt->width;
1758 format->height = bt->height;
1759 format->colorspace = state->colorimetry.colorspace;
1760 format->field = (bt->interlaced) ?
1761 V4L2_FIELD_SEQ_TB : V4L2_FIELD_NONE;
1762 }
1763
tda1997x_get_format(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * format)1764 static int tda1997x_get_format(struct v4l2_subdev *sd,
1765 struct v4l2_subdev_pad_config *cfg,
1766 struct v4l2_subdev_format *format)
1767 {
1768 struct tda1997x_state *state = to_state(sd);
1769
1770 v4l_dbg(1, debug, state->client, "%s pad=%d which=%d\n",
1771 __func__, format->pad, format->which);
1772
1773 tda1997x_fill_format(state, &format->format);
1774
1775 if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
1776 struct v4l2_mbus_framefmt *fmt;
1777
1778 fmt = v4l2_subdev_get_try_format(sd, cfg, format->pad);
1779 format->format.code = fmt->code;
1780 } else
1781 format->format.code = state->mbus_code;
1782
1783 return 0;
1784 }
1785
tda1997x_set_format(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * format)1786 static int tda1997x_set_format(struct v4l2_subdev *sd,
1787 struct v4l2_subdev_pad_config *cfg,
1788 struct v4l2_subdev_format *format)
1789 {
1790 struct tda1997x_state *state = to_state(sd);
1791 u32 code = 0;
1792 int i;
1793
1794 v4l_dbg(1, debug, state->client, "%s pad=%d which=%d fmt=0x%x\n",
1795 __func__, format->pad, format->which, format->format.code);
1796
1797 for (i = 0; i < ARRAY_SIZE(state->mbus_codes); i++) {
1798 if (format->format.code == state->mbus_codes[i]) {
1799 code = state->mbus_codes[i];
1800 break;
1801 }
1802 }
1803 if (!code)
1804 code = state->mbus_codes[0];
1805
1806 tda1997x_fill_format(state, &format->format);
1807 format->format.code = code;
1808
1809 if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
1810 struct v4l2_mbus_framefmt *fmt;
1811
1812 fmt = v4l2_subdev_get_try_format(sd, cfg, format->pad);
1813 *fmt = format->format;
1814 } else {
1815 int ret = tda1997x_setup_format(state, format->format.code);
1816
1817 if (ret)
1818 return ret;
1819 /* mbus_code has changed - re-configure csc/vidout */
1820 tda1997x_configure_csc(sd);
1821 tda1997x_configure_vidout(state);
1822 }
1823
1824 return 0;
1825 }
1826
tda1997x_get_edid(struct v4l2_subdev * sd,struct v4l2_edid * edid)1827 static int tda1997x_get_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid)
1828 {
1829 struct tda1997x_state *state = to_state(sd);
1830
1831 v4l_dbg(1, debug, state->client, "%s pad=%d\n", __func__, edid->pad);
1832 memset(edid->reserved, 0, sizeof(edid->reserved));
1833
1834 if (edid->start_block == 0 && edid->blocks == 0) {
1835 edid->blocks = state->edid.blocks;
1836 return 0;
1837 }
1838
1839 if (!state->edid.present)
1840 return -ENODATA;
1841
1842 if (edid->start_block >= state->edid.blocks)
1843 return -EINVAL;
1844
1845 if (edid->start_block + edid->blocks > state->edid.blocks)
1846 edid->blocks = state->edid.blocks - edid->start_block;
1847
1848 memcpy(edid->edid, state->edid.edid + edid->start_block * 128,
1849 edid->blocks * 128);
1850
1851 return 0;
1852 }
1853
tda1997x_set_edid(struct v4l2_subdev * sd,struct v4l2_edid * edid)1854 static int tda1997x_set_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid)
1855 {
1856 struct tda1997x_state *state = to_state(sd);
1857 int i;
1858
1859 v4l_dbg(1, debug, state->client, "%s pad=%d\n", __func__, edid->pad);
1860 memset(edid->reserved, 0, sizeof(edid->reserved));
1861
1862 if (edid->start_block != 0)
1863 return -EINVAL;
1864
1865 if (edid->blocks == 0) {
1866 state->edid.blocks = 0;
1867 state->edid.present = 0;
1868 tda1997x_disable_edid(sd);
1869 return 0;
1870 }
1871
1872 if (edid->blocks > 2) {
1873 edid->blocks = 2;
1874 return -E2BIG;
1875 }
1876
1877 tda1997x_disable_edid(sd);
1878
1879 /* write base EDID */
1880 for (i = 0; i < 128; i++)
1881 io_write(sd, REG_EDID_IN_BYTE0 + i, edid->edid[i]);
1882
1883 /* write CEA Extension */
1884 for (i = 0; i < 128; i++)
1885 io_write(sd, REG_EDID_IN_BYTE128 + i, edid->edid[i+128]);
1886
1887 tda1997x_enable_edid(sd);
1888
1889 return 0;
1890 }
1891
tda1997x_get_dv_timings_cap(struct v4l2_subdev * sd,struct v4l2_dv_timings_cap * cap)1892 static int tda1997x_get_dv_timings_cap(struct v4l2_subdev *sd,
1893 struct v4l2_dv_timings_cap *cap)
1894 {
1895 *cap = tda1997x_dv_timings_cap;
1896 return 0;
1897 }
1898
tda1997x_enum_dv_timings(struct v4l2_subdev * sd,struct v4l2_enum_dv_timings * timings)1899 static int tda1997x_enum_dv_timings(struct v4l2_subdev *sd,
1900 struct v4l2_enum_dv_timings *timings)
1901 {
1902 return v4l2_enum_dv_timings_cap(timings, &tda1997x_dv_timings_cap,
1903 NULL, NULL);
1904 }
1905
1906 static const struct v4l2_subdev_pad_ops tda1997x_pad_ops = {
1907 .init_cfg = tda1997x_init_cfg,
1908 .enum_mbus_code = tda1997x_enum_mbus_code,
1909 .get_fmt = tda1997x_get_format,
1910 .set_fmt = tda1997x_set_format,
1911 .get_edid = tda1997x_get_edid,
1912 .set_edid = tda1997x_set_edid,
1913 .dv_timings_cap = tda1997x_get_dv_timings_cap,
1914 .enum_dv_timings = tda1997x_enum_dv_timings,
1915 };
1916
1917 /* -----------------------------------------------------------------------------
1918 * v4l2_subdev_core_ops
1919 */
1920
tda1997x_log_infoframe(struct v4l2_subdev * sd,int addr)1921 static int tda1997x_log_infoframe(struct v4l2_subdev *sd, int addr)
1922 {
1923 struct tda1997x_state *state = to_state(sd);
1924 union hdmi_infoframe frame;
1925 u8 buffer[40];
1926 int len, err;
1927
1928 /* read data */
1929 len = io_readn(sd, addr, sizeof(buffer), buffer);
1930 v4l2_dbg(1, debug, sd, "infoframe: addr=%d len=%d\n", addr, len);
1931 err = hdmi_infoframe_unpack(&frame, buffer);
1932 if (err) {
1933 v4l_err(state->client,
1934 "failed parsing %d byte infoframe: 0x%04x/0x%02x\n",
1935 len, addr, buffer[0]);
1936 return err;
1937 }
1938 hdmi_infoframe_log(KERN_INFO, &state->client->dev, &frame);
1939
1940 return 0;
1941 }
1942
tda1997x_log_status(struct v4l2_subdev * sd)1943 static int tda1997x_log_status(struct v4l2_subdev *sd)
1944 {
1945 struct tda1997x_state *state = to_state(sd);
1946 struct v4l2_dv_timings timings;
1947 struct hdmi_avi_infoframe *avi = &state->avi_infoframe;
1948
1949 v4l2_info(sd, "-----Chip status-----\n");
1950 v4l2_info(sd, "Chip: %s N%d\n", state->info->name,
1951 state->chip_revision + 1);
1952 v4l2_info(sd, "EDID Enabled: %s\n", state->edid.present ? "yes" : "no");
1953
1954 v4l2_info(sd, "-----Signal status-----\n");
1955 v4l2_info(sd, "Cable detected (+5V power): %s\n",
1956 tda1997x_detect_tx_5v(sd) ? "yes" : "no");
1957 v4l2_info(sd, "HPD detected: %s\n",
1958 tda1997x_detect_tx_hpd(sd) ? "yes" : "no");
1959
1960 v4l2_info(sd, "-----Video Timings-----\n");
1961 switch (tda1997x_detect_std(state, &timings)) {
1962 case -ENOLINK:
1963 v4l2_info(sd, "No video detected\n");
1964 break;
1965 case -ERANGE:
1966 v4l2_info(sd, "Invalid signal detected\n");
1967 break;
1968 }
1969 v4l2_print_dv_timings(sd->name, "Configured format: ",
1970 &state->timings, true);
1971
1972 v4l2_info(sd, "-----Color space-----\n");
1973 v4l2_info(sd, "Input color space: %s %s %s",
1974 hdmi_colorspace_names[avi->colorspace],
1975 (avi->colorspace == HDMI_COLORSPACE_RGB) ? "" :
1976 hdmi_colorimetry_names[avi->colorimetry],
1977 v4l2_quantization_names[state->colorimetry.quantization]);
1978 v4l2_info(sd, "Output color space: %s",
1979 vidfmt_names[state->vid_fmt]);
1980 v4l2_info(sd, "Color space conversion: %s", state->conv ?
1981 state->conv->name : "None");
1982
1983 v4l2_info(sd, "-----Audio-----\n");
1984 if (state->audio_channels) {
1985 v4l2_info(sd, "audio: %dch %dHz\n", state->audio_channels,
1986 state->audio_samplerate);
1987 } else {
1988 v4l2_info(sd, "audio: none\n");
1989 }
1990
1991 v4l2_info(sd, "-----Infoframes-----\n");
1992 tda1997x_log_infoframe(sd, AUD_IF);
1993 tda1997x_log_infoframe(sd, SPD_IF);
1994 tda1997x_log_infoframe(sd, AVI_IF);
1995
1996 return 0;
1997 }
1998
tda1997x_subscribe_event(struct v4l2_subdev * sd,struct v4l2_fh * fh,struct v4l2_event_subscription * sub)1999 static int tda1997x_subscribe_event(struct v4l2_subdev *sd,
2000 struct v4l2_fh *fh,
2001 struct v4l2_event_subscription *sub)
2002 {
2003 switch (sub->type) {
2004 case V4L2_EVENT_SOURCE_CHANGE:
2005 return v4l2_src_change_event_subdev_subscribe(sd, fh, sub);
2006 case V4L2_EVENT_CTRL:
2007 return v4l2_ctrl_subdev_subscribe_event(sd, fh, sub);
2008 default:
2009 return -EINVAL;
2010 }
2011 }
2012
2013 static const struct v4l2_subdev_core_ops tda1997x_core_ops = {
2014 .log_status = tda1997x_log_status,
2015 .subscribe_event = tda1997x_subscribe_event,
2016 .unsubscribe_event = v4l2_event_subdev_unsubscribe,
2017 };
2018
2019 /* -----------------------------------------------------------------------------
2020 * v4l2_subdev_ops
2021 */
2022
2023 static const struct v4l2_subdev_ops tda1997x_subdev_ops = {
2024 .core = &tda1997x_core_ops,
2025 .video = &tda1997x_video_ops,
2026 .pad = &tda1997x_pad_ops,
2027 };
2028
2029 /* -----------------------------------------------------------------------------
2030 * v4l2_controls
2031 */
2032
tda1997x_s_ctrl(struct v4l2_ctrl * ctrl)2033 static int tda1997x_s_ctrl(struct v4l2_ctrl *ctrl)
2034 {
2035 struct v4l2_subdev *sd = to_sd(ctrl);
2036 struct tda1997x_state *state = to_state(sd);
2037
2038 switch (ctrl->id) {
2039 /* allow overriding the default RGB quantization range */
2040 case V4L2_CID_DV_RX_RGB_RANGE:
2041 state->rgb_quantization_range = ctrl->val;
2042 set_rgb_quantization_range(state);
2043 tda1997x_configure_csc(sd);
2044 return 0;
2045 }
2046
2047 return -EINVAL;
2048 };
2049
tda1997x_g_volatile_ctrl(struct v4l2_ctrl * ctrl)2050 static int tda1997x_g_volatile_ctrl(struct v4l2_ctrl *ctrl)
2051 {
2052 struct v4l2_subdev *sd = to_sd(ctrl);
2053 struct tda1997x_state *state = to_state(sd);
2054
2055 if (ctrl->id == V4L2_CID_DV_RX_IT_CONTENT_TYPE) {
2056 ctrl->val = state->avi_infoframe.content_type;
2057 return 0;
2058 }
2059 return -EINVAL;
2060 };
2061
2062 static const struct v4l2_ctrl_ops tda1997x_ctrl_ops = {
2063 .s_ctrl = tda1997x_s_ctrl,
2064 .g_volatile_ctrl = tda1997x_g_volatile_ctrl,
2065 };
2066
tda1997x_core_init(struct v4l2_subdev * sd)2067 static int tda1997x_core_init(struct v4l2_subdev *sd)
2068 {
2069 struct tda1997x_state *state = to_state(sd);
2070 struct tda1997x_platform_data *pdata = &state->pdata;
2071 u8 reg;
2072 int i;
2073
2074 /* disable HPD */
2075 io_write(sd, REG_HPD_AUTO_CTRL, HPD_AUTO_HPD_UNSEL);
2076 if (state->chip_revision == 0) {
2077 io_write(sd, REG_MAN_SUS_HDMI_SEL, MAN_DIS_HDCP | MAN_RST_HDCP);
2078 io_write(sd, REG_CGU_DBG_SEL, 1 << CGU_DBG_CLK_SEL_SHIFT);
2079 }
2080
2081 /* reset infoframe at end of start-up-sequencer */
2082 io_write(sd, REG_SUS_SET_RGB2, 0x06);
2083 io_write(sd, REG_SUS_SET_RGB3, 0x06);
2084
2085 /* Enable TMDS pull-ups */
2086 io_write(sd, REG_RT_MAN_CTRL, RT_MAN_CTRL_RT |
2087 RT_MAN_CTRL_RT_B | RT_MAN_CTRL_RT_A);
2088
2089 /* enable sync measurement timing */
2090 tda1997x_cec_write(sd, REG_PWR_CONTROL & 0xff, 0x04);
2091 /* adjust CEC clock divider */
2092 tda1997x_cec_write(sd, REG_OSC_DIVIDER & 0xff, 0x03);
2093 tda1997x_cec_write(sd, REG_EN_OSC_PERIOD_LSB & 0xff, 0xa0);
2094 io_write(sd, REG_TIMER_D, 0x54);
2095 /* enable power switch */
2096 reg = tda1997x_cec_read(sd, REG_CONTROL & 0xff);
2097 reg |= 0x20;
2098 tda1997x_cec_write(sd, REG_CONTROL & 0xff, reg);
2099 mdelay(50);
2100
2101 /* read the chip version */
2102 reg = io_read(sd, REG_VERSION);
2103 /* get the chip configuration */
2104 reg = io_read(sd, REG_CMTP_REG10);
2105
2106 /* enable interrupts we care about */
2107 io_write(sd, REG_INT_MASK_TOP,
2108 INTERRUPT_HDCP | INTERRUPT_AUDIO | INTERRUPT_INFO |
2109 INTERRUPT_RATE | INTERRUPT_SUS);
2110 /* config_mtp,fmt,sus_end,sus_st */
2111 io_write(sd, REG_INT_MASK_SUS, MASK_MPT | MASK_FMT | MASK_SUS_END);
2112 /* rate stability change for inputs A/B */
2113 io_write(sd, REG_INT_MASK_RATE, MASK_RATE_B_ST | MASK_RATE_A_ST);
2114 /* aud,spd,avi*/
2115 io_write(sd, REG_INT_MASK_INFO,
2116 MASK_AUD_IF | MASK_SPD_IF | MASK_AVI_IF);
2117 /* audio_freq,audio_flg,mute_flg,fifo_err */
2118 io_write(sd, REG_INT_MASK_AUDIO,
2119 MASK_AUDIO_FREQ_FLG | MASK_AUDIO_FLG | MASK_MUTE_FLG |
2120 MASK_ERROR_FIFO_PT);
2121 /* HDCP C5 state reached */
2122 io_write(sd, REG_INT_MASK_HDCP, MASK_STATE_C5);
2123 /* 5V detect and HDP pulse end */
2124 io_write(sd, REG_INT_MASK_DDC, MASK_DET_5V);
2125 /* don't care about AFE/MODE */
2126 io_write(sd, REG_INT_MASK_AFE, 0);
2127 io_write(sd, REG_INT_MASK_MODE, 0);
2128
2129 /* clear all interrupts */
2130 io_write(sd, REG_INT_FLG_CLR_TOP, 0xff);
2131 io_write(sd, REG_INT_FLG_CLR_SUS, 0xff);
2132 io_write(sd, REG_INT_FLG_CLR_DDC, 0xff);
2133 io_write(sd, REG_INT_FLG_CLR_RATE, 0xff);
2134 io_write(sd, REG_INT_FLG_CLR_MODE, 0xff);
2135 io_write(sd, REG_INT_FLG_CLR_INFO, 0xff);
2136 io_write(sd, REG_INT_FLG_CLR_AUDIO, 0xff);
2137 io_write(sd, REG_INT_FLG_CLR_HDCP, 0xff);
2138 io_write(sd, REG_INT_FLG_CLR_AFE, 0xff);
2139
2140 /* init TMDS equalizer */
2141 if (state->chip_revision == 0)
2142 io_write(sd, REG_CGU_DBG_SEL, 1 << CGU_DBG_CLK_SEL_SHIFT);
2143 io_write24(sd, REG_CLK_MIN_RATE, CLK_MIN_RATE);
2144 io_write24(sd, REG_CLK_MAX_RATE, CLK_MAX_RATE);
2145 if (state->chip_revision == 0)
2146 io_write(sd, REG_WDL_CFG, WDL_CFG_VAL);
2147 /* DC filter */
2148 io_write(sd, REG_DEEP_COLOR_CTRL, DC_FILTER_VAL);
2149 /* disable test pattern */
2150 io_write(sd, REG_SVC_MODE, 0x00);
2151 /* update HDMI INFO CTRL */
2152 io_write(sd, REG_INFO_CTRL, 0xff);
2153 /* write HDMI INFO EXCEED value */
2154 io_write(sd, REG_INFO_EXCEED, 3);
2155
2156 if (state->chip_revision == 0)
2157 tda1997x_reset_n1(state);
2158
2159 /*
2160 * No HDCP acknowledge when HDCP is disabled
2161 * and reset SUS to force format detection
2162 */
2163 tda1997x_hdmi_info_reset(sd, NACK_HDCP, true);
2164
2165 /* Set HPD low */
2166 tda1997x_manual_hpd(sd, HPD_LOW_BP);
2167
2168 /* Configure receiver capabilities */
2169 io_write(sd, REG_HDCP_BCAPS, HDCP_HDMI | HDCP_FAST_REAUTH);
2170
2171 /* Configure HDMI: Auto HDCP mode, packet controlled mute */
2172 reg = HDMI_CTRL_MUTE_AUTO << HDMI_CTRL_MUTE_SHIFT;
2173 reg |= HDMI_CTRL_HDCP_AUTO << HDMI_CTRL_HDCP_SHIFT;
2174 io_write(sd, REG_HDMI_CTRL, reg);
2175
2176 /* reset start-up-sequencer to force format detection */
2177 tda1997x_hdmi_info_reset(sd, 0, true);
2178
2179 /* disable matrix conversion */
2180 reg = io_read(sd, REG_VDP_CTRL);
2181 reg |= VDP_CTRL_MATRIX_BP;
2182 io_write(sd, REG_VDP_CTRL, reg);
2183
2184 /* set video output mode */
2185 tda1997x_configure_vidout(state);
2186
2187 /* configure video output port */
2188 for (i = 0; i < 9; i++) {
2189 v4l_dbg(1, debug, state->client, "vidout_cfg[%d]=0x%02x\n", i,
2190 pdata->vidout_port_cfg[i]);
2191 io_write(sd, REG_VP35_32_CTRL + i, pdata->vidout_port_cfg[i]);
2192 }
2193
2194 /* configure audio output port */
2195 tda1997x_configure_audout(sd, 0);
2196
2197 /* configure audio clock freq */
2198 switch (pdata->audout_mclk_fs) {
2199 case 512:
2200 reg = AUDIO_CLOCK_SEL_512FS;
2201 break;
2202 case 256:
2203 reg = AUDIO_CLOCK_SEL_256FS;
2204 break;
2205 case 128:
2206 reg = AUDIO_CLOCK_SEL_128FS;
2207 break;
2208 case 64:
2209 reg = AUDIO_CLOCK_SEL_64FS;
2210 break;
2211 case 32:
2212 reg = AUDIO_CLOCK_SEL_32FS;
2213 break;
2214 default:
2215 reg = AUDIO_CLOCK_SEL_16FS;
2216 break;
2217 }
2218 io_write(sd, REG_AUDIO_CLOCK, reg);
2219
2220 /* reset advanced infoframes (ISRC1/ISRC2/ACP) */
2221 tda1997x_hdmi_info_reset(sd, RESET_AI, false);
2222 /* reset infoframe */
2223 tda1997x_hdmi_info_reset(sd, RESET_IF, false);
2224 /* reset audio infoframes */
2225 tda1997x_hdmi_info_reset(sd, RESET_AUDIO, false);
2226 /* reset gamut */
2227 tda1997x_hdmi_info_reset(sd, RESET_GAMUT, false);
2228
2229 /* get initial HDMI status */
2230 state->hdmi_status = io_read(sd, REG_HDMI_FLAGS);
2231
2232 return 0;
2233 }
2234
tda1997x_set_power(struct tda1997x_state * state,bool on)2235 static int tda1997x_set_power(struct tda1997x_state *state, bool on)
2236 {
2237 int ret = 0;
2238
2239 if (on) {
2240 ret = regulator_bulk_enable(TDA1997X_NUM_SUPPLIES,
2241 state->supplies);
2242 msleep(300);
2243 } else {
2244 ret = regulator_bulk_disable(TDA1997X_NUM_SUPPLIES,
2245 state->supplies);
2246 }
2247
2248 return ret;
2249 }
2250
2251 static const struct i2c_device_id tda1997x_i2c_id[] = {
2252 {"tda19971", (kernel_ulong_t)&tda1997x_chip_info[TDA19971]},
2253 {"tda19973", (kernel_ulong_t)&tda1997x_chip_info[TDA19973]},
2254 { },
2255 };
2256 MODULE_DEVICE_TABLE(i2c, tda1997x_i2c_id);
2257
2258 static const struct of_device_id tda1997x_of_id[] __maybe_unused = {
2259 { .compatible = "nxp,tda19971", .data = &tda1997x_chip_info[TDA19971] },
2260 { .compatible = "nxp,tda19973", .data = &tda1997x_chip_info[TDA19973] },
2261 { },
2262 };
2263 MODULE_DEVICE_TABLE(of, tda1997x_of_id);
2264
tda1997x_parse_dt(struct tda1997x_state * state)2265 static int tda1997x_parse_dt(struct tda1997x_state *state)
2266 {
2267 struct tda1997x_platform_data *pdata = &state->pdata;
2268 struct v4l2_fwnode_endpoint bus_cfg;
2269 struct device_node *ep;
2270 struct device_node *np;
2271 unsigned int flags;
2272 const char *str;
2273 int ret;
2274 u32 v;
2275
2276 /*
2277 * setup default values:
2278 * - HREF: active high from start to end of row
2279 * - VS: Vertical Sync active high at beginning of frame
2280 * - DE: Active high when data valid
2281 * - A_CLK: 128*Fs
2282 */
2283 pdata->vidout_sel_hs = HS_HREF_SEL_HREF_VHREF;
2284 pdata->vidout_sel_vs = VS_VREF_SEL_VREF_HDMI;
2285 pdata->vidout_sel_de = DE_FREF_SEL_DE_VHREF;
2286
2287 np = state->client->dev.of_node;
2288 ep = of_graph_get_next_endpoint(np, NULL);
2289 if (!ep)
2290 return -EINVAL;
2291
2292 ret = v4l2_fwnode_endpoint_parse(of_fwnode_handle(ep), &bus_cfg);
2293 if (ret) {
2294 of_node_put(ep);
2295 return ret;
2296 }
2297 of_node_put(ep);
2298 pdata->vidout_bus_type = bus_cfg.bus_type;
2299
2300 /* polarity of HS/VS/DE */
2301 flags = bus_cfg.bus.parallel.flags;
2302 if (flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)
2303 pdata->vidout_inv_hs = 1;
2304 if (flags & V4L2_MBUS_VSYNC_ACTIVE_LOW)
2305 pdata->vidout_inv_vs = 1;
2306 if (flags & V4L2_MBUS_DATA_ACTIVE_LOW)
2307 pdata->vidout_inv_de = 1;
2308 pdata->vidout_bus_width = bus_cfg.bus.parallel.bus_width;
2309
2310 /* video output port config */
2311 ret = of_property_count_u32_elems(np, "nxp,vidout-portcfg");
2312 if (ret > 0) {
2313 u32 reg, val, i;
2314
2315 for (i = 0; i < ret / 2 && i < 9; i++) {
2316 of_property_read_u32_index(np, "nxp,vidout-portcfg",
2317 i * 2, ®);
2318 of_property_read_u32_index(np, "nxp,vidout-portcfg",
2319 i * 2 + 1, &val);
2320 if (reg < 9)
2321 pdata->vidout_port_cfg[reg] = val;
2322 }
2323 } else {
2324 v4l_err(state->client, "nxp,vidout-portcfg missing\n");
2325 return -EINVAL;
2326 }
2327
2328 /* default to channel layout dictated by packet header */
2329 pdata->audout_layoutauto = true;
2330
2331 pdata->audout_format = AUDFMT_TYPE_DISABLED;
2332 if (!of_property_read_string(np, "nxp,audout-format", &str)) {
2333 if (strcmp(str, "i2s") == 0)
2334 pdata->audout_format = AUDFMT_TYPE_I2S;
2335 else if (strcmp(str, "spdif") == 0)
2336 pdata->audout_format = AUDFMT_TYPE_SPDIF;
2337 else {
2338 v4l_err(state->client, "nxp,audout-format invalid\n");
2339 return -EINVAL;
2340 }
2341 if (!of_property_read_u32(np, "nxp,audout-layout", &v)) {
2342 switch (v) {
2343 case 0:
2344 case 1:
2345 break;
2346 default:
2347 v4l_err(state->client,
2348 "nxp,audout-layout invalid\n");
2349 return -EINVAL;
2350 }
2351 pdata->audout_layout = v;
2352 }
2353 if (!of_property_read_u32(np, "nxp,audout-width", &v)) {
2354 switch (v) {
2355 case 16:
2356 case 32:
2357 break;
2358 default:
2359 v4l_err(state->client,
2360 "nxp,audout-width invalid\n");
2361 return -EINVAL;
2362 }
2363 pdata->audout_width = v;
2364 }
2365 if (!of_property_read_u32(np, "nxp,audout-mclk-fs", &v)) {
2366 switch (v) {
2367 case 512:
2368 case 256:
2369 case 128:
2370 case 64:
2371 case 32:
2372 case 16:
2373 break;
2374 default:
2375 v4l_err(state->client,
2376 "nxp,audout-mclk-fs invalid\n");
2377 return -EINVAL;
2378 }
2379 pdata->audout_mclk_fs = v;
2380 }
2381 }
2382
2383 return 0;
2384 }
2385
tda1997x_get_regulators(struct tda1997x_state * state)2386 static int tda1997x_get_regulators(struct tda1997x_state *state)
2387 {
2388 int i;
2389
2390 for (i = 0; i < TDA1997X_NUM_SUPPLIES; i++)
2391 state->supplies[i].supply = tda1997x_supply_name[i];
2392
2393 return devm_regulator_bulk_get(&state->client->dev,
2394 TDA1997X_NUM_SUPPLIES,
2395 state->supplies);
2396 }
2397
tda1997x_identify_module(struct tda1997x_state * state)2398 static int tda1997x_identify_module(struct tda1997x_state *state)
2399 {
2400 struct v4l2_subdev *sd = &state->sd;
2401 enum tda1997x_type type;
2402 u8 reg;
2403
2404 /* Read chip configuration*/
2405 reg = io_read(sd, REG_CMTP_REG10);
2406 state->tmdsb_clk = (reg >> 6) & 0x01; /* use tmds clock B_inv for B */
2407 state->tmdsb_soc = (reg >> 5) & 0x01; /* tmds of input B */
2408 state->port_30bit = (reg >> 2) & 0x03; /* 30bit vs 24bit */
2409 state->output_2p5 = (reg >> 1) & 0x01; /* output supply 2.5v */
2410 switch ((reg >> 4) & 0x03) {
2411 case 0x00:
2412 type = TDA19971;
2413 break;
2414 case 0x02:
2415 case 0x03:
2416 type = TDA19973;
2417 break;
2418 default:
2419 dev_err(&state->client->dev, "unsupported chip ID\n");
2420 return -EIO;
2421 }
2422 if (state->info->type != type) {
2423 dev_err(&state->client->dev, "chip id mismatch\n");
2424 return -EIO;
2425 }
2426
2427 /* read chip revision */
2428 state->chip_revision = io_read(sd, REG_CMTP_REG11);
2429
2430 return 0;
2431 }
2432
2433 static const struct media_entity_operations tda1997x_media_ops = {
2434 .link_validate = v4l2_subdev_link_validate,
2435 };
2436
2437
2438 /* -----------------------------------------------------------------------------
2439 * HDMI Audio Codec
2440 */
2441
2442 /* refine sample-rate based on HDMI source */
tda1997x_pcm_startup(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)2443 static int tda1997x_pcm_startup(struct snd_pcm_substream *substream,
2444 struct snd_soc_dai *dai)
2445 {
2446 struct tda1997x_state *state = snd_soc_dai_get_drvdata(dai);
2447 struct snd_soc_component *component = dai->component;
2448 struct snd_pcm_runtime *rtd = substream->runtime;
2449 int rate, err;
2450
2451 rate = state->audio_samplerate;
2452 err = snd_pcm_hw_constraint_minmax(rtd, SNDRV_PCM_HW_PARAM_RATE,
2453 rate, rate);
2454 if (err < 0) {
2455 dev_err(component->dev, "failed to constrain samplerate to %dHz\n",
2456 rate);
2457 return err;
2458 }
2459 dev_info(component->dev, "set samplerate constraint to %dHz\n", rate);
2460
2461 return 0;
2462 }
2463
2464 static const struct snd_soc_dai_ops tda1997x_dai_ops = {
2465 .startup = tda1997x_pcm_startup,
2466 };
2467
2468 static struct snd_soc_dai_driver tda1997x_audio_dai = {
2469 .name = "tda1997x",
2470 .capture = {
2471 .stream_name = "Capture",
2472 .channels_min = 2,
2473 .channels_max = 8,
2474 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
2475 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
2476 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
2477 SNDRV_PCM_RATE_192000,
2478 },
2479 .ops = &tda1997x_dai_ops,
2480 };
2481
tda1997x_codec_probe(struct snd_soc_component * component)2482 static int tda1997x_codec_probe(struct snd_soc_component *component)
2483 {
2484 return 0;
2485 }
2486
tda1997x_codec_remove(struct snd_soc_component * component)2487 static void tda1997x_codec_remove(struct snd_soc_component *component)
2488 {
2489 }
2490
2491 static struct snd_soc_component_driver tda1997x_codec_driver = {
2492 .probe = tda1997x_codec_probe,
2493 .remove = tda1997x_codec_remove,
2494 .idle_bias_on = 1,
2495 .use_pmdown_time = 1,
2496 .endianness = 1,
2497 .non_legacy_dai_naming = 1,
2498 };
2499
tda1997x_probe(struct i2c_client * client,const struct i2c_device_id * id)2500 static int tda1997x_probe(struct i2c_client *client,
2501 const struct i2c_device_id *id)
2502 {
2503 struct tda1997x_state *state;
2504 struct tda1997x_platform_data *pdata;
2505 struct v4l2_subdev *sd;
2506 struct v4l2_ctrl_handler *hdl;
2507 struct v4l2_ctrl *ctrl;
2508 static const struct v4l2_dv_timings cea1920x1080 =
2509 V4L2_DV_BT_CEA_1920X1080P60;
2510 u32 *mbus_codes;
2511 int i, ret;
2512
2513 /* Check if the adapter supports the needed features */
2514 if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
2515 return -EIO;
2516
2517 state = kzalloc(sizeof(struct tda1997x_state), GFP_KERNEL);
2518 if (!state)
2519 return -ENOMEM;
2520
2521 state->client = client;
2522 pdata = &state->pdata;
2523 if (IS_ENABLED(CONFIG_OF) && client->dev.of_node) {
2524 const struct of_device_id *oid;
2525
2526 oid = of_match_node(tda1997x_of_id, client->dev.of_node);
2527 state->info = oid->data;
2528
2529 ret = tda1997x_parse_dt(state);
2530 if (ret < 0) {
2531 v4l_err(client, "DT parsing error\n");
2532 goto err_free_state;
2533 }
2534 } else if (client->dev.platform_data) {
2535 struct tda1997x_platform_data *pdata =
2536 client->dev.platform_data;
2537 state->info =
2538 (const struct tda1997x_chip_info *)id->driver_data;
2539 state->pdata = *pdata;
2540 } else {
2541 v4l_err(client, "No platform data\n");
2542 ret = -ENODEV;
2543 goto err_free_state;
2544 }
2545
2546 ret = tda1997x_get_regulators(state);
2547 if (ret)
2548 goto err_free_state;
2549
2550 ret = tda1997x_set_power(state, 1);
2551 if (ret)
2552 goto err_free_state;
2553
2554 mutex_init(&state->page_lock);
2555 mutex_init(&state->lock);
2556 state->page = 0xff;
2557
2558 INIT_DELAYED_WORK(&state->delayed_work_enable_hpd,
2559 tda1997x_delayed_work_enable_hpd);
2560
2561 /* set video format based on chip and bus width */
2562 ret = tda1997x_identify_module(state);
2563 if (ret)
2564 goto err_free_mutex;
2565
2566 /* initialize subdev */
2567 sd = &state->sd;
2568 v4l2_i2c_subdev_init(sd, client, &tda1997x_subdev_ops);
2569 snprintf(sd->name, sizeof(sd->name), "%s %d-%04x",
2570 id->name, i2c_adapter_id(client->adapter),
2571 client->addr);
2572 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS;
2573 sd->entity.function = MEDIA_ENT_F_DV_DECODER;
2574 sd->entity.ops = &tda1997x_media_ops;
2575
2576 /* set allowed mbus modes based on chip, bus-type, and bus-width */
2577 i = 0;
2578 mbus_codes = state->mbus_codes;
2579 switch (state->info->type) {
2580 case TDA19973:
2581 switch (pdata->vidout_bus_type) {
2582 case V4L2_MBUS_PARALLEL:
2583 switch (pdata->vidout_bus_width) {
2584 case 36:
2585 mbus_codes[i++] = MEDIA_BUS_FMT_RGB121212_1X36;
2586 mbus_codes[i++] = MEDIA_BUS_FMT_YUV12_1X36;
2587 /* fall-through */
2588 case 24:
2589 mbus_codes[i++] = MEDIA_BUS_FMT_UYVY12_1X24;
2590 break;
2591 }
2592 break;
2593 case V4L2_MBUS_BT656:
2594 switch (pdata->vidout_bus_width) {
2595 case 36:
2596 case 24:
2597 case 12:
2598 mbus_codes[i++] = MEDIA_BUS_FMT_UYVY12_2X12;
2599 mbus_codes[i++] = MEDIA_BUS_FMT_UYVY10_2X10;
2600 mbus_codes[i++] = MEDIA_BUS_FMT_UYVY8_2X8;
2601 break;
2602 }
2603 break;
2604 default:
2605 break;
2606 }
2607 break;
2608 case TDA19971:
2609 switch (pdata->vidout_bus_type) {
2610 case V4L2_MBUS_PARALLEL:
2611 switch (pdata->vidout_bus_width) {
2612 case 24:
2613 mbus_codes[i++] = MEDIA_BUS_FMT_RGB888_1X24;
2614 mbus_codes[i++] = MEDIA_BUS_FMT_YUV8_1X24;
2615 mbus_codes[i++] = MEDIA_BUS_FMT_UYVY12_1X24;
2616 /* fall through */
2617 case 20:
2618 mbus_codes[i++] = MEDIA_BUS_FMT_UYVY10_1X20;
2619 /* fall through */
2620 case 16:
2621 mbus_codes[i++] = MEDIA_BUS_FMT_UYVY8_1X16;
2622 break;
2623 }
2624 break;
2625 case V4L2_MBUS_BT656:
2626 switch (pdata->vidout_bus_width) {
2627 case 24:
2628 case 20:
2629 case 16:
2630 case 12:
2631 mbus_codes[i++] = MEDIA_BUS_FMT_UYVY12_2X12;
2632 /* fall through */
2633 case 10:
2634 mbus_codes[i++] = MEDIA_BUS_FMT_UYVY10_2X10;
2635 /* fall through */
2636 case 8:
2637 mbus_codes[i++] = MEDIA_BUS_FMT_UYVY8_2X8;
2638 break;
2639 }
2640 break;
2641 default:
2642 break;
2643 }
2644 break;
2645 }
2646 if (WARN_ON(i > ARRAY_SIZE(state->mbus_codes))) {
2647 ret = -EINVAL;
2648 goto err_free_mutex;
2649 }
2650
2651 /* default format */
2652 tda1997x_setup_format(state, state->mbus_codes[0]);
2653 state->timings = cea1920x1080;
2654
2655 /*
2656 * default to SRGB full range quantization
2657 * (in case we don't get an infoframe such as DVI signal
2658 */
2659 state->colorimetry.colorspace = V4L2_COLORSPACE_SRGB;
2660 state->colorimetry.quantization = V4L2_QUANTIZATION_FULL_RANGE;
2661
2662 /* disable/reset HDCP to get correct I2C access to Rx HDMI */
2663 io_write(sd, REG_MAN_SUS_HDMI_SEL, MAN_RST_HDCP | MAN_DIS_HDCP);
2664
2665 /*
2666 * if N2 version, reset compdel_bp as it may generate some small pixel
2667 * shifts in case of embedded sync/or delay lower than 4
2668 */
2669 if (state->chip_revision != 0) {
2670 io_write(sd, REG_MAN_SUS_HDMI_SEL, 0x00);
2671 io_write(sd, REG_VDP_CTRL, 0x1f);
2672 }
2673
2674 v4l_info(client, "NXP %s N%d detected\n", state->info->name,
2675 state->chip_revision + 1);
2676 v4l_info(client, "video: %dbit %s %d formats available\n",
2677 pdata->vidout_bus_width,
2678 (pdata->vidout_bus_type == V4L2_MBUS_PARALLEL) ?
2679 "parallel" : "BT656",
2680 i);
2681 if (pdata->audout_format) {
2682 v4l_info(client, "audio: %dch %s layout%d sysclk=%d*fs\n",
2683 pdata->audout_layout ? 2 : 8,
2684 audfmt_names[pdata->audout_format],
2685 pdata->audout_layout,
2686 pdata->audout_mclk_fs);
2687 }
2688
2689 ret = 0x34 + ((io_read(sd, REG_SLAVE_ADDR)>>4) & 0x03);
2690 state->client_cec = i2c_new_dummy(client->adapter, ret);
2691 v4l_info(client, "CEC slave address 0x%02x\n", ret);
2692
2693 ret = tda1997x_core_init(sd);
2694 if (ret)
2695 goto err_free_mutex;
2696
2697 /* control handlers */
2698 hdl = &state->hdl;
2699 v4l2_ctrl_handler_init(hdl, 3);
2700 ctrl = v4l2_ctrl_new_std_menu(hdl, &tda1997x_ctrl_ops,
2701 V4L2_CID_DV_RX_IT_CONTENT_TYPE,
2702 V4L2_DV_IT_CONTENT_TYPE_NO_ITC, 0,
2703 V4L2_DV_IT_CONTENT_TYPE_NO_ITC);
2704 if (ctrl)
2705 ctrl->flags |= V4L2_CTRL_FLAG_VOLATILE;
2706 /* custom controls */
2707 state->detect_tx_5v_ctrl = v4l2_ctrl_new_std(hdl, NULL,
2708 V4L2_CID_DV_RX_POWER_PRESENT, 0, 1, 0, 0);
2709 state->rgb_quantization_range_ctrl = v4l2_ctrl_new_std_menu(hdl,
2710 &tda1997x_ctrl_ops,
2711 V4L2_CID_DV_RX_RGB_RANGE, V4L2_DV_RGB_RANGE_FULL, 0,
2712 V4L2_DV_RGB_RANGE_AUTO);
2713 state->sd.ctrl_handler = hdl;
2714 if (hdl->error) {
2715 ret = hdl->error;
2716 goto err_free_handler;
2717 }
2718 v4l2_ctrl_handler_setup(hdl);
2719
2720 /* initialize source pads */
2721 state->pads[TDA1997X_PAD_SOURCE].flags = MEDIA_PAD_FL_SOURCE;
2722 ret = media_entity_pads_init(&sd->entity, TDA1997X_NUM_PADS,
2723 state->pads);
2724 if (ret) {
2725 v4l_err(client, "failed entity_init: %d", ret);
2726 goto err_free_handler;
2727 }
2728
2729 ret = v4l2_async_register_subdev(sd);
2730 if (ret)
2731 goto err_free_media;
2732
2733 /* register audio DAI */
2734 if (pdata->audout_format) {
2735 u64 formats;
2736
2737 if (pdata->audout_width == 32)
2738 formats = SNDRV_PCM_FMTBIT_S32_LE;
2739 else
2740 formats = SNDRV_PCM_FMTBIT_S16_LE;
2741 tda1997x_audio_dai.capture.formats = formats;
2742 ret = devm_snd_soc_register_component(&state->client->dev,
2743 &tda1997x_codec_driver,
2744 &tda1997x_audio_dai, 1);
2745 if (ret) {
2746 dev_err(&client->dev, "register audio codec failed\n");
2747 goto err_free_media;
2748 }
2749 dev_set_drvdata(&state->client->dev, state);
2750 v4l_info(state->client, "registered audio codec\n");
2751 }
2752
2753 /* request irq */
2754 ret = devm_request_threaded_irq(&client->dev, client->irq,
2755 NULL, tda1997x_isr_thread,
2756 IRQF_TRIGGER_LOW | IRQF_ONESHOT,
2757 KBUILD_MODNAME, state);
2758 if (ret) {
2759 v4l_err(client, "irq%d reg failed: %d\n", client->irq, ret);
2760 goto err_free_media;
2761 }
2762
2763 return 0;
2764
2765 err_free_media:
2766 media_entity_cleanup(&sd->entity);
2767 err_free_handler:
2768 v4l2_ctrl_handler_free(&state->hdl);
2769 err_free_mutex:
2770 cancel_delayed_work(&state->delayed_work_enable_hpd);
2771 mutex_destroy(&state->page_lock);
2772 mutex_destroy(&state->lock);
2773 err_free_state:
2774 kfree(state);
2775 dev_err(&client->dev, "%s failed: %d\n", __func__, ret);
2776
2777 return ret;
2778 }
2779
tda1997x_remove(struct i2c_client * client)2780 static int tda1997x_remove(struct i2c_client *client)
2781 {
2782 struct v4l2_subdev *sd = i2c_get_clientdata(client);
2783 struct tda1997x_state *state = to_state(sd);
2784 struct tda1997x_platform_data *pdata = &state->pdata;
2785
2786 if (pdata->audout_format) {
2787 mutex_destroy(&state->audio_lock);
2788 }
2789
2790 disable_irq(state->client->irq);
2791 tda1997x_power_mode(state, 0);
2792
2793 v4l2_async_unregister_subdev(sd);
2794 media_entity_cleanup(&sd->entity);
2795 v4l2_ctrl_handler_free(&state->hdl);
2796 regulator_bulk_disable(TDA1997X_NUM_SUPPLIES, state->supplies);
2797 i2c_unregister_device(state->client_cec);
2798 cancel_delayed_work(&state->delayed_work_enable_hpd);
2799 mutex_destroy(&state->page_lock);
2800 mutex_destroy(&state->lock);
2801
2802 kfree(state);
2803
2804 return 0;
2805 }
2806
2807 static struct i2c_driver tda1997x_i2c_driver = {
2808 .driver = {
2809 .name = "tda1997x",
2810 .of_match_table = of_match_ptr(tda1997x_of_id),
2811 },
2812 .probe = tda1997x_probe,
2813 .remove = tda1997x_remove,
2814 .id_table = tda1997x_i2c_id,
2815 };
2816
2817 module_i2c_driver(tda1997x_i2c_driver);
2818
2819 MODULE_AUTHOR("Tim Harvey <tharvey@gateworks.com>");
2820 MODULE_DESCRIPTION("TDA1997X HDMI Receiver driver");
2821 MODULE_LICENSE("GPL v2");
2822
