1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Omnivision OV9650/OV9652 CMOS Image Sensor driver
4 *
5 * Copyright (C) 2013, Sylwester Nawrocki <sylvester.nawrocki@gmail.com>
6 *
7 * Register definitions and initial settings based on a driver written
8 * by Vladimir Fonov.
9 * Copyright (c) 2010, Vladimir Fonov
10 */
11 #include <linux/clk.h>
12 #include <linux/delay.h>
13 #include <linux/gpio.h>
14 #include <linux/gpio/consumer.h>
15 #include <linux/i2c.h>
16 #include <linux/kernel.h>
17 #include <linux/media.h>
18 #include <linux/module.h>
19 #include <linux/ratelimit.h>
20 #include <linux/regmap.h>
21 #include <linux/slab.h>
22 #include <linux/string.h>
23 #include <linux/videodev2.h>
24
25 #include <media/media-entity.h>
26 #include <media/v4l2-async.h>
27 #include <media/v4l2-ctrls.h>
28 #include <media/v4l2-device.h>
29 #include <media/v4l2-event.h>
30 #include <media/v4l2-image-sizes.h>
31 #include <media/v4l2-subdev.h>
32 #include <media/v4l2-mediabus.h>
33 #include <media/i2c/ov9650.h>
34
35 static int debug;
36 module_param(debug, int, 0644);
37 MODULE_PARM_DESC(debug, "Debug level (0-2)");
38
39 #define DRIVER_NAME "OV9650"
40
41 /*
42 * OV9650/OV9652 register definitions
43 */
44 #define REG_GAIN 0x00 /* Gain control, AGC[7:0] */
45 #define REG_BLUE 0x01 /* AWB - Blue channel gain */
46 #define REG_RED 0x02 /* AWB - Red channel gain */
47 #define REG_VREF 0x03 /* [7:6] - AGC[9:8], [5:3]/[2:0] */
48 #define VREF_GAIN_MASK 0xc0 /* - VREF end/start low 3 bits */
49 #define REG_COM1 0x04
50 #define COM1_CCIR656 0x40
51 #define REG_B_AVE 0x05
52 #define REG_GB_AVE 0x06
53 #define REG_GR_AVE 0x07
54 #define REG_R_AVE 0x08
55 #define REG_COM2 0x09
56 #define REG_PID 0x0a /* Product ID MSB */
57 #define REG_VER 0x0b /* Product ID LSB */
58 #define REG_COM3 0x0c
59 #define COM3_SWAP 0x40
60 #define COM3_VARIOPIXEL1 0x04
61 #define REG_COM4 0x0d /* Vario Pixels */
62 #define COM4_VARIOPIXEL2 0x80
63 #define REG_COM5 0x0e /* System clock options */
64 #define COM5_SLAVE_MODE 0x10
65 #define COM5_SYSTEMCLOCK48MHZ 0x80
66 #define REG_COM6 0x0f /* HREF & ADBLC options */
67 #define REG_AECH 0x10 /* Exposure value, AEC[9:2] */
68 #define REG_CLKRC 0x11 /* Clock control */
69 #define CLK_EXT 0x40 /* Use external clock directly */
70 #define CLK_SCALE 0x3f /* Mask for internal clock scale */
71 #define REG_COM7 0x12 /* SCCB reset, output format */
72 #define COM7_RESET 0x80
73 #define COM7_FMT_MASK 0x38
74 #define COM7_FMT_VGA 0x40
75 #define COM7_FMT_CIF 0x20
76 #define COM7_FMT_QVGA 0x10
77 #define COM7_FMT_QCIF 0x08
78 #define COM7_RGB 0x04
79 #define COM7_YUV 0x00
80 #define COM7_BAYER 0x01
81 #define COM7_PBAYER 0x05
82 #define REG_COM8 0x13 /* AGC/AEC options */
83 #define COM8_FASTAEC 0x80 /* Enable fast AGC/AEC */
84 #define COM8_AECSTEP 0x40 /* Unlimited AEC step size */
85 #define COM8_BFILT 0x20 /* Band filter enable */
86 #define COM8_AGC 0x04 /* Auto gain enable */
87 #define COM8_AWB 0x02 /* White balance enable */
88 #define COM8_AEC 0x01 /* Auto exposure enable */
89 #define REG_COM9 0x14 /* Gain ceiling */
90 #define COM9_GAIN_CEIL_MASK 0x70 /* */
91 #define REG_COM10 0x15 /* PCLK, HREF, HSYNC signals polarity */
92 #define COM10_HSYNC 0x40 /* HSYNC instead of HREF */
93 #define COM10_PCLK_HB 0x20 /* Suppress PCLK on horiz blank */
94 #define COM10_HREF_REV 0x08 /* Reverse HREF */
95 #define COM10_VS_LEAD 0x04 /* VSYNC on clock leading edge */
96 #define COM10_VS_NEG 0x02 /* VSYNC negative */
97 #define COM10_HS_NEG 0x01 /* HSYNC negative */
98 #define REG_HSTART 0x17 /* Horiz start high bits */
99 #define REG_HSTOP 0x18 /* Horiz stop high bits */
100 #define REG_VSTART 0x19 /* Vert start high bits */
101 #define REG_VSTOP 0x1a /* Vert stop high bits */
102 #define REG_PSHFT 0x1b /* Pixel delay after HREF */
103 #define REG_MIDH 0x1c /* Manufacturer ID MSB */
104 #define REG_MIDL 0x1d /* Manufufacturer ID LSB */
105 #define REG_MVFP 0x1e /* Image mirror/flip */
106 #define MVFP_MIRROR 0x20 /* Mirror image */
107 #define MVFP_FLIP 0x10 /* Vertical flip */
108 #define REG_BOS 0x20 /* B channel Offset */
109 #define REG_GBOS 0x21 /* Gb channel Offset */
110 #define REG_GROS 0x22 /* Gr channel Offset */
111 #define REG_ROS 0x23 /* R channel Offset */
112 #define REG_AEW 0x24 /* AGC upper limit */
113 #define REG_AEB 0x25 /* AGC lower limit */
114 #define REG_VPT 0x26 /* AGC/AEC fast mode op region */
115 #define REG_BBIAS 0x27 /* B channel output bias */
116 #define REG_GBBIAS 0x28 /* Gb channel output bias */
117 #define REG_GRCOM 0x29 /* Analog BLC & regulator */
118 #define REG_EXHCH 0x2a /* Dummy pixel insert MSB */
119 #define REG_EXHCL 0x2b /* Dummy pixel insert LSB */
120 #define REG_RBIAS 0x2c /* R channel output bias */
121 #define REG_ADVFL 0x2d /* LSB of dummy line insert */
122 #define REG_ADVFH 0x2e /* MSB of dummy line insert */
123 #define REG_YAVE 0x2f /* Y/G channel average value */
124 #define REG_HSYST 0x30 /* HSYNC rising edge delay LSB*/
125 #define REG_HSYEN 0x31 /* HSYNC falling edge delay LSB*/
126 #define REG_HREF 0x32 /* HREF pieces */
127 #define REG_CHLF 0x33 /* reserved */
128 #define REG_ADC 0x37 /* reserved */
129 #define REG_ACOM 0x38 /* reserved */
130 #define REG_OFON 0x39 /* Power down register */
131 #define OFON_PWRDN 0x08 /* Power down bit */
132 #define REG_TSLB 0x3a /* YUVU format */
133 #define TSLB_YUYV_MASK 0x0c /* UYVY or VYUY - see com13 */
134 #define REG_COM11 0x3b /* Night mode, banding filter enable */
135 #define COM11_NIGHT 0x80 /* Night mode enable */
136 #define COM11_NMFR 0x60 /* Two bit NM frame rate */
137 #define COM11_BANDING 0x01 /* Banding filter */
138 #define COM11_AEC_REF_MASK 0x18 /* AEC reference area selection */
139 #define REG_COM12 0x3c /* HREF option, UV average */
140 #define COM12_HREF 0x80 /* HREF always */
141 #define REG_COM13 0x3d /* Gamma selection, Color matrix en. */
142 #define COM13_GAMMA 0x80 /* Gamma enable */
143 #define COM13_UVSAT 0x40 /* UV saturation auto adjustment */
144 #define COM13_UVSWAP 0x01 /* V before U - w/TSLB */
145 #define REG_COM14 0x3e /* Edge enhancement options */
146 #define COM14_EDGE_EN 0x02
147 #define COM14_EEF_X2 0x01
148 #define REG_EDGE 0x3f /* Edge enhancement factor */
149 #define EDGE_FACTOR_MASK 0x0f
150 #define REG_COM15 0x40 /* Output range, RGB 555/565 */
151 #define COM15_R10F0 0x00 /* Data range 10 to F0 */
152 #define COM15_R01FE 0x80 /* 01 to FE */
153 #define COM15_R00FF 0xc0 /* 00 to FF */
154 #define COM15_RGB565 0x10 /* RGB565 output */
155 #define COM15_RGB555 0x30 /* RGB555 output */
156 #define COM15_SWAPRB 0x04 /* Swap R&B */
157 #define REG_COM16 0x41 /* Color matrix coeff options */
158 #define REG_COM17 0x42 /* Single frame out, banding filter */
159 /* n = 1...9, 0x4f..0x57 */
160 #define REG_MTX(__n) (0x4f + (__n) - 1)
161 #define REG_MTXS 0x58
162 /* Lens Correction Option 1...5, __n = 0...5 */
163 #define REG_LCC(__n) (0x62 + (__n) - 1)
164 #define LCC5_LCC_ENABLE 0x01 /* LCC5, enable lens correction */
165 #define LCC5_LCC_COLOR 0x04
166 #define REG_MANU 0x67 /* Manual U value */
167 #define REG_MANV 0x68 /* Manual V value */
168 #define REG_HV 0x69 /* Manual banding filter MSB */
169 #define REG_MBD 0x6a /* Manual banding filter value */
170 #define REG_DBLV 0x6b /* reserved */
171 #define REG_GSP 0x6c /* Gamma curve */
172 #define GSP_LEN 15
173 #define REG_GST 0x7c /* Gamma curve */
174 #define GST_LEN 15
175 #define REG_COM21 0x8b
176 #define REG_COM22 0x8c /* Edge enhancement, denoising */
177 #define COM22_WHTPCOR 0x02 /* White pixel correction enable */
178 #define COM22_WHTPCOROPT 0x01 /* White pixel correction option */
179 #define COM22_DENOISE 0x10 /* White pixel correction option */
180 #define REG_COM23 0x8d /* Color bar test, color gain */
181 #define COM23_TEST_MODE 0x10
182 #define REG_DBLC1 0x8f /* Digital BLC */
183 #define REG_DBLC_B 0x90 /* Digital BLC B channel offset */
184 #define REG_DBLC_R 0x91 /* Digital BLC R channel offset */
185 #define REG_DM_LNL 0x92 /* Dummy line low 8 bits */
186 #define REG_DM_LNH 0x93 /* Dummy line high 8 bits */
187 #define REG_LCCFB 0x9d /* Lens Correction B channel */
188 #define REG_LCCFR 0x9e /* Lens Correction R channel */
189 #define REG_DBLC_GB 0x9f /* Digital BLC GB chan offset */
190 #define REG_DBLC_GR 0xa0 /* Digital BLC GR chan offset */
191 #define REG_AECHM 0xa1 /* Exposure value - bits AEC[15:10] */
192 #define REG_BD50ST 0xa2 /* Banding filter value for 50Hz */
193 #define REG_BD60ST 0xa3 /* Banding filter value for 60Hz */
194 #define REG_NULL 0xff /* Array end token */
195
196 #define DEF_CLKRC 0x80
197
198 #define OV965X_ID(_msb, _lsb) ((_msb) << 8 | (_lsb))
199 #define OV9650_ID 0x9650
200 #define OV9652_ID 0x9652
201
202 struct ov965x_ctrls {
203 struct v4l2_ctrl_handler handler;
204 struct {
205 struct v4l2_ctrl *auto_exp;
206 struct v4l2_ctrl *exposure;
207 };
208 struct {
209 struct v4l2_ctrl *auto_wb;
210 struct v4l2_ctrl *blue_balance;
211 struct v4l2_ctrl *red_balance;
212 };
213 struct {
214 struct v4l2_ctrl *hflip;
215 struct v4l2_ctrl *vflip;
216 };
217 struct {
218 struct v4l2_ctrl *auto_gain;
219 struct v4l2_ctrl *gain;
220 };
221 struct v4l2_ctrl *brightness;
222 struct v4l2_ctrl *saturation;
223 struct v4l2_ctrl *sharpness;
224 struct v4l2_ctrl *light_freq;
225 u8 update;
226 };
227
228 struct ov965x_framesize {
229 u16 width;
230 u16 height;
231 u16 max_exp_lines;
232 const u8 *regs;
233 };
234
235 struct ov965x_interval {
236 struct v4l2_fract interval;
237 /* Maximum resolution for this interval */
238 struct v4l2_frmsize_discrete size;
239 u8 clkrc_div;
240 };
241
242 enum gpio_id {
243 GPIO_PWDN,
244 GPIO_RST,
245 NUM_GPIOS,
246 };
247
248 struct ov965x {
249 struct v4l2_subdev sd;
250 struct media_pad pad;
251 enum v4l2_mbus_type bus_type;
252 struct gpio_desc *gpios[NUM_GPIOS];
253 /* External master clock frequency */
254 unsigned long mclk_frequency;
255 struct clk *clk;
256
257 /* Protects the struct fields below */
258 struct mutex lock;
259
260 struct regmap *regmap;
261
262 /* Exposure row interval in us */
263 unsigned int exp_row_interval;
264
265 unsigned short id;
266 const struct ov965x_framesize *frame_size;
267 /* YUYV sequence (pixel format) control register */
268 u8 tslb_reg;
269 struct v4l2_mbus_framefmt format;
270
271 struct ov965x_ctrls ctrls;
272 /* Pointer to frame rate control data structure */
273 const struct ov965x_interval *fiv;
274
275 int streaming;
276 int power;
277
278 u8 apply_frame_fmt;
279 };
280
281 struct i2c_rv {
282 u8 addr;
283 u8 value;
284 };
285
286 static const struct i2c_rv ov965x_init_regs[] = {
287 { REG_COM2, 0x10 }, /* Set soft sleep mode */
288 { REG_COM5, 0x00 }, /* System clock options */
289 { REG_COM2, 0x01 }, /* Output drive, soft sleep mode */
290 { REG_COM10, 0x00 }, /* Slave mode, HREF vs HSYNC, signals negate */
291 { REG_EDGE, 0xa6 }, /* Edge enhancement treshhold and factor */
292 { REG_COM16, 0x02 }, /* Color matrix coeff double option */
293 { REG_COM17, 0x08 }, /* Single frame out, banding filter */
294 { 0x16, 0x06 },
295 { REG_CHLF, 0xc0 }, /* Reserved */
296 { 0x34, 0xbf },
297 { 0xa8, 0x80 },
298 { 0x96, 0x04 },
299 { 0x8e, 0x00 },
300 { REG_COM12, 0x77 }, /* HREF option, UV average */
301 { 0x8b, 0x06 },
302 { 0x35, 0x91 },
303 { 0x94, 0x88 },
304 { 0x95, 0x88 },
305 { REG_COM15, 0xc1 }, /* Output range, RGB 555/565 */
306 { REG_GRCOM, 0x2f }, /* Analog BLC & regulator */
307 { REG_COM6, 0x43 }, /* HREF & ADBLC options */
308 { REG_COM8, 0xe5 }, /* AGC/AEC options */
309 { REG_COM13, 0x90 }, /* Gamma selection, colour matrix, UV delay */
310 { REG_HV, 0x80 }, /* Manual banding filter MSB */
311 { 0x5c, 0x96 }, /* Reserved up to 0xa5 */
312 { 0x5d, 0x96 },
313 { 0x5e, 0x10 },
314 { 0x59, 0xeb },
315 { 0x5a, 0x9c },
316 { 0x5b, 0x55 },
317 { 0x43, 0xf0 },
318 { 0x44, 0x10 },
319 { 0x45, 0x55 },
320 { 0x46, 0x86 },
321 { 0x47, 0x64 },
322 { 0x48, 0x86 },
323 { 0x5f, 0xe0 },
324 { 0x60, 0x8c },
325 { 0x61, 0x20 },
326 { 0xa5, 0xd9 },
327 { 0xa4, 0x74 }, /* reserved */
328 { REG_COM23, 0x02 }, /* Color gain analog/_digital_ */
329 { REG_COM8, 0xe7 }, /* Enable AEC, AWB, AEC */
330 { REG_COM22, 0x23 }, /* Edge enhancement, denoising */
331 { 0xa9, 0xb8 },
332 { 0xaa, 0x92 },
333 { 0xab, 0x0a },
334 { REG_DBLC1, 0xdf }, /* Digital BLC */
335 { REG_DBLC_B, 0x00 }, /* Digital BLC B chan offset */
336 { REG_DBLC_R, 0x00 }, /* Digital BLC R chan offset */
337 { REG_DBLC_GB, 0x00 }, /* Digital BLC GB chan offset */
338 { REG_DBLC_GR, 0x00 },
339 { REG_COM9, 0x3a }, /* Gain ceiling 16x */
340 { REG_NULL, 0 }
341 };
342
343 #define NUM_FMT_REGS 14
344 /*
345 * COM7, COM3, COM4, HSTART, HSTOP, HREF, VSTART, VSTOP, VREF,
346 * EXHCH, EXHCL, ADC, OCOM, OFON
347 */
348 static const u8 frame_size_reg_addr[NUM_FMT_REGS] = {
349 0x12, 0x0c, 0x0d, 0x17, 0x18, 0x32, 0x19, 0x1a, 0x03,
350 0x2a, 0x2b, 0x37, 0x38, 0x39,
351 };
352
353 static const u8 ov965x_sxga_regs[NUM_FMT_REGS] = {
354 0x00, 0x00, 0x00, 0x1e, 0xbe, 0xbf, 0x01, 0x81, 0x12,
355 0x10, 0x34, 0x81, 0x93, 0x51,
356 };
357
358 static const u8 ov965x_vga_regs[NUM_FMT_REGS] = {
359 0x40, 0x04, 0x80, 0x26, 0xc6, 0xed, 0x01, 0x3d, 0x00,
360 0x10, 0x40, 0x91, 0x12, 0x43,
361 };
362
363 /* Determined empirically. */
364 static const u8 ov965x_qvga_regs[NUM_FMT_REGS] = {
365 0x10, 0x04, 0x80, 0x25, 0xc5, 0xbf, 0x00, 0x80, 0x12,
366 0x10, 0x40, 0x91, 0x12, 0x43,
367 };
368
369 static const struct ov965x_framesize ov965x_framesizes[] = {
370 {
371 .width = SXGA_WIDTH,
372 .height = SXGA_HEIGHT,
373 .regs = ov965x_sxga_regs,
374 .max_exp_lines = 1048,
375 }, {
376 .width = VGA_WIDTH,
377 .height = VGA_HEIGHT,
378 .regs = ov965x_vga_regs,
379 .max_exp_lines = 498,
380 }, {
381 .width = QVGA_WIDTH,
382 .height = QVGA_HEIGHT,
383 .regs = ov965x_qvga_regs,
384 .max_exp_lines = 248,
385 },
386 };
387
388 struct ov965x_pixfmt {
389 u32 code;
390 u32 colorspace;
391 /* REG_TSLB value, only bits [3:2] may be set. */
392 u8 tslb_reg;
393 };
394
395 static const struct ov965x_pixfmt ov965x_formats[] = {
396 { MEDIA_BUS_FMT_YUYV8_2X8, V4L2_COLORSPACE_JPEG, 0x00},
397 { MEDIA_BUS_FMT_YVYU8_2X8, V4L2_COLORSPACE_JPEG, 0x04},
398 { MEDIA_BUS_FMT_UYVY8_2X8, V4L2_COLORSPACE_JPEG, 0x0c},
399 { MEDIA_BUS_FMT_VYUY8_2X8, V4L2_COLORSPACE_JPEG, 0x08},
400 };
401
402 /*
403 * This table specifies possible frame resolution and interval
404 * combinations. Default CLKRC[5:0] divider values are valid
405 * only for 24 MHz external clock frequency.
406 */
407 static struct ov965x_interval ov965x_intervals[] = {
408 {{ 100, 625 }, { SXGA_WIDTH, SXGA_HEIGHT }, 0 }, /* 6.25 fps */
409 {{ 10, 125 }, { VGA_WIDTH, VGA_HEIGHT }, 1 }, /* 12.5 fps */
410 {{ 10, 125 }, { QVGA_WIDTH, QVGA_HEIGHT }, 3 }, /* 12.5 fps */
411 {{ 1, 25 }, { VGA_WIDTH, VGA_HEIGHT }, 0 }, /* 25 fps */
412 {{ 1, 25 }, { QVGA_WIDTH, QVGA_HEIGHT }, 1 }, /* 25 fps */
413 };
414
ctrl_to_sd(struct v4l2_ctrl * ctrl)415 static inline struct v4l2_subdev *ctrl_to_sd(struct v4l2_ctrl *ctrl)
416 {
417 return &container_of(ctrl->handler, struct ov965x, ctrls.handler)->sd;
418 }
419
to_ov965x(struct v4l2_subdev * sd)420 static inline struct ov965x *to_ov965x(struct v4l2_subdev *sd)
421 {
422 return container_of(sd, struct ov965x, sd);
423 }
424
ov965x_read(struct ov965x * ov965x,u8 addr,u8 * val)425 static int ov965x_read(struct ov965x *ov965x, u8 addr, u8 *val)
426 {
427 int ret;
428 unsigned int buf;
429
430 ret = regmap_read(ov965x->regmap, addr, &buf);
431 if (!ret)
432 *val = buf;
433 else
434 *val = -1;
435
436 v4l2_dbg(2, debug, &ov965x->sd, "%s: 0x%02x @ 0x%02x. (%d)\n",
437 __func__, *val, addr, ret);
438
439 return ret;
440 }
441
ov965x_write(struct ov965x * ov965x,u8 addr,u8 val)442 static int ov965x_write(struct ov965x *ov965x, u8 addr, u8 val)
443 {
444 int ret;
445
446 ret = regmap_write(ov965x->regmap, addr, val);
447
448 v4l2_dbg(2, debug, &ov965x->sd, "%s: 0x%02x @ 0x%02X (%d)\n",
449 __func__, val, addr, ret);
450
451 return ret;
452 }
453
ov965x_write_array(struct ov965x * ov965x,const struct i2c_rv * regs)454 static int ov965x_write_array(struct ov965x *ov965x,
455 const struct i2c_rv *regs)
456 {
457 int i, ret = 0;
458
459 for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++)
460 ret = ov965x_write(ov965x, regs[i].addr, regs[i].value);
461
462 return ret;
463 }
464
ov965x_set_default_gamma_curve(struct ov965x * ov965x)465 static int ov965x_set_default_gamma_curve(struct ov965x *ov965x)
466 {
467 static const u8 gamma_curve[] = {
468 /* Values taken from OV application note. */
469 0x40, 0x30, 0x4b, 0x60, 0x70, 0x70, 0x70, 0x70,
470 0x60, 0x60, 0x50, 0x48, 0x3a, 0x2e, 0x28, 0x22,
471 0x04, 0x07, 0x10, 0x28, 0x36, 0x44, 0x52, 0x60,
472 0x6c, 0x78, 0x8c, 0x9e, 0xbb, 0xd2, 0xe6
473 };
474 u8 addr = REG_GSP;
475 unsigned int i;
476
477 for (i = 0; i < ARRAY_SIZE(gamma_curve); i++) {
478 int ret = ov965x_write(ov965x, addr, gamma_curve[i]);
479
480 if (ret < 0)
481 return ret;
482 addr++;
483 }
484
485 return 0;
486 };
487
ov965x_set_color_matrix(struct ov965x * ov965x)488 static int ov965x_set_color_matrix(struct ov965x *ov965x)
489 {
490 static const u8 mtx[] = {
491 /* MTX1..MTX9, MTXS */
492 0x3a, 0x3d, 0x03, 0x12, 0x26, 0x38, 0x40, 0x40, 0x40, 0x0d
493 };
494 u8 addr = REG_MTX(1);
495 unsigned int i;
496
497 for (i = 0; i < ARRAY_SIZE(mtx); i++) {
498 int ret = ov965x_write(ov965x, addr, mtx[i]);
499
500 if (ret < 0)
501 return ret;
502 addr++;
503 }
504
505 return 0;
506 }
507
__ov965x_set_power(struct ov965x * ov965x,int on)508 static int __ov965x_set_power(struct ov965x *ov965x, int on)
509 {
510 if (on) {
511 int ret = clk_prepare_enable(ov965x->clk);
512
513 if (ret)
514 return ret;
515
516 gpiod_set_value_cansleep(ov965x->gpios[GPIO_PWDN], 0);
517 gpiod_set_value_cansleep(ov965x->gpios[GPIO_RST], 0);
518 msleep(25);
519 } else {
520 gpiod_set_value_cansleep(ov965x->gpios[GPIO_RST], 1);
521 gpiod_set_value_cansleep(ov965x->gpios[GPIO_PWDN], 1);
522
523 clk_disable_unprepare(ov965x->clk);
524 }
525
526 ov965x->streaming = 0;
527
528 return 0;
529 }
530
ov965x_s_power(struct v4l2_subdev * sd,int on)531 static int ov965x_s_power(struct v4l2_subdev *sd, int on)
532 {
533 struct ov965x *ov965x = to_ov965x(sd);
534 int ret = 0;
535
536 v4l2_dbg(1, debug, sd, "%s: on: %d\n", __func__, on);
537
538 mutex_lock(&ov965x->lock);
539 if (ov965x->power == !on) {
540 ret = __ov965x_set_power(ov965x, on);
541 if (!ret && on) {
542 ret = ov965x_write_array(ov965x,
543 ov965x_init_regs);
544 ov965x->apply_frame_fmt = 1;
545 ov965x->ctrls.update = 1;
546 }
547 }
548 if (!ret)
549 ov965x->power += on ? 1 : -1;
550
551 WARN_ON(ov965x->power < 0);
552 mutex_unlock(&ov965x->lock);
553 return ret;
554 }
555
556 /*
557 * V4L2 controls
558 */
559
ov965x_update_exposure_ctrl(struct ov965x * ov965x)560 static void ov965x_update_exposure_ctrl(struct ov965x *ov965x)
561 {
562 struct v4l2_ctrl *ctrl = ov965x->ctrls.exposure;
563 unsigned long fint, trow;
564 int min, max, def;
565 u8 clkrc;
566
567 mutex_lock(&ov965x->lock);
568 if (WARN_ON(!ctrl || !ov965x->frame_size)) {
569 mutex_unlock(&ov965x->lock);
570 return;
571 }
572 clkrc = DEF_CLKRC + ov965x->fiv->clkrc_div;
573 /* Calculate internal clock frequency */
574 fint = ov965x->mclk_frequency * ((clkrc >> 7) + 1) /
575 ((2 * ((clkrc & 0x3f) + 1)));
576 /* and the row interval (in us). */
577 trow = (2 * 1520 * 1000000UL) / fint;
578 max = ov965x->frame_size->max_exp_lines * trow;
579 ov965x->exp_row_interval = trow;
580 mutex_unlock(&ov965x->lock);
581
582 v4l2_dbg(1, debug, &ov965x->sd, "clkrc: %#x, fi: %lu, tr: %lu, %d\n",
583 clkrc, fint, trow, max);
584
585 /* Update exposure time range to match current frame format. */
586 min = (trow + 100) / 100;
587 max = (max - 100) / 100;
588 def = min + (max - min) / 2;
589
590 if (v4l2_ctrl_modify_range(ctrl, min, max, 1, def))
591 v4l2_err(&ov965x->sd, "Exposure ctrl range update failed\n");
592 }
593
ov965x_set_banding_filter(struct ov965x * ov965x,int value)594 static int ov965x_set_banding_filter(struct ov965x *ov965x, int value)
595 {
596 unsigned long mbd, light_freq;
597 int ret;
598 u8 reg;
599
600 ret = ov965x_read(ov965x, REG_COM8, ®);
601 if (!ret) {
602 if (value == V4L2_CID_POWER_LINE_FREQUENCY_DISABLED)
603 reg &= ~COM8_BFILT;
604 else
605 reg |= COM8_BFILT;
606 ret = ov965x_write(ov965x, REG_COM8, reg);
607 }
608 if (value == V4L2_CID_POWER_LINE_FREQUENCY_DISABLED)
609 return 0;
610 if (WARN_ON(!ov965x->fiv))
611 return -EINVAL;
612 /* Set minimal exposure time for 50/60 HZ lighting */
613 if (value == V4L2_CID_POWER_LINE_FREQUENCY_50HZ)
614 light_freq = 50;
615 else
616 light_freq = 60;
617 mbd = (1000UL * ov965x->fiv->interval.denominator *
618 ov965x->frame_size->max_exp_lines) /
619 ov965x->fiv->interval.numerator;
620 mbd = ((mbd / (light_freq * 2)) + 500) / 1000UL;
621
622 return ov965x_write(ov965x, REG_MBD, mbd);
623 }
624
ov965x_set_white_balance(struct ov965x * ov965x,int awb)625 static int ov965x_set_white_balance(struct ov965x *ov965x, int awb)
626 {
627 int ret;
628 u8 reg;
629
630 ret = ov965x_read(ov965x, REG_COM8, ®);
631 if (!ret) {
632 reg = awb ? reg | REG_COM8 : reg & ~REG_COM8;
633 ret = ov965x_write(ov965x, REG_COM8, reg);
634 }
635 if (!ret && !awb) {
636 ret = ov965x_write(ov965x, REG_BLUE,
637 ov965x->ctrls.blue_balance->val);
638 if (ret < 0)
639 return ret;
640 ret = ov965x_write(ov965x, REG_RED,
641 ov965x->ctrls.red_balance->val);
642 }
643 return ret;
644 }
645
646 #define NUM_BR_LEVELS 7
647 #define NUM_BR_REGS 3
648
ov965x_set_brightness(struct ov965x * ov965x,int val)649 static int ov965x_set_brightness(struct ov965x *ov965x, int val)
650 {
651 static const u8 regs[NUM_BR_LEVELS + 1][NUM_BR_REGS] = {
652 { REG_AEW, REG_AEB, REG_VPT },
653 { 0x1c, 0x12, 0x50 }, /* -3 */
654 { 0x3d, 0x30, 0x71 }, /* -2 */
655 { 0x50, 0x44, 0x92 }, /* -1 */
656 { 0x70, 0x64, 0xc3 }, /* 0 */
657 { 0x90, 0x84, 0xd4 }, /* +1 */
658 { 0xc4, 0xbf, 0xf9 }, /* +2 */
659 { 0xd8, 0xd0, 0xfa }, /* +3 */
660 };
661 int i, ret = 0;
662
663 val += (NUM_BR_LEVELS / 2 + 1);
664 if (val > NUM_BR_LEVELS)
665 return -EINVAL;
666
667 for (i = 0; i < NUM_BR_REGS && !ret; i++)
668 ret = ov965x_write(ov965x, regs[0][i],
669 regs[val][i]);
670 return ret;
671 }
672
ov965x_set_gain(struct ov965x * ov965x,int auto_gain)673 static int ov965x_set_gain(struct ov965x *ov965x, int auto_gain)
674 {
675 struct ov965x_ctrls *ctrls = &ov965x->ctrls;
676 int ret = 0;
677 u8 reg;
678 /*
679 * For manual mode we need to disable AGC first, so
680 * gain value in REG_VREF, REG_GAIN is not overwritten.
681 */
682 if (ctrls->auto_gain->is_new) {
683 ret = ov965x_read(ov965x, REG_COM8, ®);
684 if (ret < 0)
685 return ret;
686 if (ctrls->auto_gain->val)
687 reg |= COM8_AGC;
688 else
689 reg &= ~COM8_AGC;
690 ret = ov965x_write(ov965x, REG_COM8, reg);
691 if (ret < 0)
692 return ret;
693 }
694
695 if (ctrls->gain->is_new && !auto_gain) {
696 unsigned int gain = ctrls->gain->val;
697 unsigned int rgain;
698 int m;
699 /*
700 * Convert gain control value to the sensor's gain
701 * registers (VREF[7:6], GAIN[7:0]) format.
702 */
703 for (m = 6; m >= 0; m--)
704 if (gain >= (1 << m) * 16)
705 break;
706
707 /* Sanity check: don't adjust the gain with a negative value */
708 if (m < 0)
709 return -EINVAL;
710
711 rgain = (gain - ((1 << m) * 16)) / (1 << m);
712 rgain |= (((1 << m) - 1) << 4);
713
714 ret = ov965x_write(ov965x, REG_GAIN, rgain & 0xff);
715 if (ret < 0)
716 return ret;
717 ret = ov965x_read(ov965x, REG_VREF, ®);
718 if (ret < 0)
719 return ret;
720 reg &= ~VREF_GAIN_MASK;
721 reg |= (((rgain >> 8) & 0x3) << 6);
722 ret = ov965x_write(ov965x, REG_VREF, reg);
723 if (ret < 0)
724 return ret;
725 /* Return updated control's value to userspace */
726 ctrls->gain->val = (1 << m) * (16 + (rgain & 0xf));
727 }
728
729 return ret;
730 }
731
ov965x_set_sharpness(struct ov965x * ov965x,unsigned int value)732 static int ov965x_set_sharpness(struct ov965x *ov965x, unsigned int value)
733 {
734 u8 com14, edge;
735 int ret;
736
737 ret = ov965x_read(ov965x, REG_COM14, &com14);
738 if (ret < 0)
739 return ret;
740 ret = ov965x_read(ov965x, REG_EDGE, &edge);
741 if (ret < 0)
742 return ret;
743 com14 = value ? com14 | COM14_EDGE_EN : com14 & ~COM14_EDGE_EN;
744 value--;
745 if (value > 0x0f) {
746 com14 |= COM14_EEF_X2;
747 value >>= 1;
748 } else {
749 com14 &= ~COM14_EEF_X2;
750 }
751 ret = ov965x_write(ov965x, REG_COM14, com14);
752 if (ret < 0)
753 return ret;
754
755 edge &= ~EDGE_FACTOR_MASK;
756 edge |= ((u8)value & 0x0f);
757
758 return ov965x_write(ov965x, REG_EDGE, edge);
759 }
760
ov965x_set_exposure(struct ov965x * ov965x,int exp)761 static int ov965x_set_exposure(struct ov965x *ov965x, int exp)
762 {
763 struct ov965x_ctrls *ctrls = &ov965x->ctrls;
764 bool auto_exposure = (exp == V4L2_EXPOSURE_AUTO);
765 int ret;
766 u8 reg;
767
768 if (ctrls->auto_exp->is_new) {
769 ret = ov965x_read(ov965x, REG_COM8, ®);
770 if (ret < 0)
771 return ret;
772 if (auto_exposure)
773 reg |= (COM8_AEC | COM8_AGC);
774 else
775 reg &= ~(COM8_AEC | COM8_AGC);
776 ret = ov965x_write(ov965x, REG_COM8, reg);
777 if (ret < 0)
778 return ret;
779 }
780
781 if (!auto_exposure && ctrls->exposure->is_new) {
782 unsigned int exposure = (ctrls->exposure->val * 100)
783 / ov965x->exp_row_interval;
784 /*
785 * Manual exposure value
786 * [b15:b0] - AECHM (b15:b10), AECH (b9:b2), COM1 (b1:b0)
787 */
788 ret = ov965x_write(ov965x, REG_COM1, exposure & 0x3);
789 if (!ret)
790 ret = ov965x_write(ov965x, REG_AECH,
791 (exposure >> 2) & 0xff);
792 if (!ret)
793 ret = ov965x_write(ov965x, REG_AECHM,
794 (exposure >> 10) & 0x3f);
795 /* Update the value to minimize rounding errors */
796 ctrls->exposure->val = ((exposure * ov965x->exp_row_interval)
797 + 50) / 100;
798 if (ret < 0)
799 return ret;
800 }
801
802 v4l2_ctrl_activate(ov965x->ctrls.brightness, !exp);
803 return 0;
804 }
805
ov965x_set_flip(struct ov965x * ov965x)806 static int ov965x_set_flip(struct ov965x *ov965x)
807 {
808 u8 mvfp = 0;
809
810 if (ov965x->ctrls.hflip->val)
811 mvfp |= MVFP_MIRROR;
812
813 if (ov965x->ctrls.vflip->val)
814 mvfp |= MVFP_FLIP;
815
816 return ov965x_write(ov965x, REG_MVFP, mvfp);
817 }
818
819 #define NUM_SAT_LEVELS 5
820 #define NUM_SAT_REGS 6
821
ov965x_set_saturation(struct ov965x * ov965x,int val)822 static int ov965x_set_saturation(struct ov965x *ov965x, int val)
823 {
824 static const u8 regs[NUM_SAT_LEVELS][NUM_SAT_REGS] = {
825 /* MTX(1)...MTX(6) */
826 { 0x1d, 0x1f, 0x02, 0x09, 0x13, 0x1c }, /* -2 */
827 { 0x2e, 0x31, 0x02, 0x0e, 0x1e, 0x2d }, /* -1 */
828 { 0x3a, 0x3d, 0x03, 0x12, 0x26, 0x38 }, /* 0 */
829 { 0x46, 0x49, 0x04, 0x16, 0x2e, 0x43 }, /* +1 */
830 { 0x57, 0x5c, 0x05, 0x1b, 0x39, 0x54 }, /* +2 */
831 };
832 u8 addr = REG_MTX(1);
833 int i, ret = 0;
834
835 val += (NUM_SAT_LEVELS / 2);
836 if (val >= NUM_SAT_LEVELS)
837 return -EINVAL;
838
839 for (i = 0; i < NUM_SAT_REGS && !ret; i++)
840 ret = ov965x_write(ov965x, addr + i, regs[val][i]);
841
842 return ret;
843 }
844
ov965x_set_test_pattern(struct ov965x * ov965x,int value)845 static int ov965x_set_test_pattern(struct ov965x *ov965x, int value)
846 {
847 int ret;
848 u8 reg;
849
850 ret = ov965x_read(ov965x, REG_COM23, ®);
851 if (ret < 0)
852 return ret;
853 reg = value ? reg | COM23_TEST_MODE : reg & ~COM23_TEST_MODE;
854 return ov965x_write(ov965x, REG_COM23, reg);
855 }
856
__g_volatile_ctrl(struct ov965x * ov965x,struct v4l2_ctrl * ctrl)857 static int __g_volatile_ctrl(struct ov965x *ov965x, struct v4l2_ctrl *ctrl)
858 {
859 unsigned int exposure, gain, m;
860 u8 reg0, reg1, reg2;
861 int ret;
862
863 if (!ov965x->power)
864 return 0;
865
866 switch (ctrl->id) {
867 case V4L2_CID_AUTOGAIN:
868 if (!ctrl->val)
869 return 0;
870 ret = ov965x_read(ov965x, REG_GAIN, ®0);
871 if (ret < 0)
872 return ret;
873 ret = ov965x_read(ov965x, REG_VREF, ®1);
874 if (ret < 0)
875 return ret;
876 gain = ((reg1 >> 6) << 8) | reg0;
877 m = 0x01 << fls(gain >> 4);
878 ov965x->ctrls.gain->val = m * (16 + (gain & 0xf));
879 break;
880
881 case V4L2_CID_EXPOSURE_AUTO:
882 if (ctrl->val == V4L2_EXPOSURE_MANUAL)
883 return 0;
884 ret = ov965x_read(ov965x, REG_COM1, ®0);
885 if (ret < 0)
886 return ret;
887 ret = ov965x_read(ov965x, REG_AECH, ®1);
888 if (ret < 0)
889 return ret;
890 ret = ov965x_read(ov965x, REG_AECHM, ®2);
891 if (ret < 0)
892 return ret;
893 exposure = ((reg2 & 0x3f) << 10) | (reg1 << 2) |
894 (reg0 & 0x3);
895 ov965x->ctrls.exposure->val = ((exposure *
896 ov965x->exp_row_interval) + 50) / 100;
897 break;
898 }
899
900 return 0;
901 }
902
ov965x_g_volatile_ctrl(struct v4l2_ctrl * ctrl)903 static int ov965x_g_volatile_ctrl(struct v4l2_ctrl *ctrl)
904 {
905 struct v4l2_subdev *sd = ctrl_to_sd(ctrl);
906 struct ov965x *ov965x = to_ov965x(sd);
907 int ret;
908
909 v4l2_dbg(1, debug, sd, "g_ctrl: %s\n", ctrl->name);
910
911 mutex_lock(&ov965x->lock);
912 ret = __g_volatile_ctrl(ov965x, ctrl);
913 mutex_unlock(&ov965x->lock);
914 return ret;
915 }
916
ov965x_s_ctrl(struct v4l2_ctrl * ctrl)917 static int ov965x_s_ctrl(struct v4l2_ctrl *ctrl)
918 {
919 struct v4l2_subdev *sd = ctrl_to_sd(ctrl);
920 struct ov965x *ov965x = to_ov965x(sd);
921 int ret = -EINVAL;
922
923 v4l2_dbg(1, debug, sd, "s_ctrl: %s, value: %d. power: %d\n",
924 ctrl->name, ctrl->val, ov965x->power);
925
926 mutex_lock(&ov965x->lock);
927 /*
928 * If the device is not powered up now postpone applying control's
929 * value to the hardware, until it is ready to accept commands.
930 */
931 if (ov965x->power == 0) {
932 mutex_unlock(&ov965x->lock);
933 return 0;
934 }
935
936 switch (ctrl->id) {
937 case V4L2_CID_AUTO_WHITE_BALANCE:
938 ret = ov965x_set_white_balance(ov965x, ctrl->val);
939 break;
940
941 case V4L2_CID_BRIGHTNESS:
942 ret = ov965x_set_brightness(ov965x, ctrl->val);
943 break;
944
945 case V4L2_CID_EXPOSURE_AUTO:
946 ret = ov965x_set_exposure(ov965x, ctrl->val);
947 break;
948
949 case V4L2_CID_AUTOGAIN:
950 ret = ov965x_set_gain(ov965x, ctrl->val);
951 break;
952
953 case V4L2_CID_HFLIP:
954 ret = ov965x_set_flip(ov965x);
955 break;
956
957 case V4L2_CID_POWER_LINE_FREQUENCY:
958 ret = ov965x_set_banding_filter(ov965x, ctrl->val);
959 break;
960
961 case V4L2_CID_SATURATION:
962 ret = ov965x_set_saturation(ov965x, ctrl->val);
963 break;
964
965 case V4L2_CID_SHARPNESS:
966 ret = ov965x_set_sharpness(ov965x, ctrl->val);
967 break;
968
969 case V4L2_CID_TEST_PATTERN:
970 ret = ov965x_set_test_pattern(ov965x, ctrl->val);
971 break;
972 }
973
974 mutex_unlock(&ov965x->lock);
975 return ret;
976 }
977
978 static const struct v4l2_ctrl_ops ov965x_ctrl_ops = {
979 .g_volatile_ctrl = ov965x_g_volatile_ctrl,
980 .s_ctrl = ov965x_s_ctrl,
981 };
982
983 static const char * const test_pattern_menu[] = {
984 "Disabled",
985 "Color bars",
986 };
987
ov965x_initialize_controls(struct ov965x * ov965x)988 static int ov965x_initialize_controls(struct ov965x *ov965x)
989 {
990 const struct v4l2_ctrl_ops *ops = &ov965x_ctrl_ops;
991 struct ov965x_ctrls *ctrls = &ov965x->ctrls;
992 struct v4l2_ctrl_handler *hdl = &ctrls->handler;
993 int ret;
994
995 ret = v4l2_ctrl_handler_init(hdl, 16);
996 if (ret < 0)
997 return ret;
998
999 /* Auto/manual white balance */
1000 ctrls->auto_wb = v4l2_ctrl_new_std(hdl, ops,
1001 V4L2_CID_AUTO_WHITE_BALANCE,
1002 0, 1, 1, 1);
1003 ctrls->blue_balance = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_BLUE_BALANCE,
1004 0, 0xff, 1, 0x80);
1005 ctrls->red_balance = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_RED_BALANCE,
1006 0, 0xff, 1, 0x80);
1007 /* Auto/manual exposure */
1008 ctrls->auto_exp =
1009 v4l2_ctrl_new_std_menu(hdl, ops,
1010 V4L2_CID_EXPOSURE_AUTO,
1011 V4L2_EXPOSURE_MANUAL, 0,
1012 V4L2_EXPOSURE_AUTO);
1013 /* Exposure time, in 100 us units. min/max is updated dynamically. */
1014 ctrls->exposure = v4l2_ctrl_new_std(hdl, ops,
1015 V4L2_CID_EXPOSURE_ABSOLUTE,
1016 2, 1500, 1, 500);
1017 /* Auto/manual gain */
1018 ctrls->auto_gain = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_AUTOGAIN,
1019 0, 1, 1, 1);
1020 ctrls->gain = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_GAIN,
1021 16, 64 * (16 + 15), 1, 64 * 16);
1022
1023 ctrls->saturation = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_SATURATION,
1024 -2, 2, 1, 0);
1025 ctrls->brightness = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_BRIGHTNESS,
1026 -3, 3, 1, 0);
1027 ctrls->sharpness = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_SHARPNESS,
1028 0, 32, 1, 6);
1029
1030 ctrls->hflip = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_HFLIP, 0, 1, 1, 0);
1031 ctrls->vflip = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_VFLIP, 0, 1, 1, 0);
1032
1033 ctrls->light_freq =
1034 v4l2_ctrl_new_std_menu(hdl, ops,
1035 V4L2_CID_POWER_LINE_FREQUENCY,
1036 V4L2_CID_POWER_LINE_FREQUENCY_60HZ, ~0x7,
1037 V4L2_CID_POWER_LINE_FREQUENCY_50HZ);
1038
1039 v4l2_ctrl_new_std_menu_items(hdl, ops, V4L2_CID_TEST_PATTERN,
1040 ARRAY_SIZE(test_pattern_menu) - 1, 0, 0,
1041 test_pattern_menu);
1042 if (hdl->error) {
1043 ret = hdl->error;
1044 v4l2_ctrl_handler_free(hdl);
1045 return ret;
1046 }
1047
1048 ctrls->gain->flags |= V4L2_CTRL_FLAG_VOLATILE;
1049 ctrls->exposure->flags |= V4L2_CTRL_FLAG_VOLATILE;
1050
1051 v4l2_ctrl_auto_cluster(3, &ctrls->auto_wb, 0, false);
1052 v4l2_ctrl_auto_cluster(2, &ctrls->auto_gain, 0, true);
1053 v4l2_ctrl_auto_cluster(2, &ctrls->auto_exp, 1, true);
1054 v4l2_ctrl_cluster(2, &ctrls->hflip);
1055
1056 ov965x->sd.ctrl_handler = hdl;
1057 return 0;
1058 }
1059
1060 /*
1061 * V4L2 subdev video and pad level operations
1062 */
ov965x_get_default_format(struct v4l2_mbus_framefmt * mf)1063 static void ov965x_get_default_format(struct v4l2_mbus_framefmt *mf)
1064 {
1065 mf->width = ov965x_framesizes[0].width;
1066 mf->height = ov965x_framesizes[0].height;
1067 mf->colorspace = ov965x_formats[0].colorspace;
1068 mf->code = ov965x_formats[0].code;
1069 mf->field = V4L2_FIELD_NONE;
1070 }
1071
ov965x_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_mbus_code_enum * code)1072 static int ov965x_enum_mbus_code(struct v4l2_subdev *sd,
1073 struct v4l2_subdev_pad_config *cfg,
1074 struct v4l2_subdev_mbus_code_enum *code)
1075 {
1076 if (code->index >= ARRAY_SIZE(ov965x_formats))
1077 return -EINVAL;
1078
1079 code->code = ov965x_formats[code->index].code;
1080 return 0;
1081 }
1082
ov965x_enum_frame_sizes(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_size_enum * fse)1083 static int ov965x_enum_frame_sizes(struct v4l2_subdev *sd,
1084 struct v4l2_subdev_pad_config *cfg,
1085 struct v4l2_subdev_frame_size_enum *fse)
1086 {
1087 int i = ARRAY_SIZE(ov965x_formats);
1088
1089 if (fse->index >= ARRAY_SIZE(ov965x_framesizes))
1090 return -EINVAL;
1091
1092 while (--i)
1093 if (fse->code == ov965x_formats[i].code)
1094 break;
1095
1096 fse->code = ov965x_formats[i].code;
1097
1098 fse->min_width = ov965x_framesizes[fse->index].width;
1099 fse->max_width = fse->min_width;
1100 fse->max_height = ov965x_framesizes[fse->index].height;
1101 fse->min_height = fse->max_height;
1102
1103 return 0;
1104 }
1105
ov965x_g_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_frame_interval * fi)1106 static int ov965x_g_frame_interval(struct v4l2_subdev *sd,
1107 struct v4l2_subdev_frame_interval *fi)
1108 {
1109 struct ov965x *ov965x = to_ov965x(sd);
1110
1111 mutex_lock(&ov965x->lock);
1112 fi->interval = ov965x->fiv->interval;
1113 mutex_unlock(&ov965x->lock);
1114
1115 return 0;
1116 }
1117
__ov965x_set_frame_interval(struct ov965x * ov965x,struct v4l2_subdev_frame_interval * fi)1118 static int __ov965x_set_frame_interval(struct ov965x *ov965x,
1119 struct v4l2_subdev_frame_interval *fi)
1120 {
1121 struct v4l2_mbus_framefmt *mbus_fmt = &ov965x->format;
1122 const struct ov965x_interval *fiv = &ov965x_intervals[0];
1123 u64 req_int, err, min_err = ~0ULL;
1124 unsigned int i;
1125
1126 if (fi->interval.denominator == 0)
1127 return -EINVAL;
1128
1129 req_int = (u64)fi->interval.numerator * 10000;
1130 do_div(req_int, fi->interval.denominator);
1131
1132 for (i = 0; i < ARRAY_SIZE(ov965x_intervals); i++) {
1133 const struct ov965x_interval *iv = &ov965x_intervals[i];
1134
1135 if (mbus_fmt->width != iv->size.width ||
1136 mbus_fmt->height != iv->size.height)
1137 continue;
1138 err = abs((u64)(iv->interval.numerator * 10000) /
1139 iv->interval.denominator - req_int);
1140 if (err < min_err) {
1141 fiv = iv;
1142 min_err = err;
1143 }
1144 }
1145 ov965x->fiv = fiv;
1146
1147 v4l2_dbg(1, debug, &ov965x->sd, "Changed frame interval to %u us\n",
1148 fiv->interval.numerator * 1000000 / fiv->interval.denominator);
1149
1150 return 0;
1151 }
1152
ov965x_s_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_frame_interval * fi)1153 static int ov965x_s_frame_interval(struct v4l2_subdev *sd,
1154 struct v4l2_subdev_frame_interval *fi)
1155 {
1156 struct ov965x *ov965x = to_ov965x(sd);
1157 int ret;
1158
1159 v4l2_dbg(1, debug, sd, "Setting %d/%d frame interval\n",
1160 fi->interval.numerator, fi->interval.denominator);
1161
1162 mutex_lock(&ov965x->lock);
1163 ret = __ov965x_set_frame_interval(ov965x, fi);
1164 ov965x->apply_frame_fmt = 1;
1165 mutex_unlock(&ov965x->lock);
1166 return ret;
1167 }
1168
ov965x_get_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)1169 static int ov965x_get_fmt(struct v4l2_subdev *sd,
1170 struct v4l2_subdev_pad_config *cfg,
1171 struct v4l2_subdev_format *fmt)
1172 {
1173 struct ov965x *ov965x = to_ov965x(sd);
1174 struct v4l2_mbus_framefmt *mf;
1175
1176 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
1177 mf = v4l2_subdev_get_try_format(sd, cfg, 0);
1178 fmt->format = *mf;
1179 return 0;
1180 }
1181
1182 mutex_lock(&ov965x->lock);
1183 fmt->format = ov965x->format;
1184 mutex_unlock(&ov965x->lock);
1185
1186 return 0;
1187 }
1188
__ov965x_try_frame_size(struct v4l2_mbus_framefmt * mf,const struct ov965x_framesize ** size)1189 static void __ov965x_try_frame_size(struct v4l2_mbus_framefmt *mf,
1190 const struct ov965x_framesize **size)
1191 {
1192 const struct ov965x_framesize *fsize = &ov965x_framesizes[0],
1193 *match = NULL;
1194 int i = ARRAY_SIZE(ov965x_framesizes);
1195 unsigned int min_err = UINT_MAX;
1196
1197 while (i--) {
1198 int err = abs(fsize->width - mf->width)
1199 + abs(fsize->height - mf->height);
1200 if (err < min_err) {
1201 min_err = err;
1202 match = fsize;
1203 }
1204 fsize++;
1205 }
1206 if (!match)
1207 match = &ov965x_framesizes[0];
1208 mf->width = match->width;
1209 mf->height = match->height;
1210 if (size)
1211 *size = match;
1212 }
1213
ov965x_set_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)1214 static int ov965x_set_fmt(struct v4l2_subdev *sd,
1215 struct v4l2_subdev_pad_config *cfg,
1216 struct v4l2_subdev_format *fmt)
1217 {
1218 unsigned int index = ARRAY_SIZE(ov965x_formats);
1219 struct v4l2_mbus_framefmt *mf = &fmt->format;
1220 struct ov965x *ov965x = to_ov965x(sd);
1221 const struct ov965x_framesize *size = NULL;
1222 int ret = 0;
1223
1224 __ov965x_try_frame_size(mf, &size);
1225
1226 while (--index)
1227 if (ov965x_formats[index].code == mf->code)
1228 break;
1229
1230 mf->colorspace = V4L2_COLORSPACE_JPEG;
1231 mf->code = ov965x_formats[index].code;
1232 mf->field = V4L2_FIELD_NONE;
1233
1234 mutex_lock(&ov965x->lock);
1235
1236 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
1237 if (cfg) {
1238 mf = v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
1239 *mf = fmt->format;
1240 }
1241 } else {
1242 if (ov965x->streaming) {
1243 ret = -EBUSY;
1244 } else {
1245 ov965x->frame_size = size;
1246 ov965x->format = fmt->format;
1247 ov965x->tslb_reg = ov965x_formats[index].tslb_reg;
1248 ov965x->apply_frame_fmt = 1;
1249 }
1250 }
1251
1252 if (!ret && fmt->which == V4L2_SUBDEV_FORMAT_ACTIVE) {
1253 struct v4l2_subdev_frame_interval fiv = {
1254 .interval = { 0, 1 }
1255 };
1256 /* Reset to minimum possible frame interval */
1257 __ov965x_set_frame_interval(ov965x, &fiv);
1258 }
1259 mutex_unlock(&ov965x->lock);
1260
1261 if (!ret)
1262 ov965x_update_exposure_ctrl(ov965x);
1263
1264 return ret;
1265 }
1266
ov965x_set_frame_size(struct ov965x * ov965x)1267 static int ov965x_set_frame_size(struct ov965x *ov965x)
1268 {
1269 int i, ret = 0;
1270
1271 for (i = 0; ret == 0 && i < NUM_FMT_REGS; i++)
1272 ret = ov965x_write(ov965x, frame_size_reg_addr[i],
1273 ov965x->frame_size->regs[i]);
1274 return ret;
1275 }
1276
__ov965x_set_params(struct ov965x * ov965x)1277 static int __ov965x_set_params(struct ov965x *ov965x)
1278 {
1279 struct ov965x_ctrls *ctrls = &ov965x->ctrls;
1280 int ret = 0;
1281 u8 reg;
1282
1283 if (ov965x->apply_frame_fmt) {
1284 reg = DEF_CLKRC + ov965x->fiv->clkrc_div;
1285 ret = ov965x_write(ov965x, REG_CLKRC, reg);
1286 if (ret < 0)
1287 return ret;
1288 ret = ov965x_set_frame_size(ov965x);
1289 if (ret < 0)
1290 return ret;
1291 ret = ov965x_read(ov965x, REG_TSLB, ®);
1292 if (ret < 0)
1293 return ret;
1294 reg &= ~TSLB_YUYV_MASK;
1295 reg |= ov965x->tslb_reg;
1296 ret = ov965x_write(ov965x, REG_TSLB, reg);
1297 if (ret < 0)
1298 return ret;
1299 }
1300 ret = ov965x_set_default_gamma_curve(ov965x);
1301 if (ret < 0)
1302 return ret;
1303 ret = ov965x_set_color_matrix(ov965x);
1304 if (ret < 0)
1305 return ret;
1306 /*
1307 * Select manual banding filter, the filter will
1308 * be enabled further if required.
1309 */
1310 ret = ov965x_read(ov965x, REG_COM11, ®);
1311 if (!ret)
1312 reg |= COM11_BANDING;
1313 ret = ov965x_write(ov965x, REG_COM11, reg);
1314 if (ret < 0)
1315 return ret;
1316 /*
1317 * Banding filter (REG_MBD value) needs to match selected
1318 * resolution and frame rate, so it's always updated here.
1319 */
1320 return ov965x_set_banding_filter(ov965x, ctrls->light_freq->val);
1321 }
1322
ov965x_s_stream(struct v4l2_subdev * sd,int on)1323 static int ov965x_s_stream(struct v4l2_subdev *sd, int on)
1324 {
1325 struct ov965x *ov965x = to_ov965x(sd);
1326 struct ov965x_ctrls *ctrls = &ov965x->ctrls;
1327 int ret = 0;
1328
1329 v4l2_dbg(1, debug, sd, "%s: on: %d\n", __func__, on);
1330
1331 mutex_lock(&ov965x->lock);
1332 if (ov965x->streaming == !on) {
1333 if (on)
1334 ret = __ov965x_set_params(ov965x);
1335
1336 if (!ret && ctrls->update) {
1337 /*
1338 * ov965x_s_ctrl callback takes the mutex
1339 * so it needs to be released here.
1340 */
1341 mutex_unlock(&ov965x->lock);
1342 ret = v4l2_ctrl_handler_setup(&ctrls->handler);
1343
1344 mutex_lock(&ov965x->lock);
1345 if (!ret)
1346 ctrls->update = 0;
1347 }
1348 if (!ret)
1349 ret = ov965x_write(ov965x, REG_COM2,
1350 on ? 0x01 : 0x11);
1351 }
1352 if (!ret)
1353 ov965x->streaming += on ? 1 : -1;
1354
1355 WARN_ON(ov965x->streaming < 0);
1356 mutex_unlock(&ov965x->lock);
1357
1358 return ret;
1359 }
1360
1361 /*
1362 * V4L2 subdev internal operations
1363 */
ov965x_open(struct v4l2_subdev * sd,struct v4l2_subdev_fh * fh)1364 static int ov965x_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
1365 {
1366 struct v4l2_mbus_framefmt *mf =
1367 v4l2_subdev_get_try_format(sd, fh->pad, 0);
1368
1369 ov965x_get_default_format(mf);
1370 return 0;
1371 }
1372
1373 static const struct v4l2_subdev_pad_ops ov965x_pad_ops = {
1374 .enum_mbus_code = ov965x_enum_mbus_code,
1375 .enum_frame_size = ov965x_enum_frame_sizes,
1376 .get_fmt = ov965x_get_fmt,
1377 .set_fmt = ov965x_set_fmt,
1378 };
1379
1380 static const struct v4l2_subdev_video_ops ov965x_video_ops = {
1381 .s_stream = ov965x_s_stream,
1382 .g_frame_interval = ov965x_g_frame_interval,
1383 .s_frame_interval = ov965x_s_frame_interval,
1384
1385 };
1386
1387 static const struct v4l2_subdev_internal_ops ov965x_sd_internal_ops = {
1388 .open = ov965x_open,
1389 };
1390
1391 static const struct v4l2_subdev_core_ops ov965x_core_ops = {
1392 .s_power = ov965x_s_power,
1393 .log_status = v4l2_ctrl_subdev_log_status,
1394 .subscribe_event = v4l2_ctrl_subdev_subscribe_event,
1395 .unsubscribe_event = v4l2_event_subdev_unsubscribe,
1396 };
1397
1398 static const struct v4l2_subdev_ops ov965x_subdev_ops = {
1399 .core = &ov965x_core_ops,
1400 .pad = &ov965x_pad_ops,
1401 .video = &ov965x_video_ops,
1402 };
1403
1404 /*
1405 * Reset and power down GPIOs configuration
1406 */
ov965x_configure_gpios_pdata(struct ov965x * ov965x,const struct ov9650_platform_data * pdata)1407 static int ov965x_configure_gpios_pdata(struct ov965x *ov965x,
1408 const struct ov9650_platform_data *pdata)
1409 {
1410 int ret, i;
1411 int gpios[NUM_GPIOS];
1412 struct device *dev = regmap_get_device(ov965x->regmap);
1413
1414 gpios[GPIO_PWDN] = pdata->gpio_pwdn;
1415 gpios[GPIO_RST] = pdata->gpio_reset;
1416
1417 for (i = 0; i < ARRAY_SIZE(ov965x->gpios); i++) {
1418 int gpio = gpios[i];
1419
1420 if (!gpio_is_valid(gpio))
1421 continue;
1422 ret = devm_gpio_request_one(dev, gpio,
1423 GPIOF_OUT_INIT_HIGH, "OV965X");
1424 if (ret < 0)
1425 return ret;
1426 v4l2_dbg(1, debug, &ov965x->sd, "set gpio %d to 1\n", gpio);
1427
1428 gpio_set_value_cansleep(gpio, 1);
1429 gpio_export(gpio, 0);
1430 ov965x->gpios[i] = gpio_to_desc(gpio);
1431 }
1432
1433 return 0;
1434 }
1435
ov965x_configure_gpios(struct ov965x * ov965x)1436 static int ov965x_configure_gpios(struct ov965x *ov965x)
1437 {
1438 struct device *dev = regmap_get_device(ov965x->regmap);
1439
1440 ov965x->gpios[GPIO_PWDN] = devm_gpiod_get_optional(dev, "powerdown",
1441 GPIOD_OUT_HIGH);
1442 if (IS_ERR(ov965x->gpios[GPIO_PWDN])) {
1443 dev_info(dev, "can't get %s GPIO\n", "powerdown");
1444 return PTR_ERR(ov965x->gpios[GPIO_PWDN]);
1445 }
1446
1447 ov965x->gpios[GPIO_RST] = devm_gpiod_get_optional(dev, "reset",
1448 GPIOD_OUT_HIGH);
1449 if (IS_ERR(ov965x->gpios[GPIO_RST])) {
1450 dev_info(dev, "can't get %s GPIO\n", "reset");
1451 return PTR_ERR(ov965x->gpios[GPIO_RST]);
1452 }
1453
1454 return 0;
1455 }
1456
ov965x_detect_sensor(struct v4l2_subdev * sd)1457 static int ov965x_detect_sensor(struct v4l2_subdev *sd)
1458 {
1459 struct ov965x *ov965x = to_ov965x(sd);
1460 u8 pid, ver;
1461 int ret;
1462
1463 mutex_lock(&ov965x->lock);
1464 ret = __ov965x_set_power(ov965x, 1);
1465 if (ret)
1466 goto out;
1467
1468 msleep(25);
1469
1470 /* Check sensor revision */
1471 ret = ov965x_read(ov965x, REG_PID, &pid);
1472 if (!ret)
1473 ret = ov965x_read(ov965x, REG_VER, &ver);
1474
1475 __ov965x_set_power(ov965x, 0);
1476
1477 if (!ret) {
1478 ov965x->id = OV965X_ID(pid, ver);
1479 if (ov965x->id == OV9650_ID || ov965x->id == OV9652_ID) {
1480 v4l2_info(sd, "Found OV%04X sensor\n", ov965x->id);
1481 } else {
1482 v4l2_err(sd, "Sensor detection failed (%04X, %d)\n",
1483 ov965x->id, ret);
1484 ret = -ENODEV;
1485 }
1486 }
1487 out:
1488 mutex_unlock(&ov965x->lock);
1489
1490 return ret;
1491 }
1492
ov965x_probe(struct i2c_client * client)1493 static int ov965x_probe(struct i2c_client *client)
1494 {
1495 const struct ov9650_platform_data *pdata = client->dev.platform_data;
1496 struct v4l2_subdev *sd;
1497 struct ov965x *ov965x;
1498 int ret;
1499 static const struct regmap_config ov965x_regmap_config = {
1500 .reg_bits = 8,
1501 .val_bits = 8,
1502 .max_register = 0xab,
1503 };
1504
1505 ov965x = devm_kzalloc(&client->dev, sizeof(*ov965x), GFP_KERNEL);
1506 if (!ov965x)
1507 return -ENOMEM;
1508
1509 ov965x->regmap = devm_regmap_init_sccb(client, &ov965x_regmap_config);
1510 if (IS_ERR(ov965x->regmap)) {
1511 dev_err(&client->dev, "Failed to allocate register map\n");
1512 return PTR_ERR(ov965x->regmap);
1513 }
1514
1515 if (pdata) {
1516 if (pdata->mclk_frequency == 0) {
1517 dev_err(&client->dev, "MCLK frequency not specified\n");
1518 return -EINVAL;
1519 }
1520 ov965x->mclk_frequency = pdata->mclk_frequency;
1521
1522 ret = ov965x_configure_gpios_pdata(ov965x, pdata);
1523 if (ret < 0)
1524 return ret;
1525 } else if (dev_fwnode(&client->dev)) {
1526 ov965x->clk = devm_clk_get(&client->dev, NULL);
1527 if (IS_ERR(ov965x->clk))
1528 return PTR_ERR(ov965x->clk);
1529 ov965x->mclk_frequency = clk_get_rate(ov965x->clk);
1530
1531 ret = ov965x_configure_gpios(ov965x);
1532 if (ret < 0)
1533 return ret;
1534 } else {
1535 dev_err(&client->dev,
1536 "Neither platform data nor device property specified\n");
1537
1538 return -EINVAL;
1539 }
1540
1541 mutex_init(&ov965x->lock);
1542
1543 sd = &ov965x->sd;
1544 v4l2_i2c_subdev_init(sd, client, &ov965x_subdev_ops);
1545 strscpy(sd->name, DRIVER_NAME, sizeof(sd->name));
1546
1547 sd->internal_ops = &ov965x_sd_internal_ops;
1548 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
1549 V4L2_SUBDEV_FL_HAS_EVENTS;
1550
1551 ov965x->pad.flags = MEDIA_PAD_FL_SOURCE;
1552 sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
1553 ret = media_entity_pads_init(&sd->entity, 1, &ov965x->pad);
1554 if (ret < 0)
1555 goto err_mutex;
1556
1557 ret = ov965x_initialize_controls(ov965x);
1558 if (ret < 0)
1559 goto err_me;
1560
1561 ov965x_get_default_format(&ov965x->format);
1562 ov965x->frame_size = &ov965x_framesizes[0];
1563 ov965x->fiv = &ov965x_intervals[0];
1564
1565 ret = ov965x_detect_sensor(sd);
1566 if (ret < 0)
1567 goto err_ctrls;
1568
1569 /* Update exposure time min/max to match frame format */
1570 ov965x_update_exposure_ctrl(ov965x);
1571
1572 ret = v4l2_async_register_subdev(sd);
1573 if (ret < 0)
1574 goto err_ctrls;
1575
1576 return 0;
1577 err_ctrls:
1578 v4l2_ctrl_handler_free(sd->ctrl_handler);
1579 err_me:
1580 media_entity_cleanup(&sd->entity);
1581 err_mutex:
1582 mutex_destroy(&ov965x->lock);
1583 return ret;
1584 }
1585
ov965x_remove(struct i2c_client * client)1586 static int ov965x_remove(struct i2c_client *client)
1587 {
1588 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1589 struct ov965x *ov965x = to_ov965x(sd);
1590
1591 v4l2_async_unregister_subdev(sd);
1592 v4l2_ctrl_handler_free(sd->ctrl_handler);
1593 media_entity_cleanup(&sd->entity);
1594 mutex_destroy(&ov965x->lock);
1595
1596 return 0;
1597 }
1598
1599 static const struct i2c_device_id ov965x_id[] = {
1600 { "OV9650", 0 },
1601 { "OV9652", 0 },
1602 { /* sentinel */ }
1603 };
1604 MODULE_DEVICE_TABLE(i2c, ov965x_id);
1605
1606 #if IS_ENABLED(CONFIG_OF)
1607 static const struct of_device_id ov965x_of_match[] = {
1608 { .compatible = "ovti,ov9650", },
1609 { .compatible = "ovti,ov9652", },
1610 { /* sentinel */ }
1611 };
1612 MODULE_DEVICE_TABLE(of, ov965x_of_match);
1613 #endif
1614
1615 static struct i2c_driver ov965x_i2c_driver = {
1616 .driver = {
1617 .name = DRIVER_NAME,
1618 .of_match_table = of_match_ptr(ov965x_of_match),
1619 },
1620 .probe_new = ov965x_probe,
1621 .remove = ov965x_remove,
1622 .id_table = ov965x_id,
1623 };
1624
1625 module_i2c_driver(ov965x_i2c_driver);
1626
1627 MODULE_AUTHOR("Sylwester Nawrocki <sylvester.nawrocki@gmail.com>");
1628 MODULE_DESCRIPTION("OV9650/OV9652 CMOS Image Sensor driver");
1629 MODULE_LICENSE("GPL");
1630
