1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * ov5695 driver
4 *
5 * Copyright (C) 2017 Fuzhou Rockchip Electronics Co., Ltd.
6 */
7
8 #include <linux/clk.h>
9 #include <linux/device.h>
10 #include <linux/delay.h>
11 #include <linux/gpio/consumer.h>
12 #include <linux/i2c.h>
13 #include <linux/module.h>
14 #include <linux/pm_runtime.h>
15 #include <linux/regulator/consumer.h>
16 #include <linux/sysfs.h>
17 #include <media/media-entity.h>
18 #include <media/v4l2-async.h>
19 #include <media/v4l2-ctrls.h>
20 #include <media/v4l2-subdev.h>
21
22 #ifndef V4L2_CID_DIGITAL_GAIN
23 #define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN
24 #endif
25
26 /* 45Mhz * 4 Binning */
27 #define OV5695_PIXEL_RATE (45 * 1000 * 1000 * 4)
28 #define OV5695_XVCLK_FREQ 24000000
29
30 #define CHIP_ID 0x005695
31 #define OV5695_REG_CHIP_ID 0x300a
32
33 #define OV5695_REG_CTRL_MODE 0x0100
34 #define OV5695_MODE_SW_STANDBY 0x0
35 #define OV5695_MODE_STREAMING BIT(0)
36
37 #define OV5695_REG_EXPOSURE 0x3500
38 #define OV5695_EXPOSURE_MIN 4
39 #define OV5695_EXPOSURE_STEP 1
40 #define OV5695_VTS_MAX 0x7fff
41
42 #define OV5695_REG_ANALOG_GAIN 0x3509
43 #define ANALOG_GAIN_MIN 0x10
44 #define ANALOG_GAIN_MAX 0xf8
45 #define ANALOG_GAIN_STEP 1
46 #define ANALOG_GAIN_DEFAULT 0xf8
47
48 #define OV5695_REG_DIGI_GAIN_H 0x350a
49 #define OV5695_REG_DIGI_GAIN_L 0x350b
50 #define OV5695_DIGI_GAIN_L_MASK 0x3f
51 #define OV5695_DIGI_GAIN_H_SHIFT 6
52 #define OV5695_DIGI_GAIN_MIN 0
53 #define OV5695_DIGI_GAIN_MAX (0x4000 - 1)
54 #define OV5695_DIGI_GAIN_STEP 1
55 #define OV5695_DIGI_GAIN_DEFAULT 1024
56
57 #define OV5695_REG_TEST_PATTERN 0x4503
58 #define OV5695_TEST_PATTERN_ENABLE 0x80
59 #define OV5695_TEST_PATTERN_DISABLE 0x0
60
61 #define OV5695_REG_VTS 0x380e
62
63 #define REG_NULL 0xFFFF
64
65 #define OV5695_REG_VALUE_08BIT 1
66 #define OV5695_REG_VALUE_16BIT 2
67 #define OV5695_REG_VALUE_24BIT 3
68
69 #define OV5695_LANES 2
70 #define OV5695_BITS_PER_SAMPLE 10
71
72 static const char * const ov5695_supply_names[] = {
73 "avdd", /* Analog power */
74 "dovdd", /* Digital I/O power */
75 "dvdd", /* Digital core power */
76 };
77
78 #define OV5695_NUM_SUPPLIES ARRAY_SIZE(ov5695_supply_names)
79
80 struct regval {
81 u16 addr;
82 u8 val;
83 };
84
85 struct ov5695_mode {
86 u32 width;
87 u32 height;
88 u32 max_fps;
89 u32 hts_def;
90 u32 vts_def;
91 u32 exp_def;
92 const struct regval *reg_list;
93 };
94
95 struct ov5695 {
96 struct i2c_client *client;
97 struct clk *xvclk;
98 struct gpio_desc *reset_gpio;
99 struct regulator_bulk_data supplies[OV5695_NUM_SUPPLIES];
100
101 struct v4l2_subdev subdev;
102 struct media_pad pad;
103 struct v4l2_ctrl_handler ctrl_handler;
104 struct v4l2_ctrl *exposure;
105 struct v4l2_ctrl *anal_gain;
106 struct v4l2_ctrl *digi_gain;
107 struct v4l2_ctrl *hblank;
108 struct v4l2_ctrl *vblank;
109 struct v4l2_ctrl *test_pattern;
110 struct mutex mutex;
111 bool streaming;
112 const struct ov5695_mode *cur_mode;
113 };
114
115 #define to_ov5695(sd) container_of(sd, struct ov5695, subdev)
116
117 /*
118 * Xclk 24Mhz
119 * Pclk 45Mhz
120 * linelength 672(0x2a0)
121 * framelength 2232(0x8b8)
122 * grabwindow_width 1296
123 * grabwindow_height 972
124 * max_framerate 30fps
125 * mipi_datarate per lane 840Mbps
126 */
127 static const struct regval ov5695_global_regs[] = {
128 {0x0103, 0x01},
129 {0x0100, 0x00},
130 {0x0300, 0x04},
131 {0x0301, 0x00},
132 {0x0302, 0x69},
133 {0x0303, 0x00},
134 {0x0304, 0x00},
135 {0x0305, 0x01},
136 {0x0307, 0x00},
137 {0x030b, 0x00},
138 {0x030c, 0x00},
139 {0x030d, 0x1e},
140 {0x030e, 0x04},
141 {0x030f, 0x03},
142 {0x0312, 0x01},
143 {0x3000, 0x00},
144 {0x3002, 0xa1},
145 {0x3008, 0x00},
146 {0x3010, 0x00},
147 {0x3022, 0x51},
148 {0x3106, 0x15},
149 {0x3107, 0x01},
150 {0x3108, 0x05},
151 {0x3500, 0x00},
152 {0x3501, 0x45},
153 {0x3502, 0x00},
154 {0x3503, 0x08},
155 {0x3504, 0x03},
156 {0x3505, 0x8c},
157 {0x3507, 0x03},
158 {0x3508, 0x00},
159 {0x3509, 0x10},
160 {0x350c, 0x00},
161 {0x350d, 0x80},
162 {0x3510, 0x00},
163 {0x3511, 0x02},
164 {0x3512, 0x00},
165 {0x3601, 0x55},
166 {0x3602, 0x58},
167 {0x3614, 0x30},
168 {0x3615, 0x77},
169 {0x3621, 0x08},
170 {0x3624, 0x40},
171 {0x3633, 0x0c},
172 {0x3634, 0x0c},
173 {0x3635, 0x0c},
174 {0x3636, 0x0c},
175 {0x3638, 0x00},
176 {0x3639, 0x00},
177 {0x363a, 0x00},
178 {0x363b, 0x00},
179 {0x363c, 0xff},
180 {0x363d, 0xfa},
181 {0x3650, 0x44},
182 {0x3651, 0x44},
183 {0x3652, 0x44},
184 {0x3653, 0x44},
185 {0x3654, 0x44},
186 {0x3655, 0x44},
187 {0x3656, 0x44},
188 {0x3657, 0x44},
189 {0x3660, 0x00},
190 {0x3661, 0x00},
191 {0x3662, 0x00},
192 {0x366a, 0x00},
193 {0x366e, 0x0c},
194 {0x3673, 0x04},
195 {0x3700, 0x14},
196 {0x3703, 0x0c},
197 {0x3715, 0x01},
198 {0x3733, 0x10},
199 {0x3734, 0x40},
200 {0x373f, 0xa0},
201 {0x3765, 0x20},
202 {0x37a1, 0x1d},
203 {0x37a8, 0x26},
204 {0x37ab, 0x14},
205 {0x37c2, 0x04},
206 {0x37cb, 0x09},
207 {0x37cc, 0x13},
208 {0x37cd, 0x1f},
209 {0x37ce, 0x1f},
210 {0x3800, 0x00},
211 {0x3801, 0x00},
212 {0x3802, 0x00},
213 {0x3803, 0x00},
214 {0x3804, 0x0a},
215 {0x3805, 0x3f},
216 {0x3806, 0x07},
217 {0x3807, 0xaf},
218 {0x3808, 0x05},
219 {0x3809, 0x10},
220 {0x380a, 0x03},
221 {0x380b, 0xcc},
222 {0x380c, 0x02},
223 {0x380d, 0xa0},
224 {0x380e, 0x08},
225 {0x380f, 0xb8},
226 {0x3810, 0x00},
227 {0x3811, 0x06},
228 {0x3812, 0x00},
229 {0x3813, 0x06},
230 {0x3814, 0x03},
231 {0x3815, 0x01},
232 {0x3816, 0x03},
233 {0x3817, 0x01},
234 {0x3818, 0x00},
235 {0x3819, 0x00},
236 {0x381a, 0x00},
237 {0x381b, 0x01},
238 {0x3820, 0x8b},
239 {0x3821, 0x01},
240 {0x3c80, 0x08},
241 {0x3c82, 0x00},
242 {0x3c83, 0x00},
243 {0x3c88, 0x00},
244 {0x3d85, 0x14},
245 {0x3f02, 0x08},
246 {0x3f03, 0x10},
247 {0x4008, 0x02},
248 {0x4009, 0x09},
249 {0x404e, 0x20},
250 {0x4501, 0x00},
251 {0x4502, 0x10},
252 {0x4800, 0x00},
253 {0x481f, 0x2a},
254 {0x4837, 0x13},
255 {0x5000, 0x17},
256 {0x5780, 0x3e},
257 {0x5781, 0x0f},
258 {0x5782, 0x44},
259 {0x5783, 0x02},
260 {0x5784, 0x01},
261 {0x5785, 0x01},
262 {0x5786, 0x00},
263 {0x5787, 0x04},
264 {0x5788, 0x02},
265 {0x5789, 0x0f},
266 {0x578a, 0xfd},
267 {0x578b, 0xf5},
268 {0x578c, 0xf5},
269 {0x578d, 0x03},
270 {0x578e, 0x08},
271 {0x578f, 0x0c},
272 {0x5790, 0x08},
273 {0x5791, 0x06},
274 {0x5792, 0x00},
275 {0x5793, 0x52},
276 {0x5794, 0xa3},
277 {0x5b00, 0x00},
278 {0x5b01, 0x1c},
279 {0x5b02, 0x00},
280 {0x5b03, 0x7f},
281 {0x5b05, 0x6c},
282 {0x5e10, 0xfc},
283 {0x4010, 0xf1},
284 {0x3503, 0x08},
285 {0x3505, 0x8c},
286 {0x3507, 0x03},
287 {0x3508, 0x00},
288 {0x3509, 0xf8},
289 {REG_NULL, 0x00},
290 };
291
292 /*
293 * Xclk 24Mhz
294 * Pclk 45Mhz
295 * linelength 740(0x2e4)
296 * framelength 2024(0x7e8)
297 * grabwindow_width 2592
298 * grabwindow_height 1944
299 * max_framerate 30fps
300 * mipi_datarate per lane 840Mbps
301 */
302 static const struct regval ov5695_2592x1944_regs[] = {
303 {0x3501, 0x7e},
304 {0x366e, 0x18},
305 {0x3800, 0x00},
306 {0x3801, 0x00},
307 {0x3802, 0x00},
308 {0x3803, 0x04},
309 {0x3804, 0x0a},
310 {0x3805, 0x3f},
311 {0x3806, 0x07},
312 {0x3807, 0xab},
313 {0x3808, 0x0a},
314 {0x3809, 0x20},
315 {0x380a, 0x07},
316 {0x380b, 0x98},
317 {0x380c, 0x02},
318 {0x380d, 0xe4},
319 {0x380e, 0x07},
320 {0x380f, 0xe8},
321 {0x3811, 0x06},
322 {0x3813, 0x08},
323 {0x3814, 0x01},
324 {0x3816, 0x01},
325 {0x3817, 0x01},
326 {0x3820, 0x88},
327 {0x3821, 0x00},
328 {0x4501, 0x00},
329 {0x4008, 0x04},
330 {0x4009, 0x13},
331 {REG_NULL, 0x00},
332 };
333
334 /*
335 * Xclk 24Mhz
336 * Pclk 45Mhz
337 * linelength 672(0x2a0)
338 * framelength 2232(0x8b8)
339 * grabwindow_width 1920
340 * grabwindow_height 1080
341 * max_framerate 30fps
342 * mipi_datarate per lane 840Mbps
343 */
344 static const struct regval ov5695_1920x1080_regs[] = {
345 {0x3501, 0x45},
346 {0x366e, 0x18},
347 {0x3800, 0x01},
348 {0x3801, 0x50},
349 {0x3802, 0x01},
350 {0x3803, 0xb8},
351 {0x3804, 0x08},
352 {0x3805, 0xef},
353 {0x3806, 0x05},
354 {0x3807, 0xf7},
355 {0x3808, 0x07},
356 {0x3809, 0x80},
357 {0x380a, 0x04},
358 {0x380b, 0x38},
359 {0x380c, 0x02},
360 {0x380d, 0xa0},
361 {0x380e, 0x08},
362 {0x380f, 0xb8},
363 {0x3811, 0x06},
364 {0x3813, 0x04},
365 {0x3814, 0x01},
366 {0x3816, 0x01},
367 {0x3817, 0x01},
368 {0x3820, 0x88},
369 {0x3821, 0x00},
370 {0x4501, 0x00},
371 {0x4008, 0x04},
372 {0x4009, 0x13},
373 {REG_NULL, 0x00}
374 };
375
376 /*
377 * Xclk 24Mhz
378 * Pclk 45Mhz
379 * linelength 740(0x02e4)
380 * framelength 1012(0x03f4)
381 * grabwindow_width 1296
382 * grabwindow_height 972
383 * max_framerate 60fps
384 * mipi_datarate per lane 840Mbps
385 */
386 static const struct regval ov5695_1296x972_regs[] = {
387 {0x0103, 0x01},
388 {0x0100, 0x00},
389 {0x0300, 0x04},
390 {0x0301, 0x00},
391 {0x0302, 0x69},
392 {0x0303, 0x00},
393 {0x0304, 0x00},
394 {0x0305, 0x01},
395 {0x0307, 0x00},
396 {0x030b, 0x00},
397 {0x030c, 0x00},
398 {0x030d, 0x1e},
399 {0x030e, 0x04},
400 {0x030f, 0x03},
401 {0x0312, 0x01},
402 {0x3000, 0x00},
403 {0x3002, 0xa1},
404 {0x3008, 0x00},
405 {0x3010, 0x00},
406 {0x3016, 0x32},
407 {0x3022, 0x51},
408 {0x3106, 0x15},
409 {0x3107, 0x01},
410 {0x3108, 0x05},
411 {0x3500, 0x00},
412 {0x3501, 0x3e},
413 {0x3502, 0x00},
414 {0x3503, 0x08},
415 {0x3504, 0x03},
416 {0x3505, 0x8c},
417 {0x3507, 0x03},
418 {0x3508, 0x00},
419 {0x3509, 0x10},
420 {0x350c, 0x00},
421 {0x350d, 0x80},
422 {0x3510, 0x00},
423 {0x3511, 0x02},
424 {0x3512, 0x00},
425 {0x3601, 0x55},
426 {0x3602, 0x58},
427 {0x3611, 0x58},
428 {0x3614, 0x30},
429 {0x3615, 0x77},
430 {0x3621, 0x08},
431 {0x3624, 0x40},
432 {0x3633, 0x0c},
433 {0x3634, 0x0c},
434 {0x3635, 0x0c},
435 {0x3636, 0x0c},
436 {0x3638, 0x00},
437 {0x3639, 0x00},
438 {0x363a, 0x00},
439 {0x363b, 0x00},
440 {0x363c, 0xff},
441 {0x363d, 0xfa},
442 {0x3650, 0x44},
443 {0x3651, 0x44},
444 {0x3652, 0x44},
445 {0x3653, 0x44},
446 {0x3654, 0x44},
447 {0x3655, 0x44},
448 {0x3656, 0x44},
449 {0x3657, 0x44},
450 {0x3660, 0x00},
451 {0x3661, 0x00},
452 {0x3662, 0x00},
453 {0x366a, 0x00},
454 {0x366e, 0x0c},
455 {0x3673, 0x04},
456 {0x3700, 0x14},
457 {0x3703, 0x0c},
458 {0x3706, 0x24},
459 {0x3714, 0x27},
460 {0x3715, 0x01},
461 {0x3716, 0x00},
462 {0x3717, 0x02},
463 {0x3733, 0x10},
464 {0x3734, 0x40},
465 {0x373f, 0xa0},
466 {0x3765, 0x20},
467 {0x37a1, 0x1d},
468 {0x37a8, 0x26},
469 {0x37ab, 0x14},
470 {0x37c2, 0x04},
471 {0x37c3, 0xf0},
472 {0x37cb, 0x09},
473 {0x37cc, 0x13},
474 {0x37cd, 0x1f},
475 {0x37ce, 0x1f},
476 {0x3800, 0x00},
477 {0x3801, 0x00},
478 {0x3802, 0x00},
479 {0x3803, 0x00},
480 {0x3804, 0x0a},
481 {0x3805, 0x3f},
482 {0x3806, 0x07},
483 {0x3807, 0xaf},
484 {0x3808, 0x05},
485 {0x3809, 0x10},
486 {0x380a, 0x03},
487 {0x380b, 0xcc},
488 {0x380c, 0x02},
489 {0x380d, 0xe4},
490 {0x380e, 0x03},
491 {0x380f, 0xf4},
492 {0x3810, 0x00},
493 {0x3811, 0x00},
494 {0x3812, 0x00},
495 {0x3813, 0x06},
496 {0x3814, 0x03},
497 {0x3815, 0x01},
498 {0x3816, 0x03},
499 {0x3817, 0x01},
500 {0x3818, 0x00},
501 {0x3819, 0x00},
502 {0x381a, 0x00},
503 {0x381b, 0x01},
504 {0x3820, 0x8b},
505 {0x3821, 0x01},
506 {0x3c80, 0x08},
507 {0x3c82, 0x00},
508 {0x3c83, 0x00},
509 {0x3c88, 0x00},
510 {0x3d85, 0x14},
511 {0x3f02, 0x08},
512 {0x3f03, 0x10},
513 {0x4008, 0x02},
514 {0x4009, 0x09},
515 {0x404e, 0x20},
516 {0x4501, 0x00},
517 {0x4502, 0x10},
518 {0x4800, 0x00},
519 {0x481f, 0x2a},
520 {0x4837, 0x13},
521 {0x5000, 0x13},
522 {0x5780, 0x3e},
523 {0x5781, 0x0f},
524 {0x5782, 0x44},
525 {0x5783, 0x02},
526 {0x5784, 0x01},
527 {0x5785, 0x01},
528 {0x5786, 0x00},
529 {0x5787, 0x04},
530 {0x5788, 0x02},
531 {0x5789, 0x0f},
532 {0x578a, 0xfd},
533 {0x578b, 0xf5},
534 {0x578c, 0xf5},
535 {0x578d, 0x03},
536 {0x578e, 0x08},
537 {0x578f, 0x0c},
538 {0x5790, 0x08},
539 {0x5791, 0x06},
540 {0x5792, 0x00},
541 {0x5793, 0x52},
542 {0x5794, 0xa3},
543 {0x5b00, 0x00},
544 {0x5b01, 0x1c},
545 {0x5b02, 0x00},
546 {0x5b03, 0x7f},
547 {0x5b05, 0x6c},
548 {0x5e10, 0xfc},
549 {0x4010, 0xf1},
550 {0x3503, 0x08},
551 {0x3505, 0x8c},
552 {0x3507, 0x03},
553 {0x3508, 0x00},
554 {0x3509, 0xf8},
555 {0x0100, 0x01},
556 {REG_NULL, 0x00}
557 };
558
559 /*
560 * Xclk 24Mhz
561 * Pclk 45Mhz
562 * linelength 672(0x2a0)
563 * framelength 2232(0x8b8)
564 * grabwindow_width 1280
565 * grabwindow_height 720
566 * max_framerate 30fps
567 * mipi_datarate per lane 840Mbps
568 */
569 static const struct regval ov5695_1280x720_regs[] = {
570 {0x3501, 0x45},
571 {0x366e, 0x0c},
572 {0x3800, 0x00},
573 {0x3801, 0x00},
574 {0x3802, 0x01},
575 {0x3803, 0x00},
576 {0x3804, 0x0a},
577 {0x3805, 0x3f},
578 {0x3806, 0x06},
579 {0x3807, 0xaf},
580 {0x3808, 0x05},
581 {0x3809, 0x00},
582 {0x380a, 0x02},
583 {0x380b, 0xd0},
584 {0x380c, 0x02},
585 {0x380d, 0xa0},
586 {0x380e, 0x08},
587 {0x380f, 0xb8},
588 {0x3811, 0x06},
589 {0x3813, 0x02},
590 {0x3814, 0x03},
591 {0x3816, 0x03},
592 {0x3817, 0x01},
593 {0x3820, 0x8b},
594 {0x3821, 0x01},
595 {0x4501, 0x00},
596 {0x4008, 0x02},
597 {0x4009, 0x09},
598 {REG_NULL, 0x00}
599 };
600
601 /*
602 * Xclk 24Mhz
603 * Pclk 45Mhz
604 * linelength 672(0x2a0)
605 * framelength 558(0x22e)
606 * grabwindow_width 640
607 * grabwindow_height 480
608 * max_framerate 120fps
609 * mipi_datarate per lane 840Mbps
610 */
611 static const struct regval ov5695_640x480_regs[] = {
612 {0x3501, 0x22},
613 {0x366e, 0x0c},
614 {0x3800, 0x00},
615 {0x3801, 0x00},
616 {0x3802, 0x00},
617 {0x3803, 0x08},
618 {0x3804, 0x0a},
619 {0x3805, 0x3f},
620 {0x3806, 0x07},
621 {0x3807, 0xa7},
622 {0x3808, 0x02},
623 {0x3809, 0x80},
624 {0x380a, 0x01},
625 {0x380b, 0xe0},
626 {0x380c, 0x02},
627 {0x380d, 0xa0},
628 {0x380e, 0x02},
629 {0x380f, 0x2e},
630 {0x3811, 0x06},
631 {0x3813, 0x04},
632 {0x3814, 0x07},
633 {0x3816, 0x05},
634 {0x3817, 0x03},
635 {0x3820, 0x8d},
636 {0x3821, 0x01},
637 {0x4501, 0x00},
638 {0x4008, 0x02},
639 {0x4009, 0x09},
640 {REG_NULL, 0x00}
641 };
642
643 static const struct ov5695_mode supported_modes[] = {
644 {
645 .width = 2592,
646 .height = 1944,
647 .max_fps = 30,
648 .exp_def = 0x0450,
649 .hts_def = 0x02e4 * 4,
650 .vts_def = 0x07e8,
651 .reg_list = ov5695_2592x1944_regs,
652 },
653 {
654 .width = 1920,
655 .height = 1080,
656 .max_fps = 30,
657 .exp_def = 0x0450,
658 .hts_def = 0x02a0 * 4,
659 .vts_def = 0x08b8,
660 .reg_list = ov5695_1920x1080_regs,
661 },
662 {
663 .width = 1296,
664 .height = 972,
665 .max_fps = 60,
666 .exp_def = 0x03e0,
667 .hts_def = 0x02e4 * 4,
668 .vts_def = 0x03f4,
669 .reg_list = ov5695_1296x972_regs,
670 },
671 {
672 .width = 1280,
673 .height = 720,
674 .max_fps = 30,
675 .exp_def = 0x0450,
676 .hts_def = 0x02a0 * 4,
677 .vts_def = 0x08b8,
678 .reg_list = ov5695_1280x720_regs,
679 },
680 {
681 .width = 640,
682 .height = 480,
683 .max_fps = 120,
684 .exp_def = 0x0450,
685 .hts_def = 0x02a0 * 4,
686 .vts_def = 0x022e,
687 .reg_list = ov5695_640x480_regs,
688 },
689 };
690
691 #define OV5695_LINK_FREQ_420MHZ 420000000
692 static const s64 link_freq_menu_items[] = {
693 OV5695_LINK_FREQ_420MHZ
694 };
695
696 static const char * const ov5695_test_pattern_menu[] = {
697 "Disabled",
698 "Vertical Color Bar Type 1",
699 "Vertical Color Bar Type 2",
700 "Vertical Color Bar Type 3",
701 "Vertical Color Bar Type 4"
702 };
703
704 /* Write registers up to 4 at a time */
ov5695_write_reg(struct i2c_client * client,u16 reg,u32 len,u32 val)705 static int ov5695_write_reg(struct i2c_client *client, u16 reg,
706 u32 len, u32 val)
707 {
708 u32 buf_i, val_i;
709 u8 buf[6];
710 u8 *val_p;
711 __be32 val_be;
712
713 if (len > 4)
714 return -EINVAL;
715
716 buf[0] = reg >> 8;
717 buf[1] = reg & 0xff;
718
719 val_be = cpu_to_be32(val);
720 val_p = (u8 *)&val_be;
721 buf_i = 2;
722 val_i = 4 - len;
723
724 while (val_i < 4)
725 buf[buf_i++] = val_p[val_i++];
726
727 if (i2c_master_send(client, buf, len + 2) != len + 2)
728 return -EIO;
729
730 return 0;
731 }
732
ov5695_write_array(struct i2c_client * client,const struct regval * regs)733 static int ov5695_write_array(struct i2c_client *client,
734 const struct regval *regs)
735 {
736 u32 i;
737 int ret = 0;
738
739 for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++)
740 ret = ov5695_write_reg(client, regs[i].addr,
741 OV5695_REG_VALUE_08BIT, regs[i].val);
742
743 return ret;
744 }
745
746 /* Read registers up to 4 at a time */
ov5695_read_reg(struct i2c_client * client,u16 reg,unsigned int len,u32 * val)747 static int ov5695_read_reg(struct i2c_client *client, u16 reg, unsigned int len,
748 u32 *val)
749 {
750 struct i2c_msg msgs[2];
751 u8 *data_be_p;
752 __be32 data_be = 0;
753 __be16 reg_addr_be = cpu_to_be16(reg);
754 int ret;
755
756 if (len > 4)
757 return -EINVAL;
758
759 data_be_p = (u8 *)&data_be;
760 /* Write register address */
761 msgs[0].addr = client->addr;
762 msgs[0].flags = 0;
763 msgs[0].len = 2;
764 msgs[0].buf = (u8 *)®_addr_be;
765
766 /* Read data from register */
767 msgs[1].addr = client->addr;
768 msgs[1].flags = I2C_M_RD;
769 msgs[1].len = len;
770 msgs[1].buf = &data_be_p[4 - len];
771
772 ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
773 if (ret != ARRAY_SIZE(msgs))
774 return -EIO;
775
776 *val = be32_to_cpu(data_be);
777
778 return 0;
779 }
780
ov5695_get_reso_dist(const struct ov5695_mode * mode,struct v4l2_mbus_framefmt * framefmt)781 static int ov5695_get_reso_dist(const struct ov5695_mode *mode,
782 struct v4l2_mbus_framefmt *framefmt)
783 {
784 return abs(mode->width - framefmt->width) +
785 abs(mode->height - framefmt->height);
786 }
787
788 static const struct ov5695_mode *
ov5695_find_best_fit(struct v4l2_subdev_format * fmt)789 ov5695_find_best_fit(struct v4l2_subdev_format *fmt)
790 {
791 struct v4l2_mbus_framefmt *framefmt = &fmt->format;
792 int dist;
793 int cur_best_fit = 0;
794 int cur_best_fit_dist = -1;
795 int i;
796
797 for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
798 dist = ov5695_get_reso_dist(&supported_modes[i], framefmt);
799 if (cur_best_fit_dist == -1 || dist < cur_best_fit_dist) {
800 cur_best_fit_dist = dist;
801 cur_best_fit = i;
802 }
803 }
804
805 return &supported_modes[cur_best_fit];
806 }
807
ov5695_set_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)808 static int ov5695_set_fmt(struct v4l2_subdev *sd,
809 struct v4l2_subdev_pad_config *cfg,
810 struct v4l2_subdev_format *fmt)
811 {
812 struct ov5695 *ov5695 = to_ov5695(sd);
813 const struct ov5695_mode *mode;
814 s64 h_blank, vblank_def;
815
816 mutex_lock(&ov5695->mutex);
817
818 mode = ov5695_find_best_fit(fmt);
819 fmt->format.code = MEDIA_BUS_FMT_SBGGR10_1X10;
820 fmt->format.width = mode->width;
821 fmt->format.height = mode->height;
822 fmt->format.field = V4L2_FIELD_NONE;
823 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
824 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
825 *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
826 #else
827 mutex_unlock(&ov5695->mutex);
828 return -ENOTTY;
829 #endif
830 } else {
831 ov5695->cur_mode = mode;
832 h_blank = mode->hts_def - mode->width;
833 __v4l2_ctrl_modify_range(ov5695->hblank, h_blank,
834 h_blank, 1, h_blank);
835 vblank_def = mode->vts_def - mode->height;
836 __v4l2_ctrl_modify_range(ov5695->vblank, vblank_def,
837 OV5695_VTS_MAX - mode->height,
838 1, vblank_def);
839 }
840
841 mutex_unlock(&ov5695->mutex);
842
843 return 0;
844 }
845
ov5695_get_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)846 static int ov5695_get_fmt(struct v4l2_subdev *sd,
847 struct v4l2_subdev_pad_config *cfg,
848 struct v4l2_subdev_format *fmt)
849 {
850 struct ov5695 *ov5695 = to_ov5695(sd);
851 const struct ov5695_mode *mode = ov5695->cur_mode;
852
853 mutex_lock(&ov5695->mutex);
854 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
855 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
856 fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
857 #else
858 mutex_unlock(&ov5695->mutex);
859 return -ENOTTY;
860 #endif
861 } else {
862 fmt->format.width = mode->width;
863 fmt->format.height = mode->height;
864 fmt->format.code = MEDIA_BUS_FMT_SBGGR10_1X10;
865 fmt->format.field = V4L2_FIELD_NONE;
866 }
867 mutex_unlock(&ov5695->mutex);
868
869 return 0;
870 }
871
ov5695_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_mbus_code_enum * code)872 static int ov5695_enum_mbus_code(struct v4l2_subdev *sd,
873 struct v4l2_subdev_pad_config *cfg,
874 struct v4l2_subdev_mbus_code_enum *code)
875 {
876 if (code->index != 0)
877 return -EINVAL;
878 code->code = MEDIA_BUS_FMT_SBGGR10_1X10;
879
880 return 0;
881 }
882
ov5695_enum_frame_sizes(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_size_enum * fse)883 static int ov5695_enum_frame_sizes(struct v4l2_subdev *sd,
884 struct v4l2_subdev_pad_config *cfg,
885 struct v4l2_subdev_frame_size_enum *fse)
886 {
887 if (fse->index >= ARRAY_SIZE(supported_modes))
888 return -EINVAL;
889
890 if (fse->code != MEDIA_BUS_FMT_SBGGR10_1X10)
891 return -EINVAL;
892
893 fse->min_width = supported_modes[fse->index].width;
894 fse->max_width = supported_modes[fse->index].width;
895 fse->max_height = supported_modes[fse->index].height;
896 fse->min_height = supported_modes[fse->index].height;
897
898 return 0;
899 }
900
ov5695_enable_test_pattern(struct ov5695 * ov5695,u32 pattern)901 static int ov5695_enable_test_pattern(struct ov5695 *ov5695, u32 pattern)
902 {
903 u32 val;
904
905 if (pattern)
906 val = (pattern - 1) | OV5695_TEST_PATTERN_ENABLE;
907 else
908 val = OV5695_TEST_PATTERN_DISABLE;
909
910 return ov5695_write_reg(ov5695->client, OV5695_REG_TEST_PATTERN,
911 OV5695_REG_VALUE_08BIT, val);
912 }
913
__ov5695_start_stream(struct ov5695 * ov5695)914 static int __ov5695_start_stream(struct ov5695 *ov5695)
915 {
916 int ret;
917
918 ret = ov5695_write_array(ov5695->client, ov5695_global_regs);
919 if (ret)
920 return ret;
921 ret = ov5695_write_array(ov5695->client, ov5695->cur_mode->reg_list);
922 if (ret)
923 return ret;
924
925 /* In case these controls are set before streaming */
926 ret = __v4l2_ctrl_handler_setup(&ov5695->ctrl_handler);
927 if (ret)
928 return ret;
929
930 return ov5695_write_reg(ov5695->client, OV5695_REG_CTRL_MODE,
931 OV5695_REG_VALUE_08BIT, OV5695_MODE_STREAMING);
932 }
933
__ov5695_stop_stream(struct ov5695 * ov5695)934 static int __ov5695_stop_stream(struct ov5695 *ov5695)
935 {
936 return ov5695_write_reg(ov5695->client, OV5695_REG_CTRL_MODE,
937 OV5695_REG_VALUE_08BIT, OV5695_MODE_SW_STANDBY);
938 }
939
ov5695_s_stream(struct v4l2_subdev * sd,int on)940 static int ov5695_s_stream(struct v4l2_subdev *sd, int on)
941 {
942 struct ov5695 *ov5695 = to_ov5695(sd);
943 struct i2c_client *client = ov5695->client;
944 int ret = 0;
945
946 mutex_lock(&ov5695->mutex);
947 on = !!on;
948 if (on == ov5695->streaming)
949 goto unlock_and_return;
950
951 if (on) {
952 ret = pm_runtime_get_sync(&client->dev);
953 if (ret < 0) {
954 pm_runtime_put_noidle(&client->dev);
955 goto unlock_and_return;
956 }
957
958 ret = __ov5695_start_stream(ov5695);
959 if (ret) {
960 v4l2_err(sd, "start stream failed while write regs\n");
961 pm_runtime_put(&client->dev);
962 goto unlock_and_return;
963 }
964 } else {
965 __ov5695_stop_stream(ov5695);
966 pm_runtime_put(&client->dev);
967 }
968
969 ov5695->streaming = on;
970
971 unlock_and_return:
972 mutex_unlock(&ov5695->mutex);
973
974 return ret;
975 }
976
977 /* Calculate the delay in us by clock rate and clock cycles */
ov5695_cal_delay(u32 cycles)978 static inline u32 ov5695_cal_delay(u32 cycles)
979 {
980 return DIV_ROUND_UP(cycles, OV5695_XVCLK_FREQ / 1000 / 1000);
981 }
982
__ov5695_power_on(struct ov5695 * ov5695)983 static int __ov5695_power_on(struct ov5695 *ov5695)
984 {
985 int ret;
986 u32 delay_us;
987 struct device *dev = &ov5695->client->dev;
988
989 ret = clk_prepare_enable(ov5695->xvclk);
990 if (ret < 0) {
991 dev_err(dev, "Failed to enable xvclk\n");
992 return ret;
993 }
994
995 gpiod_set_value_cansleep(ov5695->reset_gpio, 1);
996
997 ret = regulator_bulk_enable(OV5695_NUM_SUPPLIES, ov5695->supplies);
998 if (ret < 0) {
999 dev_err(dev, "Failed to enable regulators\n");
1000 goto disable_clk;
1001 }
1002
1003 gpiod_set_value_cansleep(ov5695->reset_gpio, 0);
1004
1005 /* 8192 cycles prior to first SCCB transaction */
1006 delay_us = ov5695_cal_delay(8192);
1007 usleep_range(delay_us, delay_us * 2);
1008
1009 return 0;
1010
1011 disable_clk:
1012 clk_disable_unprepare(ov5695->xvclk);
1013
1014 return ret;
1015 }
1016
__ov5695_power_off(struct ov5695 * ov5695)1017 static void __ov5695_power_off(struct ov5695 *ov5695)
1018 {
1019 clk_disable_unprepare(ov5695->xvclk);
1020 gpiod_set_value_cansleep(ov5695->reset_gpio, 1);
1021 regulator_bulk_disable(OV5695_NUM_SUPPLIES, ov5695->supplies);
1022 }
1023
ov5695_runtime_resume(struct device * dev)1024 static int __maybe_unused ov5695_runtime_resume(struct device *dev)
1025 {
1026 struct i2c_client *client = to_i2c_client(dev);
1027 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1028 struct ov5695 *ov5695 = to_ov5695(sd);
1029
1030 return __ov5695_power_on(ov5695);
1031 }
1032
ov5695_runtime_suspend(struct device * dev)1033 static int __maybe_unused ov5695_runtime_suspend(struct device *dev)
1034 {
1035 struct i2c_client *client = to_i2c_client(dev);
1036 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1037 struct ov5695 *ov5695 = to_ov5695(sd);
1038
1039 __ov5695_power_off(ov5695);
1040
1041 return 0;
1042 }
1043
1044 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
ov5695_open(struct v4l2_subdev * sd,struct v4l2_subdev_fh * fh)1045 static int ov5695_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
1046 {
1047 struct ov5695 *ov5695 = to_ov5695(sd);
1048 struct v4l2_mbus_framefmt *try_fmt =
1049 v4l2_subdev_get_try_format(sd, fh->pad, 0);
1050 const struct ov5695_mode *def_mode = &supported_modes[0];
1051
1052 mutex_lock(&ov5695->mutex);
1053 /* Initialize try_fmt */
1054 try_fmt->width = def_mode->width;
1055 try_fmt->height = def_mode->height;
1056 try_fmt->code = MEDIA_BUS_FMT_SBGGR10_1X10;
1057 try_fmt->field = V4L2_FIELD_NONE;
1058
1059 mutex_unlock(&ov5695->mutex);
1060 /* No crop or compose */
1061
1062 return 0;
1063 }
1064 #endif
1065
1066 static const struct dev_pm_ops ov5695_pm_ops = {
1067 SET_RUNTIME_PM_OPS(ov5695_runtime_suspend,
1068 ov5695_runtime_resume, NULL)
1069 };
1070
1071 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1072 static const struct v4l2_subdev_internal_ops ov5695_internal_ops = {
1073 .open = ov5695_open,
1074 };
1075 #endif
1076
1077 static const struct v4l2_subdev_video_ops ov5695_video_ops = {
1078 .s_stream = ov5695_s_stream,
1079 };
1080
1081 static const struct v4l2_subdev_pad_ops ov5695_pad_ops = {
1082 .enum_mbus_code = ov5695_enum_mbus_code,
1083 .enum_frame_size = ov5695_enum_frame_sizes,
1084 .get_fmt = ov5695_get_fmt,
1085 .set_fmt = ov5695_set_fmt,
1086 };
1087
1088 static const struct v4l2_subdev_ops ov5695_subdev_ops = {
1089 .video = &ov5695_video_ops,
1090 .pad = &ov5695_pad_ops,
1091 };
1092
ov5695_set_ctrl(struct v4l2_ctrl * ctrl)1093 static int ov5695_set_ctrl(struct v4l2_ctrl *ctrl)
1094 {
1095 struct ov5695 *ov5695 = container_of(ctrl->handler,
1096 struct ov5695, ctrl_handler);
1097 struct i2c_client *client = ov5695->client;
1098 s64 max;
1099 int ret = 0;
1100
1101 /* Propagate change of current control to all related controls */
1102 switch (ctrl->id) {
1103 case V4L2_CID_VBLANK:
1104 /* Update max exposure while meeting expected vblanking */
1105 max = ov5695->cur_mode->height + ctrl->val - 4;
1106 __v4l2_ctrl_modify_range(ov5695->exposure,
1107 ov5695->exposure->minimum, max,
1108 ov5695->exposure->step,
1109 ov5695->exposure->default_value);
1110 break;
1111 }
1112
1113 if (pm_runtime_get_if_in_use(&client->dev) <= 0)
1114 return 0;
1115
1116 switch (ctrl->id) {
1117 case V4L2_CID_EXPOSURE:
1118 /* 4 least significant bits of expsoure are fractional part */
1119 ret = ov5695_write_reg(ov5695->client, OV5695_REG_EXPOSURE,
1120 OV5695_REG_VALUE_24BIT, ctrl->val << 4);
1121 break;
1122 case V4L2_CID_ANALOGUE_GAIN:
1123 ret = ov5695_write_reg(ov5695->client, OV5695_REG_ANALOG_GAIN,
1124 OV5695_REG_VALUE_08BIT, ctrl->val);
1125 break;
1126 case V4L2_CID_DIGITAL_GAIN:
1127 ret = ov5695_write_reg(ov5695->client, OV5695_REG_DIGI_GAIN_L,
1128 OV5695_REG_VALUE_08BIT,
1129 ctrl->val & OV5695_DIGI_GAIN_L_MASK);
1130 ret = ov5695_write_reg(ov5695->client, OV5695_REG_DIGI_GAIN_H,
1131 OV5695_REG_VALUE_08BIT,
1132 ctrl->val >> OV5695_DIGI_GAIN_H_SHIFT);
1133 break;
1134 case V4L2_CID_VBLANK:
1135 ret = ov5695_write_reg(ov5695->client, OV5695_REG_VTS,
1136 OV5695_REG_VALUE_16BIT,
1137 ctrl->val + ov5695->cur_mode->height);
1138 break;
1139 case V4L2_CID_TEST_PATTERN:
1140 ret = ov5695_enable_test_pattern(ov5695, ctrl->val);
1141 break;
1142 default:
1143 dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n",
1144 __func__, ctrl->id, ctrl->val);
1145 break;
1146 };
1147
1148 pm_runtime_put(&client->dev);
1149
1150 return ret;
1151 }
1152
1153 static const struct v4l2_ctrl_ops ov5695_ctrl_ops = {
1154 .s_ctrl = ov5695_set_ctrl,
1155 };
1156
ov5695_initialize_controls(struct ov5695 * ov5695)1157 static int ov5695_initialize_controls(struct ov5695 *ov5695)
1158 {
1159 const struct ov5695_mode *mode;
1160 struct v4l2_ctrl_handler *handler;
1161 struct v4l2_ctrl *ctrl;
1162 s64 exposure_max, vblank_def;
1163 u32 h_blank;
1164 int ret;
1165
1166 handler = &ov5695->ctrl_handler;
1167 mode = ov5695->cur_mode;
1168 ret = v4l2_ctrl_handler_init(handler, 8);
1169 if (ret)
1170 return ret;
1171 handler->lock = &ov5695->mutex;
1172
1173 ctrl = v4l2_ctrl_new_int_menu(handler, NULL, V4L2_CID_LINK_FREQ,
1174 0, 0, link_freq_menu_items);
1175 if (ctrl)
1176 ctrl->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1177
1178 v4l2_ctrl_new_std(handler, NULL, V4L2_CID_PIXEL_RATE,
1179 0, OV5695_PIXEL_RATE, 1, OV5695_PIXEL_RATE);
1180
1181 h_blank = mode->hts_def - mode->width;
1182 ov5695->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,
1183 h_blank, h_blank, 1, h_blank);
1184 if (ov5695->hblank)
1185 ov5695->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1186
1187 vblank_def = mode->vts_def - mode->height;
1188 ov5695->vblank = v4l2_ctrl_new_std(handler, &ov5695_ctrl_ops,
1189 V4L2_CID_VBLANK, vblank_def,
1190 OV5695_VTS_MAX - mode->height,
1191 1, vblank_def);
1192
1193 exposure_max = mode->vts_def - 4;
1194 ov5695->exposure = v4l2_ctrl_new_std(handler, &ov5695_ctrl_ops,
1195 V4L2_CID_EXPOSURE, OV5695_EXPOSURE_MIN,
1196 exposure_max, OV5695_EXPOSURE_STEP,
1197 mode->exp_def);
1198
1199 ov5695->anal_gain = v4l2_ctrl_new_std(handler, &ov5695_ctrl_ops,
1200 V4L2_CID_ANALOGUE_GAIN, ANALOG_GAIN_MIN,
1201 ANALOG_GAIN_MAX, ANALOG_GAIN_STEP,
1202 ANALOG_GAIN_DEFAULT);
1203
1204 /* Digital gain */
1205 ov5695->digi_gain = v4l2_ctrl_new_std(handler, &ov5695_ctrl_ops,
1206 V4L2_CID_DIGITAL_GAIN, OV5695_DIGI_GAIN_MIN,
1207 OV5695_DIGI_GAIN_MAX, OV5695_DIGI_GAIN_STEP,
1208 OV5695_DIGI_GAIN_DEFAULT);
1209
1210 ov5695->test_pattern = v4l2_ctrl_new_std_menu_items(handler,
1211 &ov5695_ctrl_ops, V4L2_CID_TEST_PATTERN,
1212 ARRAY_SIZE(ov5695_test_pattern_menu) - 1,
1213 0, 0, ov5695_test_pattern_menu);
1214
1215 if (handler->error) {
1216 ret = handler->error;
1217 dev_err(&ov5695->client->dev,
1218 "Failed to init controls(%d)\n", ret);
1219 goto err_free_handler;
1220 }
1221
1222 ov5695->subdev.ctrl_handler = handler;
1223
1224 return 0;
1225
1226 err_free_handler:
1227 v4l2_ctrl_handler_free(handler);
1228
1229 return ret;
1230 }
1231
ov5695_check_sensor_id(struct ov5695 * ov5695,struct i2c_client * client)1232 static int ov5695_check_sensor_id(struct ov5695 *ov5695,
1233 struct i2c_client *client)
1234 {
1235 struct device *dev = &ov5695->client->dev;
1236 u32 id = 0;
1237 int ret;
1238
1239 ret = ov5695_read_reg(client, OV5695_REG_CHIP_ID,
1240 OV5695_REG_VALUE_24BIT, &id);
1241 if (id != CHIP_ID) {
1242 dev_err(dev, "Unexpected sensor id(%06x), ret(%d)\n", id, ret);
1243 return ret;
1244 }
1245
1246 dev_info(dev, "Detected OV%06x sensor\n", CHIP_ID);
1247
1248 return 0;
1249 }
1250
ov5695_configure_regulators(struct ov5695 * ov5695)1251 static int ov5695_configure_regulators(struct ov5695 *ov5695)
1252 {
1253 int i;
1254
1255 for (i = 0; i < OV5695_NUM_SUPPLIES; i++)
1256 ov5695->supplies[i].supply = ov5695_supply_names[i];
1257
1258 return devm_regulator_bulk_get(&ov5695->client->dev,
1259 OV5695_NUM_SUPPLIES,
1260 ov5695->supplies);
1261 }
1262
ov5695_probe(struct i2c_client * client,const struct i2c_device_id * id)1263 static int ov5695_probe(struct i2c_client *client,
1264 const struct i2c_device_id *id)
1265 {
1266 struct device *dev = &client->dev;
1267 struct ov5695 *ov5695;
1268 struct v4l2_subdev *sd;
1269 int ret;
1270
1271 ov5695 = devm_kzalloc(dev, sizeof(*ov5695), GFP_KERNEL);
1272 if (!ov5695)
1273 return -ENOMEM;
1274
1275 ov5695->client = client;
1276 ov5695->cur_mode = &supported_modes[0];
1277
1278 ov5695->xvclk = devm_clk_get(dev, "xvclk");
1279 if (IS_ERR(ov5695->xvclk)) {
1280 dev_err(dev, "Failed to get xvclk\n");
1281 return -EINVAL;
1282 }
1283 ret = clk_set_rate(ov5695->xvclk, OV5695_XVCLK_FREQ);
1284 if (ret < 0) {
1285 dev_err(dev, "Failed to set xvclk rate (24MHz)\n");
1286 return ret;
1287 }
1288 if (clk_get_rate(ov5695->xvclk) != OV5695_XVCLK_FREQ)
1289 dev_warn(dev, "xvclk mismatched, modes are based on 24MHz\n");
1290
1291 ov5695->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
1292 if (IS_ERR(ov5695->reset_gpio)) {
1293 dev_err(dev, "Failed to get reset-gpios\n");
1294 return -EINVAL;
1295 }
1296
1297 ret = ov5695_configure_regulators(ov5695);
1298 if (ret) {
1299 dev_err(dev, "Failed to get power regulators\n");
1300 return ret;
1301 }
1302
1303 mutex_init(&ov5695->mutex);
1304
1305 sd = &ov5695->subdev;
1306 v4l2_i2c_subdev_init(sd, client, &ov5695_subdev_ops);
1307 ret = ov5695_initialize_controls(ov5695);
1308 if (ret)
1309 goto err_destroy_mutex;
1310
1311 ret = __ov5695_power_on(ov5695);
1312 if (ret)
1313 goto err_free_handler;
1314
1315 ret = ov5695_check_sensor_id(ov5695, client);
1316 if (ret)
1317 goto err_power_off;
1318
1319 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1320 sd->internal_ops = &ov5695_internal_ops;
1321 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1322 #endif
1323 #if defined(CONFIG_MEDIA_CONTROLLER)
1324 ov5695->pad.flags = MEDIA_PAD_FL_SOURCE;
1325 sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
1326 ret = media_entity_pads_init(&sd->entity, 1, &ov5695->pad);
1327 if (ret < 0)
1328 goto err_power_off;
1329 #endif
1330
1331 ret = v4l2_async_register_subdev(sd);
1332 if (ret) {
1333 dev_err(dev, "v4l2 async register subdev failed\n");
1334 goto err_clean_entity;
1335 }
1336
1337 pm_runtime_set_active(dev);
1338 pm_runtime_enable(dev);
1339 pm_runtime_idle(dev);
1340
1341 return 0;
1342
1343 err_clean_entity:
1344 #if defined(CONFIG_MEDIA_CONTROLLER)
1345 media_entity_cleanup(&sd->entity);
1346 #endif
1347 err_power_off:
1348 __ov5695_power_off(ov5695);
1349 err_free_handler:
1350 v4l2_ctrl_handler_free(&ov5695->ctrl_handler);
1351 err_destroy_mutex:
1352 mutex_destroy(&ov5695->mutex);
1353
1354 return ret;
1355 }
1356
ov5695_remove(struct i2c_client * client)1357 static int ov5695_remove(struct i2c_client *client)
1358 {
1359 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1360 struct ov5695 *ov5695 = to_ov5695(sd);
1361
1362 v4l2_async_unregister_subdev(sd);
1363 #if defined(CONFIG_MEDIA_CONTROLLER)
1364 media_entity_cleanup(&sd->entity);
1365 #endif
1366 v4l2_ctrl_handler_free(&ov5695->ctrl_handler);
1367 mutex_destroy(&ov5695->mutex);
1368
1369 pm_runtime_disable(&client->dev);
1370 if (!pm_runtime_status_suspended(&client->dev))
1371 __ov5695_power_off(ov5695);
1372 pm_runtime_set_suspended(&client->dev);
1373
1374 return 0;
1375 }
1376
1377 #if IS_ENABLED(CONFIG_OF)
1378 static const struct of_device_id ov5695_of_match[] = {
1379 { .compatible = "ovti,ov5695" },
1380 {},
1381 };
1382 MODULE_DEVICE_TABLE(of, ov5695_of_match);
1383 #endif
1384
1385 static struct i2c_driver ov5695_i2c_driver = {
1386 .driver = {
1387 .name = "ov5695",
1388 .pm = &ov5695_pm_ops,
1389 .of_match_table = of_match_ptr(ov5695_of_match),
1390 },
1391 .probe = &ov5695_probe,
1392 .remove = &ov5695_remove,
1393 };
1394
1395 module_i2c_driver(ov5695_i2c_driver);
1396
1397 MODULE_DESCRIPTION("OmniVision ov5695 sensor driver");
1398 MODULE_LICENSE("GPL v2");
1399
