1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2021 Intel Corporation.
3
4 #include <linux/acpi.h>
5 #include <linux/i2c.h>
6 #include <linux/module.h>
7 #include <linux/pm_runtime.h>
8 #include <media/v4l2-ctrls.h>
9 #include <media/v4l2-device.h>
10 #include <media/v4l2-fwnode.h>
11
12 #define OV13B10_REG_VALUE_08BIT 1
13 #define OV13B10_REG_VALUE_16BIT 2
14 #define OV13B10_REG_VALUE_24BIT 3
15
16 #define OV13B10_REG_MODE_SELECT 0x0100
17 #define OV13B10_MODE_STANDBY 0x00
18 #define OV13B10_MODE_STREAMING 0x01
19
20 #define OV13B10_REG_SOFTWARE_RST 0x0103
21 #define OV13B10_SOFTWARE_RST 0x01
22
23 /* Chip ID */
24 #define OV13B10_REG_CHIP_ID 0x300a
25 #define OV13B10_CHIP_ID 0x560d42
26
27 /* V_TIMING internal */
28 #define OV13B10_REG_VTS 0x380e
29 #define OV13B10_VTS_30FPS 0x0c7c
30 #define OV13B10_VTS_60FPS 0x063e
31 #define OV13B10_VTS_MAX 0x7fff
32
33 /* HBLANK control - read only */
34 #define OV13B10_PPL_560MHZ 4704
35
36 /* Exposure control */
37 #define OV13B10_REG_EXPOSURE 0x3500
38 #define OV13B10_EXPOSURE_MIN 4
39 #define OV13B10_EXPOSURE_STEP 1
40 #define OV13B10_EXPOSURE_DEFAULT 0x40
41
42 /* Analog gain control */
43 #define OV13B10_REG_ANALOG_GAIN 0x3508
44 #define OV13B10_ANA_GAIN_MIN 0x80
45 #define OV13B10_ANA_GAIN_MAX 0x07c0
46 #define OV13B10_ANA_GAIN_STEP 1
47 #define OV13B10_ANA_GAIN_DEFAULT 0x80
48
49 /* Digital gain control */
50 #define OV13B10_REG_DGTL_GAIN_H 0x350a
51 #define OV13B10_REG_DGTL_GAIN_M 0x350b
52 #define OV13B10_REG_DGTL_GAIN_L 0x350c
53
54 #define OV13B10_DGTL_GAIN_MIN 1024 /* Min = 1 X */
55 #define OV13B10_DGTL_GAIN_MAX (4096 - 1) /* Max = 4 X */
56 #define OV13B10_DGTL_GAIN_DEFAULT 2560 /* Default gain = 2.5 X */
57 #define OV13B10_DGTL_GAIN_STEP 1 /* Each step = 1/1024 */
58
59 #define OV13B10_DGTL_GAIN_L_SHIFT 6
60 #define OV13B10_DGTL_GAIN_L_MASK 0x3
61 #define OV13B10_DGTL_GAIN_M_SHIFT 2
62 #define OV13B10_DGTL_GAIN_M_MASK 0xff
63 #define OV13B10_DGTL_GAIN_H_SHIFT 10
64 #define OV13B10_DGTL_GAIN_H_MASK 0x3
65
66 /* Test Pattern Control */
67 #define OV13B10_REG_TEST_PATTERN 0x5080
68 #define OV13B10_TEST_PATTERN_ENABLE BIT(7)
69 #define OV13B10_TEST_PATTERN_MASK 0xf3
70 #define OV13B10_TEST_PATTERN_BAR_SHIFT 2
71
72 /* Flip Control */
73 #define OV13B10_REG_FORMAT1 0x3820
74 #define OV13B10_REG_FORMAT2 0x3821
75
76 /* Horizontal Window Offset */
77 #define OV13B10_REG_H_WIN_OFFSET 0x3811
78
79 /* Vertical Window Offset */
80 #define OV13B10_REG_V_WIN_OFFSET 0x3813
81
82 struct ov13b10_reg {
83 u16 address;
84 u8 val;
85 };
86
87 struct ov13b10_reg_list {
88 u32 num_of_regs;
89 const struct ov13b10_reg *regs;
90 };
91
92 /* Link frequency config */
93 struct ov13b10_link_freq_config {
94 u32 pixels_per_line;
95
96 /* registers for this link frequency */
97 struct ov13b10_reg_list reg_list;
98 };
99
100 /* Mode : resolution and related config&values */
101 struct ov13b10_mode {
102 /* Frame width */
103 u32 width;
104 /* Frame height */
105 u32 height;
106
107 /* V-timing */
108 u32 vts_def;
109 u32 vts_min;
110
111 /* Index of Link frequency config to be used */
112 u32 link_freq_index;
113 /* Default register values */
114 struct ov13b10_reg_list reg_list;
115 };
116
117 /* 4208x3120 needs 1120Mbps/lane, 4 lanes */
118 static const struct ov13b10_reg mipi_data_rate_1120mbps[] = {
119 {0x0103, 0x01},
120 {0x0303, 0x04},
121 {0x0305, 0xaf},
122 {0x0321, 0x00},
123 {0x0323, 0x04},
124 {0x0324, 0x01},
125 {0x0325, 0xa4},
126 {0x0326, 0x81},
127 {0x0327, 0x04},
128 {0x3012, 0x07},
129 {0x3013, 0x32},
130 {0x3107, 0x23},
131 {0x3501, 0x0c},
132 {0x3502, 0x10},
133 {0x3504, 0x08},
134 {0x3508, 0x07},
135 {0x3509, 0xc0},
136 {0x3600, 0x16},
137 {0x3601, 0x54},
138 {0x3612, 0x4e},
139 {0x3620, 0x00},
140 {0x3621, 0x68},
141 {0x3622, 0x66},
142 {0x3623, 0x03},
143 {0x3662, 0x92},
144 {0x3666, 0xbb},
145 {0x3667, 0x44},
146 {0x366e, 0xff},
147 {0x366f, 0xf3},
148 {0x3675, 0x44},
149 {0x3676, 0x00},
150 {0x367f, 0xe9},
151 {0x3681, 0x32},
152 {0x3682, 0x1f},
153 {0x3683, 0x0b},
154 {0x3684, 0x0b},
155 {0x3704, 0x0f},
156 {0x3706, 0x40},
157 {0x3708, 0x3b},
158 {0x3709, 0x72},
159 {0x370b, 0xa2},
160 {0x3714, 0x24},
161 {0x371a, 0x3e},
162 {0x3725, 0x42},
163 {0x3739, 0x12},
164 {0x3767, 0x00},
165 {0x377a, 0x0d},
166 {0x3789, 0x18},
167 {0x3790, 0x40},
168 {0x3791, 0xa2},
169 {0x37c2, 0x04},
170 {0x37c3, 0xf1},
171 {0x37d9, 0x0c},
172 {0x37da, 0x02},
173 {0x37dc, 0x02},
174 {0x37e1, 0x04},
175 {0x37e2, 0x0a},
176 {0x3800, 0x00},
177 {0x3801, 0x00},
178 {0x3802, 0x00},
179 {0x3803, 0x08},
180 {0x3804, 0x10},
181 {0x3805, 0x8f},
182 {0x3806, 0x0c},
183 {0x3807, 0x47},
184 {0x3808, 0x10},
185 {0x3809, 0x70},
186 {0x380a, 0x0c},
187 {0x380b, 0x30},
188 {0x380c, 0x04},
189 {0x380d, 0x98},
190 {0x380e, 0x0c},
191 {0x380f, 0x7c},
192 {0x3811, 0x0f},
193 {0x3813, 0x09},
194 {0x3814, 0x01},
195 {0x3815, 0x01},
196 {0x3816, 0x01},
197 {0x3817, 0x01},
198 {0x381f, 0x08},
199 {0x3820, 0x88},
200 {0x3821, 0x00},
201 {0x3822, 0x14},
202 {0x382e, 0xe6},
203 {0x3c80, 0x00},
204 {0x3c87, 0x01},
205 {0x3c8c, 0x19},
206 {0x3c8d, 0x1c},
207 {0x3ca0, 0x00},
208 {0x3ca1, 0x00},
209 {0x3ca2, 0x00},
210 {0x3ca3, 0x00},
211 {0x3ca4, 0x50},
212 {0x3ca5, 0x11},
213 {0x3ca6, 0x01},
214 {0x3ca7, 0x00},
215 {0x3ca8, 0x00},
216 {0x4008, 0x02},
217 {0x4009, 0x0f},
218 {0x400a, 0x01},
219 {0x400b, 0x19},
220 {0x4011, 0x21},
221 {0x4017, 0x08},
222 {0x4019, 0x04},
223 {0x401a, 0x58},
224 {0x4032, 0x1e},
225 {0x4050, 0x02},
226 {0x4051, 0x09},
227 {0x405e, 0x00},
228 {0x4066, 0x02},
229 {0x4501, 0x00},
230 {0x4502, 0x10},
231 {0x4505, 0x00},
232 {0x4800, 0x64},
233 {0x481b, 0x3e},
234 {0x481f, 0x30},
235 {0x4825, 0x34},
236 {0x4837, 0x0e},
237 {0x484b, 0x01},
238 {0x4883, 0x02},
239 {0x5000, 0xff},
240 {0x5001, 0x0f},
241 {0x5045, 0x20},
242 {0x5046, 0x20},
243 {0x5047, 0xa4},
244 {0x5048, 0x20},
245 {0x5049, 0xa4},
246 {0x0100, 0x01},
247 };
248
249 static const struct ov13b10_reg mode_4208x3120_regs[] = {
250 {0x0305, 0xaf},
251 {0x3501, 0x0c},
252 {0x3662, 0x92},
253 {0x3714, 0x24},
254 {0x3739, 0x12},
255 {0x37c2, 0x04},
256 {0x37d9, 0x0c},
257 {0x37e2, 0x0a},
258 {0x3800, 0x00},
259 {0x3801, 0x00},
260 {0x3802, 0x00},
261 {0x3803, 0x08},
262 {0x3804, 0x10},
263 {0x3805, 0x8f},
264 {0x3806, 0x0c},
265 {0x3807, 0x47},
266 {0x3808, 0x10},
267 {0x3809, 0x70},
268 {0x380a, 0x0c},
269 {0x380b, 0x30},
270 {0x380c, 0x04},
271 {0x380d, 0x98},
272 {0x380e, 0x0c},
273 {0x380f, 0x7c},
274 {0x3810, 0x00},
275 {0x3811, 0x0f},
276 {0x3812, 0x00},
277 {0x3813, 0x09},
278 {0x3814, 0x01},
279 {0x3816, 0x01},
280 {0x3820, 0x88},
281 {0x3c8c, 0x19},
282 {0x4008, 0x02},
283 {0x4009, 0x0f},
284 {0x4050, 0x02},
285 {0x4051, 0x09},
286 {0x4501, 0x00},
287 {0x4505, 0x00},
288 {0x4837, 0x0e},
289 {0x5000, 0xff},
290 {0x5001, 0x0f},
291 };
292
293 static const struct ov13b10_reg mode_4160x3120_regs[] = {
294 {0x0305, 0xaf},
295 {0x3501, 0x0c},
296 {0x3662, 0x92},
297 {0x3714, 0x24},
298 {0x3739, 0x12},
299 {0x37c2, 0x04},
300 {0x37d9, 0x0c},
301 {0x37e2, 0x0a},
302 {0x3800, 0x00},
303 {0x3801, 0x00},
304 {0x3802, 0x00},
305 {0x3803, 0x08},
306 {0x3804, 0x10},
307 {0x3805, 0x8f},
308 {0x3806, 0x0c},
309 {0x3807, 0x47},
310 {0x3808, 0x10},
311 {0x3809, 0x40},
312 {0x380a, 0x0c},
313 {0x380b, 0x30},
314 {0x380c, 0x04},
315 {0x380d, 0x98},
316 {0x380e, 0x0c},
317 {0x380f, 0x7c},
318 {0x3810, 0x00},
319 {0x3811, 0x27},
320 {0x3812, 0x00},
321 {0x3813, 0x09},
322 {0x3814, 0x01},
323 {0x3816, 0x01},
324 {0x3820, 0x88},
325 {0x3c8c, 0x19},
326 {0x4008, 0x02},
327 {0x4009, 0x0f},
328 {0x4050, 0x02},
329 {0x4051, 0x09},
330 {0x4501, 0x00},
331 {0x4505, 0x00},
332 {0x4837, 0x0e},
333 {0x5000, 0xff},
334 {0x5001, 0x0f},
335 };
336
337 static const struct ov13b10_reg mode_4160x2340_regs[] = {
338 {0x0305, 0xaf},
339 {0x3501, 0x0c},
340 {0x3662, 0x92},
341 {0x3714, 0x24},
342 {0x3739, 0x12},
343 {0x37c2, 0x04},
344 {0x37d9, 0x0c},
345 {0x37e2, 0x0a},
346 {0x3800, 0x00},
347 {0x3801, 0x00},
348 {0x3802, 0x00},
349 {0x3803, 0x08},
350 {0x3804, 0x10},
351 {0x3805, 0x8f},
352 {0x3806, 0x0c},
353 {0x3807, 0x47},
354 {0x3808, 0x10},
355 {0x3809, 0x40},
356 {0x380a, 0x09},
357 {0x380b, 0x24},
358 {0x380c, 0x04},
359 {0x380d, 0x98},
360 {0x380e, 0x0c},
361 {0x380f, 0x7c},
362 {0x3810, 0x00},
363 {0x3811, 0x27},
364 {0x3812, 0x01},
365 {0x3813, 0x8f},
366 {0x3814, 0x01},
367 {0x3816, 0x01},
368 {0x3820, 0x88},
369 {0x3c8c, 0x19},
370 {0x4008, 0x02},
371 {0x4009, 0x0f},
372 {0x4050, 0x02},
373 {0x4051, 0x09},
374 {0x4501, 0x00},
375 {0x4505, 0x00},
376 {0x4837, 0x0e},
377 {0x5000, 0xff},
378 {0x5001, 0x0f},
379 };
380
381 static const struct ov13b10_reg mode_2104x1560_regs[] = {
382 {0x0305, 0xaf},
383 {0x3501, 0x06},
384 {0x3662, 0x88},
385 {0x3714, 0x28},
386 {0x3739, 0x10},
387 {0x37c2, 0x14},
388 {0x37d9, 0x06},
389 {0x37e2, 0x0c},
390 {0x3800, 0x00},
391 {0x3801, 0x00},
392 {0x3802, 0x00},
393 {0x3803, 0x08},
394 {0x3804, 0x10},
395 {0x3805, 0x8f},
396 {0x3806, 0x0c},
397 {0x3807, 0x47},
398 {0x3808, 0x08},
399 {0x3809, 0x38},
400 {0x380a, 0x06},
401 {0x380b, 0x18},
402 {0x380c, 0x04},
403 {0x380d, 0x98},
404 {0x380e, 0x06},
405 {0x380f, 0x3e},
406 {0x3810, 0x00},
407 {0x3811, 0x07},
408 {0x3812, 0x00},
409 {0x3813, 0x05},
410 {0x3814, 0x03},
411 {0x3816, 0x03},
412 {0x3820, 0x8b},
413 {0x3c8c, 0x18},
414 {0x4008, 0x00},
415 {0x4009, 0x05},
416 {0x4050, 0x00},
417 {0x4051, 0x05},
418 {0x4501, 0x08},
419 {0x4505, 0x00},
420 {0x4837, 0x0e},
421 {0x5000, 0xfd},
422 {0x5001, 0x0d},
423 };
424
425 static const struct ov13b10_reg mode_2080x1170_regs[] = {
426 {0x0305, 0xaf},
427 {0x3501, 0x06},
428 {0x3662, 0x88},
429 {0x3714, 0x28},
430 {0x3739, 0x10},
431 {0x37c2, 0x14},
432 {0x37d9, 0x06},
433 {0x37e2, 0x0c},
434 {0x3800, 0x00},
435 {0x3801, 0x00},
436 {0x3802, 0x00},
437 {0x3803, 0x08},
438 {0x3804, 0x10},
439 {0x3805, 0x8f},
440 {0x3806, 0x0c},
441 {0x3807, 0x47},
442 {0x3808, 0x08},
443 {0x3809, 0x20},
444 {0x380a, 0x04},
445 {0x380b, 0x92},
446 {0x380c, 0x04},
447 {0x380d, 0x98},
448 {0x380e, 0x06},
449 {0x380f, 0x3e},
450 {0x3810, 0x00},
451 {0x3811, 0x13},
452 {0x3812, 0x00},
453 {0x3813, 0xc9},
454 {0x3814, 0x03},
455 {0x3816, 0x03},
456 {0x3820, 0x8b},
457 {0x3c8c, 0x18},
458 {0x4008, 0x00},
459 {0x4009, 0x05},
460 {0x4050, 0x00},
461 {0x4051, 0x05},
462 {0x4501, 0x08},
463 {0x4505, 0x00},
464 {0x4837, 0x0e},
465 {0x5000, 0xfd},
466 {0x5001, 0x0d},
467 };
468
469 static const char * const ov13b10_test_pattern_menu[] = {
470 "Disabled",
471 "Vertical Color Bar Type 1",
472 "Vertical Color Bar Type 2",
473 "Vertical Color Bar Type 3",
474 "Vertical Color Bar Type 4"
475 };
476
477 /* Configurations for supported link frequencies */
478 #define OV13B10_LINK_FREQ_560MHZ 560000000ULL
479 #define OV13B10_LINK_FREQ_INDEX_0 0
480
481 #define OV13B10_EXT_CLK 19200000
482 #define OV13B10_DATA_LANES 4
483
484 /*
485 * pixel_rate = link_freq * data-rate * nr_of_lanes / bits_per_sample
486 * data rate => double data rate; number of lanes => 4; bits per pixel => 10
487 */
link_freq_to_pixel_rate(u64 f)488 static u64 link_freq_to_pixel_rate(u64 f)
489 {
490 f *= 2 * OV13B10_DATA_LANES;
491 do_div(f, 10);
492
493 return f;
494 }
495
496 /* Menu items for LINK_FREQ V4L2 control */
497 static const s64 link_freq_menu_items[] = {
498 OV13B10_LINK_FREQ_560MHZ
499 };
500
501 /* Link frequency configs */
502 static const struct ov13b10_link_freq_config
503 link_freq_configs[] = {
504 {
505 .pixels_per_line = OV13B10_PPL_560MHZ,
506 .reg_list = {
507 .num_of_regs = ARRAY_SIZE(mipi_data_rate_1120mbps),
508 .regs = mipi_data_rate_1120mbps,
509 }
510 }
511 };
512
513 /* Mode configs */
514 static const struct ov13b10_mode supported_modes[] = {
515 {
516 .width = 4208,
517 .height = 3120,
518 .vts_def = OV13B10_VTS_30FPS,
519 .vts_min = OV13B10_VTS_30FPS,
520 .reg_list = {
521 .num_of_regs = ARRAY_SIZE(mode_4208x3120_regs),
522 .regs = mode_4208x3120_regs,
523 },
524 .link_freq_index = OV13B10_LINK_FREQ_INDEX_0,
525 },
526 {
527 .width = 4160,
528 .height = 3120,
529 .vts_def = OV13B10_VTS_30FPS,
530 .vts_min = OV13B10_VTS_30FPS,
531 .reg_list = {
532 .num_of_regs = ARRAY_SIZE(mode_4160x3120_regs),
533 .regs = mode_4160x3120_regs,
534 },
535 .link_freq_index = OV13B10_LINK_FREQ_INDEX_0,
536 },
537 {
538 .width = 4160,
539 .height = 2340,
540 .vts_def = OV13B10_VTS_30FPS,
541 .vts_min = OV13B10_VTS_30FPS,
542 .reg_list = {
543 .num_of_regs = ARRAY_SIZE(mode_4160x2340_regs),
544 .regs = mode_4160x2340_regs,
545 },
546 .link_freq_index = OV13B10_LINK_FREQ_INDEX_0,
547 },
548 {
549 .width = 2104,
550 .height = 1560,
551 .vts_def = OV13B10_VTS_60FPS,
552 .vts_min = OV13B10_VTS_60FPS,
553 .reg_list = {
554 .num_of_regs = ARRAY_SIZE(mode_2104x1560_regs),
555 .regs = mode_2104x1560_regs,
556 },
557 .link_freq_index = OV13B10_LINK_FREQ_INDEX_0,
558 },
559 {
560 .width = 2080,
561 .height = 1170,
562 .vts_def = OV13B10_VTS_60FPS,
563 .vts_min = OV13B10_VTS_60FPS,
564 .reg_list = {
565 .num_of_regs = ARRAY_SIZE(mode_2080x1170_regs),
566 .regs = mode_2080x1170_regs,
567 },
568 .link_freq_index = OV13B10_LINK_FREQ_INDEX_0,
569 }
570 };
571
572 struct ov13b10 {
573 struct v4l2_subdev sd;
574 struct media_pad pad;
575
576 struct v4l2_ctrl_handler ctrl_handler;
577 /* V4L2 Controls */
578 struct v4l2_ctrl *link_freq;
579 struct v4l2_ctrl *pixel_rate;
580 struct v4l2_ctrl *vblank;
581 struct v4l2_ctrl *hblank;
582 struct v4l2_ctrl *exposure;
583
584 /* Current mode */
585 const struct ov13b10_mode *cur_mode;
586
587 /* Mutex for serialized access */
588 struct mutex mutex;
589
590 /* Streaming on/off */
591 bool streaming;
592 };
593
594 #define to_ov13b10(_sd) container_of(_sd, struct ov13b10, sd)
595
596 /* Read registers up to 4 at a time */
ov13b10_read_reg(struct ov13b10 * ov13b,u16 reg,u32 len,u32 * val)597 static int ov13b10_read_reg(struct ov13b10 *ov13b,
598 u16 reg, u32 len, u32 *val)
599 {
600 struct i2c_client *client = v4l2_get_subdevdata(&ov13b->sd);
601 struct i2c_msg msgs[2];
602 u8 *data_be_p;
603 int ret;
604 __be32 data_be = 0;
605 __be16 reg_addr_be = cpu_to_be16(reg);
606
607 if (len > 4)
608 return -EINVAL;
609
610 data_be_p = (u8 *)&data_be;
611 /* Write register address */
612 msgs[0].addr = client->addr;
613 msgs[0].flags = 0;
614 msgs[0].len = 2;
615 msgs[0].buf = (u8 *)®_addr_be;
616
617 /* Read data from register */
618 msgs[1].addr = client->addr;
619 msgs[1].flags = I2C_M_RD;
620 msgs[1].len = len;
621 msgs[1].buf = &data_be_p[4 - len];
622
623 ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
624 if (ret != ARRAY_SIZE(msgs))
625 return -EIO;
626
627 *val = be32_to_cpu(data_be);
628
629 return 0;
630 }
631
632 /* Write registers up to 4 at a time */
ov13b10_write_reg(struct ov13b10 * ov13b,u16 reg,u32 len,u32 __val)633 static int ov13b10_write_reg(struct ov13b10 *ov13b,
634 u16 reg, u32 len, u32 __val)
635 {
636 struct i2c_client *client = v4l2_get_subdevdata(&ov13b->sd);
637 int buf_i, val_i;
638 u8 buf[6], *val_p;
639 __be32 val;
640
641 if (len > 4)
642 return -EINVAL;
643
644 buf[0] = reg >> 8;
645 buf[1] = reg & 0xff;
646
647 val = cpu_to_be32(__val);
648 val_p = (u8 *)&val;
649 buf_i = 2;
650 val_i = 4 - len;
651
652 while (val_i < 4)
653 buf[buf_i++] = val_p[val_i++];
654
655 if (i2c_master_send(client, buf, len + 2) != len + 2)
656 return -EIO;
657
658 return 0;
659 }
660
661 /* Write a list of registers */
ov13b10_write_regs(struct ov13b10 * ov13b,const struct ov13b10_reg * regs,u32 len)662 static int ov13b10_write_regs(struct ov13b10 *ov13b,
663 const struct ov13b10_reg *regs, u32 len)
664 {
665 struct i2c_client *client = v4l2_get_subdevdata(&ov13b->sd);
666 int ret;
667 u32 i;
668
669 for (i = 0; i < len; i++) {
670 ret = ov13b10_write_reg(ov13b, regs[i].address, 1,
671 regs[i].val);
672 if (ret) {
673 dev_err_ratelimited(&client->dev,
674 "Failed to write reg 0x%4.4x. error = %d\n",
675 regs[i].address, ret);
676
677 return ret;
678 }
679 }
680
681 return 0;
682 }
683
ov13b10_write_reg_list(struct ov13b10 * ov13b,const struct ov13b10_reg_list * r_list)684 static int ov13b10_write_reg_list(struct ov13b10 *ov13b,
685 const struct ov13b10_reg_list *r_list)
686 {
687 return ov13b10_write_regs(ov13b, r_list->regs, r_list->num_of_regs);
688 }
689
690 /* Open sub-device */
ov13b10_open(struct v4l2_subdev * sd,struct v4l2_subdev_fh * fh)691 static int ov13b10_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
692 {
693 const struct ov13b10_mode *default_mode = &supported_modes[0];
694 struct ov13b10 *ov13b = to_ov13b10(sd);
695 struct v4l2_mbus_framefmt *try_fmt = v4l2_subdev_get_try_format(sd,
696 fh->state,
697 0);
698
699 mutex_lock(&ov13b->mutex);
700
701 /* Initialize try_fmt */
702 try_fmt->width = default_mode->width;
703 try_fmt->height = default_mode->height;
704 try_fmt->code = MEDIA_BUS_FMT_SGRBG10_1X10;
705 try_fmt->field = V4L2_FIELD_NONE;
706
707 /* No crop or compose */
708 mutex_unlock(&ov13b->mutex);
709
710 return 0;
711 }
712
ov13b10_update_digital_gain(struct ov13b10 * ov13b,u32 d_gain)713 static int ov13b10_update_digital_gain(struct ov13b10 *ov13b, u32 d_gain)
714 {
715 int ret;
716 u32 val;
717
718 /*
719 * 0x350C[7:6], 0x350B[7:0], 0x350A[1:0]
720 */
721
722 val = (d_gain & OV13B10_DGTL_GAIN_L_MASK) << OV13B10_DGTL_GAIN_L_SHIFT;
723 ret = ov13b10_write_reg(ov13b, OV13B10_REG_DGTL_GAIN_L,
724 OV13B10_REG_VALUE_08BIT, val);
725 if (ret)
726 return ret;
727
728 val = (d_gain >> OV13B10_DGTL_GAIN_M_SHIFT) & OV13B10_DGTL_GAIN_M_MASK;
729 ret = ov13b10_write_reg(ov13b, OV13B10_REG_DGTL_GAIN_M,
730 OV13B10_REG_VALUE_08BIT, val);
731 if (ret)
732 return ret;
733
734 val = (d_gain >> OV13B10_DGTL_GAIN_H_SHIFT) & OV13B10_DGTL_GAIN_H_MASK;
735 ret = ov13b10_write_reg(ov13b, OV13B10_REG_DGTL_GAIN_H,
736 OV13B10_REG_VALUE_08BIT, val);
737
738 return ret;
739 }
740
ov13b10_enable_test_pattern(struct ov13b10 * ov13b,u32 pattern)741 static int ov13b10_enable_test_pattern(struct ov13b10 *ov13b, u32 pattern)
742 {
743 int ret;
744 u32 val;
745
746 ret = ov13b10_read_reg(ov13b, OV13B10_REG_TEST_PATTERN,
747 OV13B10_REG_VALUE_08BIT, &val);
748 if (ret)
749 return ret;
750
751 if (pattern) {
752 val &= OV13B10_TEST_PATTERN_MASK;
753 val |= ((pattern - 1) << OV13B10_TEST_PATTERN_BAR_SHIFT) |
754 OV13B10_TEST_PATTERN_ENABLE;
755 } else {
756 val &= ~OV13B10_TEST_PATTERN_ENABLE;
757 }
758
759 return ov13b10_write_reg(ov13b, OV13B10_REG_TEST_PATTERN,
760 OV13B10_REG_VALUE_08BIT, val);
761 }
762
ov13b10_set_ctrl_hflip(struct ov13b10 * ov13b,u32 ctrl_val)763 static int ov13b10_set_ctrl_hflip(struct ov13b10 *ov13b, u32 ctrl_val)
764 {
765 int ret;
766 u32 val;
767
768 ret = ov13b10_read_reg(ov13b, OV13B10_REG_FORMAT1,
769 OV13B10_REG_VALUE_08BIT, &val);
770 if (ret)
771 return ret;
772
773 ret = ov13b10_write_reg(ov13b, OV13B10_REG_FORMAT1,
774 OV13B10_REG_VALUE_08BIT,
775 ctrl_val ? val & ~BIT(3) : val);
776
777 if (ret)
778 return ret;
779
780 ret = ov13b10_read_reg(ov13b, OV13B10_REG_H_WIN_OFFSET,
781 OV13B10_REG_VALUE_08BIT, &val);
782 if (ret)
783 return ret;
784
785 /*
786 * Applying cropping offset to reverse the change of Bayer order
787 * after mirroring image
788 */
789 return ov13b10_write_reg(ov13b, OV13B10_REG_H_WIN_OFFSET,
790 OV13B10_REG_VALUE_08BIT,
791 ctrl_val ? ++val : val);
792 }
793
ov13b10_set_ctrl_vflip(struct ov13b10 * ov13b,u32 ctrl_val)794 static int ov13b10_set_ctrl_vflip(struct ov13b10 *ov13b, u32 ctrl_val)
795 {
796 int ret;
797 u32 val;
798
799 ret = ov13b10_read_reg(ov13b, OV13B10_REG_FORMAT1,
800 OV13B10_REG_VALUE_08BIT, &val);
801 if (ret)
802 return ret;
803
804 ret = ov13b10_write_reg(ov13b, OV13B10_REG_FORMAT1,
805 OV13B10_REG_VALUE_08BIT,
806 ctrl_val ? val | BIT(4) | BIT(5) : val);
807
808 if (ret)
809 return ret;
810
811 ret = ov13b10_read_reg(ov13b, OV13B10_REG_V_WIN_OFFSET,
812 OV13B10_REG_VALUE_08BIT, &val);
813 if (ret)
814 return ret;
815
816 /*
817 * Applying cropping offset to reverse the change of Bayer order
818 * after flipping image
819 */
820 return ov13b10_write_reg(ov13b, OV13B10_REG_V_WIN_OFFSET,
821 OV13B10_REG_VALUE_08BIT,
822 ctrl_val ? --val : val);
823 }
824
ov13b10_set_ctrl(struct v4l2_ctrl * ctrl)825 static int ov13b10_set_ctrl(struct v4l2_ctrl *ctrl)
826 {
827 struct ov13b10 *ov13b = container_of(ctrl->handler,
828 struct ov13b10, ctrl_handler);
829 struct i2c_client *client = v4l2_get_subdevdata(&ov13b->sd);
830 s64 max;
831 int ret;
832
833 /* Propagate change of current control to all related controls */
834 switch (ctrl->id) {
835 case V4L2_CID_VBLANK:
836 /* Update max exposure while meeting expected vblanking */
837 max = ov13b->cur_mode->height + ctrl->val - 8;
838 __v4l2_ctrl_modify_range(ov13b->exposure,
839 ov13b->exposure->minimum,
840 max, ov13b->exposure->step, max);
841 break;
842 }
843
844 /*
845 * Applying V4L2 control value only happens
846 * when power is up for streaming
847 */
848 if (!pm_runtime_get_if_in_use(&client->dev))
849 return 0;
850
851 ret = 0;
852 switch (ctrl->id) {
853 case V4L2_CID_ANALOGUE_GAIN:
854 ret = ov13b10_write_reg(ov13b, OV13B10_REG_ANALOG_GAIN,
855 OV13B10_REG_VALUE_16BIT,
856 ctrl->val << 1);
857 break;
858 case V4L2_CID_DIGITAL_GAIN:
859 ret = ov13b10_update_digital_gain(ov13b, ctrl->val);
860 break;
861 case V4L2_CID_EXPOSURE:
862 ret = ov13b10_write_reg(ov13b, OV13B10_REG_EXPOSURE,
863 OV13B10_REG_VALUE_24BIT,
864 ctrl->val);
865 break;
866 case V4L2_CID_VBLANK:
867 ret = ov13b10_write_reg(ov13b, OV13B10_REG_VTS,
868 OV13B10_REG_VALUE_16BIT,
869 ov13b->cur_mode->height
870 + ctrl->val);
871 break;
872 case V4L2_CID_TEST_PATTERN:
873 ret = ov13b10_enable_test_pattern(ov13b, ctrl->val);
874 break;
875 case V4L2_CID_HFLIP:
876 ov13b10_set_ctrl_hflip(ov13b, ctrl->val);
877 break;
878 case V4L2_CID_VFLIP:
879 ov13b10_set_ctrl_vflip(ov13b, ctrl->val);
880 break;
881 default:
882 dev_info(&client->dev,
883 "ctrl(id:0x%x,val:0x%x) is not handled\n",
884 ctrl->id, ctrl->val);
885 break;
886 }
887
888 pm_runtime_put(&client->dev);
889
890 return ret;
891 }
892
893 static const struct v4l2_ctrl_ops ov13b10_ctrl_ops = {
894 .s_ctrl = ov13b10_set_ctrl,
895 };
896
ov13b10_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_mbus_code_enum * code)897 static int ov13b10_enum_mbus_code(struct v4l2_subdev *sd,
898 struct v4l2_subdev_state *sd_state,
899 struct v4l2_subdev_mbus_code_enum *code)
900 {
901 /* Only one bayer order(GRBG) is supported */
902 if (code->index > 0)
903 return -EINVAL;
904
905 code->code = MEDIA_BUS_FMT_SGRBG10_1X10;
906
907 return 0;
908 }
909
ov13b10_enum_frame_size(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_frame_size_enum * fse)910 static int ov13b10_enum_frame_size(struct v4l2_subdev *sd,
911 struct v4l2_subdev_state *sd_state,
912 struct v4l2_subdev_frame_size_enum *fse)
913 {
914 if (fse->index >= ARRAY_SIZE(supported_modes))
915 return -EINVAL;
916
917 if (fse->code != MEDIA_BUS_FMT_SGRBG10_1X10)
918 return -EINVAL;
919
920 fse->min_width = supported_modes[fse->index].width;
921 fse->max_width = fse->min_width;
922 fse->min_height = supported_modes[fse->index].height;
923 fse->max_height = fse->min_height;
924
925 return 0;
926 }
927
ov13b10_update_pad_format(const struct ov13b10_mode * mode,struct v4l2_subdev_format * fmt)928 static void ov13b10_update_pad_format(const struct ov13b10_mode *mode,
929 struct v4l2_subdev_format *fmt)
930 {
931 fmt->format.width = mode->width;
932 fmt->format.height = mode->height;
933 fmt->format.code = MEDIA_BUS_FMT_SGRBG10_1X10;
934 fmt->format.field = V4L2_FIELD_NONE;
935 }
936
ov13b10_do_get_pad_format(struct ov13b10 * ov13b,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_format * fmt)937 static int ov13b10_do_get_pad_format(struct ov13b10 *ov13b,
938 struct v4l2_subdev_state *sd_state,
939 struct v4l2_subdev_format *fmt)
940 {
941 struct v4l2_mbus_framefmt *framefmt;
942 struct v4l2_subdev *sd = &ov13b->sd;
943
944 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
945 framefmt = v4l2_subdev_get_try_format(sd, sd_state, fmt->pad);
946 fmt->format = *framefmt;
947 } else {
948 ov13b10_update_pad_format(ov13b->cur_mode, fmt);
949 }
950
951 return 0;
952 }
953
ov13b10_get_pad_format(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_format * fmt)954 static int ov13b10_get_pad_format(struct v4l2_subdev *sd,
955 struct v4l2_subdev_state *sd_state,
956 struct v4l2_subdev_format *fmt)
957 {
958 struct ov13b10 *ov13b = to_ov13b10(sd);
959 int ret;
960
961 mutex_lock(&ov13b->mutex);
962 ret = ov13b10_do_get_pad_format(ov13b, sd_state, fmt);
963 mutex_unlock(&ov13b->mutex);
964
965 return ret;
966 }
967
968 static int
ov13b10_set_pad_format(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_format * fmt)969 ov13b10_set_pad_format(struct v4l2_subdev *sd,
970 struct v4l2_subdev_state *sd_state,
971 struct v4l2_subdev_format *fmt)
972 {
973 struct ov13b10 *ov13b = to_ov13b10(sd);
974 const struct ov13b10_mode *mode;
975 struct v4l2_mbus_framefmt *framefmt;
976 s32 vblank_def;
977 s32 vblank_min;
978 s64 h_blank;
979 s64 pixel_rate;
980 s64 link_freq;
981
982 mutex_lock(&ov13b->mutex);
983
984 /* Only one raw bayer(GRBG) order is supported */
985 if (fmt->format.code != MEDIA_BUS_FMT_SGRBG10_1X10)
986 fmt->format.code = MEDIA_BUS_FMT_SGRBG10_1X10;
987
988 mode = v4l2_find_nearest_size(supported_modes,
989 ARRAY_SIZE(supported_modes),
990 width, height,
991 fmt->format.width, fmt->format.height);
992 ov13b10_update_pad_format(mode, fmt);
993 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
994 framefmt = v4l2_subdev_get_try_format(sd, sd_state, fmt->pad);
995 *framefmt = fmt->format;
996 } else {
997 ov13b->cur_mode = mode;
998 __v4l2_ctrl_s_ctrl(ov13b->link_freq, mode->link_freq_index);
999 link_freq = link_freq_menu_items[mode->link_freq_index];
1000 pixel_rate = link_freq_to_pixel_rate(link_freq);
1001 __v4l2_ctrl_s_ctrl_int64(ov13b->pixel_rate, pixel_rate);
1002
1003 /* Update limits and set FPS to default */
1004 vblank_def = ov13b->cur_mode->vts_def -
1005 ov13b->cur_mode->height;
1006 vblank_min = ov13b->cur_mode->vts_min -
1007 ov13b->cur_mode->height;
1008 __v4l2_ctrl_modify_range(ov13b->vblank, vblank_min,
1009 OV13B10_VTS_MAX
1010 - ov13b->cur_mode->height,
1011 1,
1012 vblank_def);
1013 __v4l2_ctrl_s_ctrl(ov13b->vblank, vblank_def);
1014 h_blank =
1015 link_freq_configs[mode->link_freq_index].pixels_per_line
1016 - ov13b->cur_mode->width;
1017 __v4l2_ctrl_modify_range(ov13b->hblank, h_blank,
1018 h_blank, 1, h_blank);
1019 }
1020
1021 mutex_unlock(&ov13b->mutex);
1022
1023 return 0;
1024 }
1025
ov13b10_start_streaming(struct ov13b10 * ov13b)1026 static int ov13b10_start_streaming(struct ov13b10 *ov13b)
1027 {
1028 struct i2c_client *client = v4l2_get_subdevdata(&ov13b->sd);
1029 const struct ov13b10_reg_list *reg_list;
1030 int ret, link_freq_index;
1031
1032 /* Get out of from software reset */
1033 ret = ov13b10_write_reg(ov13b, OV13B10_REG_SOFTWARE_RST,
1034 OV13B10_REG_VALUE_08BIT, OV13B10_SOFTWARE_RST);
1035 if (ret) {
1036 dev_err(&client->dev, "%s failed to set powerup registers\n",
1037 __func__);
1038 return ret;
1039 }
1040
1041 link_freq_index = ov13b->cur_mode->link_freq_index;
1042 reg_list = &link_freq_configs[link_freq_index].reg_list;
1043 ret = ov13b10_write_reg_list(ov13b, reg_list);
1044 if (ret) {
1045 dev_err(&client->dev, "%s failed to set plls\n", __func__);
1046 return ret;
1047 }
1048
1049 /* Apply default values of current mode */
1050 reg_list = &ov13b->cur_mode->reg_list;
1051 ret = ov13b10_write_reg_list(ov13b, reg_list);
1052 if (ret) {
1053 dev_err(&client->dev, "%s failed to set mode\n", __func__);
1054 return ret;
1055 }
1056
1057 /* Apply customized values from user */
1058 ret = __v4l2_ctrl_handler_setup(ov13b->sd.ctrl_handler);
1059 if (ret)
1060 return ret;
1061
1062 return ov13b10_write_reg(ov13b, OV13B10_REG_MODE_SELECT,
1063 OV13B10_REG_VALUE_08BIT,
1064 OV13B10_MODE_STREAMING);
1065 }
1066
1067 /* Stop streaming */
ov13b10_stop_streaming(struct ov13b10 * ov13b)1068 static int ov13b10_stop_streaming(struct ov13b10 *ov13b)
1069 {
1070 return ov13b10_write_reg(ov13b, OV13B10_REG_MODE_SELECT,
1071 OV13B10_REG_VALUE_08BIT, OV13B10_MODE_STANDBY);
1072 }
1073
ov13b10_set_stream(struct v4l2_subdev * sd,int enable)1074 static int ov13b10_set_stream(struct v4l2_subdev *sd, int enable)
1075 {
1076 struct ov13b10 *ov13b = to_ov13b10(sd);
1077 struct i2c_client *client = v4l2_get_subdevdata(sd);
1078 int ret = 0;
1079
1080 mutex_lock(&ov13b->mutex);
1081 if (ov13b->streaming == enable) {
1082 mutex_unlock(&ov13b->mutex);
1083 return 0;
1084 }
1085
1086 if (enable) {
1087 ret = pm_runtime_resume_and_get(&client->dev);
1088 if (ret < 0)
1089 goto err_unlock;
1090
1091 /*
1092 * Apply default & customized values
1093 * and then start streaming.
1094 */
1095 ret = ov13b10_start_streaming(ov13b);
1096 if (ret)
1097 goto err_rpm_put;
1098 } else {
1099 ov13b10_stop_streaming(ov13b);
1100 pm_runtime_put(&client->dev);
1101 }
1102
1103 ov13b->streaming = enable;
1104 mutex_unlock(&ov13b->mutex);
1105
1106 return ret;
1107
1108 err_rpm_put:
1109 pm_runtime_put(&client->dev);
1110 err_unlock:
1111 mutex_unlock(&ov13b->mutex);
1112
1113 return ret;
1114 }
1115
ov13b10_suspend(struct device * dev)1116 static int __maybe_unused ov13b10_suspend(struct device *dev)
1117 {
1118 struct v4l2_subdev *sd = dev_get_drvdata(dev);
1119 struct ov13b10 *ov13b = to_ov13b10(sd);
1120
1121 if (ov13b->streaming)
1122 ov13b10_stop_streaming(ov13b);
1123
1124 return 0;
1125 }
1126
ov13b10_resume(struct device * dev)1127 static int __maybe_unused ov13b10_resume(struct device *dev)
1128 {
1129 struct v4l2_subdev *sd = dev_get_drvdata(dev);
1130 struct ov13b10 *ov13b = to_ov13b10(sd);
1131 int ret;
1132
1133 if (ov13b->streaming) {
1134 ret = ov13b10_start_streaming(ov13b);
1135 if (ret)
1136 goto error;
1137 }
1138
1139 return 0;
1140
1141 error:
1142 ov13b10_stop_streaming(ov13b);
1143 ov13b->streaming = false;
1144 return ret;
1145 }
1146
1147 /* Verify chip ID */
ov13b10_identify_module(struct ov13b10 * ov13b)1148 static int ov13b10_identify_module(struct ov13b10 *ov13b)
1149 {
1150 struct i2c_client *client = v4l2_get_subdevdata(&ov13b->sd);
1151 int ret;
1152 u32 val;
1153
1154 ret = ov13b10_read_reg(ov13b, OV13B10_REG_CHIP_ID,
1155 OV13B10_REG_VALUE_24BIT, &val);
1156 if (ret)
1157 return ret;
1158
1159 if (val != OV13B10_CHIP_ID) {
1160 dev_err(&client->dev, "chip id mismatch: %x!=%x\n",
1161 OV13B10_CHIP_ID, val);
1162 return -EIO;
1163 }
1164
1165 return 0;
1166 }
1167
1168 static const struct v4l2_subdev_video_ops ov13b10_video_ops = {
1169 .s_stream = ov13b10_set_stream,
1170 };
1171
1172 static const struct v4l2_subdev_pad_ops ov13b10_pad_ops = {
1173 .enum_mbus_code = ov13b10_enum_mbus_code,
1174 .get_fmt = ov13b10_get_pad_format,
1175 .set_fmt = ov13b10_set_pad_format,
1176 .enum_frame_size = ov13b10_enum_frame_size,
1177 };
1178
1179 static const struct v4l2_subdev_ops ov13b10_subdev_ops = {
1180 .video = &ov13b10_video_ops,
1181 .pad = &ov13b10_pad_ops,
1182 };
1183
1184 static const struct media_entity_operations ov13b10_subdev_entity_ops = {
1185 .link_validate = v4l2_subdev_link_validate,
1186 };
1187
1188 static const struct v4l2_subdev_internal_ops ov13b10_internal_ops = {
1189 .open = ov13b10_open,
1190 };
1191
1192 /* Initialize control handlers */
ov13b10_init_controls(struct ov13b10 * ov13b)1193 static int ov13b10_init_controls(struct ov13b10 *ov13b)
1194 {
1195 struct i2c_client *client = v4l2_get_subdevdata(&ov13b->sd);
1196 struct v4l2_fwnode_device_properties props;
1197 struct v4l2_ctrl_handler *ctrl_hdlr;
1198 s64 exposure_max;
1199 s64 vblank_def;
1200 s64 vblank_min;
1201 s64 hblank;
1202 s64 pixel_rate_min;
1203 s64 pixel_rate_max;
1204 const struct ov13b10_mode *mode;
1205 u32 max;
1206 int ret;
1207
1208 ctrl_hdlr = &ov13b->ctrl_handler;
1209 ret = v4l2_ctrl_handler_init(ctrl_hdlr, 10);
1210 if (ret)
1211 return ret;
1212
1213 mutex_init(&ov13b->mutex);
1214 ctrl_hdlr->lock = &ov13b->mutex;
1215 max = ARRAY_SIZE(link_freq_menu_items) - 1;
1216 ov13b->link_freq = v4l2_ctrl_new_int_menu(ctrl_hdlr,
1217 &ov13b10_ctrl_ops,
1218 V4L2_CID_LINK_FREQ,
1219 max,
1220 0,
1221 link_freq_menu_items);
1222 if (ov13b->link_freq)
1223 ov13b->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1224
1225 pixel_rate_max = link_freq_to_pixel_rate(link_freq_menu_items[0]);
1226 pixel_rate_min = 0;
1227 /* By default, PIXEL_RATE is read only */
1228 ov13b->pixel_rate = v4l2_ctrl_new_std(ctrl_hdlr, &ov13b10_ctrl_ops,
1229 V4L2_CID_PIXEL_RATE,
1230 pixel_rate_min, pixel_rate_max,
1231 1, pixel_rate_max);
1232
1233 mode = ov13b->cur_mode;
1234 vblank_def = mode->vts_def - mode->height;
1235 vblank_min = mode->vts_min - mode->height;
1236 ov13b->vblank = v4l2_ctrl_new_std(ctrl_hdlr, &ov13b10_ctrl_ops,
1237 V4L2_CID_VBLANK,
1238 vblank_min,
1239 OV13B10_VTS_MAX - mode->height, 1,
1240 vblank_def);
1241
1242 hblank = link_freq_configs[mode->link_freq_index].pixels_per_line -
1243 mode->width;
1244 ov13b->hblank = v4l2_ctrl_new_std(ctrl_hdlr, &ov13b10_ctrl_ops,
1245 V4L2_CID_HBLANK,
1246 hblank, hblank, 1, hblank);
1247 if (ov13b->hblank)
1248 ov13b->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1249
1250 exposure_max = mode->vts_def - 8;
1251 ov13b->exposure = v4l2_ctrl_new_std(ctrl_hdlr, &ov13b10_ctrl_ops,
1252 V4L2_CID_EXPOSURE,
1253 OV13B10_EXPOSURE_MIN,
1254 exposure_max, OV13B10_EXPOSURE_STEP,
1255 exposure_max);
1256
1257 v4l2_ctrl_new_std(ctrl_hdlr, &ov13b10_ctrl_ops, V4L2_CID_ANALOGUE_GAIN,
1258 OV13B10_ANA_GAIN_MIN, OV13B10_ANA_GAIN_MAX,
1259 OV13B10_ANA_GAIN_STEP, OV13B10_ANA_GAIN_DEFAULT);
1260
1261 /* Digital gain */
1262 v4l2_ctrl_new_std(ctrl_hdlr, &ov13b10_ctrl_ops, V4L2_CID_DIGITAL_GAIN,
1263 OV13B10_DGTL_GAIN_MIN, OV13B10_DGTL_GAIN_MAX,
1264 OV13B10_DGTL_GAIN_STEP, OV13B10_DGTL_GAIN_DEFAULT);
1265
1266 v4l2_ctrl_new_std_menu_items(ctrl_hdlr, &ov13b10_ctrl_ops,
1267 V4L2_CID_TEST_PATTERN,
1268 ARRAY_SIZE(ov13b10_test_pattern_menu) - 1,
1269 0, 0, ov13b10_test_pattern_menu);
1270
1271 v4l2_ctrl_new_std(ctrl_hdlr, &ov13b10_ctrl_ops,
1272 V4L2_CID_HFLIP, 0, 1, 1, 0);
1273 v4l2_ctrl_new_std(ctrl_hdlr, &ov13b10_ctrl_ops,
1274 V4L2_CID_VFLIP, 0, 1, 1, 0);
1275
1276 if (ctrl_hdlr->error) {
1277 ret = ctrl_hdlr->error;
1278 dev_err(&client->dev, "%s control init failed (%d)\n",
1279 __func__, ret);
1280 goto error;
1281 }
1282
1283 ret = v4l2_fwnode_device_parse(&client->dev, &props);
1284 if (ret)
1285 goto error;
1286
1287 ret = v4l2_ctrl_new_fwnode_properties(ctrl_hdlr, &ov13b10_ctrl_ops,
1288 &props);
1289 if (ret)
1290 goto error;
1291
1292 ov13b->sd.ctrl_handler = ctrl_hdlr;
1293
1294 return 0;
1295
1296 error:
1297 v4l2_ctrl_handler_free(ctrl_hdlr);
1298 mutex_destroy(&ov13b->mutex);
1299
1300 return ret;
1301 }
1302
ov13b10_free_controls(struct ov13b10 * ov13b)1303 static void ov13b10_free_controls(struct ov13b10 *ov13b)
1304 {
1305 v4l2_ctrl_handler_free(ov13b->sd.ctrl_handler);
1306 mutex_destroy(&ov13b->mutex);
1307 }
1308
ov13b10_check_hwcfg(struct device * dev)1309 static int ov13b10_check_hwcfg(struct device *dev)
1310 {
1311 struct v4l2_fwnode_endpoint bus_cfg = {
1312 .bus_type = V4L2_MBUS_CSI2_DPHY
1313 };
1314 struct fwnode_handle *ep;
1315 struct fwnode_handle *fwnode = dev_fwnode(dev);
1316 unsigned int i, j;
1317 int ret;
1318 u32 ext_clk;
1319
1320 if (!fwnode)
1321 return -ENXIO;
1322
1323 ret = fwnode_property_read_u32(dev_fwnode(dev), "clock-frequency",
1324 &ext_clk);
1325 if (ret) {
1326 dev_err(dev, "can't get clock frequency");
1327 return ret;
1328 }
1329
1330 if (ext_clk != OV13B10_EXT_CLK) {
1331 dev_err(dev, "external clock %d is not supported",
1332 ext_clk);
1333 return -EINVAL;
1334 }
1335
1336 ep = fwnode_graph_get_next_endpoint(fwnode, NULL);
1337 if (!ep)
1338 return -ENXIO;
1339
1340 ret = v4l2_fwnode_endpoint_alloc_parse(ep, &bus_cfg);
1341 fwnode_handle_put(ep);
1342 if (ret)
1343 return ret;
1344
1345 if (bus_cfg.bus.mipi_csi2.num_data_lanes != OV13B10_DATA_LANES) {
1346 dev_err(dev, "number of CSI2 data lanes %d is not supported",
1347 bus_cfg.bus.mipi_csi2.num_data_lanes);
1348 ret = -EINVAL;
1349 goto out_err;
1350 }
1351
1352 if (!bus_cfg.nr_of_link_frequencies) {
1353 dev_err(dev, "no link frequencies defined");
1354 ret = -EINVAL;
1355 goto out_err;
1356 }
1357
1358 for (i = 0; i < ARRAY_SIZE(link_freq_menu_items); i++) {
1359 for (j = 0; j < bus_cfg.nr_of_link_frequencies; j++) {
1360 if (link_freq_menu_items[i] ==
1361 bus_cfg.link_frequencies[j])
1362 break;
1363 }
1364
1365 if (j == bus_cfg.nr_of_link_frequencies) {
1366 dev_err(dev, "no link frequency %lld supported",
1367 link_freq_menu_items[i]);
1368 ret = -EINVAL;
1369 goto out_err;
1370 }
1371 }
1372
1373 out_err:
1374 v4l2_fwnode_endpoint_free(&bus_cfg);
1375
1376 return ret;
1377 }
1378
ov13b10_probe(struct i2c_client * client)1379 static int ov13b10_probe(struct i2c_client *client)
1380 {
1381 struct ov13b10 *ov13b;
1382 int ret;
1383
1384 /* Check HW config */
1385 ret = ov13b10_check_hwcfg(&client->dev);
1386 if (ret) {
1387 dev_err(&client->dev, "failed to check hwcfg: %d", ret);
1388 return ret;
1389 }
1390
1391 ov13b = devm_kzalloc(&client->dev, sizeof(*ov13b), GFP_KERNEL);
1392 if (!ov13b)
1393 return -ENOMEM;
1394
1395 /* Initialize subdev */
1396 v4l2_i2c_subdev_init(&ov13b->sd, client, &ov13b10_subdev_ops);
1397
1398 /* Check module identity */
1399 ret = ov13b10_identify_module(ov13b);
1400 if (ret) {
1401 dev_err(&client->dev, "failed to find sensor: %d\n", ret);
1402 return ret;
1403 }
1404
1405 /* Set default mode to max resolution */
1406 ov13b->cur_mode = &supported_modes[0];
1407
1408 ret = ov13b10_init_controls(ov13b);
1409 if (ret)
1410 return ret;
1411
1412 /* Initialize subdev */
1413 ov13b->sd.internal_ops = &ov13b10_internal_ops;
1414 ov13b->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1415 ov13b->sd.entity.ops = &ov13b10_subdev_entity_ops;
1416 ov13b->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
1417
1418 /* Initialize source pad */
1419 ov13b->pad.flags = MEDIA_PAD_FL_SOURCE;
1420 ret = media_entity_pads_init(&ov13b->sd.entity, 1, &ov13b->pad);
1421 if (ret) {
1422 dev_err(&client->dev, "%s failed:%d\n", __func__, ret);
1423 goto error_handler_free;
1424 }
1425
1426 ret = v4l2_async_register_subdev_sensor(&ov13b->sd);
1427 if (ret < 0)
1428 goto error_media_entity;
1429
1430 /*
1431 * Device is already turned on by i2c-core with ACPI domain PM.
1432 * Enable runtime PM and turn off the device.
1433 */
1434 pm_runtime_set_active(&client->dev);
1435 pm_runtime_enable(&client->dev);
1436 pm_runtime_idle(&client->dev);
1437
1438 return 0;
1439
1440 error_media_entity:
1441 media_entity_cleanup(&ov13b->sd.entity);
1442
1443 error_handler_free:
1444 ov13b10_free_controls(ov13b);
1445 dev_err(&client->dev, "%s failed:%d\n", __func__, ret);
1446
1447 return ret;
1448 }
1449
ov13b10_remove(struct i2c_client * client)1450 static void ov13b10_remove(struct i2c_client *client)
1451 {
1452 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1453 struct ov13b10 *ov13b = to_ov13b10(sd);
1454
1455 v4l2_async_unregister_subdev(sd);
1456 media_entity_cleanup(&sd->entity);
1457 ov13b10_free_controls(ov13b);
1458
1459 pm_runtime_disable(&client->dev);
1460 }
1461
1462 static const struct dev_pm_ops ov13b10_pm_ops = {
1463 SET_SYSTEM_SLEEP_PM_OPS(ov13b10_suspend, ov13b10_resume)
1464 };
1465
1466 #ifdef CONFIG_ACPI
1467 static const struct acpi_device_id ov13b10_acpi_ids[] = {
1468 {"OVTIDB10"},
1469 { /* sentinel */ }
1470 };
1471
1472 MODULE_DEVICE_TABLE(acpi, ov13b10_acpi_ids);
1473 #endif
1474
1475 static struct i2c_driver ov13b10_i2c_driver = {
1476 .driver = {
1477 .name = "ov13b10",
1478 .pm = &ov13b10_pm_ops,
1479 .acpi_match_table = ACPI_PTR(ov13b10_acpi_ids),
1480 },
1481 .probe_new = ov13b10_probe,
1482 .remove = ov13b10_remove,
1483 };
1484
1485 module_i2c_driver(ov13b10_i2c_driver);
1486
1487 MODULE_AUTHOR("Kao, Arec <arec.kao@intel.com>");
1488 MODULE_DESCRIPTION("Omnivision ov13b10 sensor driver");
1489 MODULE_LICENSE("GPL v2");
1490
