1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2017 Intel Corporation.
3
4 #include <linux/acpi.h>
5 #include <linux/i2c.h>
6 #include <linux/module.h>
7 #include <linux/pm_runtime.h>
8 #include <media/v4l2-ctrls.h>
9 #include <media/v4l2-device.h>
10
11 #define OV13858_REG_VALUE_08BIT 1
12 #define OV13858_REG_VALUE_16BIT 2
13 #define OV13858_REG_VALUE_24BIT 3
14
15 #define OV13858_REG_MODE_SELECT 0x0100
16 #define OV13858_MODE_STANDBY 0x00
17 #define OV13858_MODE_STREAMING 0x01
18
19 #define OV13858_REG_SOFTWARE_RST 0x0103
20 #define OV13858_SOFTWARE_RST 0x01
21
22 /* PLL1 generates PCLK and MIPI_PHY_CLK */
23 #define OV13858_REG_PLL1_CTRL_0 0x0300
24 #define OV13858_REG_PLL1_CTRL_1 0x0301
25 #define OV13858_REG_PLL1_CTRL_2 0x0302
26 #define OV13858_REG_PLL1_CTRL_3 0x0303
27 #define OV13858_REG_PLL1_CTRL_4 0x0304
28 #define OV13858_REG_PLL1_CTRL_5 0x0305
29
30 /* PLL2 generates DAC_CLK, SCLK and SRAM_CLK */
31 #define OV13858_REG_PLL2_CTRL_B 0x030b
32 #define OV13858_REG_PLL2_CTRL_C 0x030c
33 #define OV13858_REG_PLL2_CTRL_D 0x030d
34 #define OV13858_REG_PLL2_CTRL_E 0x030e
35 #define OV13858_REG_PLL2_CTRL_F 0x030f
36 #define OV13858_REG_PLL2_CTRL_12 0x0312
37 #define OV13858_REG_MIPI_SC_CTRL0 0x3016
38 #define OV13858_REG_MIPI_SC_CTRL1 0x3022
39
40 /* Chip ID */
41 #define OV13858_REG_CHIP_ID 0x300a
42 #define OV13858_CHIP_ID 0x00d855
43
44 /* V_TIMING internal */
45 #define OV13858_REG_VTS 0x380e
46 #define OV13858_VTS_30FPS 0x0c8e /* 30 fps */
47 #define OV13858_VTS_60FPS 0x0648 /* 60 fps */
48 #define OV13858_VTS_MAX 0x7fff
49
50 /* HBLANK control - read only */
51 #define OV13858_PPL_270MHZ 2244
52 #define OV13858_PPL_540MHZ 4488
53
54 /* Exposure control */
55 #define OV13858_REG_EXPOSURE 0x3500
56 #define OV13858_EXPOSURE_MIN 4
57 #define OV13858_EXPOSURE_STEP 1
58 #define OV13858_EXPOSURE_DEFAULT 0x640
59
60 /* Analog gain control */
61 #define OV13858_REG_ANALOG_GAIN 0x3508
62 #define OV13858_ANA_GAIN_MIN 0
63 #define OV13858_ANA_GAIN_MAX 0x1fff
64 #define OV13858_ANA_GAIN_STEP 1
65 #define OV13858_ANA_GAIN_DEFAULT 0x80
66
67 /* Digital gain control */
68 #define OV13858_REG_B_MWB_GAIN 0x5100
69 #define OV13858_REG_G_MWB_GAIN 0x5102
70 #define OV13858_REG_R_MWB_GAIN 0x5104
71 #define OV13858_DGTL_GAIN_MIN 0
72 #define OV13858_DGTL_GAIN_MAX 16384 /* Max = 16 X */
73 #define OV13858_DGTL_GAIN_DEFAULT 1024 /* Default gain = 1 X */
74 #define OV13858_DGTL_GAIN_STEP 1 /* Each step = 1/1024 */
75
76 /* Test Pattern Control */
77 #define OV13858_REG_TEST_PATTERN 0x4503
78 #define OV13858_TEST_PATTERN_ENABLE BIT(7)
79 #define OV13858_TEST_PATTERN_MASK 0xfc
80
81 /* Number of frames to skip */
82 #define OV13858_NUM_OF_SKIP_FRAMES 2
83
84 struct ov13858_reg {
85 u16 address;
86 u8 val;
87 };
88
89 struct ov13858_reg_list {
90 u32 num_of_regs;
91 const struct ov13858_reg *regs;
92 };
93
94 /* Link frequency config */
95 struct ov13858_link_freq_config {
96 u32 pixels_per_line;
97
98 /* PLL registers for this link frequency */
99 struct ov13858_reg_list reg_list;
100 };
101
102 /* Mode : resolution and related config&values */
103 struct ov13858_mode {
104 /* Frame width */
105 u32 width;
106 /* Frame height */
107 u32 height;
108
109 /* V-timing */
110 u32 vts_def;
111 u32 vts_min;
112
113 /* Index of Link frequency config to be used */
114 u32 link_freq_index;
115 /* Default register values */
116 struct ov13858_reg_list reg_list;
117 };
118
119 /* 4224x3136 needs 1080Mbps/lane, 4 lanes */
120 static const struct ov13858_reg mipi_data_rate_1080mbps[] = {
121 /* PLL1 registers */
122 {OV13858_REG_PLL1_CTRL_0, 0x07},
123 {OV13858_REG_PLL1_CTRL_1, 0x01},
124 {OV13858_REG_PLL1_CTRL_2, 0xc2},
125 {OV13858_REG_PLL1_CTRL_3, 0x00},
126 {OV13858_REG_PLL1_CTRL_4, 0x00},
127 {OV13858_REG_PLL1_CTRL_5, 0x01},
128
129 /* PLL2 registers */
130 {OV13858_REG_PLL2_CTRL_B, 0x05},
131 {OV13858_REG_PLL2_CTRL_C, 0x01},
132 {OV13858_REG_PLL2_CTRL_D, 0x0e},
133 {OV13858_REG_PLL2_CTRL_E, 0x05},
134 {OV13858_REG_PLL2_CTRL_F, 0x01},
135 {OV13858_REG_PLL2_CTRL_12, 0x01},
136 {OV13858_REG_MIPI_SC_CTRL0, 0x72},
137 {OV13858_REG_MIPI_SC_CTRL1, 0x01},
138 };
139
140 /*
141 * 2112x1568, 2112x1188, 1056x784 need 540Mbps/lane,
142 * 4 lanes
143 */
144 static const struct ov13858_reg mipi_data_rate_540mbps[] = {
145 /* PLL1 registers */
146 {OV13858_REG_PLL1_CTRL_0, 0x07},
147 {OV13858_REG_PLL1_CTRL_1, 0x01},
148 {OV13858_REG_PLL1_CTRL_2, 0xc2},
149 {OV13858_REG_PLL1_CTRL_3, 0x01},
150 {OV13858_REG_PLL1_CTRL_4, 0x00},
151 {OV13858_REG_PLL1_CTRL_5, 0x01},
152
153 /* PLL2 registers */
154 {OV13858_REG_PLL2_CTRL_B, 0x05},
155 {OV13858_REG_PLL2_CTRL_C, 0x01},
156 {OV13858_REG_PLL2_CTRL_D, 0x0e},
157 {OV13858_REG_PLL2_CTRL_E, 0x05},
158 {OV13858_REG_PLL2_CTRL_F, 0x01},
159 {OV13858_REG_PLL2_CTRL_12, 0x01},
160 {OV13858_REG_MIPI_SC_CTRL0, 0x72},
161 {OV13858_REG_MIPI_SC_CTRL1, 0x01},
162 };
163
164 static const struct ov13858_reg mode_4224x3136_regs[] = {
165 {0x3013, 0x32},
166 {0x301b, 0xf0},
167 {0x301f, 0xd0},
168 {0x3106, 0x15},
169 {0x3107, 0x23},
170 {0x350a, 0x00},
171 {0x350e, 0x00},
172 {0x3510, 0x00},
173 {0x3511, 0x02},
174 {0x3512, 0x00},
175 {0x3600, 0x2b},
176 {0x3601, 0x52},
177 {0x3602, 0x60},
178 {0x3612, 0x05},
179 {0x3613, 0xa4},
180 {0x3620, 0x80},
181 {0x3621, 0x10},
182 {0x3622, 0x30},
183 {0x3624, 0x1c},
184 {0x3640, 0x10},
185 {0x3641, 0x70},
186 {0x3660, 0x04},
187 {0x3661, 0x80},
188 {0x3662, 0x12},
189 {0x3664, 0x73},
190 {0x3665, 0xa7},
191 {0x366e, 0xff},
192 {0x366f, 0xf4},
193 {0x3674, 0x00},
194 {0x3679, 0x0c},
195 {0x367f, 0x01},
196 {0x3680, 0x0c},
197 {0x3681, 0x50},
198 {0x3682, 0x50},
199 {0x3683, 0xa9},
200 {0x3684, 0xa9},
201 {0x3709, 0x5f},
202 {0x3714, 0x24},
203 {0x371a, 0x3e},
204 {0x3737, 0x04},
205 {0x3738, 0xcc},
206 {0x3739, 0x12},
207 {0x373d, 0x26},
208 {0x3764, 0x20},
209 {0x3765, 0x20},
210 {0x37a1, 0x36},
211 {0x37a8, 0x3b},
212 {0x37ab, 0x31},
213 {0x37c2, 0x04},
214 {0x37c3, 0xf1},
215 {0x37c5, 0x00},
216 {0x37d8, 0x03},
217 {0x37d9, 0x0c},
218 {0x37da, 0xc2},
219 {0x37dc, 0x02},
220 {0x37e0, 0x00},
221 {0x37e1, 0x0a},
222 {0x37e2, 0x14},
223 {0x37e3, 0x04},
224 {0x37e4, 0x2a},
225 {0x37e5, 0x03},
226 {0x37e6, 0x04},
227 {0x3800, 0x00},
228 {0x3801, 0x00},
229 {0x3802, 0x00},
230 {0x3803, 0x08},
231 {0x3804, 0x10},
232 {0x3805, 0x9f},
233 {0x3806, 0x0c},
234 {0x3807, 0x57},
235 {0x3808, 0x10},
236 {0x3809, 0x80},
237 {0x380a, 0x0c},
238 {0x380b, 0x40},
239 {0x380c, 0x04},
240 {0x380d, 0x62},
241 {0x380e, 0x0c},
242 {0x380f, 0x8e},
243 {0x3811, 0x04},
244 {0x3813, 0x05},
245 {0x3814, 0x01},
246 {0x3815, 0x01},
247 {0x3816, 0x01},
248 {0x3817, 0x01},
249 {0x3820, 0xa8},
250 {0x3821, 0x00},
251 {0x3822, 0xc2},
252 {0x3823, 0x18},
253 {0x3826, 0x11},
254 {0x3827, 0x1c},
255 {0x3829, 0x03},
256 {0x3832, 0x00},
257 {0x3c80, 0x00},
258 {0x3c87, 0x01},
259 {0x3c8c, 0x19},
260 {0x3c8d, 0x1c},
261 {0x3c90, 0x00},
262 {0x3c91, 0x00},
263 {0x3c92, 0x00},
264 {0x3c93, 0x00},
265 {0x3c94, 0x40},
266 {0x3c95, 0x54},
267 {0x3c96, 0x34},
268 {0x3c97, 0x04},
269 {0x3c98, 0x00},
270 {0x3d8c, 0x73},
271 {0x3d8d, 0xc0},
272 {0x3f00, 0x0b},
273 {0x3f03, 0x00},
274 {0x4001, 0xe0},
275 {0x4008, 0x00},
276 {0x4009, 0x0f},
277 {0x4011, 0xf0},
278 {0x4017, 0x08},
279 {0x4050, 0x04},
280 {0x4051, 0x0b},
281 {0x4052, 0x00},
282 {0x4053, 0x80},
283 {0x4054, 0x00},
284 {0x4055, 0x80},
285 {0x4056, 0x00},
286 {0x4057, 0x80},
287 {0x4058, 0x00},
288 {0x4059, 0x80},
289 {0x405e, 0x20},
290 {0x4500, 0x07},
291 {0x4503, 0x00},
292 {0x450a, 0x04},
293 {0x4809, 0x04},
294 {0x480c, 0x12},
295 {0x481f, 0x30},
296 {0x4833, 0x10},
297 {0x4837, 0x0e},
298 {0x4902, 0x01},
299 {0x4d00, 0x03},
300 {0x4d01, 0xc9},
301 {0x4d02, 0xbc},
302 {0x4d03, 0xd7},
303 {0x4d04, 0xf0},
304 {0x4d05, 0xa2},
305 {0x5000, 0xfd},
306 {0x5001, 0x01},
307 {0x5040, 0x39},
308 {0x5041, 0x10},
309 {0x5042, 0x10},
310 {0x5043, 0x84},
311 {0x5044, 0x62},
312 {0x5180, 0x00},
313 {0x5181, 0x10},
314 {0x5182, 0x02},
315 {0x5183, 0x0f},
316 {0x5200, 0x1b},
317 {0x520b, 0x07},
318 {0x520c, 0x0f},
319 {0x5300, 0x04},
320 {0x5301, 0x0c},
321 {0x5302, 0x0c},
322 {0x5303, 0x0f},
323 {0x5304, 0x00},
324 {0x5305, 0x70},
325 {0x5306, 0x00},
326 {0x5307, 0x80},
327 {0x5308, 0x00},
328 {0x5309, 0xa5},
329 {0x530a, 0x00},
330 {0x530b, 0xd3},
331 {0x530c, 0x00},
332 {0x530d, 0xf0},
333 {0x530e, 0x01},
334 {0x530f, 0x10},
335 {0x5310, 0x01},
336 {0x5311, 0x20},
337 {0x5312, 0x01},
338 {0x5313, 0x20},
339 {0x5314, 0x01},
340 {0x5315, 0x20},
341 {0x5316, 0x08},
342 {0x5317, 0x08},
343 {0x5318, 0x10},
344 {0x5319, 0x88},
345 {0x531a, 0x88},
346 {0x531b, 0xa9},
347 {0x531c, 0xaa},
348 {0x531d, 0x0a},
349 {0x5405, 0x02},
350 {0x5406, 0x67},
351 {0x5407, 0x01},
352 {0x5408, 0x4a},
353 };
354
355 static const struct ov13858_reg mode_2112x1568_regs[] = {
356 {0x3013, 0x32},
357 {0x301b, 0xf0},
358 {0x301f, 0xd0},
359 {0x3106, 0x15},
360 {0x3107, 0x23},
361 {0x350a, 0x00},
362 {0x350e, 0x00},
363 {0x3510, 0x00},
364 {0x3511, 0x02},
365 {0x3512, 0x00},
366 {0x3600, 0x2b},
367 {0x3601, 0x52},
368 {0x3602, 0x60},
369 {0x3612, 0x05},
370 {0x3613, 0xa4},
371 {0x3620, 0x80},
372 {0x3621, 0x10},
373 {0x3622, 0x30},
374 {0x3624, 0x1c},
375 {0x3640, 0x10},
376 {0x3641, 0x70},
377 {0x3660, 0x04},
378 {0x3661, 0x80},
379 {0x3662, 0x10},
380 {0x3664, 0x73},
381 {0x3665, 0xa7},
382 {0x366e, 0xff},
383 {0x366f, 0xf4},
384 {0x3674, 0x00},
385 {0x3679, 0x0c},
386 {0x367f, 0x01},
387 {0x3680, 0x0c},
388 {0x3681, 0x50},
389 {0x3682, 0x50},
390 {0x3683, 0xa9},
391 {0x3684, 0xa9},
392 {0x3709, 0x5f},
393 {0x3714, 0x28},
394 {0x371a, 0x3e},
395 {0x3737, 0x08},
396 {0x3738, 0xcc},
397 {0x3739, 0x20},
398 {0x373d, 0x26},
399 {0x3764, 0x20},
400 {0x3765, 0x20},
401 {0x37a1, 0x36},
402 {0x37a8, 0x3b},
403 {0x37ab, 0x31},
404 {0x37c2, 0x14},
405 {0x37c3, 0xf1},
406 {0x37c5, 0x00},
407 {0x37d8, 0x03},
408 {0x37d9, 0x0c},
409 {0x37da, 0xc2},
410 {0x37dc, 0x02},
411 {0x37e0, 0x00},
412 {0x37e1, 0x0a},
413 {0x37e2, 0x14},
414 {0x37e3, 0x08},
415 {0x37e4, 0x38},
416 {0x37e5, 0x03},
417 {0x37e6, 0x08},
418 {0x3800, 0x00},
419 {0x3801, 0x00},
420 {0x3802, 0x00},
421 {0x3803, 0x00},
422 {0x3804, 0x10},
423 {0x3805, 0x9f},
424 {0x3806, 0x0c},
425 {0x3807, 0x5f},
426 {0x3808, 0x08},
427 {0x3809, 0x40},
428 {0x380a, 0x06},
429 {0x380b, 0x20},
430 {0x380c, 0x04},
431 {0x380d, 0x62},
432 {0x380e, 0x0c},
433 {0x380f, 0x8e},
434 {0x3811, 0x04},
435 {0x3813, 0x05},
436 {0x3814, 0x03},
437 {0x3815, 0x01},
438 {0x3816, 0x03},
439 {0x3817, 0x01},
440 {0x3820, 0xab},
441 {0x3821, 0x00},
442 {0x3822, 0xc2},
443 {0x3823, 0x18},
444 {0x3826, 0x04},
445 {0x3827, 0x90},
446 {0x3829, 0x07},
447 {0x3832, 0x00},
448 {0x3c80, 0x00},
449 {0x3c87, 0x01},
450 {0x3c8c, 0x19},
451 {0x3c8d, 0x1c},
452 {0x3c90, 0x00},
453 {0x3c91, 0x00},
454 {0x3c92, 0x00},
455 {0x3c93, 0x00},
456 {0x3c94, 0x40},
457 {0x3c95, 0x54},
458 {0x3c96, 0x34},
459 {0x3c97, 0x04},
460 {0x3c98, 0x00},
461 {0x3d8c, 0x73},
462 {0x3d8d, 0xc0},
463 {0x3f00, 0x0b},
464 {0x3f03, 0x00},
465 {0x4001, 0xe0},
466 {0x4008, 0x00},
467 {0x4009, 0x0d},
468 {0x4011, 0xf0},
469 {0x4017, 0x08},
470 {0x4050, 0x04},
471 {0x4051, 0x0b},
472 {0x4052, 0x00},
473 {0x4053, 0x80},
474 {0x4054, 0x00},
475 {0x4055, 0x80},
476 {0x4056, 0x00},
477 {0x4057, 0x80},
478 {0x4058, 0x00},
479 {0x4059, 0x80},
480 {0x405e, 0x20},
481 {0x4500, 0x07},
482 {0x4503, 0x00},
483 {0x450a, 0x04},
484 {0x4809, 0x04},
485 {0x480c, 0x12},
486 {0x481f, 0x30},
487 {0x4833, 0x10},
488 {0x4837, 0x1c},
489 {0x4902, 0x01},
490 {0x4d00, 0x03},
491 {0x4d01, 0xc9},
492 {0x4d02, 0xbc},
493 {0x4d03, 0xd7},
494 {0x4d04, 0xf0},
495 {0x4d05, 0xa2},
496 {0x5000, 0xfd},
497 {0x5001, 0x01},
498 {0x5040, 0x39},
499 {0x5041, 0x10},
500 {0x5042, 0x10},
501 {0x5043, 0x84},
502 {0x5044, 0x62},
503 {0x5180, 0x00},
504 {0x5181, 0x10},
505 {0x5182, 0x02},
506 {0x5183, 0x0f},
507 {0x5200, 0x1b},
508 {0x520b, 0x07},
509 {0x520c, 0x0f},
510 {0x5300, 0x04},
511 {0x5301, 0x0c},
512 {0x5302, 0x0c},
513 {0x5303, 0x0f},
514 {0x5304, 0x00},
515 {0x5305, 0x70},
516 {0x5306, 0x00},
517 {0x5307, 0x80},
518 {0x5308, 0x00},
519 {0x5309, 0xa5},
520 {0x530a, 0x00},
521 {0x530b, 0xd3},
522 {0x530c, 0x00},
523 {0x530d, 0xf0},
524 {0x530e, 0x01},
525 {0x530f, 0x10},
526 {0x5310, 0x01},
527 {0x5311, 0x20},
528 {0x5312, 0x01},
529 {0x5313, 0x20},
530 {0x5314, 0x01},
531 {0x5315, 0x20},
532 {0x5316, 0x08},
533 {0x5317, 0x08},
534 {0x5318, 0x10},
535 {0x5319, 0x88},
536 {0x531a, 0x88},
537 {0x531b, 0xa9},
538 {0x531c, 0xaa},
539 {0x531d, 0x0a},
540 {0x5405, 0x02},
541 {0x5406, 0x67},
542 {0x5407, 0x01},
543 {0x5408, 0x4a},
544 };
545
546 static const struct ov13858_reg mode_2112x1188_regs[] = {
547 {0x3013, 0x32},
548 {0x301b, 0xf0},
549 {0x301f, 0xd0},
550 {0x3106, 0x15},
551 {0x3107, 0x23},
552 {0x350a, 0x00},
553 {0x350e, 0x00},
554 {0x3510, 0x00},
555 {0x3511, 0x02},
556 {0x3512, 0x00},
557 {0x3600, 0x2b},
558 {0x3601, 0x52},
559 {0x3602, 0x60},
560 {0x3612, 0x05},
561 {0x3613, 0xa4},
562 {0x3620, 0x80},
563 {0x3621, 0x10},
564 {0x3622, 0x30},
565 {0x3624, 0x1c},
566 {0x3640, 0x10},
567 {0x3641, 0x70},
568 {0x3660, 0x04},
569 {0x3661, 0x80},
570 {0x3662, 0x10},
571 {0x3664, 0x73},
572 {0x3665, 0xa7},
573 {0x366e, 0xff},
574 {0x366f, 0xf4},
575 {0x3674, 0x00},
576 {0x3679, 0x0c},
577 {0x367f, 0x01},
578 {0x3680, 0x0c},
579 {0x3681, 0x50},
580 {0x3682, 0x50},
581 {0x3683, 0xa9},
582 {0x3684, 0xa9},
583 {0x3709, 0x5f},
584 {0x3714, 0x28},
585 {0x371a, 0x3e},
586 {0x3737, 0x08},
587 {0x3738, 0xcc},
588 {0x3739, 0x20},
589 {0x373d, 0x26},
590 {0x3764, 0x20},
591 {0x3765, 0x20},
592 {0x37a1, 0x36},
593 {0x37a8, 0x3b},
594 {0x37ab, 0x31},
595 {0x37c2, 0x14},
596 {0x37c3, 0xf1},
597 {0x37c5, 0x00},
598 {0x37d8, 0x03},
599 {0x37d9, 0x0c},
600 {0x37da, 0xc2},
601 {0x37dc, 0x02},
602 {0x37e0, 0x00},
603 {0x37e1, 0x0a},
604 {0x37e2, 0x14},
605 {0x37e3, 0x08},
606 {0x37e4, 0x38},
607 {0x37e5, 0x03},
608 {0x37e6, 0x08},
609 {0x3800, 0x00},
610 {0x3801, 0x00},
611 {0x3802, 0x01},
612 {0x3803, 0x84},
613 {0x3804, 0x10},
614 {0x3805, 0x9f},
615 {0x3806, 0x0a},
616 {0x3807, 0xd3},
617 {0x3808, 0x08},
618 {0x3809, 0x40},
619 {0x380a, 0x04},
620 {0x380b, 0xa4},
621 {0x380c, 0x04},
622 {0x380d, 0x62},
623 {0x380e, 0x0c},
624 {0x380f, 0x8e},
625 {0x3811, 0x08},
626 {0x3813, 0x03},
627 {0x3814, 0x03},
628 {0x3815, 0x01},
629 {0x3816, 0x03},
630 {0x3817, 0x01},
631 {0x3820, 0xab},
632 {0x3821, 0x00},
633 {0x3822, 0xc2},
634 {0x3823, 0x18},
635 {0x3826, 0x04},
636 {0x3827, 0x90},
637 {0x3829, 0x07},
638 {0x3832, 0x00},
639 {0x3c80, 0x00},
640 {0x3c87, 0x01},
641 {0x3c8c, 0x19},
642 {0x3c8d, 0x1c},
643 {0x3c90, 0x00},
644 {0x3c91, 0x00},
645 {0x3c92, 0x00},
646 {0x3c93, 0x00},
647 {0x3c94, 0x40},
648 {0x3c95, 0x54},
649 {0x3c96, 0x34},
650 {0x3c97, 0x04},
651 {0x3c98, 0x00},
652 {0x3d8c, 0x73},
653 {0x3d8d, 0xc0},
654 {0x3f00, 0x0b},
655 {0x3f03, 0x00},
656 {0x4001, 0xe0},
657 {0x4008, 0x00},
658 {0x4009, 0x0d},
659 {0x4011, 0xf0},
660 {0x4017, 0x08},
661 {0x4050, 0x04},
662 {0x4051, 0x0b},
663 {0x4052, 0x00},
664 {0x4053, 0x80},
665 {0x4054, 0x00},
666 {0x4055, 0x80},
667 {0x4056, 0x00},
668 {0x4057, 0x80},
669 {0x4058, 0x00},
670 {0x4059, 0x80},
671 {0x405e, 0x20},
672 {0x4500, 0x07},
673 {0x4503, 0x00},
674 {0x450a, 0x04},
675 {0x4809, 0x04},
676 {0x480c, 0x12},
677 {0x481f, 0x30},
678 {0x4833, 0x10},
679 {0x4837, 0x1c},
680 {0x4902, 0x01},
681 {0x4d00, 0x03},
682 {0x4d01, 0xc9},
683 {0x4d02, 0xbc},
684 {0x4d03, 0xd7},
685 {0x4d04, 0xf0},
686 {0x4d05, 0xa2},
687 {0x5000, 0xfd},
688 {0x5001, 0x01},
689 {0x5040, 0x39},
690 {0x5041, 0x10},
691 {0x5042, 0x10},
692 {0x5043, 0x84},
693 {0x5044, 0x62},
694 {0x5180, 0x00},
695 {0x5181, 0x10},
696 {0x5182, 0x02},
697 {0x5183, 0x0f},
698 {0x5200, 0x1b},
699 {0x520b, 0x07},
700 {0x520c, 0x0f},
701 {0x5300, 0x04},
702 {0x5301, 0x0c},
703 {0x5302, 0x0c},
704 {0x5303, 0x0f},
705 {0x5304, 0x00},
706 {0x5305, 0x70},
707 {0x5306, 0x00},
708 {0x5307, 0x80},
709 {0x5308, 0x00},
710 {0x5309, 0xa5},
711 {0x530a, 0x00},
712 {0x530b, 0xd3},
713 {0x530c, 0x00},
714 {0x530d, 0xf0},
715 {0x530e, 0x01},
716 {0x530f, 0x10},
717 {0x5310, 0x01},
718 {0x5311, 0x20},
719 {0x5312, 0x01},
720 {0x5313, 0x20},
721 {0x5314, 0x01},
722 {0x5315, 0x20},
723 {0x5316, 0x08},
724 {0x5317, 0x08},
725 {0x5318, 0x10},
726 {0x5319, 0x88},
727 {0x531a, 0x88},
728 {0x531b, 0xa9},
729 {0x531c, 0xaa},
730 {0x531d, 0x0a},
731 {0x5405, 0x02},
732 {0x5406, 0x67},
733 {0x5407, 0x01},
734 {0x5408, 0x4a},
735 };
736
737 static const struct ov13858_reg mode_1056x784_regs[] = {
738 {0x3013, 0x32},
739 {0x301b, 0xf0},
740 {0x301f, 0xd0},
741 {0x3106, 0x15},
742 {0x3107, 0x23},
743 {0x350a, 0x00},
744 {0x350e, 0x00},
745 {0x3510, 0x00},
746 {0x3511, 0x02},
747 {0x3512, 0x00},
748 {0x3600, 0x2b},
749 {0x3601, 0x52},
750 {0x3602, 0x60},
751 {0x3612, 0x05},
752 {0x3613, 0xa4},
753 {0x3620, 0x80},
754 {0x3621, 0x10},
755 {0x3622, 0x30},
756 {0x3624, 0x1c},
757 {0x3640, 0x10},
758 {0x3641, 0x70},
759 {0x3660, 0x04},
760 {0x3661, 0x80},
761 {0x3662, 0x08},
762 {0x3664, 0x73},
763 {0x3665, 0xa7},
764 {0x366e, 0xff},
765 {0x366f, 0xf4},
766 {0x3674, 0x00},
767 {0x3679, 0x0c},
768 {0x367f, 0x01},
769 {0x3680, 0x0c},
770 {0x3681, 0x50},
771 {0x3682, 0x50},
772 {0x3683, 0xa9},
773 {0x3684, 0xa9},
774 {0x3709, 0x5f},
775 {0x3714, 0x30},
776 {0x371a, 0x3e},
777 {0x3737, 0x08},
778 {0x3738, 0xcc},
779 {0x3739, 0x20},
780 {0x373d, 0x26},
781 {0x3764, 0x20},
782 {0x3765, 0x20},
783 {0x37a1, 0x36},
784 {0x37a8, 0x3b},
785 {0x37ab, 0x31},
786 {0x37c2, 0x2c},
787 {0x37c3, 0xf1},
788 {0x37c5, 0x00},
789 {0x37d8, 0x03},
790 {0x37d9, 0x06},
791 {0x37da, 0xc2},
792 {0x37dc, 0x02},
793 {0x37e0, 0x00},
794 {0x37e1, 0x0a},
795 {0x37e2, 0x14},
796 {0x37e3, 0x08},
797 {0x37e4, 0x36},
798 {0x37e5, 0x03},
799 {0x37e6, 0x08},
800 {0x3800, 0x00},
801 {0x3801, 0x00},
802 {0x3802, 0x00},
803 {0x3803, 0x00},
804 {0x3804, 0x10},
805 {0x3805, 0x9f},
806 {0x3806, 0x0c},
807 {0x3807, 0x5f},
808 {0x3808, 0x04},
809 {0x3809, 0x20},
810 {0x380a, 0x03},
811 {0x380b, 0x10},
812 {0x380c, 0x04},
813 {0x380d, 0x62},
814 {0x380e, 0x0c},
815 {0x380f, 0x8e},
816 {0x3811, 0x04},
817 {0x3813, 0x05},
818 {0x3814, 0x07},
819 {0x3815, 0x01},
820 {0x3816, 0x07},
821 {0x3817, 0x01},
822 {0x3820, 0xac},
823 {0x3821, 0x00},
824 {0x3822, 0xc2},
825 {0x3823, 0x18},
826 {0x3826, 0x04},
827 {0x3827, 0x48},
828 {0x3829, 0x03},
829 {0x3832, 0x00},
830 {0x3c80, 0x00},
831 {0x3c87, 0x01},
832 {0x3c8c, 0x19},
833 {0x3c8d, 0x1c},
834 {0x3c90, 0x00},
835 {0x3c91, 0x00},
836 {0x3c92, 0x00},
837 {0x3c93, 0x00},
838 {0x3c94, 0x40},
839 {0x3c95, 0x54},
840 {0x3c96, 0x34},
841 {0x3c97, 0x04},
842 {0x3c98, 0x00},
843 {0x3d8c, 0x73},
844 {0x3d8d, 0xc0},
845 {0x3f00, 0x0b},
846 {0x3f03, 0x00},
847 {0x4001, 0xe0},
848 {0x4008, 0x00},
849 {0x4009, 0x05},
850 {0x4011, 0xf0},
851 {0x4017, 0x08},
852 {0x4050, 0x02},
853 {0x4051, 0x05},
854 {0x4052, 0x00},
855 {0x4053, 0x80},
856 {0x4054, 0x00},
857 {0x4055, 0x80},
858 {0x4056, 0x00},
859 {0x4057, 0x80},
860 {0x4058, 0x00},
861 {0x4059, 0x80},
862 {0x405e, 0x20},
863 {0x4500, 0x07},
864 {0x4503, 0x00},
865 {0x450a, 0x04},
866 {0x4809, 0x04},
867 {0x480c, 0x12},
868 {0x481f, 0x30},
869 {0x4833, 0x10},
870 {0x4837, 0x1e},
871 {0x4902, 0x02},
872 {0x4d00, 0x03},
873 {0x4d01, 0xc9},
874 {0x4d02, 0xbc},
875 {0x4d03, 0xd7},
876 {0x4d04, 0xf0},
877 {0x4d05, 0xa2},
878 {0x5000, 0xfd},
879 {0x5001, 0x01},
880 {0x5040, 0x39},
881 {0x5041, 0x10},
882 {0x5042, 0x10},
883 {0x5043, 0x84},
884 {0x5044, 0x62},
885 {0x5180, 0x00},
886 {0x5181, 0x10},
887 {0x5182, 0x02},
888 {0x5183, 0x0f},
889 {0x5200, 0x1b},
890 {0x520b, 0x07},
891 {0x520c, 0x0f},
892 {0x5300, 0x04},
893 {0x5301, 0x0c},
894 {0x5302, 0x0c},
895 {0x5303, 0x0f},
896 {0x5304, 0x00},
897 {0x5305, 0x70},
898 {0x5306, 0x00},
899 {0x5307, 0x80},
900 {0x5308, 0x00},
901 {0x5309, 0xa5},
902 {0x530a, 0x00},
903 {0x530b, 0xd3},
904 {0x530c, 0x00},
905 {0x530d, 0xf0},
906 {0x530e, 0x01},
907 {0x530f, 0x10},
908 {0x5310, 0x01},
909 {0x5311, 0x20},
910 {0x5312, 0x01},
911 {0x5313, 0x20},
912 {0x5314, 0x01},
913 {0x5315, 0x20},
914 {0x5316, 0x08},
915 {0x5317, 0x08},
916 {0x5318, 0x10},
917 {0x5319, 0x88},
918 {0x531a, 0x88},
919 {0x531b, 0xa9},
920 {0x531c, 0xaa},
921 {0x531d, 0x0a},
922 {0x5405, 0x02},
923 {0x5406, 0x67},
924 {0x5407, 0x01},
925 {0x5408, 0x4a},
926 };
927
928 static const char * const ov13858_test_pattern_menu[] = {
929 "Disabled",
930 "Vertical Color Bar Type 1",
931 "Vertical Color Bar Type 2",
932 "Vertical Color Bar Type 3",
933 "Vertical Color Bar Type 4"
934 };
935
936 /* Configurations for supported link frequencies */
937 #define OV13858_NUM_OF_LINK_FREQS 2
938 #define OV13858_LINK_FREQ_540MHZ 540000000ULL
939 #define OV13858_LINK_FREQ_270MHZ 270000000ULL
940 #define OV13858_LINK_FREQ_INDEX_0 0
941 #define OV13858_LINK_FREQ_INDEX_1 1
942
943 /*
944 * pixel_rate = link_freq * data-rate * nr_of_lanes / bits_per_sample
945 * data rate => double data rate; number of lanes => 4; bits per pixel => 10
946 */
link_freq_to_pixel_rate(u64 f)947 static u64 link_freq_to_pixel_rate(u64 f)
948 {
949 f *= 2 * 4;
950 do_div(f, 10);
951
952 return f;
953 }
954
955 /* Menu items for LINK_FREQ V4L2 control */
956 static const s64 link_freq_menu_items[OV13858_NUM_OF_LINK_FREQS] = {
957 OV13858_LINK_FREQ_540MHZ,
958 OV13858_LINK_FREQ_270MHZ
959 };
960
961 /* Link frequency configs */
962 static const struct ov13858_link_freq_config
963 link_freq_configs[OV13858_NUM_OF_LINK_FREQS] = {
964 {
965 .pixels_per_line = OV13858_PPL_540MHZ,
966 .reg_list = {
967 .num_of_regs = ARRAY_SIZE(mipi_data_rate_1080mbps),
968 .regs = mipi_data_rate_1080mbps,
969 }
970 },
971 {
972 .pixels_per_line = OV13858_PPL_270MHZ,
973 .reg_list = {
974 .num_of_regs = ARRAY_SIZE(mipi_data_rate_540mbps),
975 .regs = mipi_data_rate_540mbps,
976 }
977 }
978 };
979
980 /* Mode configs */
981 static const struct ov13858_mode supported_modes[] = {
982 {
983 .width = 4224,
984 .height = 3136,
985 .vts_def = OV13858_VTS_30FPS,
986 .vts_min = OV13858_VTS_30FPS,
987 .reg_list = {
988 .num_of_regs = ARRAY_SIZE(mode_4224x3136_regs),
989 .regs = mode_4224x3136_regs,
990 },
991 .link_freq_index = OV13858_LINK_FREQ_INDEX_0,
992 },
993 {
994 .width = 2112,
995 .height = 1568,
996 .vts_def = OV13858_VTS_30FPS,
997 .vts_min = 1608,
998 .reg_list = {
999 .num_of_regs = ARRAY_SIZE(mode_2112x1568_regs),
1000 .regs = mode_2112x1568_regs,
1001 },
1002 .link_freq_index = OV13858_LINK_FREQ_INDEX_1,
1003 },
1004 {
1005 .width = 2112,
1006 .height = 1188,
1007 .vts_def = OV13858_VTS_30FPS,
1008 .vts_min = 1608,
1009 .reg_list = {
1010 .num_of_regs = ARRAY_SIZE(mode_2112x1188_regs),
1011 .regs = mode_2112x1188_regs,
1012 },
1013 .link_freq_index = OV13858_LINK_FREQ_INDEX_1,
1014 },
1015 {
1016 .width = 1056,
1017 .height = 784,
1018 .vts_def = OV13858_VTS_30FPS,
1019 .vts_min = 804,
1020 .reg_list = {
1021 .num_of_regs = ARRAY_SIZE(mode_1056x784_regs),
1022 .regs = mode_1056x784_regs,
1023 },
1024 .link_freq_index = OV13858_LINK_FREQ_INDEX_1,
1025 }
1026 };
1027
1028 struct ov13858 {
1029 struct v4l2_subdev sd;
1030 struct media_pad pad;
1031
1032 struct v4l2_ctrl_handler ctrl_handler;
1033 /* V4L2 Controls */
1034 struct v4l2_ctrl *link_freq;
1035 struct v4l2_ctrl *pixel_rate;
1036 struct v4l2_ctrl *vblank;
1037 struct v4l2_ctrl *hblank;
1038 struct v4l2_ctrl *exposure;
1039
1040 /* Current mode */
1041 const struct ov13858_mode *cur_mode;
1042
1043 /* Mutex for serialized access */
1044 struct mutex mutex;
1045
1046 /* Streaming on/off */
1047 bool streaming;
1048 };
1049
1050 #define to_ov13858(_sd) container_of(_sd, struct ov13858, sd)
1051
1052 /* Read registers up to 4 at a time */
ov13858_read_reg(struct ov13858 * ov13858,u16 reg,u32 len,u32 * val)1053 static int ov13858_read_reg(struct ov13858 *ov13858, u16 reg, u32 len,
1054 u32 *val)
1055 {
1056 struct i2c_client *client = v4l2_get_subdevdata(&ov13858->sd);
1057 struct i2c_msg msgs[2];
1058 u8 *data_be_p;
1059 int ret;
1060 __be32 data_be = 0;
1061 __be16 reg_addr_be = cpu_to_be16(reg);
1062
1063 if (len > 4)
1064 return -EINVAL;
1065
1066 data_be_p = (u8 *)&data_be;
1067 /* Write register address */
1068 msgs[0].addr = client->addr;
1069 msgs[0].flags = 0;
1070 msgs[0].len = 2;
1071 msgs[0].buf = (u8 *)®_addr_be;
1072
1073 /* Read data from register */
1074 msgs[1].addr = client->addr;
1075 msgs[1].flags = I2C_M_RD;
1076 msgs[1].len = len;
1077 msgs[1].buf = &data_be_p[4 - len];
1078
1079 ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
1080 if (ret != ARRAY_SIZE(msgs))
1081 return -EIO;
1082
1083 *val = be32_to_cpu(data_be);
1084
1085 return 0;
1086 }
1087
1088 /* Write registers up to 4 at a time */
ov13858_write_reg(struct ov13858 * ov13858,u16 reg,u32 len,u32 __val)1089 static int ov13858_write_reg(struct ov13858 *ov13858, u16 reg, u32 len,
1090 u32 __val)
1091 {
1092 struct i2c_client *client = v4l2_get_subdevdata(&ov13858->sd);
1093 int buf_i, val_i;
1094 u8 buf[6], *val_p;
1095 __be32 val;
1096
1097 if (len > 4)
1098 return -EINVAL;
1099
1100 buf[0] = reg >> 8;
1101 buf[1] = reg & 0xff;
1102
1103 val = cpu_to_be32(__val);
1104 val_p = (u8 *)&val;
1105 buf_i = 2;
1106 val_i = 4 - len;
1107
1108 while (val_i < 4)
1109 buf[buf_i++] = val_p[val_i++];
1110
1111 if (i2c_master_send(client, buf, len + 2) != len + 2)
1112 return -EIO;
1113
1114 return 0;
1115 }
1116
1117 /* Write a list of registers */
ov13858_write_regs(struct ov13858 * ov13858,const struct ov13858_reg * regs,u32 len)1118 static int ov13858_write_regs(struct ov13858 *ov13858,
1119 const struct ov13858_reg *regs, u32 len)
1120 {
1121 struct i2c_client *client = v4l2_get_subdevdata(&ov13858->sd);
1122 int ret;
1123 u32 i;
1124
1125 for (i = 0; i < len; i++) {
1126 ret = ov13858_write_reg(ov13858, regs[i].address, 1,
1127 regs[i].val);
1128 if (ret) {
1129 dev_err_ratelimited(
1130 &client->dev,
1131 "Failed to write reg 0x%4.4x. error = %d\n",
1132 regs[i].address, ret);
1133
1134 return ret;
1135 }
1136 }
1137
1138 return 0;
1139 }
1140
ov13858_write_reg_list(struct ov13858 * ov13858,const struct ov13858_reg_list * r_list)1141 static int ov13858_write_reg_list(struct ov13858 *ov13858,
1142 const struct ov13858_reg_list *r_list)
1143 {
1144 return ov13858_write_regs(ov13858, r_list->regs, r_list->num_of_regs);
1145 }
1146
1147 /* Open sub-device */
ov13858_open(struct v4l2_subdev * sd,struct v4l2_subdev_fh * fh)1148 static int ov13858_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
1149 {
1150 struct ov13858 *ov13858 = to_ov13858(sd);
1151 struct v4l2_mbus_framefmt *try_fmt = v4l2_subdev_get_try_format(sd,
1152 fh->pad,
1153 0);
1154
1155 mutex_lock(&ov13858->mutex);
1156
1157 /* Initialize try_fmt */
1158 try_fmt->width = ov13858->cur_mode->width;
1159 try_fmt->height = ov13858->cur_mode->height;
1160 try_fmt->code = MEDIA_BUS_FMT_SGRBG10_1X10;
1161 try_fmt->field = V4L2_FIELD_NONE;
1162
1163 /* No crop or compose */
1164 mutex_unlock(&ov13858->mutex);
1165
1166 return 0;
1167 }
1168
ov13858_update_digital_gain(struct ov13858 * ov13858,u32 d_gain)1169 static int ov13858_update_digital_gain(struct ov13858 *ov13858, u32 d_gain)
1170 {
1171 int ret;
1172
1173 ret = ov13858_write_reg(ov13858, OV13858_REG_B_MWB_GAIN,
1174 OV13858_REG_VALUE_16BIT, d_gain);
1175 if (ret)
1176 return ret;
1177
1178 ret = ov13858_write_reg(ov13858, OV13858_REG_G_MWB_GAIN,
1179 OV13858_REG_VALUE_16BIT, d_gain);
1180 if (ret)
1181 return ret;
1182
1183 ret = ov13858_write_reg(ov13858, OV13858_REG_R_MWB_GAIN,
1184 OV13858_REG_VALUE_16BIT, d_gain);
1185
1186 return ret;
1187 }
1188
ov13858_enable_test_pattern(struct ov13858 * ov13858,u32 pattern)1189 static int ov13858_enable_test_pattern(struct ov13858 *ov13858, u32 pattern)
1190 {
1191 int ret;
1192 u32 val;
1193
1194 ret = ov13858_read_reg(ov13858, OV13858_REG_TEST_PATTERN,
1195 OV13858_REG_VALUE_08BIT, &val);
1196 if (ret)
1197 return ret;
1198
1199 if (pattern) {
1200 val &= OV13858_TEST_PATTERN_MASK;
1201 val |= (pattern - 1) | OV13858_TEST_PATTERN_ENABLE;
1202 } else {
1203 val &= ~OV13858_TEST_PATTERN_ENABLE;
1204 }
1205
1206 return ov13858_write_reg(ov13858, OV13858_REG_TEST_PATTERN,
1207 OV13858_REG_VALUE_08BIT, val);
1208 }
1209
ov13858_set_ctrl(struct v4l2_ctrl * ctrl)1210 static int ov13858_set_ctrl(struct v4l2_ctrl *ctrl)
1211 {
1212 struct ov13858 *ov13858 = container_of(ctrl->handler,
1213 struct ov13858, ctrl_handler);
1214 struct i2c_client *client = v4l2_get_subdevdata(&ov13858->sd);
1215 s64 max;
1216 int ret;
1217
1218 /* Propagate change of current control to all related controls */
1219 switch (ctrl->id) {
1220 case V4L2_CID_VBLANK:
1221 /* Update max exposure while meeting expected vblanking */
1222 max = ov13858->cur_mode->height + ctrl->val - 8;
1223 __v4l2_ctrl_modify_range(ov13858->exposure,
1224 ov13858->exposure->minimum,
1225 max, ov13858->exposure->step, max);
1226 break;
1227 };
1228
1229 /*
1230 * Applying V4L2 control value only happens
1231 * when power is up for streaming
1232 */
1233 if (pm_runtime_get_if_in_use(&client->dev) <= 0)
1234 return 0;
1235
1236 ret = 0;
1237 switch (ctrl->id) {
1238 case V4L2_CID_ANALOGUE_GAIN:
1239 ret = ov13858_write_reg(ov13858, OV13858_REG_ANALOG_GAIN,
1240 OV13858_REG_VALUE_16BIT, ctrl->val);
1241 break;
1242 case V4L2_CID_DIGITAL_GAIN:
1243 ret = ov13858_update_digital_gain(ov13858, ctrl->val);
1244 break;
1245 case V4L2_CID_EXPOSURE:
1246 ret = ov13858_write_reg(ov13858, OV13858_REG_EXPOSURE,
1247 OV13858_REG_VALUE_24BIT,
1248 ctrl->val << 4);
1249 break;
1250 case V4L2_CID_VBLANK:
1251 /* Update VTS that meets expected vertical blanking */
1252 ret = ov13858_write_reg(ov13858, OV13858_REG_VTS,
1253 OV13858_REG_VALUE_16BIT,
1254 ov13858->cur_mode->height
1255 + ctrl->val);
1256 break;
1257 case V4L2_CID_TEST_PATTERN:
1258 ret = ov13858_enable_test_pattern(ov13858, ctrl->val);
1259 break;
1260 default:
1261 dev_info(&client->dev,
1262 "ctrl(id:0x%x,val:0x%x) is not handled\n",
1263 ctrl->id, ctrl->val);
1264 break;
1265 };
1266
1267 pm_runtime_put(&client->dev);
1268
1269 return ret;
1270 }
1271
1272 static const struct v4l2_ctrl_ops ov13858_ctrl_ops = {
1273 .s_ctrl = ov13858_set_ctrl,
1274 };
1275
ov13858_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_mbus_code_enum * code)1276 static int ov13858_enum_mbus_code(struct v4l2_subdev *sd,
1277 struct v4l2_subdev_pad_config *cfg,
1278 struct v4l2_subdev_mbus_code_enum *code)
1279 {
1280 /* Only one bayer order(GRBG) is supported */
1281 if (code->index > 0)
1282 return -EINVAL;
1283
1284 code->code = MEDIA_BUS_FMT_SGRBG10_1X10;
1285
1286 return 0;
1287 }
1288
ov13858_enum_frame_size(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_size_enum * fse)1289 static int ov13858_enum_frame_size(struct v4l2_subdev *sd,
1290 struct v4l2_subdev_pad_config *cfg,
1291 struct v4l2_subdev_frame_size_enum *fse)
1292 {
1293 if (fse->index >= ARRAY_SIZE(supported_modes))
1294 return -EINVAL;
1295
1296 if (fse->code != MEDIA_BUS_FMT_SGRBG10_1X10)
1297 return -EINVAL;
1298
1299 fse->min_width = supported_modes[fse->index].width;
1300 fse->max_width = fse->min_width;
1301 fse->min_height = supported_modes[fse->index].height;
1302 fse->max_height = fse->min_height;
1303
1304 return 0;
1305 }
1306
ov13858_update_pad_format(const struct ov13858_mode * mode,struct v4l2_subdev_format * fmt)1307 static void ov13858_update_pad_format(const struct ov13858_mode *mode,
1308 struct v4l2_subdev_format *fmt)
1309 {
1310 fmt->format.width = mode->width;
1311 fmt->format.height = mode->height;
1312 fmt->format.code = MEDIA_BUS_FMT_SGRBG10_1X10;
1313 fmt->format.field = V4L2_FIELD_NONE;
1314 }
1315
ov13858_do_get_pad_format(struct ov13858 * ov13858,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)1316 static int ov13858_do_get_pad_format(struct ov13858 *ov13858,
1317 struct v4l2_subdev_pad_config *cfg,
1318 struct v4l2_subdev_format *fmt)
1319 {
1320 struct v4l2_mbus_framefmt *framefmt;
1321 struct v4l2_subdev *sd = &ov13858->sd;
1322
1323 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
1324 framefmt = v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
1325 fmt->format = *framefmt;
1326 } else {
1327 ov13858_update_pad_format(ov13858->cur_mode, fmt);
1328 }
1329
1330 return 0;
1331 }
1332
ov13858_get_pad_format(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)1333 static int ov13858_get_pad_format(struct v4l2_subdev *sd,
1334 struct v4l2_subdev_pad_config *cfg,
1335 struct v4l2_subdev_format *fmt)
1336 {
1337 struct ov13858 *ov13858 = to_ov13858(sd);
1338 int ret;
1339
1340 mutex_lock(&ov13858->mutex);
1341 ret = ov13858_do_get_pad_format(ov13858, cfg, fmt);
1342 mutex_unlock(&ov13858->mutex);
1343
1344 return ret;
1345 }
1346
1347 static int
ov13858_set_pad_format(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)1348 ov13858_set_pad_format(struct v4l2_subdev *sd,
1349 struct v4l2_subdev_pad_config *cfg,
1350 struct v4l2_subdev_format *fmt)
1351 {
1352 struct ov13858 *ov13858 = to_ov13858(sd);
1353 const struct ov13858_mode *mode;
1354 struct v4l2_mbus_framefmt *framefmt;
1355 s32 vblank_def;
1356 s32 vblank_min;
1357 s64 h_blank;
1358 s64 pixel_rate;
1359 s64 link_freq;
1360
1361 mutex_lock(&ov13858->mutex);
1362
1363 /* Only one raw bayer(GRBG) order is supported */
1364 if (fmt->format.code != MEDIA_BUS_FMT_SGRBG10_1X10)
1365 fmt->format.code = MEDIA_BUS_FMT_SGRBG10_1X10;
1366
1367 mode = v4l2_find_nearest_size(supported_modes,
1368 ARRAY_SIZE(supported_modes),
1369 width, height,
1370 fmt->format.width, fmt->format.height);
1371 ov13858_update_pad_format(mode, fmt);
1372 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
1373 framefmt = v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
1374 *framefmt = fmt->format;
1375 } else {
1376 ov13858->cur_mode = mode;
1377 __v4l2_ctrl_s_ctrl(ov13858->link_freq, mode->link_freq_index);
1378 link_freq = link_freq_menu_items[mode->link_freq_index];
1379 pixel_rate = link_freq_to_pixel_rate(link_freq);
1380 __v4l2_ctrl_s_ctrl_int64(ov13858->pixel_rate, pixel_rate);
1381
1382 /* Update limits and set FPS to default */
1383 vblank_def = ov13858->cur_mode->vts_def -
1384 ov13858->cur_mode->height;
1385 vblank_min = ov13858->cur_mode->vts_min -
1386 ov13858->cur_mode->height;
1387 __v4l2_ctrl_modify_range(
1388 ov13858->vblank, vblank_min,
1389 OV13858_VTS_MAX - ov13858->cur_mode->height, 1,
1390 vblank_def);
1391 __v4l2_ctrl_s_ctrl(ov13858->vblank, vblank_def);
1392 h_blank =
1393 link_freq_configs[mode->link_freq_index].pixels_per_line
1394 - ov13858->cur_mode->width;
1395 __v4l2_ctrl_modify_range(ov13858->hblank, h_blank,
1396 h_blank, 1, h_blank);
1397 }
1398
1399 mutex_unlock(&ov13858->mutex);
1400
1401 return 0;
1402 }
1403
ov13858_get_skip_frames(struct v4l2_subdev * sd,u32 * frames)1404 static int ov13858_get_skip_frames(struct v4l2_subdev *sd, u32 *frames)
1405 {
1406 *frames = OV13858_NUM_OF_SKIP_FRAMES;
1407
1408 return 0;
1409 }
1410
1411 /* Start streaming */
ov13858_start_streaming(struct ov13858 * ov13858)1412 static int ov13858_start_streaming(struct ov13858 *ov13858)
1413 {
1414 struct i2c_client *client = v4l2_get_subdevdata(&ov13858->sd);
1415 const struct ov13858_reg_list *reg_list;
1416 int ret, link_freq_index;
1417
1418 /* Get out of from software reset */
1419 ret = ov13858_write_reg(ov13858, OV13858_REG_SOFTWARE_RST,
1420 OV13858_REG_VALUE_08BIT, OV13858_SOFTWARE_RST);
1421 if (ret) {
1422 dev_err(&client->dev, "%s failed to set powerup registers\n",
1423 __func__);
1424 return ret;
1425 }
1426
1427 /* Setup PLL */
1428 link_freq_index = ov13858->cur_mode->link_freq_index;
1429 reg_list = &link_freq_configs[link_freq_index].reg_list;
1430 ret = ov13858_write_reg_list(ov13858, reg_list);
1431 if (ret) {
1432 dev_err(&client->dev, "%s failed to set plls\n", __func__);
1433 return ret;
1434 }
1435
1436 /* Apply default values of current mode */
1437 reg_list = &ov13858->cur_mode->reg_list;
1438 ret = ov13858_write_reg_list(ov13858, reg_list);
1439 if (ret) {
1440 dev_err(&client->dev, "%s failed to set mode\n", __func__);
1441 return ret;
1442 }
1443
1444 /* Apply customized values from user */
1445 ret = __v4l2_ctrl_handler_setup(ov13858->sd.ctrl_handler);
1446 if (ret)
1447 return ret;
1448
1449 return ov13858_write_reg(ov13858, OV13858_REG_MODE_SELECT,
1450 OV13858_REG_VALUE_08BIT,
1451 OV13858_MODE_STREAMING);
1452 }
1453
1454 /* Stop streaming */
ov13858_stop_streaming(struct ov13858 * ov13858)1455 static int ov13858_stop_streaming(struct ov13858 *ov13858)
1456 {
1457 return ov13858_write_reg(ov13858, OV13858_REG_MODE_SELECT,
1458 OV13858_REG_VALUE_08BIT, OV13858_MODE_STANDBY);
1459 }
1460
ov13858_set_stream(struct v4l2_subdev * sd,int enable)1461 static int ov13858_set_stream(struct v4l2_subdev *sd, int enable)
1462 {
1463 struct ov13858 *ov13858 = to_ov13858(sd);
1464 struct i2c_client *client = v4l2_get_subdevdata(sd);
1465 int ret = 0;
1466
1467 mutex_lock(&ov13858->mutex);
1468 if (ov13858->streaming == enable) {
1469 mutex_unlock(&ov13858->mutex);
1470 return 0;
1471 }
1472
1473 if (enable) {
1474 ret = pm_runtime_get_sync(&client->dev);
1475 if (ret < 0) {
1476 pm_runtime_put_noidle(&client->dev);
1477 goto err_unlock;
1478 }
1479
1480 /*
1481 * Apply default & customized values
1482 * and then start streaming.
1483 */
1484 ret = ov13858_start_streaming(ov13858);
1485 if (ret)
1486 goto err_rpm_put;
1487 } else {
1488 ov13858_stop_streaming(ov13858);
1489 pm_runtime_put(&client->dev);
1490 }
1491
1492 ov13858->streaming = enable;
1493 mutex_unlock(&ov13858->mutex);
1494
1495 return ret;
1496
1497 err_rpm_put:
1498 pm_runtime_put(&client->dev);
1499 err_unlock:
1500 mutex_unlock(&ov13858->mutex);
1501
1502 return ret;
1503 }
1504
ov13858_suspend(struct device * dev)1505 static int __maybe_unused ov13858_suspend(struct device *dev)
1506 {
1507 struct i2c_client *client = to_i2c_client(dev);
1508 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1509 struct ov13858 *ov13858 = to_ov13858(sd);
1510
1511 if (ov13858->streaming)
1512 ov13858_stop_streaming(ov13858);
1513
1514 return 0;
1515 }
1516
ov13858_resume(struct device * dev)1517 static int __maybe_unused ov13858_resume(struct device *dev)
1518 {
1519 struct i2c_client *client = to_i2c_client(dev);
1520 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1521 struct ov13858 *ov13858 = to_ov13858(sd);
1522 int ret;
1523
1524 if (ov13858->streaming) {
1525 ret = ov13858_start_streaming(ov13858);
1526 if (ret)
1527 goto error;
1528 }
1529
1530 return 0;
1531
1532 error:
1533 ov13858_stop_streaming(ov13858);
1534 ov13858->streaming = false;
1535 return ret;
1536 }
1537
1538 /* Verify chip ID */
ov13858_identify_module(struct ov13858 * ov13858)1539 static int ov13858_identify_module(struct ov13858 *ov13858)
1540 {
1541 struct i2c_client *client = v4l2_get_subdevdata(&ov13858->sd);
1542 int ret;
1543 u32 val;
1544
1545 ret = ov13858_read_reg(ov13858, OV13858_REG_CHIP_ID,
1546 OV13858_REG_VALUE_24BIT, &val);
1547 if (ret)
1548 return ret;
1549
1550 if (val != OV13858_CHIP_ID) {
1551 dev_err(&client->dev, "chip id mismatch: %x!=%x\n",
1552 OV13858_CHIP_ID, val);
1553 return -EIO;
1554 }
1555
1556 return 0;
1557 }
1558
1559 static const struct v4l2_subdev_video_ops ov13858_video_ops = {
1560 .s_stream = ov13858_set_stream,
1561 };
1562
1563 static const struct v4l2_subdev_pad_ops ov13858_pad_ops = {
1564 .enum_mbus_code = ov13858_enum_mbus_code,
1565 .get_fmt = ov13858_get_pad_format,
1566 .set_fmt = ov13858_set_pad_format,
1567 .enum_frame_size = ov13858_enum_frame_size,
1568 };
1569
1570 static const struct v4l2_subdev_sensor_ops ov13858_sensor_ops = {
1571 .g_skip_frames = ov13858_get_skip_frames,
1572 };
1573
1574 static const struct v4l2_subdev_ops ov13858_subdev_ops = {
1575 .video = &ov13858_video_ops,
1576 .pad = &ov13858_pad_ops,
1577 .sensor = &ov13858_sensor_ops,
1578 };
1579
1580 static const struct media_entity_operations ov13858_subdev_entity_ops = {
1581 .link_validate = v4l2_subdev_link_validate,
1582 };
1583
1584 static const struct v4l2_subdev_internal_ops ov13858_internal_ops = {
1585 .open = ov13858_open,
1586 };
1587
1588 /* Initialize control handlers */
ov13858_init_controls(struct ov13858 * ov13858)1589 static int ov13858_init_controls(struct ov13858 *ov13858)
1590 {
1591 struct i2c_client *client = v4l2_get_subdevdata(&ov13858->sd);
1592 struct v4l2_ctrl_handler *ctrl_hdlr;
1593 s64 exposure_max;
1594 s64 vblank_def;
1595 s64 vblank_min;
1596 s64 hblank;
1597 s64 pixel_rate_min;
1598 s64 pixel_rate_max;
1599 const struct ov13858_mode *mode;
1600 int ret;
1601
1602 ctrl_hdlr = &ov13858->ctrl_handler;
1603 ret = v4l2_ctrl_handler_init(ctrl_hdlr, 8);
1604 if (ret)
1605 return ret;
1606
1607 mutex_init(&ov13858->mutex);
1608 ctrl_hdlr->lock = &ov13858->mutex;
1609 ov13858->link_freq = v4l2_ctrl_new_int_menu(ctrl_hdlr,
1610 &ov13858_ctrl_ops,
1611 V4L2_CID_LINK_FREQ,
1612 OV13858_NUM_OF_LINK_FREQS - 1,
1613 0,
1614 link_freq_menu_items);
1615 ov13858->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1616
1617 pixel_rate_max = link_freq_to_pixel_rate(link_freq_menu_items[0]);
1618 pixel_rate_min = link_freq_to_pixel_rate(link_freq_menu_items[1]);
1619 /* By default, PIXEL_RATE is read only */
1620 ov13858->pixel_rate = v4l2_ctrl_new_std(ctrl_hdlr, &ov13858_ctrl_ops,
1621 V4L2_CID_PIXEL_RATE,
1622 pixel_rate_min, pixel_rate_max,
1623 1, pixel_rate_max);
1624
1625 mode = ov13858->cur_mode;
1626 vblank_def = mode->vts_def - mode->height;
1627 vblank_min = mode->vts_min - mode->height;
1628 ov13858->vblank = v4l2_ctrl_new_std(
1629 ctrl_hdlr, &ov13858_ctrl_ops, V4L2_CID_VBLANK,
1630 vblank_min, OV13858_VTS_MAX - mode->height, 1,
1631 vblank_def);
1632
1633 hblank = link_freq_configs[mode->link_freq_index].pixels_per_line -
1634 mode->width;
1635 ov13858->hblank = v4l2_ctrl_new_std(
1636 ctrl_hdlr, &ov13858_ctrl_ops, V4L2_CID_HBLANK,
1637 hblank, hblank, 1, hblank);
1638 ov13858->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1639
1640 exposure_max = mode->vts_def - 8;
1641 ov13858->exposure = v4l2_ctrl_new_std(
1642 ctrl_hdlr, &ov13858_ctrl_ops,
1643 V4L2_CID_EXPOSURE, OV13858_EXPOSURE_MIN,
1644 exposure_max, OV13858_EXPOSURE_STEP,
1645 OV13858_EXPOSURE_DEFAULT);
1646
1647 v4l2_ctrl_new_std(ctrl_hdlr, &ov13858_ctrl_ops, V4L2_CID_ANALOGUE_GAIN,
1648 OV13858_ANA_GAIN_MIN, OV13858_ANA_GAIN_MAX,
1649 OV13858_ANA_GAIN_STEP, OV13858_ANA_GAIN_DEFAULT);
1650
1651 /* Digital gain */
1652 v4l2_ctrl_new_std(ctrl_hdlr, &ov13858_ctrl_ops, V4L2_CID_DIGITAL_GAIN,
1653 OV13858_DGTL_GAIN_MIN, OV13858_DGTL_GAIN_MAX,
1654 OV13858_DGTL_GAIN_STEP, OV13858_DGTL_GAIN_DEFAULT);
1655
1656 v4l2_ctrl_new_std_menu_items(ctrl_hdlr, &ov13858_ctrl_ops,
1657 V4L2_CID_TEST_PATTERN,
1658 ARRAY_SIZE(ov13858_test_pattern_menu) - 1,
1659 0, 0, ov13858_test_pattern_menu);
1660 if (ctrl_hdlr->error) {
1661 ret = ctrl_hdlr->error;
1662 dev_err(&client->dev, "%s control init failed (%d)\n",
1663 __func__, ret);
1664 goto error;
1665 }
1666
1667 ov13858->sd.ctrl_handler = ctrl_hdlr;
1668
1669 return 0;
1670
1671 error:
1672 v4l2_ctrl_handler_free(ctrl_hdlr);
1673 mutex_destroy(&ov13858->mutex);
1674
1675 return ret;
1676 }
1677
ov13858_free_controls(struct ov13858 * ov13858)1678 static void ov13858_free_controls(struct ov13858 *ov13858)
1679 {
1680 v4l2_ctrl_handler_free(ov13858->sd.ctrl_handler);
1681 mutex_destroy(&ov13858->mutex);
1682 }
1683
ov13858_probe(struct i2c_client * client,const struct i2c_device_id * devid)1684 static int ov13858_probe(struct i2c_client *client,
1685 const struct i2c_device_id *devid)
1686 {
1687 struct ov13858 *ov13858;
1688 int ret;
1689 u32 val = 0;
1690
1691 device_property_read_u32(&client->dev, "clock-frequency", &val);
1692 if (val != 19200000)
1693 return -EINVAL;
1694
1695 ov13858 = devm_kzalloc(&client->dev, sizeof(*ov13858), GFP_KERNEL);
1696 if (!ov13858)
1697 return -ENOMEM;
1698
1699 /* Initialize subdev */
1700 v4l2_i2c_subdev_init(&ov13858->sd, client, &ov13858_subdev_ops);
1701
1702 /* Check module identity */
1703 ret = ov13858_identify_module(ov13858);
1704 if (ret) {
1705 dev_err(&client->dev, "failed to find sensor: %d\n", ret);
1706 return ret;
1707 }
1708
1709 /* Set default mode to max resolution */
1710 ov13858->cur_mode = &supported_modes[0];
1711
1712 ret = ov13858_init_controls(ov13858);
1713 if (ret)
1714 return ret;
1715
1716 /* Initialize subdev */
1717 ov13858->sd.internal_ops = &ov13858_internal_ops;
1718 ov13858->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1719 ov13858->sd.entity.ops = &ov13858_subdev_entity_ops;
1720 ov13858->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
1721
1722 /* Initialize source pad */
1723 ov13858->pad.flags = MEDIA_PAD_FL_SOURCE;
1724 ret = media_entity_pads_init(&ov13858->sd.entity, 1, &ov13858->pad);
1725 if (ret) {
1726 dev_err(&client->dev, "%s failed:%d\n", __func__, ret);
1727 goto error_handler_free;
1728 }
1729
1730 ret = v4l2_async_register_subdev_sensor_common(&ov13858->sd);
1731 if (ret < 0)
1732 goto error_media_entity;
1733
1734 /*
1735 * Device is already turned on by i2c-core with ACPI domain PM.
1736 * Enable runtime PM and turn off the device.
1737 */
1738 pm_runtime_get_noresume(&client->dev);
1739 pm_runtime_set_active(&client->dev);
1740 pm_runtime_enable(&client->dev);
1741 pm_runtime_put(&client->dev);
1742
1743 return 0;
1744
1745 error_media_entity:
1746 media_entity_cleanup(&ov13858->sd.entity);
1747
1748 error_handler_free:
1749 ov13858_free_controls(ov13858);
1750 dev_err(&client->dev, "%s failed:%d\n", __func__, ret);
1751
1752 return ret;
1753 }
1754
ov13858_remove(struct i2c_client * client)1755 static int ov13858_remove(struct i2c_client *client)
1756 {
1757 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1758 struct ov13858 *ov13858 = to_ov13858(sd);
1759
1760 v4l2_async_unregister_subdev(sd);
1761 media_entity_cleanup(&sd->entity);
1762 ov13858_free_controls(ov13858);
1763
1764 /*
1765 * Disable runtime PM but keep the device turned on.
1766 * i2c-core with ACPI domain PM will turn off the device.
1767 */
1768 pm_runtime_get_sync(&client->dev);
1769 pm_runtime_disable(&client->dev);
1770 pm_runtime_set_suspended(&client->dev);
1771 pm_runtime_put_noidle(&client->dev);
1772
1773 return 0;
1774 }
1775
1776 static const struct i2c_device_id ov13858_id_table[] = {
1777 {"ov13858", 0},
1778 {},
1779 };
1780
1781 MODULE_DEVICE_TABLE(i2c, ov13858_id_table);
1782
1783 static const struct dev_pm_ops ov13858_pm_ops = {
1784 SET_SYSTEM_SLEEP_PM_OPS(ov13858_suspend, ov13858_resume)
1785 };
1786
1787 #ifdef CONFIG_ACPI
1788 static const struct acpi_device_id ov13858_acpi_ids[] = {
1789 {"OVTID858"},
1790 { /* sentinel */ }
1791 };
1792
1793 MODULE_DEVICE_TABLE(acpi, ov13858_acpi_ids);
1794 #endif
1795
1796 static struct i2c_driver ov13858_i2c_driver = {
1797 .driver = {
1798 .name = "ov13858",
1799 .pm = &ov13858_pm_ops,
1800 .acpi_match_table = ACPI_PTR(ov13858_acpi_ids),
1801 },
1802 .probe = ov13858_probe,
1803 .remove = ov13858_remove,
1804 .id_table = ov13858_id_table,
1805 };
1806
1807 module_i2c_driver(ov13858_i2c_driver);
1808
1809 MODULE_AUTHOR("Kan, Chris <chris.kan@intel.com>");
1810 MODULE_AUTHOR("Rapolu, Chiranjeevi <chiranjeevi.rapolu@intel.com>");
1811 MODULE_AUTHOR("Yang, Hyungwoo <hyungwoo.yang@intel.com>");
1812 MODULE_DESCRIPTION("Omnivision ov13858 sensor driver");
1813 MODULE_LICENSE("GPL v2");
1814
