1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Driver for MT9T001 CMOS Image Sensor from Aptina (Micron)
4 *
5 * Copyright (C) 2010-2011, Laurent Pinchart <laurent.pinchart@ideasonboard.com>
6 *
7 * Based on the MT9M001 driver,
8 *
9 * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
10 */
11
12 #include <linux/clk.h>
13 #include <linux/i2c.h>
14 #include <linux/log2.h>
15 #include <linux/module.h>
16 #include <linux/regulator/consumer.h>
17 #include <linux/slab.h>
18 #include <linux/videodev2.h>
19 #include <linux/v4l2-mediabus.h>
20
21 #include <media/i2c/mt9t001.h>
22 #include <media/v4l2-ctrls.h>
23 #include <media/v4l2-device.h>
24 #include <media/v4l2-subdev.h>
25
26 #define MT9T001_PIXEL_ARRAY_HEIGHT 1568
27 #define MT9T001_PIXEL_ARRAY_WIDTH 2112
28
29 #define MT9T001_CHIP_VERSION 0x00
30 #define MT9T001_CHIP_ID 0x1621
31 #define MT9T001_ROW_START 0x01
32 #define MT9T001_ROW_START_MIN 0
33 #define MT9T001_ROW_START_DEF 20
34 #define MT9T001_ROW_START_MAX 1534
35 #define MT9T001_COLUMN_START 0x02
36 #define MT9T001_COLUMN_START_MIN 0
37 #define MT9T001_COLUMN_START_DEF 32
38 #define MT9T001_COLUMN_START_MAX 2046
39 #define MT9T001_WINDOW_HEIGHT 0x03
40 #define MT9T001_WINDOW_HEIGHT_MIN 1
41 #define MT9T001_WINDOW_HEIGHT_DEF 1535
42 #define MT9T001_WINDOW_HEIGHT_MAX 1567
43 #define MT9T001_WINDOW_WIDTH 0x04
44 #define MT9T001_WINDOW_WIDTH_MIN 1
45 #define MT9T001_WINDOW_WIDTH_DEF 2047
46 #define MT9T001_WINDOW_WIDTH_MAX 2111
47 #define MT9T001_HORIZONTAL_BLANKING 0x05
48 #define MT9T001_HORIZONTAL_BLANKING_MIN 21
49 #define MT9T001_HORIZONTAL_BLANKING_MAX 1023
50 #define MT9T001_VERTICAL_BLANKING 0x06
51 #define MT9T001_VERTICAL_BLANKING_MIN 3
52 #define MT9T001_VERTICAL_BLANKING_MAX 1023
53 #define MT9T001_OUTPUT_CONTROL 0x07
54 #define MT9T001_OUTPUT_CONTROL_SYNC (1 << 0)
55 #define MT9T001_OUTPUT_CONTROL_CHIP_ENABLE (1 << 1)
56 #define MT9T001_OUTPUT_CONTROL_TEST_DATA (1 << 6)
57 #define MT9T001_OUTPUT_CONTROL_DEF 0x0002
58 #define MT9T001_SHUTTER_WIDTH_HIGH 0x08
59 #define MT9T001_SHUTTER_WIDTH_LOW 0x09
60 #define MT9T001_SHUTTER_WIDTH_MIN 1
61 #define MT9T001_SHUTTER_WIDTH_DEF 1561
62 #define MT9T001_SHUTTER_WIDTH_MAX (1024 * 1024)
63 #define MT9T001_PIXEL_CLOCK 0x0a
64 #define MT9T001_PIXEL_CLOCK_INVERT (1 << 15)
65 #define MT9T001_PIXEL_CLOCK_SHIFT_MASK (7 << 8)
66 #define MT9T001_PIXEL_CLOCK_SHIFT_SHIFT 8
67 #define MT9T001_PIXEL_CLOCK_DIVIDE_MASK (0x7f << 0)
68 #define MT9T001_FRAME_RESTART 0x0b
69 #define MT9T001_SHUTTER_DELAY 0x0c
70 #define MT9T001_SHUTTER_DELAY_MAX 2047
71 #define MT9T001_RESET 0x0d
72 #define MT9T001_READ_MODE1 0x1e
73 #define MT9T001_READ_MODE_SNAPSHOT (1 << 8)
74 #define MT9T001_READ_MODE_STROBE_ENABLE (1 << 9)
75 #define MT9T001_READ_MODE_STROBE_WIDTH (1 << 10)
76 #define MT9T001_READ_MODE_STROBE_OVERRIDE (1 << 11)
77 #define MT9T001_READ_MODE2 0x20
78 #define MT9T001_READ_MODE_BAD_FRAMES (1 << 0)
79 #define MT9T001_READ_MODE_LINE_VALID_CONTINUOUS (1 << 9)
80 #define MT9T001_READ_MODE_LINE_VALID_FRAME (1 << 10)
81 #define MT9T001_READ_MODE3 0x21
82 #define MT9T001_READ_MODE_GLOBAL_RESET (1 << 0)
83 #define MT9T001_READ_MODE_GHST_CTL (1 << 1)
84 #define MT9T001_ROW_ADDRESS_MODE 0x22
85 #define MT9T001_ROW_SKIP_MASK (7 << 0)
86 #define MT9T001_ROW_BIN_MASK (3 << 3)
87 #define MT9T001_ROW_BIN_SHIFT 3
88 #define MT9T001_COLUMN_ADDRESS_MODE 0x23
89 #define MT9T001_COLUMN_SKIP_MASK (7 << 0)
90 #define MT9T001_COLUMN_BIN_MASK (3 << 3)
91 #define MT9T001_COLUMN_BIN_SHIFT 3
92 #define MT9T001_GREEN1_GAIN 0x2b
93 #define MT9T001_BLUE_GAIN 0x2c
94 #define MT9T001_RED_GAIN 0x2d
95 #define MT9T001_GREEN2_GAIN 0x2e
96 #define MT9T001_TEST_DATA 0x32
97 #define MT9T001_GLOBAL_GAIN 0x35
98 #define MT9T001_GLOBAL_GAIN_MIN 8
99 #define MT9T001_GLOBAL_GAIN_MAX 1024
100 #define MT9T001_BLACK_LEVEL 0x49
101 #define MT9T001_ROW_BLACK_DEFAULT_OFFSET 0x4b
102 #define MT9T001_BLC_DELTA_THRESHOLDS 0x5d
103 #define MT9T001_CAL_THRESHOLDS 0x5f
104 #define MT9T001_GREEN1_OFFSET 0x60
105 #define MT9T001_GREEN2_OFFSET 0x61
106 #define MT9T001_BLACK_LEVEL_CALIBRATION 0x62
107 #define MT9T001_BLACK_LEVEL_OVERRIDE (1 << 0)
108 #define MT9T001_BLACK_LEVEL_DISABLE_OFFSET (1 << 1)
109 #define MT9T001_BLACK_LEVEL_RECALCULATE (1 << 12)
110 #define MT9T001_BLACK_LEVEL_LOCK_RED_BLUE (1 << 13)
111 #define MT9T001_BLACK_LEVEL_LOCK_GREEN (1 << 14)
112 #define MT9T001_RED_OFFSET 0x63
113 #define MT9T001_BLUE_OFFSET 0x64
114
115 struct mt9t001 {
116 struct v4l2_subdev subdev;
117 struct media_pad pad;
118
119 struct clk *clk;
120 struct regulator_bulk_data regulators[2];
121
122 struct mutex power_lock; /* lock to protect power_count */
123 int power_count;
124
125 struct v4l2_mbus_framefmt format;
126 struct v4l2_rect crop;
127
128 struct v4l2_ctrl_handler ctrls;
129 struct v4l2_ctrl *gains[4];
130
131 u16 output_control;
132 u16 black_level;
133 };
134
to_mt9t001(struct v4l2_subdev * sd)135 static inline struct mt9t001 *to_mt9t001(struct v4l2_subdev *sd)
136 {
137 return container_of(sd, struct mt9t001, subdev);
138 }
139
mt9t001_read(struct i2c_client * client,u8 reg)140 static int mt9t001_read(struct i2c_client *client, u8 reg)
141 {
142 return i2c_smbus_read_word_swapped(client, reg);
143 }
144
mt9t001_write(struct i2c_client * client,u8 reg,u16 data)145 static int mt9t001_write(struct i2c_client *client, u8 reg, u16 data)
146 {
147 return i2c_smbus_write_word_swapped(client, reg, data);
148 }
149
mt9t001_set_output_control(struct mt9t001 * mt9t001,u16 clear,u16 set)150 static int mt9t001_set_output_control(struct mt9t001 *mt9t001, u16 clear,
151 u16 set)
152 {
153 struct i2c_client *client = v4l2_get_subdevdata(&mt9t001->subdev);
154 u16 value = (mt9t001->output_control & ~clear) | set;
155 int ret;
156
157 if (value == mt9t001->output_control)
158 return 0;
159
160 ret = mt9t001_write(client, MT9T001_OUTPUT_CONTROL, value);
161 if (ret < 0)
162 return ret;
163
164 mt9t001->output_control = value;
165 return 0;
166 }
167
mt9t001_reset(struct mt9t001 * mt9t001)168 static int mt9t001_reset(struct mt9t001 *mt9t001)
169 {
170 struct i2c_client *client = v4l2_get_subdevdata(&mt9t001->subdev);
171 int ret;
172
173 /* Reset the chip and stop data read out */
174 ret = mt9t001_write(client, MT9T001_RESET, 1);
175 if (ret < 0)
176 return ret;
177
178 ret = mt9t001_write(client, MT9T001_RESET, 0);
179 if (ret < 0)
180 return ret;
181
182 mt9t001->output_control = MT9T001_OUTPUT_CONTROL_DEF;
183
184 return mt9t001_set_output_control(mt9t001,
185 MT9T001_OUTPUT_CONTROL_CHIP_ENABLE,
186 0);
187 }
188
mt9t001_power_on(struct mt9t001 * mt9t001)189 static int mt9t001_power_on(struct mt9t001 *mt9t001)
190 {
191 int ret;
192
193 /* Bring up the supplies */
194 ret = regulator_bulk_enable(ARRAY_SIZE(mt9t001->regulators),
195 mt9t001->regulators);
196 if (ret < 0)
197 return ret;
198
199 /* Enable clock */
200 ret = clk_prepare_enable(mt9t001->clk);
201 if (ret < 0)
202 regulator_bulk_disable(ARRAY_SIZE(mt9t001->regulators),
203 mt9t001->regulators);
204
205 return ret;
206 }
207
mt9t001_power_off(struct mt9t001 * mt9t001)208 static void mt9t001_power_off(struct mt9t001 *mt9t001)
209 {
210 regulator_bulk_disable(ARRAY_SIZE(mt9t001->regulators),
211 mt9t001->regulators);
212
213 clk_disable_unprepare(mt9t001->clk);
214 }
215
__mt9t001_set_power(struct mt9t001 * mt9t001,bool on)216 static int __mt9t001_set_power(struct mt9t001 *mt9t001, bool on)
217 {
218 struct i2c_client *client = v4l2_get_subdevdata(&mt9t001->subdev);
219 int ret;
220
221 if (!on) {
222 mt9t001_power_off(mt9t001);
223 return 0;
224 }
225
226 ret = mt9t001_power_on(mt9t001);
227 if (ret < 0)
228 return ret;
229
230 ret = mt9t001_reset(mt9t001);
231 if (ret < 0) {
232 dev_err(&client->dev, "Failed to reset the camera\n");
233 goto e_power;
234 }
235
236 ret = v4l2_ctrl_handler_setup(&mt9t001->ctrls);
237 if (ret < 0) {
238 dev_err(&client->dev, "Failed to set up control handlers\n");
239 goto e_power;
240 }
241
242 return 0;
243
244 e_power:
245 mt9t001_power_off(mt9t001);
246
247 return ret;
248 }
249
250 /* -----------------------------------------------------------------------------
251 * V4L2 subdev video operations
252 */
253
254 static struct v4l2_mbus_framefmt *
__mt9t001_get_pad_format(struct mt9t001 * mt9t001,struct v4l2_subdev_pad_config * cfg,unsigned int pad,enum v4l2_subdev_format_whence which)255 __mt9t001_get_pad_format(struct mt9t001 *mt9t001, struct v4l2_subdev_pad_config *cfg,
256 unsigned int pad, enum v4l2_subdev_format_whence which)
257 {
258 switch (which) {
259 case V4L2_SUBDEV_FORMAT_TRY:
260 return v4l2_subdev_get_try_format(&mt9t001->subdev, cfg, pad);
261 case V4L2_SUBDEV_FORMAT_ACTIVE:
262 return &mt9t001->format;
263 default:
264 return NULL;
265 }
266 }
267
268 static struct v4l2_rect *
__mt9t001_get_pad_crop(struct mt9t001 * mt9t001,struct v4l2_subdev_pad_config * cfg,unsigned int pad,enum v4l2_subdev_format_whence which)269 __mt9t001_get_pad_crop(struct mt9t001 *mt9t001, struct v4l2_subdev_pad_config *cfg,
270 unsigned int pad, enum v4l2_subdev_format_whence which)
271 {
272 switch (which) {
273 case V4L2_SUBDEV_FORMAT_TRY:
274 return v4l2_subdev_get_try_crop(&mt9t001->subdev, cfg, pad);
275 case V4L2_SUBDEV_FORMAT_ACTIVE:
276 return &mt9t001->crop;
277 default:
278 return NULL;
279 }
280 }
281
mt9t001_s_stream(struct v4l2_subdev * subdev,int enable)282 static int mt9t001_s_stream(struct v4l2_subdev *subdev, int enable)
283 {
284 const u16 mode = MT9T001_OUTPUT_CONTROL_CHIP_ENABLE;
285 struct i2c_client *client = v4l2_get_subdevdata(subdev);
286 struct mt9t001_platform_data *pdata = client->dev.platform_data;
287 struct mt9t001 *mt9t001 = to_mt9t001(subdev);
288 struct v4l2_mbus_framefmt *format = &mt9t001->format;
289 struct v4l2_rect *crop = &mt9t001->crop;
290 unsigned int hratio;
291 unsigned int vratio;
292 int ret;
293
294 if (!enable)
295 return mt9t001_set_output_control(mt9t001, mode, 0);
296
297 /* Configure the pixel clock polarity */
298 if (pdata->clk_pol) {
299 ret = mt9t001_write(client, MT9T001_PIXEL_CLOCK,
300 MT9T001_PIXEL_CLOCK_INVERT);
301 if (ret < 0)
302 return ret;
303 }
304
305 /* Configure the window size and row/column bin */
306 hratio = DIV_ROUND_CLOSEST(crop->width, format->width);
307 vratio = DIV_ROUND_CLOSEST(crop->height, format->height);
308
309 ret = mt9t001_write(client, MT9T001_ROW_ADDRESS_MODE, hratio - 1);
310 if (ret < 0)
311 return ret;
312
313 ret = mt9t001_write(client, MT9T001_COLUMN_ADDRESS_MODE, vratio - 1);
314 if (ret < 0)
315 return ret;
316
317 ret = mt9t001_write(client, MT9T001_COLUMN_START, crop->left);
318 if (ret < 0)
319 return ret;
320
321 ret = mt9t001_write(client, MT9T001_ROW_START, crop->top);
322 if (ret < 0)
323 return ret;
324
325 ret = mt9t001_write(client, MT9T001_WINDOW_WIDTH, crop->width - 1);
326 if (ret < 0)
327 return ret;
328
329 ret = mt9t001_write(client, MT9T001_WINDOW_HEIGHT, crop->height - 1);
330 if (ret < 0)
331 return ret;
332
333 /* Switch to master "normal" mode */
334 return mt9t001_set_output_control(mt9t001, 0, mode);
335 }
336
mt9t001_enum_mbus_code(struct v4l2_subdev * subdev,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_mbus_code_enum * code)337 static int mt9t001_enum_mbus_code(struct v4l2_subdev *subdev,
338 struct v4l2_subdev_pad_config *cfg,
339 struct v4l2_subdev_mbus_code_enum *code)
340 {
341 if (code->index > 0)
342 return -EINVAL;
343
344 code->code = MEDIA_BUS_FMT_SGRBG10_1X10;
345 return 0;
346 }
347
mt9t001_enum_frame_size(struct v4l2_subdev * subdev,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_size_enum * fse)348 static int mt9t001_enum_frame_size(struct v4l2_subdev *subdev,
349 struct v4l2_subdev_pad_config *cfg,
350 struct v4l2_subdev_frame_size_enum *fse)
351 {
352 if (fse->index >= 8 || fse->code != MEDIA_BUS_FMT_SGRBG10_1X10)
353 return -EINVAL;
354
355 fse->min_width = (MT9T001_WINDOW_WIDTH_DEF + 1) / fse->index;
356 fse->max_width = fse->min_width;
357 fse->min_height = (MT9T001_WINDOW_HEIGHT_DEF + 1) / fse->index;
358 fse->max_height = fse->min_height;
359
360 return 0;
361 }
362
mt9t001_get_format(struct v4l2_subdev * subdev,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * format)363 static int mt9t001_get_format(struct v4l2_subdev *subdev,
364 struct v4l2_subdev_pad_config *cfg,
365 struct v4l2_subdev_format *format)
366 {
367 struct mt9t001 *mt9t001 = to_mt9t001(subdev);
368
369 format->format = *__mt9t001_get_pad_format(mt9t001, cfg, format->pad,
370 format->which);
371 return 0;
372 }
373
mt9t001_set_format(struct v4l2_subdev * subdev,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * format)374 static int mt9t001_set_format(struct v4l2_subdev *subdev,
375 struct v4l2_subdev_pad_config *cfg,
376 struct v4l2_subdev_format *format)
377 {
378 struct mt9t001 *mt9t001 = to_mt9t001(subdev);
379 struct v4l2_mbus_framefmt *__format;
380 struct v4l2_rect *__crop;
381 unsigned int width;
382 unsigned int height;
383 unsigned int hratio;
384 unsigned int vratio;
385
386 __crop = __mt9t001_get_pad_crop(mt9t001, cfg, format->pad,
387 format->which);
388
389 /* Clamp the width and height to avoid dividing by zero. */
390 width = clamp_t(unsigned int, ALIGN(format->format.width, 2),
391 max_t(unsigned int, __crop->width / 8,
392 MT9T001_WINDOW_HEIGHT_MIN + 1),
393 __crop->width);
394 height = clamp_t(unsigned int, ALIGN(format->format.height, 2),
395 max_t(unsigned int, __crop->height / 8,
396 MT9T001_WINDOW_HEIGHT_MIN + 1),
397 __crop->height);
398
399 hratio = DIV_ROUND_CLOSEST(__crop->width, width);
400 vratio = DIV_ROUND_CLOSEST(__crop->height, height);
401
402 __format = __mt9t001_get_pad_format(mt9t001, cfg, format->pad,
403 format->which);
404 __format->width = __crop->width / hratio;
405 __format->height = __crop->height / vratio;
406
407 format->format = *__format;
408
409 return 0;
410 }
411
mt9t001_get_selection(struct v4l2_subdev * subdev,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_selection * sel)412 static int mt9t001_get_selection(struct v4l2_subdev *subdev,
413 struct v4l2_subdev_pad_config *cfg,
414 struct v4l2_subdev_selection *sel)
415 {
416 struct mt9t001 *mt9t001 = to_mt9t001(subdev);
417
418 if (sel->target != V4L2_SEL_TGT_CROP)
419 return -EINVAL;
420
421 sel->r = *__mt9t001_get_pad_crop(mt9t001, cfg, sel->pad, sel->which);
422 return 0;
423 }
424
mt9t001_set_selection(struct v4l2_subdev * subdev,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_selection * sel)425 static int mt9t001_set_selection(struct v4l2_subdev *subdev,
426 struct v4l2_subdev_pad_config *cfg,
427 struct v4l2_subdev_selection *sel)
428 {
429 struct mt9t001 *mt9t001 = to_mt9t001(subdev);
430 struct v4l2_mbus_framefmt *__format;
431 struct v4l2_rect *__crop;
432 struct v4l2_rect rect;
433
434 if (sel->target != V4L2_SEL_TGT_CROP)
435 return -EINVAL;
436
437 /* Clamp the crop rectangle boundaries and align them to a multiple of 2
438 * pixels.
439 */
440 rect.left = clamp(ALIGN(sel->r.left, 2),
441 MT9T001_COLUMN_START_MIN,
442 MT9T001_COLUMN_START_MAX);
443 rect.top = clamp(ALIGN(sel->r.top, 2),
444 MT9T001_ROW_START_MIN,
445 MT9T001_ROW_START_MAX);
446 rect.width = clamp_t(unsigned int, ALIGN(sel->r.width, 2),
447 MT9T001_WINDOW_WIDTH_MIN + 1,
448 MT9T001_WINDOW_WIDTH_MAX + 1);
449 rect.height = clamp_t(unsigned int, ALIGN(sel->r.height, 2),
450 MT9T001_WINDOW_HEIGHT_MIN + 1,
451 MT9T001_WINDOW_HEIGHT_MAX + 1);
452
453 rect.width = min_t(unsigned int, rect.width,
454 MT9T001_PIXEL_ARRAY_WIDTH - rect.left);
455 rect.height = min_t(unsigned int, rect.height,
456 MT9T001_PIXEL_ARRAY_HEIGHT - rect.top);
457
458 __crop = __mt9t001_get_pad_crop(mt9t001, cfg, sel->pad, sel->which);
459
460 if (rect.width != __crop->width || rect.height != __crop->height) {
461 /* Reset the output image size if the crop rectangle size has
462 * been modified.
463 */
464 __format = __mt9t001_get_pad_format(mt9t001, cfg, sel->pad,
465 sel->which);
466 __format->width = rect.width;
467 __format->height = rect.height;
468 }
469
470 *__crop = rect;
471 sel->r = rect;
472
473 return 0;
474 }
475
476 /* -----------------------------------------------------------------------------
477 * V4L2 subdev control operations
478 */
479
480 #define V4L2_CID_TEST_PATTERN_COLOR (V4L2_CID_USER_BASE | 0x1001)
481 #define V4L2_CID_BLACK_LEVEL_AUTO (V4L2_CID_USER_BASE | 0x1002)
482 #define V4L2_CID_BLACK_LEVEL_OFFSET (V4L2_CID_USER_BASE | 0x1003)
483 #define V4L2_CID_BLACK_LEVEL_CALIBRATE (V4L2_CID_USER_BASE | 0x1004)
484
485 #define V4L2_CID_GAIN_RED (V4L2_CTRL_CLASS_CAMERA | 0x1001)
486 #define V4L2_CID_GAIN_GREEN_RED (V4L2_CTRL_CLASS_CAMERA | 0x1002)
487 #define V4L2_CID_GAIN_GREEN_BLUE (V4L2_CTRL_CLASS_CAMERA | 0x1003)
488 #define V4L2_CID_GAIN_BLUE (V4L2_CTRL_CLASS_CAMERA | 0x1004)
489
mt9t001_gain_value(s32 * gain)490 static u16 mt9t001_gain_value(s32 *gain)
491 {
492 /* Gain is controlled by 2 analog stages and a digital stage. Valid
493 * values for the 3 stages are
494 *
495 * Stage Min Max Step
496 * ------------------------------------------
497 * First analog stage x1 x2 1
498 * Second analog stage x1 x4 0.125
499 * Digital stage x1 x16 0.125
500 *
501 * To minimize noise, the gain stages should be used in the second
502 * analog stage, first analog stage, digital stage order. Gain from a
503 * previous stage should be pushed to its maximum value before the next
504 * stage is used.
505 */
506 if (*gain <= 32)
507 return *gain;
508
509 if (*gain <= 64) {
510 *gain &= ~1;
511 return (1 << 6) | (*gain >> 1);
512 }
513
514 *gain &= ~7;
515 return ((*gain - 64) << 5) | (1 << 6) | 32;
516 }
517
mt9t001_ctrl_freeze(struct mt9t001 * mt9t001,bool freeze)518 static int mt9t001_ctrl_freeze(struct mt9t001 *mt9t001, bool freeze)
519 {
520 return mt9t001_set_output_control(mt9t001,
521 freeze ? 0 : MT9T001_OUTPUT_CONTROL_SYNC,
522 freeze ? MT9T001_OUTPUT_CONTROL_SYNC : 0);
523 }
524
mt9t001_s_ctrl(struct v4l2_ctrl * ctrl)525 static int mt9t001_s_ctrl(struct v4l2_ctrl *ctrl)
526 {
527 static const u8 gains[4] = {
528 MT9T001_RED_GAIN, MT9T001_GREEN1_GAIN,
529 MT9T001_GREEN2_GAIN, MT9T001_BLUE_GAIN
530 };
531
532 struct mt9t001 *mt9t001 =
533 container_of(ctrl->handler, struct mt9t001, ctrls);
534 struct i2c_client *client = v4l2_get_subdevdata(&mt9t001->subdev);
535 unsigned int count;
536 unsigned int i;
537 u16 value;
538 int ret;
539
540 switch (ctrl->id) {
541 case V4L2_CID_GAIN_RED:
542 case V4L2_CID_GAIN_GREEN_RED:
543 case V4L2_CID_GAIN_GREEN_BLUE:
544 case V4L2_CID_GAIN_BLUE:
545
546 /* Disable control updates if more than one control has changed
547 * in the cluster.
548 */
549 for (i = 0, count = 0; i < 4; ++i) {
550 struct v4l2_ctrl *gain = mt9t001->gains[i];
551
552 if (gain->val != gain->cur.val)
553 count++;
554 }
555
556 if (count > 1) {
557 ret = mt9t001_ctrl_freeze(mt9t001, true);
558 if (ret < 0)
559 return ret;
560 }
561
562 /* Update the gain controls. */
563 for (i = 0; i < 4; ++i) {
564 struct v4l2_ctrl *gain = mt9t001->gains[i];
565
566 if (gain->val == gain->cur.val)
567 continue;
568
569 value = mt9t001_gain_value(&gain->val);
570 ret = mt9t001_write(client, gains[i], value);
571 if (ret < 0) {
572 mt9t001_ctrl_freeze(mt9t001, false);
573 return ret;
574 }
575 }
576
577 /* Enable control updates. */
578 if (count > 1) {
579 ret = mt9t001_ctrl_freeze(mt9t001, false);
580 if (ret < 0)
581 return ret;
582 }
583
584 break;
585
586 case V4L2_CID_EXPOSURE:
587 ret = mt9t001_write(client, MT9T001_SHUTTER_WIDTH_LOW,
588 ctrl->val & 0xffff);
589 if (ret < 0)
590 return ret;
591
592 return mt9t001_write(client, MT9T001_SHUTTER_WIDTH_HIGH,
593 ctrl->val >> 16);
594
595 case V4L2_CID_TEST_PATTERN:
596 return mt9t001_set_output_control(mt9t001,
597 ctrl->val ? 0 : MT9T001_OUTPUT_CONTROL_TEST_DATA,
598 ctrl->val ? MT9T001_OUTPUT_CONTROL_TEST_DATA : 0);
599
600 case V4L2_CID_TEST_PATTERN_COLOR:
601 return mt9t001_write(client, MT9T001_TEST_DATA, ctrl->val << 2);
602
603 case V4L2_CID_BLACK_LEVEL_AUTO:
604 value = ctrl->val ? 0 : MT9T001_BLACK_LEVEL_OVERRIDE;
605 ret = mt9t001_write(client, MT9T001_BLACK_LEVEL_CALIBRATION,
606 value);
607 if (ret < 0)
608 return ret;
609
610 mt9t001->black_level = value;
611 break;
612
613 case V4L2_CID_BLACK_LEVEL_OFFSET:
614 ret = mt9t001_write(client, MT9T001_GREEN1_OFFSET, ctrl->val);
615 if (ret < 0)
616 return ret;
617
618 ret = mt9t001_write(client, MT9T001_GREEN2_OFFSET, ctrl->val);
619 if (ret < 0)
620 return ret;
621
622 ret = mt9t001_write(client, MT9T001_RED_OFFSET, ctrl->val);
623 if (ret < 0)
624 return ret;
625
626 return mt9t001_write(client, MT9T001_BLUE_OFFSET, ctrl->val);
627
628 case V4L2_CID_BLACK_LEVEL_CALIBRATE:
629 return mt9t001_write(client, MT9T001_BLACK_LEVEL_CALIBRATION,
630 MT9T001_BLACK_LEVEL_RECALCULATE |
631 mt9t001->black_level);
632 }
633
634 return 0;
635 }
636
637 static const struct v4l2_ctrl_ops mt9t001_ctrl_ops = {
638 .s_ctrl = mt9t001_s_ctrl,
639 };
640
641 static const char * const mt9t001_test_pattern_menu[] = {
642 "Disabled",
643 "Enabled",
644 };
645
646 static const struct v4l2_ctrl_config mt9t001_ctrls[] = {
647 {
648 .ops = &mt9t001_ctrl_ops,
649 .id = V4L2_CID_TEST_PATTERN_COLOR,
650 .type = V4L2_CTRL_TYPE_INTEGER,
651 .name = "Test Pattern Color",
652 .min = 0,
653 .max = 1023,
654 .step = 1,
655 .def = 0,
656 .flags = 0,
657 }, {
658 .ops = &mt9t001_ctrl_ops,
659 .id = V4L2_CID_BLACK_LEVEL_AUTO,
660 .type = V4L2_CTRL_TYPE_BOOLEAN,
661 .name = "Black Level, Auto",
662 .min = 0,
663 .max = 1,
664 .step = 1,
665 .def = 1,
666 .flags = 0,
667 }, {
668 .ops = &mt9t001_ctrl_ops,
669 .id = V4L2_CID_BLACK_LEVEL_OFFSET,
670 .type = V4L2_CTRL_TYPE_INTEGER,
671 .name = "Black Level, Offset",
672 .min = -256,
673 .max = 255,
674 .step = 1,
675 .def = 32,
676 .flags = 0,
677 }, {
678 .ops = &mt9t001_ctrl_ops,
679 .id = V4L2_CID_BLACK_LEVEL_CALIBRATE,
680 .type = V4L2_CTRL_TYPE_BUTTON,
681 .name = "Black Level, Calibrate",
682 .min = 0,
683 .max = 0,
684 .step = 0,
685 .def = 0,
686 .flags = V4L2_CTRL_FLAG_WRITE_ONLY,
687 },
688 };
689
690 static const struct v4l2_ctrl_config mt9t001_gains[] = {
691 {
692 .ops = &mt9t001_ctrl_ops,
693 .id = V4L2_CID_GAIN_RED,
694 .type = V4L2_CTRL_TYPE_INTEGER,
695 .name = "Gain, Red",
696 .min = MT9T001_GLOBAL_GAIN_MIN,
697 .max = MT9T001_GLOBAL_GAIN_MAX,
698 .step = 1,
699 .def = MT9T001_GLOBAL_GAIN_MIN,
700 .flags = 0,
701 }, {
702 .ops = &mt9t001_ctrl_ops,
703 .id = V4L2_CID_GAIN_GREEN_RED,
704 .type = V4L2_CTRL_TYPE_INTEGER,
705 .name = "Gain, Green (R)",
706 .min = MT9T001_GLOBAL_GAIN_MIN,
707 .max = MT9T001_GLOBAL_GAIN_MAX,
708 .step = 1,
709 .def = MT9T001_GLOBAL_GAIN_MIN,
710 .flags = 0,
711 }, {
712 .ops = &mt9t001_ctrl_ops,
713 .id = V4L2_CID_GAIN_GREEN_BLUE,
714 .type = V4L2_CTRL_TYPE_INTEGER,
715 .name = "Gain, Green (B)",
716 .min = MT9T001_GLOBAL_GAIN_MIN,
717 .max = MT9T001_GLOBAL_GAIN_MAX,
718 .step = 1,
719 .def = MT9T001_GLOBAL_GAIN_MIN,
720 .flags = 0,
721 }, {
722 .ops = &mt9t001_ctrl_ops,
723 .id = V4L2_CID_GAIN_BLUE,
724 .type = V4L2_CTRL_TYPE_INTEGER,
725 .name = "Gain, Blue",
726 .min = MT9T001_GLOBAL_GAIN_MIN,
727 .max = MT9T001_GLOBAL_GAIN_MAX,
728 .step = 1,
729 .def = MT9T001_GLOBAL_GAIN_MIN,
730 .flags = 0,
731 },
732 };
733
734 /* -----------------------------------------------------------------------------
735 * V4L2 subdev core operations
736 */
737
mt9t001_set_power(struct v4l2_subdev * subdev,int on)738 static int mt9t001_set_power(struct v4l2_subdev *subdev, int on)
739 {
740 struct mt9t001 *mt9t001 = to_mt9t001(subdev);
741 int ret = 0;
742
743 mutex_lock(&mt9t001->power_lock);
744
745 /* If the power count is modified from 0 to != 0 or from != 0 to 0,
746 * update the power state.
747 */
748 if (mt9t001->power_count == !on) {
749 ret = __mt9t001_set_power(mt9t001, !!on);
750 if (ret < 0)
751 goto out;
752 }
753
754 /* Update the power count. */
755 mt9t001->power_count += on ? 1 : -1;
756 WARN_ON(mt9t001->power_count < 0);
757
758 out:
759 mutex_unlock(&mt9t001->power_lock);
760 return ret;
761 }
762
763 /* -----------------------------------------------------------------------------
764 * V4L2 subdev internal operations
765 */
766
mt9t001_registered(struct v4l2_subdev * subdev)767 static int mt9t001_registered(struct v4l2_subdev *subdev)
768 {
769 struct i2c_client *client = v4l2_get_subdevdata(subdev);
770 struct mt9t001 *mt9t001 = to_mt9t001(subdev);
771 s32 data;
772 int ret;
773
774 ret = mt9t001_power_on(mt9t001);
775 if (ret < 0) {
776 dev_err(&client->dev, "MT9T001 power up failed\n");
777 return ret;
778 }
779
780 /* Read out the chip version register */
781 data = mt9t001_read(client, MT9T001_CHIP_VERSION);
782 mt9t001_power_off(mt9t001);
783
784 if (data != MT9T001_CHIP_ID) {
785 dev_err(&client->dev,
786 "MT9T001 not detected, wrong version 0x%04x\n", data);
787 return -ENODEV;
788 }
789
790 dev_info(&client->dev, "MT9T001 detected at address 0x%02x\n",
791 client->addr);
792
793 return 0;
794 }
795
mt9t001_open(struct v4l2_subdev * subdev,struct v4l2_subdev_fh * fh)796 static int mt9t001_open(struct v4l2_subdev *subdev, struct v4l2_subdev_fh *fh)
797 {
798 struct v4l2_mbus_framefmt *format;
799 struct v4l2_rect *crop;
800
801 crop = v4l2_subdev_get_try_crop(subdev, fh->pad, 0);
802 crop->left = MT9T001_COLUMN_START_DEF;
803 crop->top = MT9T001_ROW_START_DEF;
804 crop->width = MT9T001_WINDOW_WIDTH_DEF + 1;
805 crop->height = MT9T001_WINDOW_HEIGHT_DEF + 1;
806
807 format = v4l2_subdev_get_try_format(subdev, fh->pad, 0);
808 format->code = MEDIA_BUS_FMT_SGRBG10_1X10;
809 format->width = MT9T001_WINDOW_WIDTH_DEF + 1;
810 format->height = MT9T001_WINDOW_HEIGHT_DEF + 1;
811 format->field = V4L2_FIELD_NONE;
812 format->colorspace = V4L2_COLORSPACE_SRGB;
813
814 return mt9t001_set_power(subdev, 1);
815 }
816
mt9t001_close(struct v4l2_subdev * subdev,struct v4l2_subdev_fh * fh)817 static int mt9t001_close(struct v4l2_subdev *subdev, struct v4l2_subdev_fh *fh)
818 {
819 return mt9t001_set_power(subdev, 0);
820 }
821
822 static const struct v4l2_subdev_core_ops mt9t001_subdev_core_ops = {
823 .s_power = mt9t001_set_power,
824 };
825
826 static const struct v4l2_subdev_video_ops mt9t001_subdev_video_ops = {
827 .s_stream = mt9t001_s_stream,
828 };
829
830 static const struct v4l2_subdev_pad_ops mt9t001_subdev_pad_ops = {
831 .enum_mbus_code = mt9t001_enum_mbus_code,
832 .enum_frame_size = mt9t001_enum_frame_size,
833 .get_fmt = mt9t001_get_format,
834 .set_fmt = mt9t001_set_format,
835 .get_selection = mt9t001_get_selection,
836 .set_selection = mt9t001_set_selection,
837 };
838
839 static const struct v4l2_subdev_ops mt9t001_subdev_ops = {
840 .core = &mt9t001_subdev_core_ops,
841 .video = &mt9t001_subdev_video_ops,
842 .pad = &mt9t001_subdev_pad_ops,
843 };
844
845 static const struct v4l2_subdev_internal_ops mt9t001_subdev_internal_ops = {
846 .registered = mt9t001_registered,
847 .open = mt9t001_open,
848 .close = mt9t001_close,
849 };
850
mt9t001_probe(struct i2c_client * client,const struct i2c_device_id * did)851 static int mt9t001_probe(struct i2c_client *client,
852 const struct i2c_device_id *did)
853 {
854 struct mt9t001_platform_data *pdata = client->dev.platform_data;
855 struct mt9t001 *mt9t001;
856 unsigned int i;
857 int ret;
858
859 if (pdata == NULL) {
860 dev_err(&client->dev, "No platform data\n");
861 return -EINVAL;
862 }
863
864 if (!i2c_check_functionality(client->adapter,
865 I2C_FUNC_SMBUS_WORD_DATA)) {
866 dev_warn(&client->adapter->dev,
867 "I2C-Adapter doesn't support I2C_FUNC_SMBUS_WORD\n");
868 return -EIO;
869 }
870
871 mt9t001 = devm_kzalloc(&client->dev, sizeof(*mt9t001), GFP_KERNEL);
872 if (!mt9t001)
873 return -ENOMEM;
874
875 mutex_init(&mt9t001->power_lock);
876 mt9t001->output_control = MT9T001_OUTPUT_CONTROL_DEF;
877
878 mt9t001->regulators[0].supply = "vdd";
879 mt9t001->regulators[1].supply = "vaa";
880
881 ret = devm_regulator_bulk_get(&client->dev, 2, mt9t001->regulators);
882 if (ret < 0) {
883 dev_err(&client->dev, "Unable to get regulators\n");
884 return ret;
885 }
886
887 mt9t001->clk = devm_clk_get(&client->dev, NULL);
888 if (IS_ERR(mt9t001->clk)) {
889 dev_err(&client->dev, "Unable to get clock\n");
890 return PTR_ERR(mt9t001->clk);
891 }
892
893 v4l2_ctrl_handler_init(&mt9t001->ctrls, ARRAY_SIZE(mt9t001_ctrls) +
894 ARRAY_SIZE(mt9t001_gains) + 4);
895
896 v4l2_ctrl_new_std(&mt9t001->ctrls, &mt9t001_ctrl_ops,
897 V4L2_CID_EXPOSURE, MT9T001_SHUTTER_WIDTH_MIN,
898 MT9T001_SHUTTER_WIDTH_MAX, 1,
899 MT9T001_SHUTTER_WIDTH_DEF);
900 v4l2_ctrl_new_std(&mt9t001->ctrls, &mt9t001_ctrl_ops,
901 V4L2_CID_BLACK_LEVEL, 1, 1, 1, 1);
902 v4l2_ctrl_new_std(&mt9t001->ctrls, &mt9t001_ctrl_ops,
903 V4L2_CID_PIXEL_RATE, pdata->ext_clk, pdata->ext_clk,
904 1, pdata->ext_clk);
905 v4l2_ctrl_new_std_menu_items(&mt9t001->ctrls, &mt9t001_ctrl_ops,
906 V4L2_CID_TEST_PATTERN,
907 ARRAY_SIZE(mt9t001_test_pattern_menu) - 1, 0,
908 0, mt9t001_test_pattern_menu);
909
910 for (i = 0; i < ARRAY_SIZE(mt9t001_ctrls); ++i)
911 v4l2_ctrl_new_custom(&mt9t001->ctrls, &mt9t001_ctrls[i], NULL);
912
913 for (i = 0; i < ARRAY_SIZE(mt9t001_gains); ++i)
914 mt9t001->gains[i] = v4l2_ctrl_new_custom(&mt9t001->ctrls,
915 &mt9t001_gains[i], NULL);
916
917 v4l2_ctrl_cluster(ARRAY_SIZE(mt9t001_gains), mt9t001->gains);
918
919 mt9t001->subdev.ctrl_handler = &mt9t001->ctrls;
920
921 if (mt9t001->ctrls.error) {
922 printk(KERN_INFO "%s: control initialization error %d\n",
923 __func__, mt9t001->ctrls.error);
924 ret = -EINVAL;
925 goto done;
926 }
927
928 mt9t001->crop.left = MT9T001_COLUMN_START_DEF;
929 mt9t001->crop.top = MT9T001_ROW_START_DEF;
930 mt9t001->crop.width = MT9T001_WINDOW_WIDTH_DEF + 1;
931 mt9t001->crop.height = MT9T001_WINDOW_HEIGHT_DEF + 1;
932
933 mt9t001->format.code = MEDIA_BUS_FMT_SGRBG10_1X10;
934 mt9t001->format.width = MT9T001_WINDOW_WIDTH_DEF + 1;
935 mt9t001->format.height = MT9T001_WINDOW_HEIGHT_DEF + 1;
936 mt9t001->format.field = V4L2_FIELD_NONE;
937 mt9t001->format.colorspace = V4L2_COLORSPACE_SRGB;
938
939 v4l2_i2c_subdev_init(&mt9t001->subdev, client, &mt9t001_subdev_ops);
940 mt9t001->subdev.internal_ops = &mt9t001_subdev_internal_ops;
941 mt9t001->subdev.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
942
943 mt9t001->subdev.entity.function = MEDIA_ENT_F_CAM_SENSOR;
944 mt9t001->pad.flags = MEDIA_PAD_FL_SOURCE;
945 ret = media_entity_pads_init(&mt9t001->subdev.entity, 1, &mt9t001->pad);
946
947 done:
948 if (ret < 0) {
949 v4l2_ctrl_handler_free(&mt9t001->ctrls);
950 media_entity_cleanup(&mt9t001->subdev.entity);
951 }
952
953 return ret;
954 }
955
mt9t001_remove(struct i2c_client * client)956 static int mt9t001_remove(struct i2c_client *client)
957 {
958 struct v4l2_subdev *subdev = i2c_get_clientdata(client);
959 struct mt9t001 *mt9t001 = to_mt9t001(subdev);
960
961 v4l2_ctrl_handler_free(&mt9t001->ctrls);
962 v4l2_device_unregister_subdev(subdev);
963 media_entity_cleanup(&subdev->entity);
964 return 0;
965 }
966
967 static const struct i2c_device_id mt9t001_id[] = {
968 { "mt9t001", 0 },
969 { }
970 };
971 MODULE_DEVICE_TABLE(i2c, mt9t001_id);
972
973 static struct i2c_driver mt9t001_driver = {
974 .driver = {
975 .name = "mt9t001",
976 },
977 .probe = mt9t001_probe,
978 .remove = mt9t001_remove,
979 .id_table = mt9t001_id,
980 };
981
982 module_i2c_driver(mt9t001_driver);
983
984 MODULE_DESCRIPTION("Aptina (Micron) MT9T001 Camera driver");
985 MODULE_AUTHOR("Laurent Pinchart <laurent.pinchart@ideasonboard.com>");
986 MODULE_LICENSE("GPL");
987
