1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (C) 2018 Intel Corporation
3
4 #include <linux/acpi.h>
5 #include <linux/clk.h>
6 #include <linux/delay.h>
7 #include <linux/i2c.h>
8 #include <linux/module.h>
9 #include <linux/pm_runtime.h>
10 #include <media/v4l2-ctrls.h>
11 #include <media/v4l2-device.h>
12 #include <media/v4l2-fwnode.h>
13 #include <asm/unaligned.h>
14
15 #define IMX258_REG_VALUE_08BIT 1
16 #define IMX258_REG_VALUE_16BIT 2
17
18 #define IMX258_REG_MODE_SELECT 0x0100
19 #define IMX258_MODE_STANDBY 0x00
20 #define IMX258_MODE_STREAMING 0x01
21
22 /* Chip ID */
23 #define IMX258_REG_CHIP_ID 0x0016
24 #define IMX258_CHIP_ID 0x0258
25
26 /* V_TIMING internal */
27 #define IMX258_VTS_30FPS 0x0c50
28 #define IMX258_VTS_30FPS_2K 0x0638
29 #define IMX258_VTS_30FPS_VGA 0x034c
30 #define IMX258_VTS_MAX 0xffff
31
32 /*Frame Length Line*/
33 #define IMX258_FLL_MIN 0x08a6
34 #define IMX258_FLL_MAX 0xffff
35 #define IMX258_FLL_STEP 1
36 #define IMX258_FLL_DEFAULT 0x0c98
37
38 /* HBLANK control - read only */
39 #define IMX258_PPL_DEFAULT 5352
40
41 /* Exposure control */
42 #define IMX258_REG_EXPOSURE 0x0202
43 #define IMX258_EXPOSURE_MIN 4
44 #define IMX258_EXPOSURE_STEP 1
45 #define IMX258_EXPOSURE_DEFAULT 0x640
46 #define IMX258_EXPOSURE_MAX 65535
47
48 /* Analog gain control */
49 #define IMX258_REG_ANALOG_GAIN 0x0204
50 #define IMX258_ANA_GAIN_MIN 0
51 #define IMX258_ANA_GAIN_MAX 480
52 #define IMX258_ANA_GAIN_STEP 1
53 #define IMX258_ANA_GAIN_DEFAULT 0x0
54
55 /* Digital gain control */
56 #define IMX258_REG_GR_DIGITAL_GAIN 0x020e
57 #define IMX258_REG_R_DIGITAL_GAIN 0x0210
58 #define IMX258_REG_B_DIGITAL_GAIN 0x0212
59 #define IMX258_REG_GB_DIGITAL_GAIN 0x0214
60 #define IMX258_DGTL_GAIN_MIN 0
61 #define IMX258_DGTL_GAIN_MAX 4096 /* Max = 0xFFF */
62 #define IMX258_DGTL_GAIN_DEFAULT 1024
63 #define IMX258_DGTL_GAIN_STEP 1
64
65 /* HDR control */
66 #define IMX258_REG_HDR 0x0220
67 #define IMX258_HDR_ON BIT(0)
68 #define IMX258_REG_HDR_RATIO 0x0222
69 #define IMX258_HDR_RATIO_MIN 0
70 #define IMX258_HDR_RATIO_MAX 5
71 #define IMX258_HDR_RATIO_STEP 1
72 #define IMX258_HDR_RATIO_DEFAULT 0x0
73
74 /* Test Pattern Control */
75 #define IMX258_REG_TEST_PATTERN 0x0600
76
77 /* Orientation */
78 #define REG_MIRROR_FLIP_CONTROL 0x0101
79 #define REG_CONFIG_MIRROR_FLIP 0x03
80 #define REG_CONFIG_FLIP_TEST_PATTERN 0x02
81
82 /* Input clock frequency in Hz */
83 #define IMX258_INPUT_CLOCK_FREQ 19200000
84
85 struct imx258_reg {
86 u16 address;
87 u8 val;
88 };
89
90 struct imx258_reg_list {
91 u32 num_of_regs;
92 const struct imx258_reg *regs;
93 };
94
95 /* Link frequency config */
96 struct imx258_link_freq_config {
97 u32 pixels_per_line;
98
99 /* PLL registers for this link frequency */
100 struct imx258_reg_list reg_list;
101 };
102
103 /* Mode : resolution and related config&values */
104 struct imx258_mode {
105 /* Frame width */
106 u32 width;
107 /* Frame height */
108 u32 height;
109
110 /* V-timing */
111 u32 vts_def;
112 u32 vts_min;
113
114 /* Index of Link frequency config to be used */
115 u32 link_freq_index;
116 /* Default register values */
117 struct imx258_reg_list reg_list;
118 };
119
120 /* 4208x3118 needs 1267Mbps/lane, 4 lanes */
121 static const struct imx258_reg mipi_data_rate_1267mbps[] = {
122 { 0x0301, 0x05 },
123 { 0x0303, 0x02 },
124 { 0x0305, 0x03 },
125 { 0x0306, 0x00 },
126 { 0x0307, 0xC6 },
127 { 0x0309, 0x0A },
128 { 0x030B, 0x01 },
129 { 0x030D, 0x02 },
130 { 0x030E, 0x00 },
131 { 0x030F, 0xD8 },
132 { 0x0310, 0x00 },
133 { 0x0820, 0x13 },
134 { 0x0821, 0x4C },
135 { 0x0822, 0xCC },
136 { 0x0823, 0xCC },
137 };
138
139 static const struct imx258_reg mipi_data_rate_640mbps[] = {
140 { 0x0301, 0x05 },
141 { 0x0303, 0x02 },
142 { 0x0305, 0x03 },
143 { 0x0306, 0x00 },
144 { 0x0307, 0x64 },
145 { 0x0309, 0x0A },
146 { 0x030B, 0x01 },
147 { 0x030D, 0x02 },
148 { 0x030E, 0x00 },
149 { 0x030F, 0xD8 },
150 { 0x0310, 0x00 },
151 { 0x0820, 0x0A },
152 { 0x0821, 0x00 },
153 { 0x0822, 0x00 },
154 { 0x0823, 0x00 },
155 };
156
157 static const struct imx258_reg mode_4208x3118_regs[] = {
158 { 0x0136, 0x13 },
159 { 0x0137, 0x33 },
160 { 0x3051, 0x00 },
161 { 0x3052, 0x00 },
162 { 0x4E21, 0x14 },
163 { 0x6B11, 0xCF },
164 { 0x7FF0, 0x08 },
165 { 0x7FF1, 0x0F },
166 { 0x7FF2, 0x08 },
167 { 0x7FF3, 0x1B },
168 { 0x7FF4, 0x23 },
169 { 0x7FF5, 0x60 },
170 { 0x7FF6, 0x00 },
171 { 0x7FF7, 0x01 },
172 { 0x7FF8, 0x00 },
173 { 0x7FF9, 0x78 },
174 { 0x7FFA, 0x00 },
175 { 0x7FFB, 0x00 },
176 { 0x7FFC, 0x00 },
177 { 0x7FFD, 0x00 },
178 { 0x7FFE, 0x00 },
179 { 0x7FFF, 0x03 },
180 { 0x7F76, 0x03 },
181 { 0x7F77, 0xFE },
182 { 0x7FA8, 0x03 },
183 { 0x7FA9, 0xFE },
184 { 0x7B24, 0x81 },
185 { 0x7B25, 0x00 },
186 { 0x6564, 0x07 },
187 { 0x6B0D, 0x41 },
188 { 0x653D, 0x04 },
189 { 0x6B05, 0x8C },
190 { 0x6B06, 0xF9 },
191 { 0x6B08, 0x65 },
192 { 0x6B09, 0xFC },
193 { 0x6B0A, 0xCF },
194 { 0x6B0B, 0xD2 },
195 { 0x6700, 0x0E },
196 { 0x6707, 0x0E },
197 { 0x9104, 0x00 },
198 { 0x4648, 0x7F },
199 { 0x7420, 0x00 },
200 { 0x7421, 0x1C },
201 { 0x7422, 0x00 },
202 { 0x7423, 0xD7 },
203 { 0x5F04, 0x00 },
204 { 0x5F05, 0xED },
205 { 0x0112, 0x0A },
206 { 0x0113, 0x0A },
207 { 0x0114, 0x03 },
208 { 0x0342, 0x14 },
209 { 0x0343, 0xE8 },
210 { 0x0340, 0x0C },
211 { 0x0341, 0x50 },
212 { 0x0344, 0x00 },
213 { 0x0345, 0x00 },
214 { 0x0346, 0x00 },
215 { 0x0347, 0x00 },
216 { 0x0348, 0x10 },
217 { 0x0349, 0x6F },
218 { 0x034A, 0x0C },
219 { 0x034B, 0x2E },
220 { 0x0381, 0x01 },
221 { 0x0383, 0x01 },
222 { 0x0385, 0x01 },
223 { 0x0387, 0x01 },
224 { 0x0900, 0x00 },
225 { 0x0901, 0x11 },
226 { 0x0401, 0x00 },
227 { 0x0404, 0x00 },
228 { 0x0405, 0x10 },
229 { 0x0408, 0x00 },
230 { 0x0409, 0x00 },
231 { 0x040A, 0x00 },
232 { 0x040B, 0x00 },
233 { 0x040C, 0x10 },
234 { 0x040D, 0x70 },
235 { 0x040E, 0x0C },
236 { 0x040F, 0x30 },
237 { 0x3038, 0x00 },
238 { 0x303A, 0x00 },
239 { 0x303B, 0x10 },
240 { 0x300D, 0x00 },
241 { 0x034C, 0x10 },
242 { 0x034D, 0x70 },
243 { 0x034E, 0x0C },
244 { 0x034F, 0x30 },
245 { 0x0350, 0x01 },
246 { 0x0202, 0x0C },
247 { 0x0203, 0x46 },
248 { 0x0204, 0x00 },
249 { 0x0205, 0x00 },
250 { 0x020E, 0x01 },
251 { 0x020F, 0x00 },
252 { 0x0210, 0x01 },
253 { 0x0211, 0x00 },
254 { 0x0212, 0x01 },
255 { 0x0213, 0x00 },
256 { 0x0214, 0x01 },
257 { 0x0215, 0x00 },
258 { 0x7BCD, 0x00 },
259 { 0x94DC, 0x20 },
260 { 0x94DD, 0x20 },
261 { 0x94DE, 0x20 },
262 { 0x95DC, 0x20 },
263 { 0x95DD, 0x20 },
264 { 0x95DE, 0x20 },
265 { 0x7FB0, 0x00 },
266 { 0x9010, 0x3E },
267 { 0x9419, 0x50 },
268 { 0x941B, 0x50 },
269 { 0x9519, 0x50 },
270 { 0x951B, 0x50 },
271 { 0x3030, 0x00 },
272 { 0x3032, 0x00 },
273 { 0x0220, 0x00 },
274 };
275
276 static const struct imx258_reg mode_2104_1560_regs[] = {
277 { 0x0136, 0x13 },
278 { 0x0137, 0x33 },
279 { 0x3051, 0x00 },
280 { 0x3052, 0x00 },
281 { 0x4E21, 0x14 },
282 { 0x6B11, 0xCF },
283 { 0x7FF0, 0x08 },
284 { 0x7FF1, 0x0F },
285 { 0x7FF2, 0x08 },
286 { 0x7FF3, 0x1B },
287 { 0x7FF4, 0x23 },
288 { 0x7FF5, 0x60 },
289 { 0x7FF6, 0x00 },
290 { 0x7FF7, 0x01 },
291 { 0x7FF8, 0x00 },
292 { 0x7FF9, 0x78 },
293 { 0x7FFA, 0x00 },
294 { 0x7FFB, 0x00 },
295 { 0x7FFC, 0x00 },
296 { 0x7FFD, 0x00 },
297 { 0x7FFE, 0x00 },
298 { 0x7FFF, 0x03 },
299 { 0x7F76, 0x03 },
300 { 0x7F77, 0xFE },
301 { 0x7FA8, 0x03 },
302 { 0x7FA9, 0xFE },
303 { 0x7B24, 0x81 },
304 { 0x7B25, 0x00 },
305 { 0x6564, 0x07 },
306 { 0x6B0D, 0x41 },
307 { 0x653D, 0x04 },
308 { 0x6B05, 0x8C },
309 { 0x6B06, 0xF9 },
310 { 0x6B08, 0x65 },
311 { 0x6B09, 0xFC },
312 { 0x6B0A, 0xCF },
313 { 0x6B0B, 0xD2 },
314 { 0x6700, 0x0E },
315 { 0x6707, 0x0E },
316 { 0x9104, 0x00 },
317 { 0x4648, 0x7F },
318 { 0x7420, 0x00 },
319 { 0x7421, 0x1C },
320 { 0x7422, 0x00 },
321 { 0x7423, 0xD7 },
322 { 0x5F04, 0x00 },
323 { 0x5F05, 0xED },
324 { 0x0112, 0x0A },
325 { 0x0113, 0x0A },
326 { 0x0114, 0x03 },
327 { 0x0342, 0x14 },
328 { 0x0343, 0xE8 },
329 { 0x0340, 0x06 },
330 { 0x0341, 0x38 },
331 { 0x0344, 0x00 },
332 { 0x0345, 0x00 },
333 { 0x0346, 0x00 },
334 { 0x0347, 0x00 },
335 { 0x0348, 0x10 },
336 { 0x0349, 0x6F },
337 { 0x034A, 0x0C },
338 { 0x034B, 0x2E },
339 { 0x0381, 0x01 },
340 { 0x0383, 0x01 },
341 { 0x0385, 0x01 },
342 { 0x0387, 0x01 },
343 { 0x0900, 0x01 },
344 { 0x0901, 0x12 },
345 { 0x0401, 0x01 },
346 { 0x0404, 0x00 },
347 { 0x0405, 0x20 },
348 { 0x0408, 0x00 },
349 { 0x0409, 0x02 },
350 { 0x040A, 0x00 },
351 { 0x040B, 0x00 },
352 { 0x040C, 0x10 },
353 { 0x040D, 0x6A },
354 { 0x040E, 0x06 },
355 { 0x040F, 0x18 },
356 { 0x3038, 0x00 },
357 { 0x303A, 0x00 },
358 { 0x303B, 0x10 },
359 { 0x300D, 0x00 },
360 { 0x034C, 0x08 },
361 { 0x034D, 0x38 },
362 { 0x034E, 0x06 },
363 { 0x034F, 0x18 },
364 { 0x0350, 0x01 },
365 { 0x0202, 0x06 },
366 { 0x0203, 0x2E },
367 { 0x0204, 0x00 },
368 { 0x0205, 0x00 },
369 { 0x020E, 0x01 },
370 { 0x020F, 0x00 },
371 { 0x0210, 0x01 },
372 { 0x0211, 0x00 },
373 { 0x0212, 0x01 },
374 { 0x0213, 0x00 },
375 { 0x0214, 0x01 },
376 { 0x0215, 0x00 },
377 { 0x7BCD, 0x01 },
378 { 0x94DC, 0x20 },
379 { 0x94DD, 0x20 },
380 { 0x94DE, 0x20 },
381 { 0x95DC, 0x20 },
382 { 0x95DD, 0x20 },
383 { 0x95DE, 0x20 },
384 { 0x7FB0, 0x00 },
385 { 0x9010, 0x3E },
386 { 0x9419, 0x50 },
387 { 0x941B, 0x50 },
388 { 0x9519, 0x50 },
389 { 0x951B, 0x50 },
390 { 0x3030, 0x00 },
391 { 0x3032, 0x00 },
392 { 0x0220, 0x00 },
393 };
394
395 static const struct imx258_reg mode_1048_780_regs[] = {
396 { 0x0136, 0x13 },
397 { 0x0137, 0x33 },
398 { 0x3051, 0x00 },
399 { 0x3052, 0x00 },
400 { 0x4E21, 0x14 },
401 { 0x6B11, 0xCF },
402 { 0x7FF0, 0x08 },
403 { 0x7FF1, 0x0F },
404 { 0x7FF2, 0x08 },
405 { 0x7FF3, 0x1B },
406 { 0x7FF4, 0x23 },
407 { 0x7FF5, 0x60 },
408 { 0x7FF6, 0x00 },
409 { 0x7FF7, 0x01 },
410 { 0x7FF8, 0x00 },
411 { 0x7FF9, 0x78 },
412 { 0x7FFA, 0x00 },
413 { 0x7FFB, 0x00 },
414 { 0x7FFC, 0x00 },
415 { 0x7FFD, 0x00 },
416 { 0x7FFE, 0x00 },
417 { 0x7FFF, 0x03 },
418 { 0x7F76, 0x03 },
419 { 0x7F77, 0xFE },
420 { 0x7FA8, 0x03 },
421 { 0x7FA9, 0xFE },
422 { 0x7B24, 0x81 },
423 { 0x7B25, 0x00 },
424 { 0x6564, 0x07 },
425 { 0x6B0D, 0x41 },
426 { 0x653D, 0x04 },
427 { 0x6B05, 0x8C },
428 { 0x6B06, 0xF9 },
429 { 0x6B08, 0x65 },
430 { 0x6B09, 0xFC },
431 { 0x6B0A, 0xCF },
432 { 0x6B0B, 0xD2 },
433 { 0x6700, 0x0E },
434 { 0x6707, 0x0E },
435 { 0x9104, 0x00 },
436 { 0x4648, 0x7F },
437 { 0x7420, 0x00 },
438 { 0x7421, 0x1C },
439 { 0x7422, 0x00 },
440 { 0x7423, 0xD7 },
441 { 0x5F04, 0x00 },
442 { 0x5F05, 0xED },
443 { 0x0112, 0x0A },
444 { 0x0113, 0x0A },
445 { 0x0114, 0x03 },
446 { 0x0342, 0x14 },
447 { 0x0343, 0xE8 },
448 { 0x0340, 0x03 },
449 { 0x0341, 0x4C },
450 { 0x0344, 0x00 },
451 { 0x0345, 0x00 },
452 { 0x0346, 0x00 },
453 { 0x0347, 0x00 },
454 { 0x0348, 0x10 },
455 { 0x0349, 0x6F },
456 { 0x034A, 0x0C },
457 { 0x034B, 0x2E },
458 { 0x0381, 0x01 },
459 { 0x0383, 0x01 },
460 { 0x0385, 0x01 },
461 { 0x0387, 0x01 },
462 { 0x0900, 0x01 },
463 { 0x0901, 0x14 },
464 { 0x0401, 0x01 },
465 { 0x0404, 0x00 },
466 { 0x0405, 0x40 },
467 { 0x0408, 0x00 },
468 { 0x0409, 0x06 },
469 { 0x040A, 0x00 },
470 { 0x040B, 0x00 },
471 { 0x040C, 0x10 },
472 { 0x040D, 0x64 },
473 { 0x040E, 0x03 },
474 { 0x040F, 0x0C },
475 { 0x3038, 0x00 },
476 { 0x303A, 0x00 },
477 { 0x303B, 0x10 },
478 { 0x300D, 0x00 },
479 { 0x034C, 0x04 },
480 { 0x034D, 0x18 },
481 { 0x034E, 0x03 },
482 { 0x034F, 0x0C },
483 { 0x0350, 0x01 },
484 { 0x0202, 0x03 },
485 { 0x0203, 0x42 },
486 { 0x0204, 0x00 },
487 { 0x0205, 0x00 },
488 { 0x020E, 0x01 },
489 { 0x020F, 0x00 },
490 { 0x0210, 0x01 },
491 { 0x0211, 0x00 },
492 { 0x0212, 0x01 },
493 { 0x0213, 0x00 },
494 { 0x0214, 0x01 },
495 { 0x0215, 0x00 },
496 { 0x7BCD, 0x00 },
497 { 0x94DC, 0x20 },
498 { 0x94DD, 0x20 },
499 { 0x94DE, 0x20 },
500 { 0x95DC, 0x20 },
501 { 0x95DD, 0x20 },
502 { 0x95DE, 0x20 },
503 { 0x7FB0, 0x00 },
504 { 0x9010, 0x3E },
505 { 0x9419, 0x50 },
506 { 0x941B, 0x50 },
507 { 0x9519, 0x50 },
508 { 0x951B, 0x50 },
509 { 0x3030, 0x00 },
510 { 0x3032, 0x00 },
511 { 0x0220, 0x00 },
512 };
513
514 static const char * const imx258_test_pattern_menu[] = {
515 "Disabled",
516 "Solid Colour",
517 "Eight Vertical Colour Bars",
518 "Colour Bars With Fade to Grey",
519 "Pseudorandom Sequence (PN9)",
520 };
521
522 /* Configurations for supported link frequencies */
523 #define IMX258_LINK_FREQ_634MHZ 633600000ULL
524 #define IMX258_LINK_FREQ_320MHZ 320000000ULL
525
526 enum {
527 IMX258_LINK_FREQ_1267MBPS,
528 IMX258_LINK_FREQ_640MBPS,
529 };
530
531 /*
532 * pixel_rate = link_freq * data-rate * nr_of_lanes / bits_per_sample
533 * data rate => double data rate; number of lanes => 4; bits per pixel => 10
534 */
link_freq_to_pixel_rate(u64 f)535 static u64 link_freq_to_pixel_rate(u64 f)
536 {
537 f *= 2 * 4;
538 do_div(f, 10);
539
540 return f;
541 }
542
543 /* Menu items for LINK_FREQ V4L2 control */
544 static const s64 link_freq_menu_items[] = {
545 IMX258_LINK_FREQ_634MHZ,
546 IMX258_LINK_FREQ_320MHZ,
547 };
548
549 /* Link frequency configs */
550 static const struct imx258_link_freq_config link_freq_configs[] = {
551 [IMX258_LINK_FREQ_1267MBPS] = {
552 .pixels_per_line = IMX258_PPL_DEFAULT,
553 .reg_list = {
554 .num_of_regs = ARRAY_SIZE(mipi_data_rate_1267mbps),
555 .regs = mipi_data_rate_1267mbps,
556 }
557 },
558 [IMX258_LINK_FREQ_640MBPS] = {
559 .pixels_per_line = IMX258_PPL_DEFAULT,
560 .reg_list = {
561 .num_of_regs = ARRAY_SIZE(mipi_data_rate_640mbps),
562 .regs = mipi_data_rate_640mbps,
563 }
564 },
565 };
566
567 /* Mode configs */
568 static const struct imx258_mode supported_modes[] = {
569 {
570 .width = 4208,
571 .height = 3118,
572 .vts_def = IMX258_VTS_30FPS,
573 .vts_min = IMX258_VTS_30FPS,
574 .reg_list = {
575 .num_of_regs = ARRAY_SIZE(mode_4208x3118_regs),
576 .regs = mode_4208x3118_regs,
577 },
578 .link_freq_index = IMX258_LINK_FREQ_1267MBPS,
579 },
580 {
581 .width = 2104,
582 .height = 1560,
583 .vts_def = IMX258_VTS_30FPS_2K,
584 .vts_min = IMX258_VTS_30FPS_2K,
585 .reg_list = {
586 .num_of_regs = ARRAY_SIZE(mode_2104_1560_regs),
587 .regs = mode_2104_1560_regs,
588 },
589 .link_freq_index = IMX258_LINK_FREQ_640MBPS,
590 },
591 {
592 .width = 1048,
593 .height = 780,
594 .vts_def = IMX258_VTS_30FPS_VGA,
595 .vts_min = IMX258_VTS_30FPS_VGA,
596 .reg_list = {
597 .num_of_regs = ARRAY_SIZE(mode_1048_780_regs),
598 .regs = mode_1048_780_regs,
599 },
600 .link_freq_index = IMX258_LINK_FREQ_640MBPS,
601 },
602 };
603
604 struct imx258 {
605 struct v4l2_subdev sd;
606 struct media_pad pad;
607
608 struct v4l2_ctrl_handler ctrl_handler;
609 /* V4L2 Controls */
610 struct v4l2_ctrl *link_freq;
611 struct v4l2_ctrl *pixel_rate;
612 struct v4l2_ctrl *vblank;
613 struct v4l2_ctrl *hblank;
614 struct v4l2_ctrl *exposure;
615
616 /* Current mode */
617 const struct imx258_mode *cur_mode;
618
619 /*
620 * Mutex for serialized access:
621 * Protect sensor module set pad format and start/stop streaming safely.
622 */
623 struct mutex mutex;
624
625 /* Streaming on/off */
626 bool streaming;
627
628 struct clk *clk;
629 };
630
to_imx258(struct v4l2_subdev * _sd)631 static inline struct imx258 *to_imx258(struct v4l2_subdev *_sd)
632 {
633 return container_of(_sd, struct imx258, sd);
634 }
635
636 /* Read registers up to 2 at a time */
imx258_read_reg(struct imx258 * imx258,u16 reg,u32 len,u32 * val)637 static int imx258_read_reg(struct imx258 *imx258, u16 reg, u32 len, u32 *val)
638 {
639 struct i2c_client *client = v4l2_get_subdevdata(&imx258->sd);
640 struct i2c_msg msgs[2];
641 u8 addr_buf[2] = { reg >> 8, reg & 0xff };
642 u8 data_buf[4] = { 0, };
643 int ret;
644
645 if (len > 4)
646 return -EINVAL;
647
648 /* Write register address */
649 msgs[0].addr = client->addr;
650 msgs[0].flags = 0;
651 msgs[0].len = ARRAY_SIZE(addr_buf);
652 msgs[0].buf = addr_buf;
653
654 /* Read data from register */
655 msgs[1].addr = client->addr;
656 msgs[1].flags = I2C_M_RD;
657 msgs[1].len = len;
658 msgs[1].buf = &data_buf[4 - len];
659
660 ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
661 if (ret != ARRAY_SIZE(msgs))
662 return -EIO;
663
664 *val = get_unaligned_be32(data_buf);
665
666 return 0;
667 }
668
669 /* Write registers up to 2 at a time */
imx258_write_reg(struct imx258 * imx258,u16 reg,u32 len,u32 val)670 static int imx258_write_reg(struct imx258 *imx258, u16 reg, u32 len, u32 val)
671 {
672 struct i2c_client *client = v4l2_get_subdevdata(&imx258->sd);
673 u8 buf[6];
674
675 if (len > 4)
676 return -EINVAL;
677
678 put_unaligned_be16(reg, buf);
679 put_unaligned_be32(val << (8 * (4 - len)), buf + 2);
680 if (i2c_master_send(client, buf, len + 2) != len + 2)
681 return -EIO;
682
683 return 0;
684 }
685
686 /* Write a list of registers */
imx258_write_regs(struct imx258 * imx258,const struct imx258_reg * regs,u32 len)687 static int imx258_write_regs(struct imx258 *imx258,
688 const struct imx258_reg *regs, u32 len)
689 {
690 struct i2c_client *client = v4l2_get_subdevdata(&imx258->sd);
691 unsigned int i;
692 int ret;
693
694 for (i = 0; i < len; i++) {
695 ret = imx258_write_reg(imx258, regs[i].address, 1,
696 regs[i].val);
697 if (ret) {
698 dev_err_ratelimited(
699 &client->dev,
700 "Failed to write reg 0x%4.4x. error = %d\n",
701 regs[i].address, ret);
702
703 return ret;
704 }
705 }
706
707 return 0;
708 }
709
710 /* Open sub-device */
imx258_open(struct v4l2_subdev * sd,struct v4l2_subdev_fh * fh)711 static int imx258_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
712 {
713 struct v4l2_mbus_framefmt *try_fmt =
714 v4l2_subdev_get_try_format(sd, fh->state, 0);
715
716 /* Initialize try_fmt */
717 try_fmt->width = supported_modes[0].width;
718 try_fmt->height = supported_modes[0].height;
719 try_fmt->code = MEDIA_BUS_FMT_SGRBG10_1X10;
720 try_fmt->field = V4L2_FIELD_NONE;
721
722 return 0;
723 }
724
imx258_update_digital_gain(struct imx258 * imx258,u32 len,u32 val)725 static int imx258_update_digital_gain(struct imx258 *imx258, u32 len, u32 val)
726 {
727 int ret;
728
729 ret = imx258_write_reg(imx258, IMX258_REG_GR_DIGITAL_GAIN,
730 IMX258_REG_VALUE_16BIT,
731 val);
732 if (ret)
733 return ret;
734 ret = imx258_write_reg(imx258, IMX258_REG_GB_DIGITAL_GAIN,
735 IMX258_REG_VALUE_16BIT,
736 val);
737 if (ret)
738 return ret;
739 ret = imx258_write_reg(imx258, IMX258_REG_R_DIGITAL_GAIN,
740 IMX258_REG_VALUE_16BIT,
741 val);
742 if (ret)
743 return ret;
744 ret = imx258_write_reg(imx258, IMX258_REG_B_DIGITAL_GAIN,
745 IMX258_REG_VALUE_16BIT,
746 val);
747 if (ret)
748 return ret;
749 return 0;
750 }
751
imx258_set_ctrl(struct v4l2_ctrl * ctrl)752 static int imx258_set_ctrl(struct v4l2_ctrl *ctrl)
753 {
754 struct imx258 *imx258 =
755 container_of(ctrl->handler, struct imx258, ctrl_handler);
756 struct i2c_client *client = v4l2_get_subdevdata(&imx258->sd);
757 int ret = 0;
758
759 /*
760 * Applying V4L2 control value only happens
761 * when power is up for streaming
762 */
763 if (pm_runtime_get_if_in_use(&client->dev) == 0)
764 return 0;
765
766 switch (ctrl->id) {
767 case V4L2_CID_ANALOGUE_GAIN:
768 ret = imx258_write_reg(imx258, IMX258_REG_ANALOG_GAIN,
769 IMX258_REG_VALUE_16BIT,
770 ctrl->val);
771 break;
772 case V4L2_CID_EXPOSURE:
773 ret = imx258_write_reg(imx258, IMX258_REG_EXPOSURE,
774 IMX258_REG_VALUE_16BIT,
775 ctrl->val);
776 break;
777 case V4L2_CID_DIGITAL_GAIN:
778 ret = imx258_update_digital_gain(imx258, IMX258_REG_VALUE_16BIT,
779 ctrl->val);
780 break;
781 case V4L2_CID_TEST_PATTERN:
782 ret = imx258_write_reg(imx258, IMX258_REG_TEST_PATTERN,
783 IMX258_REG_VALUE_16BIT,
784 ctrl->val);
785 ret = imx258_write_reg(imx258, REG_MIRROR_FLIP_CONTROL,
786 IMX258_REG_VALUE_08BIT,
787 !ctrl->val ? REG_CONFIG_MIRROR_FLIP :
788 REG_CONFIG_FLIP_TEST_PATTERN);
789 break;
790 case V4L2_CID_WIDE_DYNAMIC_RANGE:
791 if (!ctrl->val) {
792 ret = imx258_write_reg(imx258, IMX258_REG_HDR,
793 IMX258_REG_VALUE_08BIT,
794 IMX258_HDR_RATIO_MIN);
795 } else {
796 ret = imx258_write_reg(imx258, IMX258_REG_HDR,
797 IMX258_REG_VALUE_08BIT,
798 IMX258_HDR_ON);
799 if (ret)
800 break;
801 ret = imx258_write_reg(imx258, IMX258_REG_HDR_RATIO,
802 IMX258_REG_VALUE_08BIT,
803 BIT(IMX258_HDR_RATIO_MAX));
804 }
805 break;
806 default:
807 dev_info(&client->dev,
808 "ctrl(id:0x%x,val:0x%x) is not handled\n",
809 ctrl->id, ctrl->val);
810 ret = -EINVAL;
811 break;
812 }
813
814 pm_runtime_put(&client->dev);
815
816 return ret;
817 }
818
819 static const struct v4l2_ctrl_ops imx258_ctrl_ops = {
820 .s_ctrl = imx258_set_ctrl,
821 };
822
imx258_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_mbus_code_enum * code)823 static int imx258_enum_mbus_code(struct v4l2_subdev *sd,
824 struct v4l2_subdev_state *sd_state,
825 struct v4l2_subdev_mbus_code_enum *code)
826 {
827 /* Only one bayer order(GRBG) is supported */
828 if (code->index > 0)
829 return -EINVAL;
830
831 code->code = MEDIA_BUS_FMT_SGRBG10_1X10;
832
833 return 0;
834 }
835
imx258_enum_frame_size(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_frame_size_enum * fse)836 static int imx258_enum_frame_size(struct v4l2_subdev *sd,
837 struct v4l2_subdev_state *sd_state,
838 struct v4l2_subdev_frame_size_enum *fse)
839 {
840 if (fse->index >= ARRAY_SIZE(supported_modes))
841 return -EINVAL;
842
843 if (fse->code != MEDIA_BUS_FMT_SGRBG10_1X10)
844 return -EINVAL;
845
846 fse->min_width = supported_modes[fse->index].width;
847 fse->max_width = fse->min_width;
848 fse->min_height = supported_modes[fse->index].height;
849 fse->max_height = fse->min_height;
850
851 return 0;
852 }
853
imx258_update_pad_format(const struct imx258_mode * mode,struct v4l2_subdev_format * fmt)854 static void imx258_update_pad_format(const struct imx258_mode *mode,
855 struct v4l2_subdev_format *fmt)
856 {
857 fmt->format.width = mode->width;
858 fmt->format.height = mode->height;
859 fmt->format.code = MEDIA_BUS_FMT_SGRBG10_1X10;
860 fmt->format.field = V4L2_FIELD_NONE;
861 }
862
__imx258_get_pad_format(struct imx258 * imx258,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_format * fmt)863 static int __imx258_get_pad_format(struct imx258 *imx258,
864 struct v4l2_subdev_state *sd_state,
865 struct v4l2_subdev_format *fmt)
866 {
867 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY)
868 fmt->format = *v4l2_subdev_get_try_format(&imx258->sd,
869 sd_state,
870 fmt->pad);
871 else
872 imx258_update_pad_format(imx258->cur_mode, fmt);
873
874 return 0;
875 }
876
imx258_get_pad_format(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_format * fmt)877 static int imx258_get_pad_format(struct v4l2_subdev *sd,
878 struct v4l2_subdev_state *sd_state,
879 struct v4l2_subdev_format *fmt)
880 {
881 struct imx258 *imx258 = to_imx258(sd);
882 int ret;
883
884 mutex_lock(&imx258->mutex);
885 ret = __imx258_get_pad_format(imx258, sd_state, fmt);
886 mutex_unlock(&imx258->mutex);
887
888 return ret;
889 }
890
imx258_set_pad_format(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_format * fmt)891 static int imx258_set_pad_format(struct v4l2_subdev *sd,
892 struct v4l2_subdev_state *sd_state,
893 struct v4l2_subdev_format *fmt)
894 {
895 struct imx258 *imx258 = to_imx258(sd);
896 const struct imx258_mode *mode;
897 struct v4l2_mbus_framefmt *framefmt;
898 s32 vblank_def;
899 s32 vblank_min;
900 s64 h_blank;
901 s64 pixel_rate;
902 s64 link_freq;
903
904 mutex_lock(&imx258->mutex);
905
906 /* Only one raw bayer(GBRG) order is supported */
907 fmt->format.code = MEDIA_BUS_FMT_SGRBG10_1X10;
908
909 mode = v4l2_find_nearest_size(supported_modes,
910 ARRAY_SIZE(supported_modes), width, height,
911 fmt->format.width, fmt->format.height);
912 imx258_update_pad_format(mode, fmt);
913 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
914 framefmt = v4l2_subdev_get_try_format(sd, sd_state, fmt->pad);
915 *framefmt = fmt->format;
916 } else {
917 imx258->cur_mode = mode;
918 __v4l2_ctrl_s_ctrl(imx258->link_freq, mode->link_freq_index);
919
920 link_freq = link_freq_menu_items[mode->link_freq_index];
921 pixel_rate = link_freq_to_pixel_rate(link_freq);
922 __v4l2_ctrl_s_ctrl_int64(imx258->pixel_rate, pixel_rate);
923 /* Update limits and set FPS to default */
924 vblank_def = imx258->cur_mode->vts_def -
925 imx258->cur_mode->height;
926 vblank_min = imx258->cur_mode->vts_min -
927 imx258->cur_mode->height;
928 __v4l2_ctrl_modify_range(
929 imx258->vblank, vblank_min,
930 IMX258_VTS_MAX - imx258->cur_mode->height, 1,
931 vblank_def);
932 __v4l2_ctrl_s_ctrl(imx258->vblank, vblank_def);
933 h_blank =
934 link_freq_configs[mode->link_freq_index].pixels_per_line
935 - imx258->cur_mode->width;
936 __v4l2_ctrl_modify_range(imx258->hblank, h_blank,
937 h_blank, 1, h_blank);
938 }
939
940 mutex_unlock(&imx258->mutex);
941
942 return 0;
943 }
944
945 /* Start streaming */
imx258_start_streaming(struct imx258 * imx258)946 static int imx258_start_streaming(struct imx258 *imx258)
947 {
948 struct i2c_client *client = v4l2_get_subdevdata(&imx258->sd);
949 const struct imx258_reg_list *reg_list;
950 int ret, link_freq_index;
951
952 /* Setup PLL */
953 link_freq_index = imx258->cur_mode->link_freq_index;
954 reg_list = &link_freq_configs[link_freq_index].reg_list;
955 ret = imx258_write_regs(imx258, reg_list->regs, reg_list->num_of_regs);
956 if (ret) {
957 dev_err(&client->dev, "%s failed to set plls\n", __func__);
958 return ret;
959 }
960
961 /* Apply default values of current mode */
962 reg_list = &imx258->cur_mode->reg_list;
963 ret = imx258_write_regs(imx258, reg_list->regs, reg_list->num_of_regs);
964 if (ret) {
965 dev_err(&client->dev, "%s failed to set mode\n", __func__);
966 return ret;
967 }
968
969 /* Set Orientation be 180 degree */
970 ret = imx258_write_reg(imx258, REG_MIRROR_FLIP_CONTROL,
971 IMX258_REG_VALUE_08BIT, REG_CONFIG_MIRROR_FLIP);
972 if (ret) {
973 dev_err(&client->dev, "%s failed to set orientation\n",
974 __func__);
975 return ret;
976 }
977
978 /* Apply customized values from user */
979 ret = __v4l2_ctrl_handler_setup(imx258->sd.ctrl_handler);
980 if (ret)
981 return ret;
982
983 /* set stream on register */
984 return imx258_write_reg(imx258, IMX258_REG_MODE_SELECT,
985 IMX258_REG_VALUE_08BIT,
986 IMX258_MODE_STREAMING);
987 }
988
989 /* Stop streaming */
imx258_stop_streaming(struct imx258 * imx258)990 static int imx258_stop_streaming(struct imx258 *imx258)
991 {
992 struct i2c_client *client = v4l2_get_subdevdata(&imx258->sd);
993 int ret;
994
995 /* set stream off register */
996 ret = imx258_write_reg(imx258, IMX258_REG_MODE_SELECT,
997 IMX258_REG_VALUE_08BIT, IMX258_MODE_STANDBY);
998 if (ret)
999 dev_err(&client->dev, "%s failed to set stream\n", __func__);
1000
1001 /*
1002 * Return success even if it was an error, as there is nothing the
1003 * caller can do about it.
1004 */
1005 return 0;
1006 }
1007
imx258_power_on(struct device * dev)1008 static int imx258_power_on(struct device *dev)
1009 {
1010 struct v4l2_subdev *sd = dev_get_drvdata(dev);
1011 struct imx258 *imx258 = to_imx258(sd);
1012 int ret;
1013
1014 ret = clk_prepare_enable(imx258->clk);
1015 if (ret)
1016 dev_err(dev, "failed to enable clock\n");
1017
1018 return ret;
1019 }
1020
imx258_power_off(struct device * dev)1021 static int imx258_power_off(struct device *dev)
1022 {
1023 struct v4l2_subdev *sd = dev_get_drvdata(dev);
1024 struct imx258 *imx258 = to_imx258(sd);
1025
1026 clk_disable_unprepare(imx258->clk);
1027
1028 return 0;
1029 }
1030
imx258_set_stream(struct v4l2_subdev * sd,int enable)1031 static int imx258_set_stream(struct v4l2_subdev *sd, int enable)
1032 {
1033 struct imx258 *imx258 = to_imx258(sd);
1034 struct i2c_client *client = v4l2_get_subdevdata(sd);
1035 int ret = 0;
1036
1037 mutex_lock(&imx258->mutex);
1038 if (imx258->streaming == enable) {
1039 mutex_unlock(&imx258->mutex);
1040 return 0;
1041 }
1042
1043 if (enable) {
1044 ret = pm_runtime_resume_and_get(&client->dev);
1045 if (ret < 0)
1046 goto err_unlock;
1047
1048 /*
1049 * Apply default & customized values
1050 * and then start streaming.
1051 */
1052 ret = imx258_start_streaming(imx258);
1053 if (ret)
1054 goto err_rpm_put;
1055 } else {
1056 imx258_stop_streaming(imx258);
1057 pm_runtime_put(&client->dev);
1058 }
1059
1060 imx258->streaming = enable;
1061 mutex_unlock(&imx258->mutex);
1062
1063 return ret;
1064
1065 err_rpm_put:
1066 pm_runtime_put(&client->dev);
1067 err_unlock:
1068 mutex_unlock(&imx258->mutex);
1069
1070 return ret;
1071 }
1072
imx258_suspend(struct device * dev)1073 static int __maybe_unused imx258_suspend(struct device *dev)
1074 {
1075 struct v4l2_subdev *sd = dev_get_drvdata(dev);
1076 struct imx258 *imx258 = to_imx258(sd);
1077
1078 if (imx258->streaming)
1079 imx258_stop_streaming(imx258);
1080
1081 return 0;
1082 }
1083
imx258_resume(struct device * dev)1084 static int __maybe_unused imx258_resume(struct device *dev)
1085 {
1086 struct v4l2_subdev *sd = dev_get_drvdata(dev);
1087 struct imx258 *imx258 = to_imx258(sd);
1088 int ret;
1089
1090 if (imx258->streaming) {
1091 ret = imx258_start_streaming(imx258);
1092 if (ret)
1093 goto error;
1094 }
1095
1096 return 0;
1097
1098 error:
1099 imx258_stop_streaming(imx258);
1100 imx258->streaming = 0;
1101 return ret;
1102 }
1103
1104 /* Verify chip ID */
imx258_identify_module(struct imx258 * imx258)1105 static int imx258_identify_module(struct imx258 *imx258)
1106 {
1107 struct i2c_client *client = v4l2_get_subdevdata(&imx258->sd);
1108 int ret;
1109 u32 val;
1110
1111 ret = imx258_read_reg(imx258, IMX258_REG_CHIP_ID,
1112 IMX258_REG_VALUE_16BIT, &val);
1113 if (ret) {
1114 dev_err(&client->dev, "failed to read chip id %x\n",
1115 IMX258_CHIP_ID);
1116 return ret;
1117 }
1118
1119 if (val != IMX258_CHIP_ID) {
1120 dev_err(&client->dev, "chip id mismatch: %x!=%x\n",
1121 IMX258_CHIP_ID, val);
1122 return -EIO;
1123 }
1124
1125 return 0;
1126 }
1127
1128 static const struct v4l2_subdev_video_ops imx258_video_ops = {
1129 .s_stream = imx258_set_stream,
1130 };
1131
1132 static const struct v4l2_subdev_pad_ops imx258_pad_ops = {
1133 .enum_mbus_code = imx258_enum_mbus_code,
1134 .get_fmt = imx258_get_pad_format,
1135 .set_fmt = imx258_set_pad_format,
1136 .enum_frame_size = imx258_enum_frame_size,
1137 };
1138
1139 static const struct v4l2_subdev_ops imx258_subdev_ops = {
1140 .video = &imx258_video_ops,
1141 .pad = &imx258_pad_ops,
1142 };
1143
1144 static const struct v4l2_subdev_internal_ops imx258_internal_ops = {
1145 .open = imx258_open,
1146 };
1147
1148 /* Initialize control handlers */
imx258_init_controls(struct imx258 * imx258)1149 static int imx258_init_controls(struct imx258 *imx258)
1150 {
1151 struct i2c_client *client = v4l2_get_subdevdata(&imx258->sd);
1152 struct v4l2_fwnode_device_properties props;
1153 struct v4l2_ctrl_handler *ctrl_hdlr;
1154 struct v4l2_ctrl *vflip, *hflip;
1155 s64 vblank_def;
1156 s64 vblank_min;
1157 s64 pixel_rate_min;
1158 s64 pixel_rate_max;
1159 int ret;
1160
1161 ctrl_hdlr = &imx258->ctrl_handler;
1162 ret = v4l2_ctrl_handler_init(ctrl_hdlr, 13);
1163 if (ret)
1164 return ret;
1165
1166 mutex_init(&imx258->mutex);
1167 ctrl_hdlr->lock = &imx258->mutex;
1168 imx258->link_freq = v4l2_ctrl_new_int_menu(ctrl_hdlr,
1169 &imx258_ctrl_ops,
1170 V4L2_CID_LINK_FREQ,
1171 ARRAY_SIZE(link_freq_menu_items) - 1,
1172 0,
1173 link_freq_menu_items);
1174
1175 if (imx258->link_freq)
1176 imx258->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1177
1178 /* The driver only supports one bayer order and flips by default. */
1179 hflip = v4l2_ctrl_new_std(ctrl_hdlr, &imx258_ctrl_ops,
1180 V4L2_CID_HFLIP, 1, 1, 1, 1);
1181 if (hflip)
1182 hflip->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1183
1184 vflip = v4l2_ctrl_new_std(ctrl_hdlr, &imx258_ctrl_ops,
1185 V4L2_CID_VFLIP, 1, 1, 1, 1);
1186 if (vflip)
1187 vflip->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1188
1189 pixel_rate_max = link_freq_to_pixel_rate(link_freq_menu_items[0]);
1190 pixel_rate_min = link_freq_to_pixel_rate(link_freq_menu_items[1]);
1191 /* By default, PIXEL_RATE is read only */
1192 imx258->pixel_rate = v4l2_ctrl_new_std(ctrl_hdlr, &imx258_ctrl_ops,
1193 V4L2_CID_PIXEL_RATE,
1194 pixel_rate_min, pixel_rate_max,
1195 1, pixel_rate_max);
1196
1197
1198 vblank_def = imx258->cur_mode->vts_def - imx258->cur_mode->height;
1199 vblank_min = imx258->cur_mode->vts_min - imx258->cur_mode->height;
1200 imx258->vblank = v4l2_ctrl_new_std(
1201 ctrl_hdlr, &imx258_ctrl_ops, V4L2_CID_VBLANK,
1202 vblank_min,
1203 IMX258_VTS_MAX - imx258->cur_mode->height, 1,
1204 vblank_def);
1205
1206 if (imx258->vblank)
1207 imx258->vblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1208
1209 imx258->hblank = v4l2_ctrl_new_std(
1210 ctrl_hdlr, &imx258_ctrl_ops, V4L2_CID_HBLANK,
1211 IMX258_PPL_DEFAULT - imx258->cur_mode->width,
1212 IMX258_PPL_DEFAULT - imx258->cur_mode->width,
1213 1,
1214 IMX258_PPL_DEFAULT - imx258->cur_mode->width);
1215
1216 if (imx258->hblank)
1217 imx258->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1218
1219 imx258->exposure = v4l2_ctrl_new_std(
1220 ctrl_hdlr, &imx258_ctrl_ops,
1221 V4L2_CID_EXPOSURE, IMX258_EXPOSURE_MIN,
1222 IMX258_EXPOSURE_MAX, IMX258_EXPOSURE_STEP,
1223 IMX258_EXPOSURE_DEFAULT);
1224
1225 v4l2_ctrl_new_std(ctrl_hdlr, &imx258_ctrl_ops, V4L2_CID_ANALOGUE_GAIN,
1226 IMX258_ANA_GAIN_MIN, IMX258_ANA_GAIN_MAX,
1227 IMX258_ANA_GAIN_STEP, IMX258_ANA_GAIN_DEFAULT);
1228
1229 v4l2_ctrl_new_std(ctrl_hdlr, &imx258_ctrl_ops, V4L2_CID_DIGITAL_GAIN,
1230 IMX258_DGTL_GAIN_MIN, IMX258_DGTL_GAIN_MAX,
1231 IMX258_DGTL_GAIN_STEP,
1232 IMX258_DGTL_GAIN_DEFAULT);
1233
1234 v4l2_ctrl_new_std(ctrl_hdlr, &imx258_ctrl_ops, V4L2_CID_WIDE_DYNAMIC_RANGE,
1235 0, 1, 1, IMX258_HDR_RATIO_DEFAULT);
1236
1237 v4l2_ctrl_new_std_menu_items(ctrl_hdlr, &imx258_ctrl_ops,
1238 V4L2_CID_TEST_PATTERN,
1239 ARRAY_SIZE(imx258_test_pattern_menu) - 1,
1240 0, 0, imx258_test_pattern_menu);
1241
1242 if (ctrl_hdlr->error) {
1243 ret = ctrl_hdlr->error;
1244 dev_err(&client->dev, "%s control init failed (%d)\n",
1245 __func__, ret);
1246 goto error;
1247 }
1248
1249 ret = v4l2_fwnode_device_parse(&client->dev, &props);
1250 if (ret)
1251 goto error;
1252
1253 ret = v4l2_ctrl_new_fwnode_properties(ctrl_hdlr, &imx258_ctrl_ops,
1254 &props);
1255 if (ret)
1256 goto error;
1257
1258 imx258->sd.ctrl_handler = ctrl_hdlr;
1259
1260 return 0;
1261
1262 error:
1263 v4l2_ctrl_handler_free(ctrl_hdlr);
1264 mutex_destroy(&imx258->mutex);
1265
1266 return ret;
1267 }
1268
imx258_free_controls(struct imx258 * imx258)1269 static void imx258_free_controls(struct imx258 *imx258)
1270 {
1271 v4l2_ctrl_handler_free(imx258->sd.ctrl_handler);
1272 mutex_destroy(&imx258->mutex);
1273 }
1274
imx258_probe(struct i2c_client * client)1275 static int imx258_probe(struct i2c_client *client)
1276 {
1277 struct imx258 *imx258;
1278 int ret;
1279 u32 val = 0;
1280
1281 imx258 = devm_kzalloc(&client->dev, sizeof(*imx258), GFP_KERNEL);
1282 if (!imx258)
1283 return -ENOMEM;
1284
1285 imx258->clk = devm_clk_get_optional(&client->dev, NULL);
1286 if (IS_ERR(imx258->clk))
1287 return dev_err_probe(&client->dev, PTR_ERR(imx258->clk),
1288 "error getting clock\n");
1289 if (!imx258->clk) {
1290 dev_dbg(&client->dev,
1291 "no clock provided, using clock-frequency property\n");
1292
1293 device_property_read_u32(&client->dev, "clock-frequency", &val);
1294 } else {
1295 val = clk_get_rate(imx258->clk);
1296 }
1297 if (val != IMX258_INPUT_CLOCK_FREQ) {
1298 dev_err(&client->dev, "input clock frequency not supported\n");
1299 return -EINVAL;
1300 }
1301
1302 /* Initialize subdev */
1303 v4l2_i2c_subdev_init(&imx258->sd, client, &imx258_subdev_ops);
1304
1305 /* Will be powered off via pm_runtime_idle */
1306 ret = imx258_power_on(&client->dev);
1307 if (ret)
1308 return ret;
1309
1310 /* Check module identity */
1311 ret = imx258_identify_module(imx258);
1312 if (ret)
1313 goto error_identify;
1314
1315 /* Set default mode to max resolution */
1316 imx258->cur_mode = &supported_modes[0];
1317
1318 ret = imx258_init_controls(imx258);
1319 if (ret)
1320 goto error_identify;
1321
1322 /* Initialize subdev */
1323 imx258->sd.internal_ops = &imx258_internal_ops;
1324 imx258->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1325 imx258->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
1326
1327 /* Initialize source pad */
1328 imx258->pad.flags = MEDIA_PAD_FL_SOURCE;
1329
1330 ret = media_entity_pads_init(&imx258->sd.entity, 1, &imx258->pad);
1331 if (ret)
1332 goto error_handler_free;
1333
1334 ret = v4l2_async_register_subdev_sensor(&imx258->sd);
1335 if (ret < 0)
1336 goto error_media_entity;
1337
1338 pm_runtime_set_active(&client->dev);
1339 pm_runtime_enable(&client->dev);
1340 pm_runtime_idle(&client->dev);
1341
1342 return 0;
1343
1344 error_media_entity:
1345 media_entity_cleanup(&imx258->sd.entity);
1346
1347 error_handler_free:
1348 imx258_free_controls(imx258);
1349
1350 error_identify:
1351 imx258_power_off(&client->dev);
1352
1353 return ret;
1354 }
1355
imx258_remove(struct i2c_client * client)1356 static void imx258_remove(struct i2c_client *client)
1357 {
1358 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1359 struct imx258 *imx258 = to_imx258(sd);
1360
1361 v4l2_async_unregister_subdev(sd);
1362 media_entity_cleanup(&sd->entity);
1363 imx258_free_controls(imx258);
1364
1365 pm_runtime_disable(&client->dev);
1366 if (!pm_runtime_status_suspended(&client->dev))
1367 imx258_power_off(&client->dev);
1368 pm_runtime_set_suspended(&client->dev);
1369 }
1370
1371 static const struct dev_pm_ops imx258_pm_ops = {
1372 SET_SYSTEM_SLEEP_PM_OPS(imx258_suspend, imx258_resume)
1373 SET_RUNTIME_PM_OPS(imx258_power_off, imx258_power_on, NULL)
1374 };
1375
1376 #ifdef CONFIG_ACPI
1377 static const struct acpi_device_id imx258_acpi_ids[] = {
1378 { "SONY258A" },
1379 { /* sentinel */ }
1380 };
1381
1382 MODULE_DEVICE_TABLE(acpi, imx258_acpi_ids);
1383 #endif
1384
1385 static const struct of_device_id imx258_dt_ids[] = {
1386 { .compatible = "sony,imx258" },
1387 { /* sentinel */ }
1388 };
1389 MODULE_DEVICE_TABLE(of, imx258_dt_ids);
1390
1391 static struct i2c_driver imx258_i2c_driver = {
1392 .driver = {
1393 .name = "imx258",
1394 .pm = &imx258_pm_ops,
1395 .acpi_match_table = ACPI_PTR(imx258_acpi_ids),
1396 .of_match_table = imx258_dt_ids,
1397 },
1398 .probe = imx258_probe,
1399 .remove = imx258_remove,
1400 };
1401
1402 module_i2c_driver(imx258_i2c_driver);
1403
1404 MODULE_AUTHOR("Yeh, Andy <andy.yeh@intel.com>");
1405 MODULE_AUTHOR("Chiang, Alan");
1406 MODULE_AUTHOR("Chen, Jason");
1407 MODULE_DESCRIPTION("Sony IMX258 sensor driver");
1408 MODULE_LICENSE("GPL v2");
1409
