1 /*
2 * adv7180.c Analog Devices ADV7180 video decoder driver
3 * Copyright (c) 2009 Intel Corporation
4 * Copyright (C) 2013 Cogent Embedded, Inc.
5 * Copyright (C) 2013 Renesas Solutions Corp.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17 #include <linux/module.h>
18 #include <linux/init.h>
19 #include <linux/errno.h>
20 #include <linux/kernel.h>
21 #include <linux/interrupt.h>
22 #include <linux/i2c.h>
23 #include <linux/slab.h>
24 #include <linux/of.h>
25 #include <linux/gpio/consumer.h>
26 #include <linux/videodev2.h>
27 #include <media/v4l2-ioctl.h>
28 #include <media/v4l2-event.h>
29 #include <media/v4l2-device.h>
30 #include <media/v4l2-ctrls.h>
31 #include <linux/mutex.h>
32 #include <linux/delay.h>
33
34 #define ADV7180_STD_AD_PAL_BG_NTSC_J_SECAM 0x0
35 #define ADV7180_STD_AD_PAL_BG_NTSC_J_SECAM_PED 0x1
36 #define ADV7180_STD_AD_PAL_N_NTSC_J_SECAM 0x2
37 #define ADV7180_STD_AD_PAL_N_NTSC_M_SECAM 0x3
38 #define ADV7180_STD_NTSC_J 0x4
39 #define ADV7180_STD_NTSC_M 0x5
40 #define ADV7180_STD_PAL60 0x6
41 #define ADV7180_STD_NTSC_443 0x7
42 #define ADV7180_STD_PAL_BG 0x8
43 #define ADV7180_STD_PAL_N 0x9
44 #define ADV7180_STD_PAL_M 0xa
45 #define ADV7180_STD_PAL_M_PED 0xb
46 #define ADV7180_STD_PAL_COMB_N 0xc
47 #define ADV7180_STD_PAL_COMB_N_PED 0xd
48 #define ADV7180_STD_PAL_SECAM 0xe
49 #define ADV7180_STD_PAL_SECAM_PED 0xf
50
51 #define ADV7180_REG_INPUT_CONTROL 0x0000
52 #define ADV7180_INPUT_CONTROL_INSEL_MASK 0x0f
53
54 #define ADV7182_REG_INPUT_VIDSEL 0x0002
55
56 #define ADV7180_REG_OUTPUT_CONTROL 0x0003
57 #define ADV7180_REG_EXTENDED_OUTPUT_CONTROL 0x0004
58 #define ADV7180_EXTENDED_OUTPUT_CONTROL_NTSCDIS 0xC5
59
60 #define ADV7180_REG_AUTODETECT_ENABLE 0x0007
61 #define ADV7180_AUTODETECT_DEFAULT 0x7f
62 /* Contrast */
63 #define ADV7180_REG_CON 0x0008 /*Unsigned */
64 #define ADV7180_CON_MIN 0
65 #define ADV7180_CON_DEF 128
66 #define ADV7180_CON_MAX 255
67 /* Brightness*/
68 #define ADV7180_REG_BRI 0x000a /*Signed */
69 #define ADV7180_BRI_MIN -128
70 #define ADV7180_BRI_DEF 0
71 #define ADV7180_BRI_MAX 127
72 /* Hue */
73 #define ADV7180_REG_HUE 0x000b /*Signed, inverted */
74 #define ADV7180_HUE_MIN -127
75 #define ADV7180_HUE_DEF 0
76 #define ADV7180_HUE_MAX 128
77
78 #define ADV7180_REG_CTRL 0x000e
79 #define ADV7180_CTRL_IRQ_SPACE 0x20
80
81 #define ADV7180_REG_PWR_MAN 0x0f
82 #define ADV7180_PWR_MAN_ON 0x04
83 #define ADV7180_PWR_MAN_OFF 0x24
84 #define ADV7180_PWR_MAN_RES 0x80
85
86 #define ADV7180_REG_STATUS1 0x0010
87 #define ADV7180_STATUS1_IN_LOCK 0x01
88 #define ADV7180_STATUS1_AUTOD_MASK 0x70
89 #define ADV7180_STATUS1_AUTOD_NTSM_M_J 0x00
90 #define ADV7180_STATUS1_AUTOD_NTSC_4_43 0x10
91 #define ADV7180_STATUS1_AUTOD_PAL_M 0x20
92 #define ADV7180_STATUS1_AUTOD_PAL_60 0x30
93 #define ADV7180_STATUS1_AUTOD_PAL_B_G 0x40
94 #define ADV7180_STATUS1_AUTOD_SECAM 0x50
95 #define ADV7180_STATUS1_AUTOD_PAL_COMB 0x60
96 #define ADV7180_STATUS1_AUTOD_SECAM_525 0x70
97
98 #define ADV7180_REG_IDENT 0x0011
99 #define ADV7180_ID_7180 0x18
100
101 #define ADV7180_REG_STATUS3 0x0013
102 #define ADV7180_REG_ANALOG_CLAMP_CTL 0x0014
103 #define ADV7180_REG_SHAP_FILTER_CTL_1 0x0017
104 #define ADV7180_REG_CTRL_2 0x001d
105 #define ADV7180_REG_VSYNC_FIELD_CTL_1 0x0031
106 #define ADV7180_REG_MANUAL_WIN_CTL_1 0x003d
107 #define ADV7180_REG_MANUAL_WIN_CTL_2 0x003e
108 #define ADV7180_REG_MANUAL_WIN_CTL_3 0x003f
109 #define ADV7180_REG_LOCK_CNT 0x0051
110 #define ADV7180_REG_CVBS_TRIM 0x0052
111 #define ADV7180_REG_CLAMP_ADJ 0x005a
112 #define ADV7180_REG_RES_CIR 0x005f
113 #define ADV7180_REG_DIFF_MODE 0x0060
114
115 #define ADV7180_REG_ICONF1 0x2040
116 #define ADV7180_ICONF1_ACTIVE_LOW 0x01
117 #define ADV7180_ICONF1_PSYNC_ONLY 0x10
118 #define ADV7180_ICONF1_ACTIVE_TO_CLR 0xC0
119 /* Saturation */
120 #define ADV7180_REG_SD_SAT_CB 0x00e3 /*Unsigned */
121 #define ADV7180_REG_SD_SAT_CR 0x00e4 /*Unsigned */
122 #define ADV7180_SAT_MIN 0
123 #define ADV7180_SAT_DEF 128
124 #define ADV7180_SAT_MAX 255
125
126 #define ADV7180_IRQ1_LOCK 0x01
127 #define ADV7180_IRQ1_UNLOCK 0x02
128 #define ADV7180_REG_ISR1 0x2042
129 #define ADV7180_REG_ICR1 0x2043
130 #define ADV7180_REG_IMR1 0x2044
131 #define ADV7180_REG_IMR2 0x2048
132 #define ADV7180_IRQ3_AD_CHANGE 0x08
133 #define ADV7180_REG_ISR3 0x204A
134 #define ADV7180_REG_ICR3 0x204B
135 #define ADV7180_REG_IMR3 0x204C
136 #define ADV7180_REG_IMR4 0x2050
137
138 #define ADV7180_REG_NTSC_V_BIT_END 0x00E6
139 #define ADV7180_NTSC_V_BIT_END_MANUAL_NVEND 0x4F
140
141 #define ADV7180_REG_VPP_SLAVE_ADDR 0xFD
142 #define ADV7180_REG_CSI_SLAVE_ADDR 0xFE
143
144 #define ADV7180_REG_ACE_CTRL1 0x4080
145 #define ADV7180_REG_ACE_CTRL5 0x4084
146 #define ADV7180_REG_FLCONTROL 0x40e0
147 #define ADV7180_FLCONTROL_FL_ENABLE 0x1
148
149 #define ADV7180_REG_RST_CLAMP 0x809c
150 #define ADV7180_REG_AGC_ADJ1 0x80b6
151 #define ADV7180_REG_AGC_ADJ2 0x80c0
152
153 #define ADV7180_CSI_REG_PWRDN 0x00
154 #define ADV7180_CSI_PWRDN 0x80
155
156 #define ADV7180_INPUT_CVBS_AIN1 0x00
157 #define ADV7180_INPUT_CVBS_AIN2 0x01
158 #define ADV7180_INPUT_CVBS_AIN3 0x02
159 #define ADV7180_INPUT_CVBS_AIN4 0x03
160 #define ADV7180_INPUT_CVBS_AIN5 0x04
161 #define ADV7180_INPUT_CVBS_AIN6 0x05
162 #define ADV7180_INPUT_SVIDEO_AIN1_AIN2 0x06
163 #define ADV7180_INPUT_SVIDEO_AIN3_AIN4 0x07
164 #define ADV7180_INPUT_SVIDEO_AIN5_AIN6 0x08
165 #define ADV7180_INPUT_YPRPB_AIN1_AIN2_AIN3 0x09
166 #define ADV7180_INPUT_YPRPB_AIN4_AIN5_AIN6 0x0a
167
168 #define ADV7182_INPUT_CVBS_AIN1 0x00
169 #define ADV7182_INPUT_CVBS_AIN2 0x01
170 #define ADV7182_INPUT_CVBS_AIN3 0x02
171 #define ADV7182_INPUT_CVBS_AIN4 0x03
172 #define ADV7182_INPUT_CVBS_AIN5 0x04
173 #define ADV7182_INPUT_CVBS_AIN6 0x05
174 #define ADV7182_INPUT_CVBS_AIN7 0x06
175 #define ADV7182_INPUT_CVBS_AIN8 0x07
176 #define ADV7182_INPUT_SVIDEO_AIN1_AIN2 0x08
177 #define ADV7182_INPUT_SVIDEO_AIN3_AIN4 0x09
178 #define ADV7182_INPUT_SVIDEO_AIN5_AIN6 0x0a
179 #define ADV7182_INPUT_SVIDEO_AIN7_AIN8 0x0b
180 #define ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3 0x0c
181 #define ADV7182_INPUT_YPRPB_AIN4_AIN5_AIN6 0x0d
182 #define ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2 0x0e
183 #define ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4 0x0f
184 #define ADV7182_INPUT_DIFF_CVBS_AIN5_AIN6 0x10
185 #define ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8 0x11
186
187 #define ADV7180_DEFAULT_CSI_I2C_ADDR 0x44
188 #define ADV7180_DEFAULT_VPP_I2C_ADDR 0x42
189
190 #define V4L2_CID_ADV_FAST_SWITCH (V4L2_CID_USER_ADV7180_BASE + 0x00)
191
192 struct adv7180_state;
193
194 #define ADV7180_FLAG_RESET_POWERED BIT(0)
195 #define ADV7180_FLAG_V2 BIT(1)
196 #define ADV7180_FLAG_MIPI_CSI2 BIT(2)
197 #define ADV7180_FLAG_I2P BIT(3)
198
199 struct adv7180_chip_info {
200 unsigned int flags;
201 unsigned int valid_input_mask;
202 int (*set_std)(struct adv7180_state *st, unsigned int std);
203 int (*select_input)(struct adv7180_state *st, unsigned int input);
204 int (*init)(struct adv7180_state *state);
205 };
206
207 struct adv7180_state {
208 struct v4l2_ctrl_handler ctrl_hdl;
209 struct v4l2_subdev sd;
210 struct media_pad pad;
211 struct mutex mutex; /* mutual excl. when accessing chip */
212 int irq;
213 struct gpio_desc *pwdn_gpio;
214 v4l2_std_id curr_norm;
215 bool powered;
216 bool streaming;
217 u8 input;
218
219 struct i2c_client *client;
220 unsigned int register_page;
221 struct i2c_client *csi_client;
222 struct i2c_client *vpp_client;
223 const struct adv7180_chip_info *chip_info;
224 enum v4l2_field field;
225 };
226 #define to_adv7180_sd(_ctrl) (&container_of(_ctrl->handler, \
227 struct adv7180_state, \
228 ctrl_hdl)->sd)
229
adv7180_select_page(struct adv7180_state * state,unsigned int page)230 static int adv7180_select_page(struct adv7180_state *state, unsigned int page)
231 {
232 if (state->register_page != page) {
233 i2c_smbus_write_byte_data(state->client, ADV7180_REG_CTRL,
234 page);
235 state->register_page = page;
236 }
237
238 return 0;
239 }
240
adv7180_write(struct adv7180_state * state,unsigned int reg,unsigned int value)241 static int adv7180_write(struct adv7180_state *state, unsigned int reg,
242 unsigned int value)
243 {
244 lockdep_assert_held(&state->mutex);
245 adv7180_select_page(state, reg >> 8);
246 return i2c_smbus_write_byte_data(state->client, reg & 0xff, value);
247 }
248
adv7180_read(struct adv7180_state * state,unsigned int reg)249 static int adv7180_read(struct adv7180_state *state, unsigned int reg)
250 {
251 lockdep_assert_held(&state->mutex);
252 adv7180_select_page(state, reg >> 8);
253 return i2c_smbus_read_byte_data(state->client, reg & 0xff);
254 }
255
adv7180_csi_write(struct adv7180_state * state,unsigned int reg,unsigned int value)256 static int adv7180_csi_write(struct adv7180_state *state, unsigned int reg,
257 unsigned int value)
258 {
259 return i2c_smbus_write_byte_data(state->csi_client, reg, value);
260 }
261
adv7180_set_video_standard(struct adv7180_state * state,unsigned int std)262 static int adv7180_set_video_standard(struct adv7180_state *state,
263 unsigned int std)
264 {
265 return state->chip_info->set_std(state, std);
266 }
267
adv7180_vpp_write(struct adv7180_state * state,unsigned int reg,unsigned int value)268 static int adv7180_vpp_write(struct adv7180_state *state, unsigned int reg,
269 unsigned int value)
270 {
271 return i2c_smbus_write_byte_data(state->vpp_client, reg, value);
272 }
273
adv7180_std_to_v4l2(u8 status1)274 static v4l2_std_id adv7180_std_to_v4l2(u8 status1)
275 {
276 /* in case V4L2_IN_ST_NO_SIGNAL */
277 if (!(status1 & ADV7180_STATUS1_IN_LOCK))
278 return V4L2_STD_UNKNOWN;
279
280 switch (status1 & ADV7180_STATUS1_AUTOD_MASK) {
281 case ADV7180_STATUS1_AUTOD_NTSM_M_J:
282 return V4L2_STD_NTSC;
283 case ADV7180_STATUS1_AUTOD_NTSC_4_43:
284 return V4L2_STD_NTSC_443;
285 case ADV7180_STATUS1_AUTOD_PAL_M:
286 return V4L2_STD_PAL_M;
287 case ADV7180_STATUS1_AUTOD_PAL_60:
288 return V4L2_STD_PAL_60;
289 case ADV7180_STATUS1_AUTOD_PAL_B_G:
290 return V4L2_STD_PAL;
291 case ADV7180_STATUS1_AUTOD_SECAM:
292 return V4L2_STD_SECAM;
293 case ADV7180_STATUS1_AUTOD_PAL_COMB:
294 return V4L2_STD_PAL_Nc | V4L2_STD_PAL_N;
295 case ADV7180_STATUS1_AUTOD_SECAM_525:
296 return V4L2_STD_SECAM;
297 default:
298 return V4L2_STD_UNKNOWN;
299 }
300 }
301
v4l2_std_to_adv7180(v4l2_std_id std)302 static int v4l2_std_to_adv7180(v4l2_std_id std)
303 {
304 if (std == V4L2_STD_PAL_60)
305 return ADV7180_STD_PAL60;
306 if (std == V4L2_STD_NTSC_443)
307 return ADV7180_STD_NTSC_443;
308 if (std == V4L2_STD_PAL_N)
309 return ADV7180_STD_PAL_N;
310 if (std == V4L2_STD_PAL_M)
311 return ADV7180_STD_PAL_M;
312 if (std == V4L2_STD_PAL_Nc)
313 return ADV7180_STD_PAL_COMB_N;
314
315 if (std & V4L2_STD_PAL)
316 return ADV7180_STD_PAL_BG;
317 if (std & V4L2_STD_NTSC)
318 return ADV7180_STD_NTSC_M;
319 if (std & V4L2_STD_SECAM)
320 return ADV7180_STD_PAL_SECAM;
321
322 return -EINVAL;
323 }
324
adv7180_status_to_v4l2(u8 status1)325 static u32 adv7180_status_to_v4l2(u8 status1)
326 {
327 if (!(status1 & ADV7180_STATUS1_IN_LOCK))
328 return V4L2_IN_ST_NO_SIGNAL;
329
330 return 0;
331 }
332
__adv7180_status(struct adv7180_state * state,u32 * status,v4l2_std_id * std)333 static int __adv7180_status(struct adv7180_state *state, u32 *status,
334 v4l2_std_id *std)
335 {
336 int status1 = adv7180_read(state, ADV7180_REG_STATUS1);
337
338 if (status1 < 0)
339 return status1;
340
341 if (status)
342 *status = adv7180_status_to_v4l2(status1);
343 if (std)
344 *std = adv7180_std_to_v4l2(status1);
345
346 return 0;
347 }
348
to_state(struct v4l2_subdev * sd)349 static inline struct adv7180_state *to_state(struct v4l2_subdev *sd)
350 {
351 return container_of(sd, struct adv7180_state, sd);
352 }
353
adv7180_querystd(struct v4l2_subdev * sd,v4l2_std_id * std)354 static int adv7180_querystd(struct v4l2_subdev *sd, v4l2_std_id *std)
355 {
356 struct adv7180_state *state = to_state(sd);
357 int err = mutex_lock_interruptible(&state->mutex);
358 if (err)
359 return err;
360
361 if (state->streaming) {
362 err = -EBUSY;
363 goto unlock;
364 }
365
366 err = adv7180_set_video_standard(state,
367 ADV7180_STD_AD_PAL_BG_NTSC_J_SECAM);
368 if (err)
369 goto unlock;
370
371 msleep(100);
372 __adv7180_status(state, NULL, std);
373
374 err = v4l2_std_to_adv7180(state->curr_norm);
375 if (err < 0)
376 goto unlock;
377
378 err = adv7180_set_video_standard(state, err);
379
380 unlock:
381 mutex_unlock(&state->mutex);
382 return err;
383 }
384
adv7180_s_routing(struct v4l2_subdev * sd,u32 input,u32 output,u32 config)385 static int adv7180_s_routing(struct v4l2_subdev *sd, u32 input,
386 u32 output, u32 config)
387 {
388 struct adv7180_state *state = to_state(sd);
389 int ret = mutex_lock_interruptible(&state->mutex);
390
391 if (ret)
392 return ret;
393
394 if (input > 31 || !(BIT(input) & state->chip_info->valid_input_mask)) {
395 ret = -EINVAL;
396 goto out;
397 }
398
399 ret = state->chip_info->select_input(state, input);
400
401 if (ret == 0)
402 state->input = input;
403 out:
404 mutex_unlock(&state->mutex);
405 return ret;
406 }
407
adv7180_g_input_status(struct v4l2_subdev * sd,u32 * status)408 static int adv7180_g_input_status(struct v4l2_subdev *sd, u32 *status)
409 {
410 struct adv7180_state *state = to_state(sd);
411 int ret = mutex_lock_interruptible(&state->mutex);
412 if (ret)
413 return ret;
414
415 ret = __adv7180_status(state, status, NULL);
416 mutex_unlock(&state->mutex);
417 return ret;
418 }
419
adv7180_program_std(struct adv7180_state * state)420 static int adv7180_program_std(struct adv7180_state *state)
421 {
422 int ret;
423
424 ret = v4l2_std_to_adv7180(state->curr_norm);
425 if (ret < 0)
426 return ret;
427
428 ret = adv7180_set_video_standard(state, ret);
429 if (ret < 0)
430 return ret;
431 return 0;
432 }
433
adv7180_s_std(struct v4l2_subdev * sd,v4l2_std_id std)434 static int adv7180_s_std(struct v4l2_subdev *sd, v4l2_std_id std)
435 {
436 struct adv7180_state *state = to_state(sd);
437 int ret = mutex_lock_interruptible(&state->mutex);
438
439 if (ret)
440 return ret;
441
442 /* Make sure we can support this std */
443 ret = v4l2_std_to_adv7180(std);
444 if (ret < 0)
445 goto out;
446
447 state->curr_norm = std;
448
449 ret = adv7180_program_std(state);
450 out:
451 mutex_unlock(&state->mutex);
452 return ret;
453 }
454
adv7180_g_std(struct v4l2_subdev * sd,v4l2_std_id * norm)455 static int adv7180_g_std(struct v4l2_subdev *sd, v4l2_std_id *norm)
456 {
457 struct adv7180_state *state = to_state(sd);
458
459 *norm = state->curr_norm;
460
461 return 0;
462 }
463
adv7180_g_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_frame_interval * fi)464 static int adv7180_g_frame_interval(struct v4l2_subdev *sd,
465 struct v4l2_subdev_frame_interval *fi)
466 {
467 struct adv7180_state *state = to_state(sd);
468
469 if (state->curr_norm & V4L2_STD_525_60) {
470 fi->interval.numerator = 1001;
471 fi->interval.denominator = 30000;
472 } else {
473 fi->interval.numerator = 1;
474 fi->interval.denominator = 25;
475 }
476
477 return 0;
478 }
479
adv7180_set_power_pin(struct adv7180_state * state,bool on)480 static void adv7180_set_power_pin(struct adv7180_state *state, bool on)
481 {
482 if (!state->pwdn_gpio)
483 return;
484
485 if (on) {
486 gpiod_set_value_cansleep(state->pwdn_gpio, 0);
487 usleep_range(5000, 10000);
488 } else {
489 gpiod_set_value_cansleep(state->pwdn_gpio, 1);
490 }
491 }
492
adv7180_set_power(struct adv7180_state * state,bool on)493 static int adv7180_set_power(struct adv7180_state *state, bool on)
494 {
495 u8 val;
496 int ret;
497
498 if (on)
499 val = ADV7180_PWR_MAN_ON;
500 else
501 val = ADV7180_PWR_MAN_OFF;
502
503 ret = adv7180_write(state, ADV7180_REG_PWR_MAN, val);
504 if (ret)
505 return ret;
506
507 if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) {
508 if (on) {
509 adv7180_csi_write(state, 0xDE, 0x02);
510 adv7180_csi_write(state, 0xD2, 0xF7);
511 adv7180_csi_write(state, 0xD8, 0x65);
512 adv7180_csi_write(state, 0xE0, 0x09);
513 adv7180_csi_write(state, 0x2C, 0x00);
514 if (state->field == V4L2_FIELD_NONE)
515 adv7180_csi_write(state, 0x1D, 0x80);
516 adv7180_csi_write(state, 0x00, 0x00);
517 } else {
518 adv7180_csi_write(state, 0x00, 0x80);
519 }
520 }
521
522 return 0;
523 }
524
adv7180_s_power(struct v4l2_subdev * sd,int on)525 static int adv7180_s_power(struct v4l2_subdev *sd, int on)
526 {
527 struct adv7180_state *state = to_state(sd);
528 int ret;
529
530 ret = mutex_lock_interruptible(&state->mutex);
531 if (ret)
532 return ret;
533
534 ret = adv7180_set_power(state, on);
535 if (ret == 0)
536 state->powered = on;
537
538 mutex_unlock(&state->mutex);
539 return ret;
540 }
541
adv7180_s_ctrl(struct v4l2_ctrl * ctrl)542 static int adv7180_s_ctrl(struct v4l2_ctrl *ctrl)
543 {
544 struct v4l2_subdev *sd = to_adv7180_sd(ctrl);
545 struct adv7180_state *state = to_state(sd);
546 int ret = mutex_lock_interruptible(&state->mutex);
547 int val;
548
549 if (ret)
550 return ret;
551 val = ctrl->val;
552 switch (ctrl->id) {
553 case V4L2_CID_BRIGHTNESS:
554 ret = adv7180_write(state, ADV7180_REG_BRI, val);
555 break;
556 case V4L2_CID_HUE:
557 /*Hue is inverted according to HSL chart */
558 ret = adv7180_write(state, ADV7180_REG_HUE, -val);
559 break;
560 case V4L2_CID_CONTRAST:
561 ret = adv7180_write(state, ADV7180_REG_CON, val);
562 break;
563 case V4L2_CID_SATURATION:
564 /*
565 *This could be V4L2_CID_BLUE_BALANCE/V4L2_CID_RED_BALANCE
566 *Let's not confuse the user, everybody understands saturation
567 */
568 ret = adv7180_write(state, ADV7180_REG_SD_SAT_CB, val);
569 if (ret < 0)
570 break;
571 ret = adv7180_write(state, ADV7180_REG_SD_SAT_CR, val);
572 break;
573 case V4L2_CID_ADV_FAST_SWITCH:
574 if (ctrl->val) {
575 /* ADI required write */
576 adv7180_write(state, 0x80d9, 0x44);
577 adv7180_write(state, ADV7180_REG_FLCONTROL,
578 ADV7180_FLCONTROL_FL_ENABLE);
579 } else {
580 /* ADI required write */
581 adv7180_write(state, 0x80d9, 0xc4);
582 adv7180_write(state, ADV7180_REG_FLCONTROL, 0x00);
583 }
584 break;
585 default:
586 ret = -EINVAL;
587 }
588
589 mutex_unlock(&state->mutex);
590 return ret;
591 }
592
593 static const struct v4l2_ctrl_ops adv7180_ctrl_ops = {
594 .s_ctrl = adv7180_s_ctrl,
595 };
596
597 static const struct v4l2_ctrl_config adv7180_ctrl_fast_switch = {
598 .ops = &adv7180_ctrl_ops,
599 .id = V4L2_CID_ADV_FAST_SWITCH,
600 .name = "Fast Switching",
601 .type = V4L2_CTRL_TYPE_BOOLEAN,
602 .min = 0,
603 .max = 1,
604 .step = 1,
605 };
606
adv7180_init_controls(struct adv7180_state * state)607 static int adv7180_init_controls(struct adv7180_state *state)
608 {
609 v4l2_ctrl_handler_init(&state->ctrl_hdl, 4);
610
611 v4l2_ctrl_new_std(&state->ctrl_hdl, &adv7180_ctrl_ops,
612 V4L2_CID_BRIGHTNESS, ADV7180_BRI_MIN,
613 ADV7180_BRI_MAX, 1, ADV7180_BRI_DEF);
614 v4l2_ctrl_new_std(&state->ctrl_hdl, &adv7180_ctrl_ops,
615 V4L2_CID_CONTRAST, ADV7180_CON_MIN,
616 ADV7180_CON_MAX, 1, ADV7180_CON_DEF);
617 v4l2_ctrl_new_std(&state->ctrl_hdl, &adv7180_ctrl_ops,
618 V4L2_CID_SATURATION, ADV7180_SAT_MIN,
619 ADV7180_SAT_MAX, 1, ADV7180_SAT_DEF);
620 v4l2_ctrl_new_std(&state->ctrl_hdl, &adv7180_ctrl_ops,
621 V4L2_CID_HUE, ADV7180_HUE_MIN,
622 ADV7180_HUE_MAX, 1, ADV7180_HUE_DEF);
623 v4l2_ctrl_new_custom(&state->ctrl_hdl, &adv7180_ctrl_fast_switch, NULL);
624
625 state->sd.ctrl_handler = &state->ctrl_hdl;
626 if (state->ctrl_hdl.error) {
627 int err = state->ctrl_hdl.error;
628
629 v4l2_ctrl_handler_free(&state->ctrl_hdl);
630 return err;
631 }
632 v4l2_ctrl_handler_setup(&state->ctrl_hdl);
633
634 return 0;
635 }
adv7180_exit_controls(struct adv7180_state * state)636 static void adv7180_exit_controls(struct adv7180_state *state)
637 {
638 v4l2_ctrl_handler_free(&state->ctrl_hdl);
639 }
640
adv7180_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_mbus_code_enum * code)641 static int adv7180_enum_mbus_code(struct v4l2_subdev *sd,
642 struct v4l2_subdev_pad_config *cfg,
643 struct v4l2_subdev_mbus_code_enum *code)
644 {
645 if (code->index != 0)
646 return -EINVAL;
647
648 code->code = MEDIA_BUS_FMT_UYVY8_2X8;
649
650 return 0;
651 }
652
adv7180_mbus_fmt(struct v4l2_subdev * sd,struct v4l2_mbus_framefmt * fmt)653 static int adv7180_mbus_fmt(struct v4l2_subdev *sd,
654 struct v4l2_mbus_framefmt *fmt)
655 {
656 struct adv7180_state *state = to_state(sd);
657
658 fmt->code = MEDIA_BUS_FMT_UYVY8_2X8;
659 fmt->colorspace = V4L2_COLORSPACE_SMPTE170M;
660 fmt->width = 720;
661 fmt->height = state->curr_norm & V4L2_STD_525_60 ? 480 : 576;
662
663 if (state->field == V4L2_FIELD_ALTERNATE)
664 fmt->height /= 2;
665
666 return 0;
667 }
668
adv7180_set_field_mode(struct adv7180_state * state)669 static int adv7180_set_field_mode(struct adv7180_state *state)
670 {
671 if (!(state->chip_info->flags & ADV7180_FLAG_I2P))
672 return 0;
673
674 if (state->field == V4L2_FIELD_NONE) {
675 if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) {
676 adv7180_csi_write(state, 0x01, 0x20);
677 adv7180_csi_write(state, 0x02, 0x28);
678 adv7180_csi_write(state, 0x03, 0x38);
679 adv7180_csi_write(state, 0x04, 0x30);
680 adv7180_csi_write(state, 0x05, 0x30);
681 adv7180_csi_write(state, 0x06, 0x80);
682 adv7180_csi_write(state, 0x07, 0x70);
683 adv7180_csi_write(state, 0x08, 0x50);
684 }
685 adv7180_vpp_write(state, 0xa3, 0x00);
686 adv7180_vpp_write(state, 0x5b, 0x00);
687 adv7180_vpp_write(state, 0x55, 0x80);
688 } else {
689 if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) {
690 adv7180_csi_write(state, 0x01, 0x18);
691 adv7180_csi_write(state, 0x02, 0x18);
692 adv7180_csi_write(state, 0x03, 0x30);
693 adv7180_csi_write(state, 0x04, 0x20);
694 adv7180_csi_write(state, 0x05, 0x28);
695 adv7180_csi_write(state, 0x06, 0x40);
696 adv7180_csi_write(state, 0x07, 0x58);
697 adv7180_csi_write(state, 0x08, 0x30);
698 }
699 adv7180_vpp_write(state, 0xa3, 0x70);
700 adv7180_vpp_write(state, 0x5b, 0x80);
701 adv7180_vpp_write(state, 0x55, 0x00);
702 }
703
704 return 0;
705 }
706
adv7180_get_pad_format(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * format)707 static int adv7180_get_pad_format(struct v4l2_subdev *sd,
708 struct v4l2_subdev_pad_config *cfg,
709 struct v4l2_subdev_format *format)
710 {
711 struct adv7180_state *state = to_state(sd);
712
713 if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
714 format->format = *v4l2_subdev_get_try_format(sd, cfg, 0);
715 } else {
716 adv7180_mbus_fmt(sd, &format->format);
717 format->format.field = state->field;
718 }
719
720 return 0;
721 }
722
adv7180_set_pad_format(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * format)723 static int adv7180_set_pad_format(struct v4l2_subdev *sd,
724 struct v4l2_subdev_pad_config *cfg,
725 struct v4l2_subdev_format *format)
726 {
727 struct adv7180_state *state = to_state(sd);
728 struct v4l2_mbus_framefmt *framefmt;
729 int ret;
730
731 switch (format->format.field) {
732 case V4L2_FIELD_NONE:
733 if (state->chip_info->flags & ADV7180_FLAG_I2P)
734 break;
735 /* fall through */
736 default:
737 format->format.field = V4L2_FIELD_ALTERNATE;
738 break;
739 }
740
741 ret = adv7180_mbus_fmt(sd, &format->format);
742
743 if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE) {
744 if (state->field != format->format.field) {
745 state->field = format->format.field;
746 adv7180_set_power(state, false);
747 adv7180_set_field_mode(state);
748 adv7180_set_power(state, true);
749 }
750 } else {
751 framefmt = v4l2_subdev_get_try_format(sd, cfg, 0);
752 *framefmt = format->format;
753 }
754
755 return ret;
756 }
757
adv7180_g_mbus_config(struct v4l2_subdev * sd,struct v4l2_mbus_config * cfg)758 static int adv7180_g_mbus_config(struct v4l2_subdev *sd,
759 struct v4l2_mbus_config *cfg)
760 {
761 struct adv7180_state *state = to_state(sd);
762
763 if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) {
764 cfg->type = V4L2_MBUS_CSI2;
765 cfg->flags = V4L2_MBUS_CSI2_1_LANE |
766 V4L2_MBUS_CSI2_CHANNEL_0 |
767 V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
768 } else {
769 /*
770 * The ADV7180 sensor supports BT.601/656 output modes.
771 * The BT.656 is default and not yet configurable by s/w.
772 */
773 cfg->flags = V4L2_MBUS_MASTER | V4L2_MBUS_PCLK_SAMPLE_RISING |
774 V4L2_MBUS_DATA_ACTIVE_HIGH;
775 cfg->type = V4L2_MBUS_BT656;
776 }
777
778 return 0;
779 }
780
adv7180_g_pixelaspect(struct v4l2_subdev * sd,struct v4l2_fract * aspect)781 static int adv7180_g_pixelaspect(struct v4l2_subdev *sd, struct v4l2_fract *aspect)
782 {
783 struct adv7180_state *state = to_state(sd);
784
785 if (state->curr_norm & V4L2_STD_525_60) {
786 aspect->numerator = 11;
787 aspect->denominator = 10;
788 } else {
789 aspect->numerator = 54;
790 aspect->denominator = 59;
791 }
792
793 return 0;
794 }
795
adv7180_g_tvnorms(struct v4l2_subdev * sd,v4l2_std_id * norm)796 static int adv7180_g_tvnorms(struct v4l2_subdev *sd, v4l2_std_id *norm)
797 {
798 *norm = V4L2_STD_ALL;
799 return 0;
800 }
801
adv7180_s_stream(struct v4l2_subdev * sd,int enable)802 static int adv7180_s_stream(struct v4l2_subdev *sd, int enable)
803 {
804 struct adv7180_state *state = to_state(sd);
805 int ret;
806
807 /* It's always safe to stop streaming, no need to take the lock */
808 if (!enable) {
809 state->streaming = enable;
810 return 0;
811 }
812
813 /* Must wait until querystd released the lock */
814 ret = mutex_lock_interruptible(&state->mutex);
815 if (ret)
816 return ret;
817 state->streaming = enable;
818 mutex_unlock(&state->mutex);
819 return 0;
820 }
821
adv7180_subscribe_event(struct v4l2_subdev * sd,struct v4l2_fh * fh,struct v4l2_event_subscription * sub)822 static int adv7180_subscribe_event(struct v4l2_subdev *sd,
823 struct v4l2_fh *fh,
824 struct v4l2_event_subscription *sub)
825 {
826 switch (sub->type) {
827 case V4L2_EVENT_SOURCE_CHANGE:
828 return v4l2_src_change_event_subdev_subscribe(sd, fh, sub);
829 case V4L2_EVENT_CTRL:
830 return v4l2_ctrl_subdev_subscribe_event(sd, fh, sub);
831 default:
832 return -EINVAL;
833 }
834 }
835
836 static const struct v4l2_subdev_video_ops adv7180_video_ops = {
837 .s_std = adv7180_s_std,
838 .g_std = adv7180_g_std,
839 .g_frame_interval = adv7180_g_frame_interval,
840 .querystd = adv7180_querystd,
841 .g_input_status = adv7180_g_input_status,
842 .s_routing = adv7180_s_routing,
843 .g_mbus_config = adv7180_g_mbus_config,
844 .g_pixelaspect = adv7180_g_pixelaspect,
845 .g_tvnorms = adv7180_g_tvnorms,
846 .s_stream = adv7180_s_stream,
847 };
848
849 static const struct v4l2_subdev_core_ops adv7180_core_ops = {
850 .s_power = adv7180_s_power,
851 .subscribe_event = adv7180_subscribe_event,
852 .unsubscribe_event = v4l2_event_subdev_unsubscribe,
853 };
854
855 static const struct v4l2_subdev_pad_ops adv7180_pad_ops = {
856 .enum_mbus_code = adv7180_enum_mbus_code,
857 .set_fmt = adv7180_set_pad_format,
858 .get_fmt = adv7180_get_pad_format,
859 };
860
861 static const struct v4l2_subdev_ops adv7180_ops = {
862 .core = &adv7180_core_ops,
863 .video = &adv7180_video_ops,
864 .pad = &adv7180_pad_ops,
865 };
866
adv7180_irq(int irq,void * devid)867 static irqreturn_t adv7180_irq(int irq, void *devid)
868 {
869 struct adv7180_state *state = devid;
870 u8 isr3;
871
872 mutex_lock(&state->mutex);
873 isr3 = adv7180_read(state, ADV7180_REG_ISR3);
874 /* clear */
875 adv7180_write(state, ADV7180_REG_ICR3, isr3);
876
877 if (isr3 & ADV7180_IRQ3_AD_CHANGE) {
878 static const struct v4l2_event src_ch = {
879 .type = V4L2_EVENT_SOURCE_CHANGE,
880 .u.src_change.changes = V4L2_EVENT_SRC_CH_RESOLUTION,
881 };
882
883 v4l2_subdev_notify_event(&state->sd, &src_ch);
884 }
885 mutex_unlock(&state->mutex);
886
887 return IRQ_HANDLED;
888 }
889
adv7180_init(struct adv7180_state * state)890 static int adv7180_init(struct adv7180_state *state)
891 {
892 int ret;
893
894 /* ITU-R BT.656-4 compatible */
895 ret = adv7180_write(state, ADV7180_REG_EXTENDED_OUTPUT_CONTROL,
896 ADV7180_EXTENDED_OUTPUT_CONTROL_NTSCDIS);
897 if (ret < 0)
898 return ret;
899
900 /* Manually set V bit end position in NTSC mode */
901 return adv7180_write(state, ADV7180_REG_NTSC_V_BIT_END,
902 ADV7180_NTSC_V_BIT_END_MANUAL_NVEND);
903 }
904
adv7180_set_std(struct adv7180_state * state,unsigned int std)905 static int adv7180_set_std(struct adv7180_state *state, unsigned int std)
906 {
907 return adv7180_write(state, ADV7180_REG_INPUT_CONTROL,
908 (std << 4) | state->input);
909 }
910
adv7180_select_input(struct adv7180_state * state,unsigned int input)911 static int adv7180_select_input(struct adv7180_state *state, unsigned int input)
912 {
913 int ret;
914
915 ret = adv7180_read(state, ADV7180_REG_INPUT_CONTROL);
916 if (ret < 0)
917 return ret;
918
919 ret &= ~ADV7180_INPUT_CONTROL_INSEL_MASK;
920 ret |= input;
921 return adv7180_write(state, ADV7180_REG_INPUT_CONTROL, ret);
922 }
923
adv7182_init(struct adv7180_state * state)924 static int adv7182_init(struct adv7180_state *state)
925 {
926 if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2)
927 adv7180_write(state, ADV7180_REG_CSI_SLAVE_ADDR,
928 ADV7180_DEFAULT_CSI_I2C_ADDR << 1);
929
930 if (state->chip_info->flags & ADV7180_FLAG_I2P)
931 adv7180_write(state, ADV7180_REG_VPP_SLAVE_ADDR,
932 ADV7180_DEFAULT_VPP_I2C_ADDR << 1);
933
934 if (state->chip_info->flags & ADV7180_FLAG_V2) {
935 /* ADI recommended writes for improved video quality */
936 adv7180_write(state, 0x0080, 0x51);
937 adv7180_write(state, 0x0081, 0x51);
938 adv7180_write(state, 0x0082, 0x68);
939 }
940
941 /* ADI required writes */
942 if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) {
943 adv7180_write(state, ADV7180_REG_OUTPUT_CONTROL, 0x4e);
944 adv7180_write(state, ADV7180_REG_EXTENDED_OUTPUT_CONTROL, 0x57);
945 adv7180_write(state, ADV7180_REG_CTRL_2, 0xc0);
946 } else {
947 if (state->chip_info->flags & ADV7180_FLAG_V2)
948 adv7180_write(state,
949 ADV7180_REG_EXTENDED_OUTPUT_CONTROL,
950 0x17);
951 else
952 adv7180_write(state,
953 ADV7180_REG_EXTENDED_OUTPUT_CONTROL,
954 0x07);
955 adv7180_write(state, ADV7180_REG_OUTPUT_CONTROL, 0x0c);
956 adv7180_write(state, ADV7180_REG_CTRL_2, 0x40);
957 }
958
959 adv7180_write(state, 0x0013, 0x00);
960
961 return 0;
962 }
963
adv7182_set_std(struct adv7180_state * state,unsigned int std)964 static int adv7182_set_std(struct adv7180_state *state, unsigned int std)
965 {
966 return adv7180_write(state, ADV7182_REG_INPUT_VIDSEL, std << 4);
967 }
968
969 enum adv7182_input_type {
970 ADV7182_INPUT_TYPE_CVBS,
971 ADV7182_INPUT_TYPE_DIFF_CVBS,
972 ADV7182_INPUT_TYPE_SVIDEO,
973 ADV7182_INPUT_TYPE_YPBPR,
974 };
975
adv7182_get_input_type(unsigned int input)976 static enum adv7182_input_type adv7182_get_input_type(unsigned int input)
977 {
978 switch (input) {
979 case ADV7182_INPUT_CVBS_AIN1:
980 case ADV7182_INPUT_CVBS_AIN2:
981 case ADV7182_INPUT_CVBS_AIN3:
982 case ADV7182_INPUT_CVBS_AIN4:
983 case ADV7182_INPUT_CVBS_AIN5:
984 case ADV7182_INPUT_CVBS_AIN6:
985 case ADV7182_INPUT_CVBS_AIN7:
986 case ADV7182_INPUT_CVBS_AIN8:
987 return ADV7182_INPUT_TYPE_CVBS;
988 case ADV7182_INPUT_SVIDEO_AIN1_AIN2:
989 case ADV7182_INPUT_SVIDEO_AIN3_AIN4:
990 case ADV7182_INPUT_SVIDEO_AIN5_AIN6:
991 case ADV7182_INPUT_SVIDEO_AIN7_AIN8:
992 return ADV7182_INPUT_TYPE_SVIDEO;
993 case ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3:
994 case ADV7182_INPUT_YPRPB_AIN4_AIN5_AIN6:
995 return ADV7182_INPUT_TYPE_YPBPR;
996 case ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2:
997 case ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4:
998 case ADV7182_INPUT_DIFF_CVBS_AIN5_AIN6:
999 case ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8:
1000 return ADV7182_INPUT_TYPE_DIFF_CVBS;
1001 default: /* Will never happen */
1002 return 0;
1003 }
1004 }
1005
1006 /* ADI recommended writes to registers 0x52, 0x53, 0x54 */
1007 static unsigned int adv7182_lbias_settings[][3] = {
1008 [ADV7182_INPUT_TYPE_CVBS] = { 0xCB, 0x4E, 0x80 },
1009 [ADV7182_INPUT_TYPE_DIFF_CVBS] = { 0xC0, 0x4E, 0x80 },
1010 [ADV7182_INPUT_TYPE_SVIDEO] = { 0x0B, 0xCE, 0x80 },
1011 [ADV7182_INPUT_TYPE_YPBPR] = { 0x0B, 0x4E, 0xC0 },
1012 };
1013
1014 static unsigned int adv7280_lbias_settings[][3] = {
1015 [ADV7182_INPUT_TYPE_CVBS] = { 0xCD, 0x4E, 0x80 },
1016 [ADV7182_INPUT_TYPE_DIFF_CVBS] = { 0xC0, 0x4E, 0x80 },
1017 [ADV7182_INPUT_TYPE_SVIDEO] = { 0x0B, 0xCE, 0x80 },
1018 [ADV7182_INPUT_TYPE_YPBPR] = { 0x0B, 0x4E, 0xC0 },
1019 };
1020
adv7182_select_input(struct adv7180_state * state,unsigned int input)1021 static int adv7182_select_input(struct adv7180_state *state, unsigned int input)
1022 {
1023 enum adv7182_input_type input_type;
1024 unsigned int *lbias;
1025 unsigned int i;
1026 int ret;
1027
1028 ret = adv7180_write(state, ADV7180_REG_INPUT_CONTROL, input);
1029 if (ret)
1030 return ret;
1031
1032 /* Reset clamp circuitry - ADI recommended writes */
1033 adv7180_write(state, ADV7180_REG_RST_CLAMP, 0x00);
1034 adv7180_write(state, ADV7180_REG_RST_CLAMP, 0xff);
1035
1036 input_type = adv7182_get_input_type(input);
1037
1038 switch (input_type) {
1039 case ADV7182_INPUT_TYPE_CVBS:
1040 case ADV7182_INPUT_TYPE_DIFF_CVBS:
1041 /* ADI recommends to use the SH1 filter */
1042 adv7180_write(state, ADV7180_REG_SHAP_FILTER_CTL_1, 0x41);
1043 break;
1044 default:
1045 adv7180_write(state, ADV7180_REG_SHAP_FILTER_CTL_1, 0x01);
1046 break;
1047 }
1048
1049 if (state->chip_info->flags & ADV7180_FLAG_V2)
1050 lbias = adv7280_lbias_settings[input_type];
1051 else
1052 lbias = adv7182_lbias_settings[input_type];
1053
1054 for (i = 0; i < ARRAY_SIZE(adv7182_lbias_settings[0]); i++)
1055 adv7180_write(state, ADV7180_REG_CVBS_TRIM + i, lbias[i]);
1056
1057 if (input_type == ADV7182_INPUT_TYPE_DIFF_CVBS) {
1058 /* ADI required writes to make differential CVBS work */
1059 adv7180_write(state, ADV7180_REG_RES_CIR, 0xa8);
1060 adv7180_write(state, ADV7180_REG_CLAMP_ADJ, 0x90);
1061 adv7180_write(state, ADV7180_REG_DIFF_MODE, 0xb0);
1062 adv7180_write(state, ADV7180_REG_AGC_ADJ1, 0x08);
1063 adv7180_write(state, ADV7180_REG_AGC_ADJ2, 0xa0);
1064 } else {
1065 adv7180_write(state, ADV7180_REG_RES_CIR, 0xf0);
1066 adv7180_write(state, ADV7180_REG_CLAMP_ADJ, 0xd0);
1067 adv7180_write(state, ADV7180_REG_DIFF_MODE, 0x10);
1068 adv7180_write(state, ADV7180_REG_AGC_ADJ1, 0x9c);
1069 adv7180_write(state, ADV7180_REG_AGC_ADJ2, 0x00);
1070 }
1071
1072 return 0;
1073 }
1074
1075 static const struct adv7180_chip_info adv7180_info = {
1076 .flags = ADV7180_FLAG_RESET_POWERED,
1077 /* We cannot discriminate between LQFP and 40-pin LFCSP, so accept
1078 * all inputs and let the card driver take care of validation
1079 */
1080 .valid_input_mask = BIT(ADV7180_INPUT_CVBS_AIN1) |
1081 BIT(ADV7180_INPUT_CVBS_AIN2) |
1082 BIT(ADV7180_INPUT_CVBS_AIN3) |
1083 BIT(ADV7180_INPUT_CVBS_AIN4) |
1084 BIT(ADV7180_INPUT_CVBS_AIN5) |
1085 BIT(ADV7180_INPUT_CVBS_AIN6) |
1086 BIT(ADV7180_INPUT_SVIDEO_AIN1_AIN2) |
1087 BIT(ADV7180_INPUT_SVIDEO_AIN3_AIN4) |
1088 BIT(ADV7180_INPUT_SVIDEO_AIN5_AIN6) |
1089 BIT(ADV7180_INPUT_YPRPB_AIN1_AIN2_AIN3) |
1090 BIT(ADV7180_INPUT_YPRPB_AIN4_AIN5_AIN6),
1091 .init = adv7180_init,
1092 .set_std = adv7180_set_std,
1093 .select_input = adv7180_select_input,
1094 };
1095
1096 static const struct adv7180_chip_info adv7182_info = {
1097 .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) |
1098 BIT(ADV7182_INPUT_CVBS_AIN2) |
1099 BIT(ADV7182_INPUT_CVBS_AIN3) |
1100 BIT(ADV7182_INPUT_CVBS_AIN4) |
1101 BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) |
1102 BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) |
1103 BIT(ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3) |
1104 BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) |
1105 BIT(ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4),
1106 .init = adv7182_init,
1107 .set_std = adv7182_set_std,
1108 .select_input = adv7182_select_input,
1109 };
1110
1111 static const struct adv7180_chip_info adv7280_info = {
1112 .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_I2P,
1113 .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) |
1114 BIT(ADV7182_INPUT_CVBS_AIN2) |
1115 BIT(ADV7182_INPUT_CVBS_AIN3) |
1116 BIT(ADV7182_INPUT_CVBS_AIN4) |
1117 BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) |
1118 BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) |
1119 BIT(ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3),
1120 .init = adv7182_init,
1121 .set_std = adv7182_set_std,
1122 .select_input = adv7182_select_input,
1123 };
1124
1125 static const struct adv7180_chip_info adv7280_m_info = {
1126 .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_MIPI_CSI2 | ADV7180_FLAG_I2P,
1127 .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) |
1128 BIT(ADV7182_INPUT_CVBS_AIN2) |
1129 BIT(ADV7182_INPUT_CVBS_AIN3) |
1130 BIT(ADV7182_INPUT_CVBS_AIN4) |
1131 BIT(ADV7182_INPUT_CVBS_AIN5) |
1132 BIT(ADV7182_INPUT_CVBS_AIN6) |
1133 BIT(ADV7182_INPUT_CVBS_AIN7) |
1134 BIT(ADV7182_INPUT_CVBS_AIN8) |
1135 BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) |
1136 BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) |
1137 BIT(ADV7182_INPUT_SVIDEO_AIN5_AIN6) |
1138 BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) |
1139 BIT(ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3) |
1140 BIT(ADV7182_INPUT_YPRPB_AIN4_AIN5_AIN6),
1141 .init = adv7182_init,
1142 .set_std = adv7182_set_std,
1143 .select_input = adv7182_select_input,
1144 };
1145
1146 static const struct adv7180_chip_info adv7281_info = {
1147 .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_MIPI_CSI2,
1148 .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) |
1149 BIT(ADV7182_INPUT_CVBS_AIN2) |
1150 BIT(ADV7182_INPUT_CVBS_AIN7) |
1151 BIT(ADV7182_INPUT_CVBS_AIN8) |
1152 BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) |
1153 BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) |
1154 BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) |
1155 BIT(ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8),
1156 .init = adv7182_init,
1157 .set_std = adv7182_set_std,
1158 .select_input = adv7182_select_input,
1159 };
1160
1161 static const struct adv7180_chip_info adv7281_m_info = {
1162 .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_MIPI_CSI2,
1163 .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) |
1164 BIT(ADV7182_INPUT_CVBS_AIN2) |
1165 BIT(ADV7182_INPUT_CVBS_AIN3) |
1166 BIT(ADV7182_INPUT_CVBS_AIN4) |
1167 BIT(ADV7182_INPUT_CVBS_AIN7) |
1168 BIT(ADV7182_INPUT_CVBS_AIN8) |
1169 BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) |
1170 BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) |
1171 BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) |
1172 BIT(ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3) |
1173 BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) |
1174 BIT(ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4) |
1175 BIT(ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8),
1176 .init = adv7182_init,
1177 .set_std = adv7182_set_std,
1178 .select_input = adv7182_select_input,
1179 };
1180
1181 static const struct adv7180_chip_info adv7281_ma_info = {
1182 .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_MIPI_CSI2,
1183 .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) |
1184 BIT(ADV7182_INPUT_CVBS_AIN2) |
1185 BIT(ADV7182_INPUT_CVBS_AIN3) |
1186 BIT(ADV7182_INPUT_CVBS_AIN4) |
1187 BIT(ADV7182_INPUT_CVBS_AIN5) |
1188 BIT(ADV7182_INPUT_CVBS_AIN6) |
1189 BIT(ADV7182_INPUT_CVBS_AIN7) |
1190 BIT(ADV7182_INPUT_CVBS_AIN8) |
1191 BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) |
1192 BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) |
1193 BIT(ADV7182_INPUT_SVIDEO_AIN5_AIN6) |
1194 BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) |
1195 BIT(ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3) |
1196 BIT(ADV7182_INPUT_YPRPB_AIN4_AIN5_AIN6) |
1197 BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) |
1198 BIT(ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4) |
1199 BIT(ADV7182_INPUT_DIFF_CVBS_AIN5_AIN6) |
1200 BIT(ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8),
1201 .init = adv7182_init,
1202 .set_std = adv7182_set_std,
1203 .select_input = adv7182_select_input,
1204 };
1205
1206 static const struct adv7180_chip_info adv7282_info = {
1207 .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_I2P,
1208 .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) |
1209 BIT(ADV7182_INPUT_CVBS_AIN2) |
1210 BIT(ADV7182_INPUT_CVBS_AIN7) |
1211 BIT(ADV7182_INPUT_CVBS_AIN8) |
1212 BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) |
1213 BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) |
1214 BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) |
1215 BIT(ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8),
1216 .init = adv7182_init,
1217 .set_std = adv7182_set_std,
1218 .select_input = adv7182_select_input,
1219 };
1220
1221 static const struct adv7180_chip_info adv7282_m_info = {
1222 .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_MIPI_CSI2 | ADV7180_FLAG_I2P,
1223 .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) |
1224 BIT(ADV7182_INPUT_CVBS_AIN2) |
1225 BIT(ADV7182_INPUT_CVBS_AIN3) |
1226 BIT(ADV7182_INPUT_CVBS_AIN4) |
1227 BIT(ADV7182_INPUT_CVBS_AIN7) |
1228 BIT(ADV7182_INPUT_CVBS_AIN8) |
1229 BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) |
1230 BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) |
1231 BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) |
1232 BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) |
1233 BIT(ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4) |
1234 BIT(ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8),
1235 .init = adv7182_init,
1236 .set_std = adv7182_set_std,
1237 .select_input = adv7182_select_input,
1238 };
1239
init_device(struct adv7180_state * state)1240 static int init_device(struct adv7180_state *state)
1241 {
1242 int ret;
1243
1244 mutex_lock(&state->mutex);
1245
1246 adv7180_set_power_pin(state, true);
1247
1248 adv7180_write(state, ADV7180_REG_PWR_MAN, ADV7180_PWR_MAN_RES);
1249 usleep_range(5000, 10000);
1250
1251 ret = state->chip_info->init(state);
1252 if (ret)
1253 goto out_unlock;
1254
1255 ret = adv7180_program_std(state);
1256 if (ret)
1257 goto out_unlock;
1258
1259 adv7180_set_field_mode(state);
1260
1261 /* register for interrupts */
1262 if (state->irq > 0) {
1263 /* config the Interrupt pin to be active low */
1264 ret = adv7180_write(state, ADV7180_REG_ICONF1,
1265 ADV7180_ICONF1_ACTIVE_LOW |
1266 ADV7180_ICONF1_PSYNC_ONLY);
1267 if (ret < 0)
1268 goto out_unlock;
1269
1270 ret = adv7180_write(state, ADV7180_REG_IMR1, 0);
1271 if (ret < 0)
1272 goto out_unlock;
1273
1274 ret = adv7180_write(state, ADV7180_REG_IMR2, 0);
1275 if (ret < 0)
1276 goto out_unlock;
1277
1278 /* enable AD change interrupts interrupts */
1279 ret = adv7180_write(state, ADV7180_REG_IMR3,
1280 ADV7180_IRQ3_AD_CHANGE);
1281 if (ret < 0)
1282 goto out_unlock;
1283
1284 ret = adv7180_write(state, ADV7180_REG_IMR4, 0);
1285 if (ret < 0)
1286 goto out_unlock;
1287 }
1288
1289 out_unlock:
1290 mutex_unlock(&state->mutex);
1291
1292 return ret;
1293 }
1294
adv7180_probe(struct i2c_client * client,const struct i2c_device_id * id)1295 static int adv7180_probe(struct i2c_client *client,
1296 const struct i2c_device_id *id)
1297 {
1298 struct adv7180_state *state;
1299 struct v4l2_subdev *sd;
1300 int ret;
1301
1302 /* Check if the adapter supports the needed features */
1303 if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
1304 return -EIO;
1305
1306 v4l_info(client, "chip found @ 0x%02x (%s)\n",
1307 client->addr, client->adapter->name);
1308
1309 state = devm_kzalloc(&client->dev, sizeof(*state), GFP_KERNEL);
1310 if (state == NULL)
1311 return -ENOMEM;
1312
1313 state->client = client;
1314 state->field = V4L2_FIELD_ALTERNATE;
1315 state->chip_info = (struct adv7180_chip_info *)id->driver_data;
1316
1317 state->pwdn_gpio = devm_gpiod_get_optional(&client->dev, "powerdown",
1318 GPIOD_OUT_HIGH);
1319 if (IS_ERR(state->pwdn_gpio)) {
1320 ret = PTR_ERR(state->pwdn_gpio);
1321 v4l_err(client, "request for power pin failed: %d\n", ret);
1322 return ret;
1323 }
1324
1325 if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) {
1326 state->csi_client = i2c_new_dummy(client->adapter,
1327 ADV7180_DEFAULT_CSI_I2C_ADDR);
1328 if (!state->csi_client)
1329 return -ENOMEM;
1330 }
1331
1332 if (state->chip_info->flags & ADV7180_FLAG_I2P) {
1333 state->vpp_client = i2c_new_dummy(client->adapter,
1334 ADV7180_DEFAULT_VPP_I2C_ADDR);
1335 if (!state->vpp_client) {
1336 ret = -ENOMEM;
1337 goto err_unregister_csi_client;
1338 }
1339 }
1340
1341 state->irq = client->irq;
1342 mutex_init(&state->mutex);
1343 state->curr_norm = V4L2_STD_NTSC;
1344 if (state->chip_info->flags & ADV7180_FLAG_RESET_POWERED)
1345 state->powered = true;
1346 else
1347 state->powered = false;
1348 state->input = 0;
1349 sd = &state->sd;
1350 v4l2_i2c_subdev_init(sd, client, &adv7180_ops);
1351 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS;
1352
1353 ret = adv7180_init_controls(state);
1354 if (ret)
1355 goto err_unregister_vpp_client;
1356
1357 state->pad.flags = MEDIA_PAD_FL_SOURCE;
1358 sd->entity.function = MEDIA_ENT_F_ATV_DECODER;
1359 ret = media_entity_pads_init(&sd->entity, 1, &state->pad);
1360 if (ret)
1361 goto err_free_ctrl;
1362
1363 ret = init_device(state);
1364 if (ret)
1365 goto err_media_entity_cleanup;
1366
1367 if (state->irq) {
1368 ret = request_threaded_irq(client->irq, NULL, adv7180_irq,
1369 IRQF_ONESHOT | IRQF_TRIGGER_FALLING,
1370 KBUILD_MODNAME, state);
1371 if (ret)
1372 goto err_media_entity_cleanup;
1373 }
1374
1375 ret = v4l2_async_register_subdev(sd);
1376 if (ret)
1377 goto err_free_irq;
1378
1379 return 0;
1380
1381 err_free_irq:
1382 if (state->irq > 0)
1383 free_irq(client->irq, state);
1384 err_media_entity_cleanup:
1385 media_entity_cleanup(&sd->entity);
1386 err_free_ctrl:
1387 adv7180_exit_controls(state);
1388 err_unregister_vpp_client:
1389 i2c_unregister_device(state->vpp_client);
1390 err_unregister_csi_client:
1391 i2c_unregister_device(state->csi_client);
1392 mutex_destroy(&state->mutex);
1393 return ret;
1394 }
1395
adv7180_remove(struct i2c_client * client)1396 static int adv7180_remove(struct i2c_client *client)
1397 {
1398 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1399 struct adv7180_state *state = to_state(sd);
1400
1401 v4l2_async_unregister_subdev(sd);
1402
1403 if (state->irq > 0)
1404 free_irq(client->irq, state);
1405
1406 media_entity_cleanup(&sd->entity);
1407 adv7180_exit_controls(state);
1408
1409 i2c_unregister_device(state->vpp_client);
1410 i2c_unregister_device(state->csi_client);
1411
1412 adv7180_set_power_pin(state, false);
1413
1414 mutex_destroy(&state->mutex);
1415
1416 return 0;
1417 }
1418
1419 static const struct i2c_device_id adv7180_id[] = {
1420 { "adv7180", (kernel_ulong_t)&adv7180_info },
1421 { "adv7180cp", (kernel_ulong_t)&adv7180_info },
1422 { "adv7180st", (kernel_ulong_t)&adv7180_info },
1423 { "adv7182", (kernel_ulong_t)&adv7182_info },
1424 { "adv7280", (kernel_ulong_t)&adv7280_info },
1425 { "adv7280-m", (kernel_ulong_t)&adv7280_m_info },
1426 { "adv7281", (kernel_ulong_t)&adv7281_info },
1427 { "adv7281-m", (kernel_ulong_t)&adv7281_m_info },
1428 { "adv7281-ma", (kernel_ulong_t)&adv7281_ma_info },
1429 { "adv7282", (kernel_ulong_t)&adv7282_info },
1430 { "adv7282-m", (kernel_ulong_t)&adv7282_m_info },
1431 {},
1432 };
1433 MODULE_DEVICE_TABLE(i2c, adv7180_id);
1434
1435 #ifdef CONFIG_PM_SLEEP
adv7180_suspend(struct device * dev)1436 static int adv7180_suspend(struct device *dev)
1437 {
1438 struct i2c_client *client = to_i2c_client(dev);
1439 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1440 struct adv7180_state *state = to_state(sd);
1441
1442 return adv7180_set_power(state, false);
1443 }
1444
adv7180_resume(struct device * dev)1445 static int adv7180_resume(struct device *dev)
1446 {
1447 struct i2c_client *client = to_i2c_client(dev);
1448 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1449 struct adv7180_state *state = to_state(sd);
1450 int ret;
1451
1452 ret = init_device(state);
1453 if (ret < 0)
1454 return ret;
1455
1456 ret = adv7180_set_power(state, state->powered);
1457 if (ret)
1458 return ret;
1459
1460 return 0;
1461 }
1462
1463 static SIMPLE_DEV_PM_OPS(adv7180_pm_ops, adv7180_suspend, adv7180_resume);
1464 #define ADV7180_PM_OPS (&adv7180_pm_ops)
1465
1466 #else
1467 #define ADV7180_PM_OPS NULL
1468 #endif
1469
1470 #ifdef CONFIG_OF
1471 static const struct of_device_id adv7180_of_id[] = {
1472 { .compatible = "adi,adv7180", },
1473 { .compatible = "adi,adv7180cp", },
1474 { .compatible = "adi,adv7180st", },
1475 { .compatible = "adi,adv7182", },
1476 { .compatible = "adi,adv7280", },
1477 { .compatible = "adi,adv7280-m", },
1478 { .compatible = "adi,adv7281", },
1479 { .compatible = "adi,adv7281-m", },
1480 { .compatible = "adi,adv7281-ma", },
1481 { .compatible = "adi,adv7282", },
1482 { .compatible = "adi,adv7282-m", },
1483 { },
1484 };
1485
1486 MODULE_DEVICE_TABLE(of, adv7180_of_id);
1487 #endif
1488
1489 static struct i2c_driver adv7180_driver = {
1490 .driver = {
1491 .name = KBUILD_MODNAME,
1492 .pm = ADV7180_PM_OPS,
1493 .of_match_table = of_match_ptr(adv7180_of_id),
1494 },
1495 .probe = adv7180_probe,
1496 .remove = adv7180_remove,
1497 .id_table = adv7180_id,
1498 };
1499
1500 module_i2c_driver(adv7180_driver);
1501
1502 MODULE_DESCRIPTION("Analog Devices ADV7180 video decoder driver");
1503 MODULE_AUTHOR("Mocean Laboratories");
1504 MODULE_LICENSE("GPL v2");
1505
