1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * IOMMU API for QCOM secure IOMMUs. Somewhat based on arm-smmu.c
4 *
5 * Copyright (C) 2013 ARM Limited
6 * Copyright (C) 2017 Red Hat
7 */
8
9 #include <linux/atomic.h>
10 #include <linux/bitfield.h>
11 #include <linux/clk.h>
12 #include <linux/delay.h>
13 #include <linux/dma-mapping.h>
14 #include <linux/err.h>
15 #include <linux/interrupt.h>
16 #include <linux/io.h>
17 #include <linux/io-64-nonatomic-hi-lo.h>
18 #include <linux/io-pgtable.h>
19 #include <linux/iommu.h>
20 #include <linux/iopoll.h>
21 #include <linux/kconfig.h>
22 #include <linux/init.h>
23 #include <linux/mutex.h>
24 #include <linux/of.h>
25 #include <linux/of_platform.h>
26 #include <linux/platform_device.h>
27 #include <linux/pm.h>
28 #include <linux/pm_runtime.h>
29 #include <linux/firmware/qcom/qcom_scm.h>
30 #include <linux/slab.h>
31 #include <linux/spinlock.h>
32
33 #include "arm-smmu.h"
34
35 #define SMMU_INTR_SEL_NS 0x2000
36
37 enum qcom_iommu_clk {
38 CLK_IFACE,
39 CLK_BUS,
40 CLK_TBU,
41 CLK_NUM,
42 };
43
44 struct qcom_iommu_ctx;
45
46 struct qcom_iommu_dev {
47 /* IOMMU core code handle */
48 struct iommu_device iommu;
49 struct device *dev;
50 struct clk_bulk_data clks[CLK_NUM];
51 void __iomem *local_base;
52 u32 sec_id;
53 u8 max_asid;
54 struct qcom_iommu_ctx *ctxs[]; /* indexed by asid */
55 };
56
57 struct qcom_iommu_ctx {
58 struct device *dev;
59 void __iomem *base;
60 bool secure_init;
61 bool secured_ctx;
62 u8 asid; /* asid and ctx bank # are 1:1 */
63 struct iommu_domain *domain;
64 };
65
66 struct qcom_iommu_domain {
67 struct io_pgtable_ops *pgtbl_ops;
68 spinlock_t pgtbl_lock;
69 struct mutex init_mutex; /* Protects iommu pointer */
70 struct iommu_domain domain;
71 struct qcom_iommu_dev *iommu;
72 struct iommu_fwspec *fwspec;
73 };
74
to_qcom_iommu_domain(struct iommu_domain * dom)75 static struct qcom_iommu_domain *to_qcom_iommu_domain(struct iommu_domain *dom)
76 {
77 return container_of(dom, struct qcom_iommu_domain, domain);
78 }
79
80 static const struct iommu_ops qcom_iommu_ops;
81
to_iommu(struct device * dev)82 static struct qcom_iommu_dev * to_iommu(struct device *dev)
83 {
84 struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
85
86 if (!fwspec || fwspec->ops != &qcom_iommu_ops)
87 return NULL;
88
89 return dev_iommu_priv_get(dev);
90 }
91
to_ctx(struct qcom_iommu_domain * d,unsigned asid)92 static struct qcom_iommu_ctx * to_ctx(struct qcom_iommu_domain *d, unsigned asid)
93 {
94 struct qcom_iommu_dev *qcom_iommu = d->iommu;
95 if (!qcom_iommu)
96 return NULL;
97 return qcom_iommu->ctxs[asid];
98 }
99
100 static inline void
iommu_writel(struct qcom_iommu_ctx * ctx,unsigned reg,u32 val)101 iommu_writel(struct qcom_iommu_ctx *ctx, unsigned reg, u32 val)
102 {
103 writel_relaxed(val, ctx->base + reg);
104 }
105
106 static inline void
iommu_writeq(struct qcom_iommu_ctx * ctx,unsigned reg,u64 val)107 iommu_writeq(struct qcom_iommu_ctx *ctx, unsigned reg, u64 val)
108 {
109 writeq_relaxed(val, ctx->base + reg);
110 }
111
112 static inline u32
iommu_readl(struct qcom_iommu_ctx * ctx,unsigned reg)113 iommu_readl(struct qcom_iommu_ctx *ctx, unsigned reg)
114 {
115 return readl_relaxed(ctx->base + reg);
116 }
117
118 static inline u64
iommu_readq(struct qcom_iommu_ctx * ctx,unsigned reg)119 iommu_readq(struct qcom_iommu_ctx *ctx, unsigned reg)
120 {
121 return readq_relaxed(ctx->base + reg);
122 }
123
qcom_iommu_tlb_sync(void * cookie)124 static void qcom_iommu_tlb_sync(void *cookie)
125 {
126 struct qcom_iommu_domain *qcom_domain = cookie;
127 struct iommu_fwspec *fwspec = qcom_domain->fwspec;
128 unsigned i;
129
130 for (i = 0; i < fwspec->num_ids; i++) {
131 struct qcom_iommu_ctx *ctx = to_ctx(qcom_domain, fwspec->ids[i]);
132 unsigned int val, ret;
133
134 iommu_writel(ctx, ARM_SMMU_CB_TLBSYNC, 0);
135
136 ret = readl_poll_timeout(ctx->base + ARM_SMMU_CB_TLBSTATUS, val,
137 (val & 0x1) == 0, 0, 5000000);
138 if (ret)
139 dev_err(ctx->dev, "timeout waiting for TLB SYNC\n");
140 }
141 }
142
qcom_iommu_tlb_inv_context(void * cookie)143 static void qcom_iommu_tlb_inv_context(void *cookie)
144 {
145 struct qcom_iommu_domain *qcom_domain = cookie;
146 struct iommu_fwspec *fwspec = qcom_domain->fwspec;
147 unsigned i;
148
149 for (i = 0; i < fwspec->num_ids; i++) {
150 struct qcom_iommu_ctx *ctx = to_ctx(qcom_domain, fwspec->ids[i]);
151 iommu_writel(ctx, ARM_SMMU_CB_S1_TLBIASID, ctx->asid);
152 }
153
154 qcom_iommu_tlb_sync(cookie);
155 }
156
qcom_iommu_tlb_inv_range_nosync(unsigned long iova,size_t size,size_t granule,bool leaf,void * cookie)157 static void qcom_iommu_tlb_inv_range_nosync(unsigned long iova, size_t size,
158 size_t granule, bool leaf, void *cookie)
159 {
160 struct qcom_iommu_domain *qcom_domain = cookie;
161 struct iommu_fwspec *fwspec = qcom_domain->fwspec;
162 unsigned i, reg;
163
164 reg = leaf ? ARM_SMMU_CB_S1_TLBIVAL : ARM_SMMU_CB_S1_TLBIVA;
165
166 for (i = 0; i < fwspec->num_ids; i++) {
167 struct qcom_iommu_ctx *ctx = to_ctx(qcom_domain, fwspec->ids[i]);
168 size_t s = size;
169
170 iova = (iova >> 12) << 12;
171 iova |= ctx->asid;
172 do {
173 iommu_writel(ctx, reg, iova);
174 iova += granule;
175 } while (s -= granule);
176 }
177 }
178
qcom_iommu_tlb_flush_walk(unsigned long iova,size_t size,size_t granule,void * cookie)179 static void qcom_iommu_tlb_flush_walk(unsigned long iova, size_t size,
180 size_t granule, void *cookie)
181 {
182 qcom_iommu_tlb_inv_range_nosync(iova, size, granule, false, cookie);
183 qcom_iommu_tlb_sync(cookie);
184 }
185
qcom_iommu_tlb_add_page(struct iommu_iotlb_gather * gather,unsigned long iova,size_t granule,void * cookie)186 static void qcom_iommu_tlb_add_page(struct iommu_iotlb_gather *gather,
187 unsigned long iova, size_t granule,
188 void *cookie)
189 {
190 qcom_iommu_tlb_inv_range_nosync(iova, granule, granule, true, cookie);
191 }
192
193 static const struct iommu_flush_ops qcom_flush_ops = {
194 .tlb_flush_all = qcom_iommu_tlb_inv_context,
195 .tlb_flush_walk = qcom_iommu_tlb_flush_walk,
196 .tlb_add_page = qcom_iommu_tlb_add_page,
197 };
198
qcom_iommu_fault(int irq,void * dev)199 static irqreturn_t qcom_iommu_fault(int irq, void *dev)
200 {
201 struct qcom_iommu_ctx *ctx = dev;
202 u32 fsr, fsynr;
203 u64 iova;
204
205 fsr = iommu_readl(ctx, ARM_SMMU_CB_FSR);
206
207 if (!(fsr & ARM_SMMU_FSR_FAULT))
208 return IRQ_NONE;
209
210 fsynr = iommu_readl(ctx, ARM_SMMU_CB_FSYNR0);
211 iova = iommu_readq(ctx, ARM_SMMU_CB_FAR);
212
213 if (!report_iommu_fault(ctx->domain, ctx->dev, iova, 0)) {
214 dev_err_ratelimited(ctx->dev,
215 "Unhandled context fault: fsr=0x%x, "
216 "iova=0x%016llx, fsynr=0x%x, cb=%d\n",
217 fsr, iova, fsynr, ctx->asid);
218 }
219
220 iommu_writel(ctx, ARM_SMMU_CB_FSR, fsr);
221 iommu_writel(ctx, ARM_SMMU_CB_RESUME, ARM_SMMU_RESUME_TERMINATE);
222
223 return IRQ_HANDLED;
224 }
225
qcom_iommu_init_domain(struct iommu_domain * domain,struct qcom_iommu_dev * qcom_iommu,struct device * dev)226 static int qcom_iommu_init_domain(struct iommu_domain *domain,
227 struct qcom_iommu_dev *qcom_iommu,
228 struct device *dev)
229 {
230 struct qcom_iommu_domain *qcom_domain = to_qcom_iommu_domain(domain);
231 struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
232 struct io_pgtable_ops *pgtbl_ops;
233 struct io_pgtable_cfg pgtbl_cfg;
234 int i, ret = 0;
235 u32 reg;
236
237 mutex_lock(&qcom_domain->init_mutex);
238 if (qcom_domain->iommu)
239 goto out_unlock;
240
241 pgtbl_cfg = (struct io_pgtable_cfg) {
242 .pgsize_bitmap = qcom_iommu_ops.pgsize_bitmap,
243 .ias = 32,
244 .oas = 40,
245 .tlb = &qcom_flush_ops,
246 .iommu_dev = qcom_iommu->dev,
247 };
248
249 qcom_domain->iommu = qcom_iommu;
250 qcom_domain->fwspec = fwspec;
251
252 pgtbl_ops = alloc_io_pgtable_ops(ARM_32_LPAE_S1, &pgtbl_cfg, qcom_domain);
253 if (!pgtbl_ops) {
254 dev_err(qcom_iommu->dev, "failed to allocate pagetable ops\n");
255 ret = -ENOMEM;
256 goto out_clear_iommu;
257 }
258
259 /* Update the domain's page sizes to reflect the page table format */
260 domain->pgsize_bitmap = pgtbl_cfg.pgsize_bitmap;
261 domain->geometry.aperture_end = (1ULL << pgtbl_cfg.ias) - 1;
262 domain->geometry.force_aperture = true;
263
264 for (i = 0; i < fwspec->num_ids; i++) {
265 struct qcom_iommu_ctx *ctx = to_ctx(qcom_domain, fwspec->ids[i]);
266
267 if (!ctx->secure_init) {
268 ret = qcom_scm_restore_sec_cfg(qcom_iommu->sec_id, ctx->asid);
269 if (ret) {
270 dev_err(qcom_iommu->dev, "secure init failed: %d\n", ret);
271 goto out_clear_iommu;
272 }
273 ctx->secure_init = true;
274 }
275
276 /* Secured QSMMU-500/QSMMU-v2 contexts cannot be programmed */
277 if (ctx->secured_ctx) {
278 ctx->domain = domain;
279 continue;
280 }
281
282 /* Disable context bank before programming */
283 iommu_writel(ctx, ARM_SMMU_CB_SCTLR, 0);
284
285 /* Clear context bank fault address fault status registers */
286 iommu_writel(ctx, ARM_SMMU_CB_FAR, 0);
287 iommu_writel(ctx, ARM_SMMU_CB_FSR, ARM_SMMU_FSR_FAULT);
288
289 /* TTBRs */
290 iommu_writeq(ctx, ARM_SMMU_CB_TTBR0,
291 pgtbl_cfg.arm_lpae_s1_cfg.ttbr |
292 FIELD_PREP(ARM_SMMU_TTBRn_ASID, ctx->asid));
293 iommu_writeq(ctx, ARM_SMMU_CB_TTBR1, 0);
294
295 /* TCR */
296 iommu_writel(ctx, ARM_SMMU_CB_TCR2,
297 arm_smmu_lpae_tcr2(&pgtbl_cfg));
298 iommu_writel(ctx, ARM_SMMU_CB_TCR,
299 arm_smmu_lpae_tcr(&pgtbl_cfg) | ARM_SMMU_TCR_EAE);
300
301 /* MAIRs (stage-1 only) */
302 iommu_writel(ctx, ARM_SMMU_CB_S1_MAIR0,
303 pgtbl_cfg.arm_lpae_s1_cfg.mair);
304 iommu_writel(ctx, ARM_SMMU_CB_S1_MAIR1,
305 pgtbl_cfg.arm_lpae_s1_cfg.mair >> 32);
306
307 /* SCTLR */
308 reg = ARM_SMMU_SCTLR_CFIE | ARM_SMMU_SCTLR_CFRE |
309 ARM_SMMU_SCTLR_AFE | ARM_SMMU_SCTLR_TRE |
310 ARM_SMMU_SCTLR_M | ARM_SMMU_SCTLR_S1_ASIDPNE |
311 ARM_SMMU_SCTLR_CFCFG;
312
313 if (IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
314 reg |= ARM_SMMU_SCTLR_E;
315
316 iommu_writel(ctx, ARM_SMMU_CB_SCTLR, reg);
317
318 ctx->domain = domain;
319 }
320
321 mutex_unlock(&qcom_domain->init_mutex);
322
323 /* Publish page table ops for map/unmap */
324 qcom_domain->pgtbl_ops = pgtbl_ops;
325
326 return 0;
327
328 out_clear_iommu:
329 qcom_domain->iommu = NULL;
330 out_unlock:
331 mutex_unlock(&qcom_domain->init_mutex);
332 return ret;
333 }
334
qcom_iommu_domain_alloc(unsigned type)335 static struct iommu_domain *qcom_iommu_domain_alloc(unsigned type)
336 {
337 struct qcom_iommu_domain *qcom_domain;
338
339 if (type != IOMMU_DOMAIN_UNMANAGED && type != IOMMU_DOMAIN_DMA)
340 return NULL;
341 /*
342 * Allocate the domain and initialise some of its data structures.
343 * We can't really do anything meaningful until we've added a
344 * master.
345 */
346 qcom_domain = kzalloc(sizeof(*qcom_domain), GFP_KERNEL);
347 if (!qcom_domain)
348 return NULL;
349
350 mutex_init(&qcom_domain->init_mutex);
351 spin_lock_init(&qcom_domain->pgtbl_lock);
352
353 return &qcom_domain->domain;
354 }
355
qcom_iommu_domain_free(struct iommu_domain * domain)356 static void qcom_iommu_domain_free(struct iommu_domain *domain)
357 {
358 struct qcom_iommu_domain *qcom_domain = to_qcom_iommu_domain(domain);
359
360 if (qcom_domain->iommu) {
361 /*
362 * NOTE: unmap can be called after client device is powered
363 * off, for example, with GPUs or anything involving dma-buf.
364 * So we cannot rely on the device_link. Make sure the IOMMU
365 * is on to avoid unclocked accesses in the TLB inv path:
366 */
367 pm_runtime_get_sync(qcom_domain->iommu->dev);
368 free_io_pgtable_ops(qcom_domain->pgtbl_ops);
369 pm_runtime_put_sync(qcom_domain->iommu->dev);
370 }
371
372 kfree(qcom_domain);
373 }
374
qcom_iommu_attach_dev(struct iommu_domain * domain,struct device * dev)375 static int qcom_iommu_attach_dev(struct iommu_domain *domain, struct device *dev)
376 {
377 struct qcom_iommu_dev *qcom_iommu = to_iommu(dev);
378 struct qcom_iommu_domain *qcom_domain = to_qcom_iommu_domain(domain);
379 int ret;
380
381 if (!qcom_iommu) {
382 dev_err(dev, "cannot attach to IOMMU, is it on the same bus?\n");
383 return -ENXIO;
384 }
385
386 /* Ensure that the domain is finalized */
387 pm_runtime_get_sync(qcom_iommu->dev);
388 ret = qcom_iommu_init_domain(domain, qcom_iommu, dev);
389 pm_runtime_put_sync(qcom_iommu->dev);
390 if (ret < 0)
391 return ret;
392
393 /*
394 * Sanity check the domain. We don't support domains across
395 * different IOMMUs.
396 */
397 if (qcom_domain->iommu != qcom_iommu)
398 return -EINVAL;
399
400 return 0;
401 }
402
qcom_iommu_map(struct iommu_domain * domain,unsigned long iova,phys_addr_t paddr,size_t pgsize,size_t pgcount,int prot,gfp_t gfp,size_t * mapped)403 static int qcom_iommu_map(struct iommu_domain *domain, unsigned long iova,
404 phys_addr_t paddr, size_t pgsize, size_t pgcount,
405 int prot, gfp_t gfp, size_t *mapped)
406 {
407 int ret;
408 unsigned long flags;
409 struct qcom_iommu_domain *qcom_domain = to_qcom_iommu_domain(domain);
410 struct io_pgtable_ops *ops = qcom_domain->pgtbl_ops;
411
412 if (!ops)
413 return -ENODEV;
414
415 spin_lock_irqsave(&qcom_domain->pgtbl_lock, flags);
416 ret = ops->map_pages(ops, iova, paddr, pgsize, pgcount, prot, GFP_ATOMIC, mapped);
417 spin_unlock_irqrestore(&qcom_domain->pgtbl_lock, flags);
418 return ret;
419 }
420
qcom_iommu_unmap(struct iommu_domain * domain,unsigned long iova,size_t pgsize,size_t pgcount,struct iommu_iotlb_gather * gather)421 static size_t qcom_iommu_unmap(struct iommu_domain *domain, unsigned long iova,
422 size_t pgsize, size_t pgcount,
423 struct iommu_iotlb_gather *gather)
424 {
425 size_t ret;
426 unsigned long flags;
427 struct qcom_iommu_domain *qcom_domain = to_qcom_iommu_domain(domain);
428 struct io_pgtable_ops *ops = qcom_domain->pgtbl_ops;
429
430 if (!ops)
431 return 0;
432
433 /* NOTE: unmap can be called after client device is powered off,
434 * for example, with GPUs or anything involving dma-buf. So we
435 * cannot rely on the device_link. Make sure the IOMMU is on to
436 * avoid unclocked accesses in the TLB inv path:
437 */
438 pm_runtime_get_sync(qcom_domain->iommu->dev);
439 spin_lock_irqsave(&qcom_domain->pgtbl_lock, flags);
440 ret = ops->unmap_pages(ops, iova, pgsize, pgcount, gather);
441 spin_unlock_irqrestore(&qcom_domain->pgtbl_lock, flags);
442 pm_runtime_put_sync(qcom_domain->iommu->dev);
443
444 return ret;
445 }
446
qcom_iommu_flush_iotlb_all(struct iommu_domain * domain)447 static void qcom_iommu_flush_iotlb_all(struct iommu_domain *domain)
448 {
449 struct qcom_iommu_domain *qcom_domain = to_qcom_iommu_domain(domain);
450 struct io_pgtable *pgtable = container_of(qcom_domain->pgtbl_ops,
451 struct io_pgtable, ops);
452 if (!qcom_domain->pgtbl_ops)
453 return;
454
455 pm_runtime_get_sync(qcom_domain->iommu->dev);
456 qcom_iommu_tlb_sync(pgtable->cookie);
457 pm_runtime_put_sync(qcom_domain->iommu->dev);
458 }
459
qcom_iommu_iotlb_sync(struct iommu_domain * domain,struct iommu_iotlb_gather * gather)460 static void qcom_iommu_iotlb_sync(struct iommu_domain *domain,
461 struct iommu_iotlb_gather *gather)
462 {
463 qcom_iommu_flush_iotlb_all(domain);
464 }
465
qcom_iommu_iova_to_phys(struct iommu_domain * domain,dma_addr_t iova)466 static phys_addr_t qcom_iommu_iova_to_phys(struct iommu_domain *domain,
467 dma_addr_t iova)
468 {
469 phys_addr_t ret;
470 unsigned long flags;
471 struct qcom_iommu_domain *qcom_domain = to_qcom_iommu_domain(domain);
472 struct io_pgtable_ops *ops = qcom_domain->pgtbl_ops;
473
474 if (!ops)
475 return 0;
476
477 spin_lock_irqsave(&qcom_domain->pgtbl_lock, flags);
478 ret = ops->iova_to_phys(ops, iova);
479 spin_unlock_irqrestore(&qcom_domain->pgtbl_lock, flags);
480
481 return ret;
482 }
483
qcom_iommu_capable(struct device * dev,enum iommu_cap cap)484 static bool qcom_iommu_capable(struct device *dev, enum iommu_cap cap)
485 {
486 switch (cap) {
487 case IOMMU_CAP_CACHE_COHERENCY:
488 /*
489 * Return true here as the SMMU can always send out coherent
490 * requests.
491 */
492 return true;
493 case IOMMU_CAP_NOEXEC:
494 return true;
495 default:
496 return false;
497 }
498 }
499
qcom_iommu_probe_device(struct device * dev)500 static struct iommu_device *qcom_iommu_probe_device(struct device *dev)
501 {
502 struct qcom_iommu_dev *qcom_iommu = to_iommu(dev);
503 struct device_link *link;
504
505 if (!qcom_iommu)
506 return ERR_PTR(-ENODEV);
507
508 /*
509 * Establish the link between iommu and master, so that the
510 * iommu gets runtime enabled/disabled as per the master's
511 * needs.
512 */
513 link = device_link_add(dev, qcom_iommu->dev, DL_FLAG_PM_RUNTIME);
514 if (!link) {
515 dev_err(qcom_iommu->dev, "Unable to create device link between %s and %s\n",
516 dev_name(qcom_iommu->dev), dev_name(dev));
517 return ERR_PTR(-ENODEV);
518 }
519
520 return &qcom_iommu->iommu;
521 }
522
qcom_iommu_of_xlate(struct device * dev,struct of_phandle_args * args)523 static int qcom_iommu_of_xlate(struct device *dev, struct of_phandle_args *args)
524 {
525 struct qcom_iommu_dev *qcom_iommu;
526 struct platform_device *iommu_pdev;
527 unsigned asid = args->args[0];
528
529 if (args->args_count != 1) {
530 dev_err(dev, "incorrect number of iommu params found for %s "
531 "(found %d, expected 1)\n",
532 args->np->full_name, args->args_count);
533 return -EINVAL;
534 }
535
536 iommu_pdev = of_find_device_by_node(args->np);
537 if (WARN_ON(!iommu_pdev))
538 return -EINVAL;
539
540 qcom_iommu = platform_get_drvdata(iommu_pdev);
541
542 /* make sure the asid specified in dt is valid, so we don't have
543 * to sanity check this elsewhere:
544 */
545 if (WARN_ON(asid > qcom_iommu->max_asid) ||
546 WARN_ON(qcom_iommu->ctxs[asid] == NULL)) {
547 put_device(&iommu_pdev->dev);
548 return -EINVAL;
549 }
550
551 if (!dev_iommu_priv_get(dev)) {
552 dev_iommu_priv_set(dev, qcom_iommu);
553 } else {
554 /* make sure devices iommus dt node isn't referring to
555 * multiple different iommu devices. Multiple context
556 * banks are ok, but multiple devices are not:
557 */
558 if (WARN_ON(qcom_iommu != dev_iommu_priv_get(dev))) {
559 put_device(&iommu_pdev->dev);
560 return -EINVAL;
561 }
562 }
563
564 return iommu_fwspec_add_ids(dev, &asid, 1);
565 }
566
567 static const struct iommu_ops qcom_iommu_ops = {
568 .capable = qcom_iommu_capable,
569 .domain_alloc = qcom_iommu_domain_alloc,
570 .probe_device = qcom_iommu_probe_device,
571 .device_group = generic_device_group,
572 .of_xlate = qcom_iommu_of_xlate,
573 .pgsize_bitmap = SZ_4K | SZ_64K | SZ_1M | SZ_16M,
574 .default_domain_ops = &(const struct iommu_domain_ops) {
575 .attach_dev = qcom_iommu_attach_dev,
576 .map_pages = qcom_iommu_map,
577 .unmap_pages = qcom_iommu_unmap,
578 .flush_iotlb_all = qcom_iommu_flush_iotlb_all,
579 .iotlb_sync = qcom_iommu_iotlb_sync,
580 .iova_to_phys = qcom_iommu_iova_to_phys,
581 .free = qcom_iommu_domain_free,
582 }
583 };
584
qcom_iommu_sec_ptbl_init(struct device * dev)585 static int qcom_iommu_sec_ptbl_init(struct device *dev)
586 {
587 size_t psize = 0;
588 unsigned int spare = 0;
589 void *cpu_addr;
590 dma_addr_t paddr;
591 unsigned long attrs;
592 static bool allocated = false;
593 int ret;
594
595 if (allocated)
596 return 0;
597
598 ret = qcom_scm_iommu_secure_ptbl_size(spare, &psize);
599 if (ret) {
600 dev_err(dev, "failed to get iommu secure pgtable size (%d)\n",
601 ret);
602 return ret;
603 }
604
605 dev_info(dev, "iommu sec: pgtable size: %zu\n", psize);
606
607 attrs = DMA_ATTR_NO_KERNEL_MAPPING;
608
609 cpu_addr = dma_alloc_attrs(dev, psize, &paddr, GFP_KERNEL, attrs);
610 if (!cpu_addr) {
611 dev_err(dev, "failed to allocate %zu bytes for pgtable\n",
612 psize);
613 return -ENOMEM;
614 }
615
616 ret = qcom_scm_iommu_secure_ptbl_init(paddr, psize, spare);
617 if (ret) {
618 dev_err(dev, "failed to init iommu pgtable (%d)\n", ret);
619 goto free_mem;
620 }
621
622 allocated = true;
623 return 0;
624
625 free_mem:
626 dma_free_attrs(dev, psize, cpu_addr, paddr, attrs);
627 return ret;
628 }
629
get_asid(const struct device_node * np)630 static int get_asid(const struct device_node *np)
631 {
632 u32 reg, val;
633 int asid;
634
635 /* read the "reg" property directly to get the relative address
636 * of the context bank, and calculate the asid from that:
637 */
638 if (of_property_read_u32_index(np, "reg", 0, ®))
639 return -ENODEV;
640
641 /*
642 * Context banks are 0x1000 apart but, in some cases, the ASID
643 * number doesn't match to this logic and needs to be passed
644 * from the DT configuration explicitly.
645 */
646 if (!of_property_read_u32(np, "qcom,ctx-asid", &val))
647 asid = val;
648 else
649 asid = reg / 0x1000;
650
651 return asid;
652 }
653
qcom_iommu_ctx_probe(struct platform_device * pdev)654 static int qcom_iommu_ctx_probe(struct platform_device *pdev)
655 {
656 struct qcom_iommu_ctx *ctx;
657 struct device *dev = &pdev->dev;
658 struct qcom_iommu_dev *qcom_iommu = dev_get_drvdata(dev->parent);
659 int ret, irq;
660
661 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
662 if (!ctx)
663 return -ENOMEM;
664
665 ctx->dev = dev;
666 platform_set_drvdata(pdev, ctx);
667
668 ctx->base = devm_platform_ioremap_resource(pdev, 0);
669 if (IS_ERR(ctx->base))
670 return PTR_ERR(ctx->base);
671
672 irq = platform_get_irq(pdev, 0);
673 if (irq < 0)
674 return irq;
675
676 if (of_device_is_compatible(dev->of_node, "qcom,msm-iommu-v2-sec"))
677 ctx->secured_ctx = true;
678
679 /* clear IRQs before registering fault handler, just in case the
680 * boot-loader left us a surprise:
681 */
682 if (!ctx->secured_ctx)
683 iommu_writel(ctx, ARM_SMMU_CB_FSR, iommu_readl(ctx, ARM_SMMU_CB_FSR));
684
685 ret = devm_request_irq(dev, irq,
686 qcom_iommu_fault,
687 IRQF_SHARED,
688 "qcom-iommu-fault",
689 ctx);
690 if (ret) {
691 dev_err(dev, "failed to request IRQ %u\n", irq);
692 return ret;
693 }
694
695 ret = get_asid(dev->of_node);
696 if (ret < 0) {
697 dev_err(dev, "missing reg property\n");
698 return ret;
699 }
700
701 ctx->asid = ret;
702
703 dev_dbg(dev, "found asid %u\n", ctx->asid);
704
705 qcom_iommu->ctxs[ctx->asid] = ctx;
706
707 return 0;
708 }
709
qcom_iommu_ctx_remove(struct platform_device * pdev)710 static void qcom_iommu_ctx_remove(struct platform_device *pdev)
711 {
712 struct qcom_iommu_dev *qcom_iommu = dev_get_drvdata(pdev->dev.parent);
713 struct qcom_iommu_ctx *ctx = platform_get_drvdata(pdev);
714
715 platform_set_drvdata(pdev, NULL);
716
717 qcom_iommu->ctxs[ctx->asid] = NULL;
718 }
719
720 static const struct of_device_id ctx_of_match[] = {
721 { .compatible = "qcom,msm-iommu-v1-ns" },
722 { .compatible = "qcom,msm-iommu-v1-sec" },
723 { .compatible = "qcom,msm-iommu-v2-ns" },
724 { .compatible = "qcom,msm-iommu-v2-sec" },
725 { /* sentinel */ }
726 };
727
728 static struct platform_driver qcom_iommu_ctx_driver = {
729 .driver = {
730 .name = "qcom-iommu-ctx",
731 .of_match_table = ctx_of_match,
732 },
733 .probe = qcom_iommu_ctx_probe,
734 .remove_new = qcom_iommu_ctx_remove,
735 };
736
qcom_iommu_has_secure_context(struct qcom_iommu_dev * qcom_iommu)737 static bool qcom_iommu_has_secure_context(struct qcom_iommu_dev *qcom_iommu)
738 {
739 struct device_node *child;
740
741 for_each_child_of_node(qcom_iommu->dev->of_node, child) {
742 if (of_device_is_compatible(child, "qcom,msm-iommu-v1-sec") ||
743 of_device_is_compatible(child, "qcom,msm-iommu-v2-sec")) {
744 of_node_put(child);
745 return true;
746 }
747 }
748
749 return false;
750 }
751
qcom_iommu_device_probe(struct platform_device * pdev)752 static int qcom_iommu_device_probe(struct platform_device *pdev)
753 {
754 struct device_node *child;
755 struct qcom_iommu_dev *qcom_iommu;
756 struct device *dev = &pdev->dev;
757 struct resource *res;
758 struct clk *clk;
759 int ret, max_asid = 0;
760
761 /* find the max asid (which is 1:1 to ctx bank idx), so we know how
762 * many child ctx devices we have:
763 */
764 for_each_child_of_node(dev->of_node, child)
765 max_asid = max(max_asid, get_asid(child));
766
767 qcom_iommu = devm_kzalloc(dev, struct_size(qcom_iommu, ctxs, max_asid + 1),
768 GFP_KERNEL);
769 if (!qcom_iommu)
770 return -ENOMEM;
771 qcom_iommu->max_asid = max_asid;
772 qcom_iommu->dev = dev;
773
774 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
775 if (res) {
776 qcom_iommu->local_base = devm_ioremap_resource(dev, res);
777 if (IS_ERR(qcom_iommu->local_base))
778 return PTR_ERR(qcom_iommu->local_base);
779 }
780
781 clk = devm_clk_get(dev, "iface");
782 if (IS_ERR(clk)) {
783 dev_err(dev, "failed to get iface clock\n");
784 return PTR_ERR(clk);
785 }
786 qcom_iommu->clks[CLK_IFACE].clk = clk;
787
788 clk = devm_clk_get(dev, "bus");
789 if (IS_ERR(clk)) {
790 dev_err(dev, "failed to get bus clock\n");
791 return PTR_ERR(clk);
792 }
793 qcom_iommu->clks[CLK_BUS].clk = clk;
794
795 clk = devm_clk_get_optional(dev, "tbu");
796 if (IS_ERR(clk)) {
797 dev_err(dev, "failed to get tbu clock\n");
798 return PTR_ERR(clk);
799 }
800 qcom_iommu->clks[CLK_TBU].clk = clk;
801
802 if (of_property_read_u32(dev->of_node, "qcom,iommu-secure-id",
803 &qcom_iommu->sec_id)) {
804 dev_err(dev, "missing qcom,iommu-secure-id property\n");
805 return -ENODEV;
806 }
807
808 if (qcom_iommu_has_secure_context(qcom_iommu)) {
809 ret = qcom_iommu_sec_ptbl_init(dev);
810 if (ret) {
811 dev_err(dev, "cannot init secure pg table(%d)\n", ret);
812 return ret;
813 }
814 }
815
816 platform_set_drvdata(pdev, qcom_iommu);
817
818 pm_runtime_enable(dev);
819
820 /* register context bank devices, which are child nodes: */
821 ret = devm_of_platform_populate(dev);
822 if (ret) {
823 dev_err(dev, "Failed to populate iommu contexts\n");
824 goto err_pm_disable;
825 }
826
827 ret = iommu_device_sysfs_add(&qcom_iommu->iommu, dev, NULL,
828 dev_name(dev));
829 if (ret) {
830 dev_err(dev, "Failed to register iommu in sysfs\n");
831 goto err_pm_disable;
832 }
833
834 ret = iommu_device_register(&qcom_iommu->iommu, &qcom_iommu_ops, dev);
835 if (ret) {
836 dev_err(dev, "Failed to register iommu\n");
837 goto err_pm_disable;
838 }
839
840 if (qcom_iommu->local_base) {
841 pm_runtime_get_sync(dev);
842 writel_relaxed(0xffffffff, qcom_iommu->local_base + SMMU_INTR_SEL_NS);
843 pm_runtime_put_sync(dev);
844 }
845
846 return 0;
847
848 err_pm_disable:
849 pm_runtime_disable(dev);
850 return ret;
851 }
852
qcom_iommu_device_remove(struct platform_device * pdev)853 static void qcom_iommu_device_remove(struct platform_device *pdev)
854 {
855 struct qcom_iommu_dev *qcom_iommu = platform_get_drvdata(pdev);
856
857 pm_runtime_force_suspend(&pdev->dev);
858 platform_set_drvdata(pdev, NULL);
859 iommu_device_sysfs_remove(&qcom_iommu->iommu);
860 iommu_device_unregister(&qcom_iommu->iommu);
861 }
862
qcom_iommu_resume(struct device * dev)863 static int __maybe_unused qcom_iommu_resume(struct device *dev)
864 {
865 struct qcom_iommu_dev *qcom_iommu = dev_get_drvdata(dev);
866
867 return clk_bulk_prepare_enable(CLK_NUM, qcom_iommu->clks);
868 }
869
qcom_iommu_suspend(struct device * dev)870 static int __maybe_unused qcom_iommu_suspend(struct device *dev)
871 {
872 struct qcom_iommu_dev *qcom_iommu = dev_get_drvdata(dev);
873
874 clk_bulk_disable_unprepare(CLK_NUM, qcom_iommu->clks);
875
876 return 0;
877 }
878
879 static const struct dev_pm_ops qcom_iommu_pm_ops = {
880 SET_RUNTIME_PM_OPS(qcom_iommu_suspend, qcom_iommu_resume, NULL)
881 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
882 pm_runtime_force_resume)
883 };
884
885 static const struct of_device_id qcom_iommu_of_match[] = {
886 { .compatible = "qcom,msm-iommu-v1" },
887 { .compatible = "qcom,msm-iommu-v2" },
888 { /* sentinel */ }
889 };
890
891 static struct platform_driver qcom_iommu_driver = {
892 .driver = {
893 .name = "qcom-iommu",
894 .of_match_table = qcom_iommu_of_match,
895 .pm = &qcom_iommu_pm_ops,
896 },
897 .probe = qcom_iommu_device_probe,
898 .remove_new = qcom_iommu_device_remove,
899 };
900
qcom_iommu_init(void)901 static int __init qcom_iommu_init(void)
902 {
903 int ret;
904
905 ret = platform_driver_register(&qcom_iommu_ctx_driver);
906 if (ret)
907 return ret;
908
909 ret = platform_driver_register(&qcom_iommu_driver);
910 if (ret)
911 platform_driver_unregister(&qcom_iommu_ctx_driver);
912
913 return ret;
914 }
915 device_initcall(qcom_iommu_init);
916
