1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Xilinx AMS driver
4 *
5 * Copyright (C) 2021 Xilinx, Inc.
6 *
7 * Manish Narani <mnarani@xilinx.com>
8 * Rajnikant Bhojani <rajnikant.bhojani@xilinx.com>
9 */
10
11 #include <linux/bits.h>
12 #include <linux/bitfield.h>
13 #include <linux/clk.h>
14 #include <linux/delay.h>
15 #include <linux/devm-helpers.h>
16 #include <linux/interrupt.h>
17 #include <linux/io.h>
18 #include <linux/iopoll.h>
19 #include <linux/kernel.h>
20 #include <linux/module.h>
21 #include <linux/mod_devicetable.h>
22 #include <linux/overflow.h>
23 #include <linux/platform_device.h>
24 #include <linux/property.h>
25 #include <linux/slab.h>
26
27 #include <linux/iio/events.h>
28 #include <linux/iio/iio.h>
29
30 /* AMS registers definitions */
31 #define AMS_ISR_0 0x010
32 #define AMS_ISR_1 0x014
33 #define AMS_IER_0 0x020
34 #define AMS_IER_1 0x024
35 #define AMS_IDR_0 0x028
36 #define AMS_IDR_1 0x02C
37 #define AMS_PS_CSTS 0x040
38 #define AMS_PL_CSTS 0x044
39
40 #define AMS_VCC_PSPLL0 0x060
41 #define AMS_VCC_PSPLL3 0x06C
42 #define AMS_VCCINT 0x078
43 #define AMS_VCCBRAM 0x07C
44 #define AMS_VCCAUX 0x080
45 #define AMS_PSDDRPLL 0x084
46 #define AMS_PSINTFPDDR 0x09C
47
48 #define AMS_VCC_PSPLL0_CH 48
49 #define AMS_VCC_PSPLL3_CH 51
50 #define AMS_VCCINT_CH 54
51 #define AMS_VCCBRAM_CH 55
52 #define AMS_VCCAUX_CH 56
53 #define AMS_PSDDRPLL_CH 57
54 #define AMS_PSINTFPDDR_CH 63
55
56 #define AMS_REG_CONFIG0 0x100
57 #define AMS_REG_CONFIG1 0x104
58 #define AMS_REG_CONFIG3 0x10C
59 #define AMS_REG_CONFIG4 0x110
60 #define AMS_REG_SEQ_CH0 0x120
61 #define AMS_REG_SEQ_CH1 0x124
62 #define AMS_REG_SEQ_CH2 0x118
63
64 #define AMS_VUSER0_MASK BIT(0)
65 #define AMS_VUSER1_MASK BIT(1)
66 #define AMS_VUSER2_MASK BIT(2)
67 #define AMS_VUSER3_MASK BIT(3)
68
69 #define AMS_TEMP 0x000
70 #define AMS_SUPPLY1 0x004
71 #define AMS_SUPPLY2 0x008
72 #define AMS_VP_VN 0x00C
73 #define AMS_VREFP 0x010
74 #define AMS_VREFN 0x014
75 #define AMS_SUPPLY3 0x018
76 #define AMS_SUPPLY4 0x034
77 #define AMS_SUPPLY5 0x038
78 #define AMS_SUPPLY6 0x03C
79 #define AMS_SUPPLY7 0x200
80 #define AMS_SUPPLY8 0x204
81 #define AMS_SUPPLY9 0x208
82 #define AMS_SUPPLY10 0x20C
83 #define AMS_VCCAMS 0x210
84 #define AMS_TEMP_REMOTE 0x214
85
86 #define AMS_REG_VAUX(x) (0x40 + 4 * (x))
87
88 #define AMS_PS_RESET_VALUE 0xFFFF
89 #define AMS_PL_RESET_VALUE 0xFFFF
90
91 #define AMS_CONF0_CHANNEL_NUM_MASK GENMASK(6, 0)
92
93 #define AMS_CONF1_SEQ_MASK GENMASK(15, 12)
94 #define AMS_CONF1_SEQ_DEFAULT FIELD_PREP(AMS_CONF1_SEQ_MASK, 0)
95 #define AMS_CONF1_SEQ_CONTINUOUS FIELD_PREP(AMS_CONF1_SEQ_MASK, 2)
96 #define AMS_CONF1_SEQ_SINGLE_CHANNEL FIELD_PREP(AMS_CONF1_SEQ_MASK, 3)
97
98 #define AMS_REG_SEQ0_MASK GENMASK(15, 0)
99 #define AMS_REG_SEQ2_MASK GENMASK(21, 16)
100 #define AMS_REG_SEQ1_MASK GENMASK_ULL(37, 22)
101
102 #define AMS_PS_SEQ_MASK GENMASK(21, 0)
103 #define AMS_PL_SEQ_MASK GENMASK_ULL(59, 22)
104
105 #define AMS_ALARM_TEMP 0x140
106 #define AMS_ALARM_SUPPLY1 0x144
107 #define AMS_ALARM_SUPPLY2 0x148
108 #define AMS_ALARM_SUPPLY3 0x160
109 #define AMS_ALARM_SUPPLY4 0x164
110 #define AMS_ALARM_SUPPLY5 0x168
111 #define AMS_ALARM_SUPPLY6 0x16C
112 #define AMS_ALARM_SUPPLY7 0x180
113 #define AMS_ALARM_SUPPLY8 0x184
114 #define AMS_ALARM_SUPPLY9 0x188
115 #define AMS_ALARM_SUPPLY10 0x18C
116 #define AMS_ALARM_VCCAMS 0x190
117 #define AMS_ALARM_TEMP_REMOTE 0x194
118 #define AMS_ALARM_THRESHOLD_OFF_10 0x10
119 #define AMS_ALARM_THRESHOLD_OFF_20 0x20
120
121 #define AMS_ALARM_THR_DIRECT_MASK BIT(1)
122 #define AMS_ALARM_THR_MIN 0x0000
123 #define AMS_ALARM_THR_MAX (BIT(16) - 1)
124
125 #define AMS_ALARM_MASK GENMASK_ULL(63, 0)
126 #define AMS_NO_OF_ALARMS 32
127 #define AMS_PL_ALARM_START 16
128 #define AMS_PL_ALARM_MASK GENMASK(31, 16)
129 #define AMS_ISR0_ALARM_MASK GENMASK(31, 0)
130 #define AMS_ISR1_ALARM_MASK (GENMASK(31, 29) | GENMASK(4, 0))
131 #define AMS_ISR1_EOC_MASK BIT(3)
132 #define AMS_ISR1_INTR_MASK GENMASK_ULL(63, 32)
133 #define AMS_ISR0_ALARM_2_TO_0_MASK GENMASK(2, 0)
134 #define AMS_ISR0_ALARM_6_TO_3_MASK GENMASK(6, 3)
135 #define AMS_ISR0_ALARM_12_TO_7_MASK GENMASK(13, 8)
136 #define AMS_CONF1_ALARM_2_TO_0_MASK GENMASK(3, 1)
137 #define AMS_CONF1_ALARM_6_TO_3_MASK GENMASK(11, 8)
138 #define AMS_CONF1_ALARM_12_TO_7_MASK GENMASK(5, 0)
139 #define AMS_REGCFG1_ALARM_MASK \
140 (AMS_CONF1_ALARM_2_TO_0_MASK | AMS_CONF1_ALARM_6_TO_3_MASK | BIT(0))
141 #define AMS_REGCFG3_ALARM_MASK AMS_CONF1_ALARM_12_TO_7_MASK
142
143 #define AMS_PS_CSTS_PS_READY (BIT(27) | BIT(16))
144 #define AMS_PL_CSTS_ACCESS_MASK BIT(1)
145
146 #define AMS_PL_MAX_FIXED_CHANNEL 10
147 #define AMS_PL_MAX_EXT_CHANNEL 20
148
149 #define AMS_INIT_POLL_TIME_US 200
150 #define AMS_INIT_TIMEOUT_US 10000
151 #define AMS_UNMASK_TIMEOUT_MS 500
152
153 /*
154 * Following scale and offset value is derived from
155 * UG580 (v1.7) December 20, 2016
156 */
157 #define AMS_SUPPLY_SCALE_1VOLT_mV 1000
158 #define AMS_SUPPLY_SCALE_3VOLT_mV 3000
159 #define AMS_SUPPLY_SCALE_6VOLT_mV 6000
160 #define AMS_SUPPLY_SCALE_DIV_BIT 16
161
162 #define AMS_TEMP_SCALE 509314
163 #define AMS_TEMP_SCALE_DIV_BIT 16
164 #define AMS_TEMP_OFFSET -((280230LL << 16) / 509314)
165
166 enum ams_alarm_bit {
167 AMS_ALARM_BIT_TEMP = 0,
168 AMS_ALARM_BIT_SUPPLY1 = 1,
169 AMS_ALARM_BIT_SUPPLY2 = 2,
170 AMS_ALARM_BIT_SUPPLY3 = 3,
171 AMS_ALARM_BIT_SUPPLY4 = 4,
172 AMS_ALARM_BIT_SUPPLY5 = 5,
173 AMS_ALARM_BIT_SUPPLY6 = 6,
174 AMS_ALARM_BIT_RESERVED = 7,
175 AMS_ALARM_BIT_SUPPLY7 = 8,
176 AMS_ALARM_BIT_SUPPLY8 = 9,
177 AMS_ALARM_BIT_SUPPLY9 = 10,
178 AMS_ALARM_BIT_SUPPLY10 = 11,
179 AMS_ALARM_BIT_VCCAMS = 12,
180 AMS_ALARM_BIT_TEMP_REMOTE = 13,
181 };
182
183 enum ams_seq {
184 AMS_SEQ_VCC_PSPLL = 0,
185 AMS_SEQ_VCC_PSBATT = 1,
186 AMS_SEQ_VCCINT = 2,
187 AMS_SEQ_VCCBRAM = 3,
188 AMS_SEQ_VCCAUX = 4,
189 AMS_SEQ_PSDDRPLL = 5,
190 AMS_SEQ_INTDDR = 6,
191 };
192
193 enum ams_ps_pl_seq {
194 AMS_SEQ_CALIB = 0,
195 AMS_SEQ_RSVD_1 = 1,
196 AMS_SEQ_RSVD_2 = 2,
197 AMS_SEQ_TEST = 3,
198 AMS_SEQ_RSVD_4 = 4,
199 AMS_SEQ_SUPPLY4 = 5,
200 AMS_SEQ_SUPPLY5 = 6,
201 AMS_SEQ_SUPPLY6 = 7,
202 AMS_SEQ_TEMP = 8,
203 AMS_SEQ_SUPPLY2 = 9,
204 AMS_SEQ_SUPPLY1 = 10,
205 AMS_SEQ_VP_VN = 11,
206 AMS_SEQ_VREFP = 12,
207 AMS_SEQ_VREFN = 13,
208 AMS_SEQ_SUPPLY3 = 14,
209 AMS_SEQ_CURRENT_MON = 15,
210 AMS_SEQ_SUPPLY7 = 16,
211 AMS_SEQ_SUPPLY8 = 17,
212 AMS_SEQ_SUPPLY9 = 18,
213 AMS_SEQ_SUPPLY10 = 19,
214 AMS_SEQ_VCCAMS = 20,
215 AMS_SEQ_TEMP_REMOTE = 21,
216 AMS_SEQ_MAX = 22
217 };
218
219 #define AMS_PS_SEQ_MAX AMS_SEQ_MAX
220 #define AMS_SEQ(x) (AMS_SEQ_MAX + (x))
221 #define PS_SEQ(x) (x)
222 #define PL_SEQ(x) (AMS_PS_SEQ_MAX + (x))
223 #define AMS_CTRL_SEQ_BASE (AMS_PS_SEQ_MAX * 3)
224
225 #define AMS_CHAN_TEMP(_scan_index, _addr) { \
226 .type = IIO_TEMP, \
227 .indexed = 1, \
228 .address = (_addr), \
229 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
230 BIT(IIO_CHAN_INFO_SCALE) | \
231 BIT(IIO_CHAN_INFO_OFFSET), \
232 .event_spec = ams_temp_events, \
233 .scan_index = _scan_index, \
234 .num_event_specs = ARRAY_SIZE(ams_temp_events), \
235 }
236
237 #define AMS_CHAN_VOLTAGE(_scan_index, _addr, _alarm) { \
238 .type = IIO_VOLTAGE, \
239 .indexed = 1, \
240 .address = (_addr), \
241 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
242 BIT(IIO_CHAN_INFO_SCALE), \
243 .event_spec = (_alarm) ? ams_voltage_events : NULL, \
244 .scan_index = _scan_index, \
245 .num_event_specs = (_alarm) ? ARRAY_SIZE(ams_voltage_events) : 0, \
246 }
247
248 #define AMS_PS_CHAN_TEMP(_scan_index, _addr) \
249 AMS_CHAN_TEMP(PS_SEQ(_scan_index), _addr)
250 #define AMS_PS_CHAN_VOLTAGE(_scan_index, _addr) \
251 AMS_CHAN_VOLTAGE(PS_SEQ(_scan_index), _addr, true)
252
253 #define AMS_PL_CHAN_TEMP(_scan_index, _addr) \
254 AMS_CHAN_TEMP(PL_SEQ(_scan_index), _addr)
255 #define AMS_PL_CHAN_VOLTAGE(_scan_index, _addr, _alarm) \
256 AMS_CHAN_VOLTAGE(PL_SEQ(_scan_index), _addr, _alarm)
257 #define AMS_PL_AUX_CHAN_VOLTAGE(_auxno) \
258 AMS_CHAN_VOLTAGE(PL_SEQ(AMS_SEQ(_auxno)), AMS_REG_VAUX(_auxno), false)
259 #define AMS_CTRL_CHAN_VOLTAGE(_scan_index, _addr) \
260 AMS_CHAN_VOLTAGE(PL_SEQ(AMS_SEQ(AMS_SEQ(_scan_index))), _addr, false)
261
262 /**
263 * struct ams - This structure contains necessary state for xilinx-ams to operate
264 * @base: physical base address of device
265 * @ps_base: physical base address of PS device
266 * @pl_base: physical base address of PL device
267 * @clk: clocks associated with the device
268 * @dev: pointer to device struct
269 * @lock: to handle multiple user interaction
270 * @intr_lock: to protect interrupt mask values
271 * @alarm_mask: alarm configuration
272 * @current_masked_alarm: currently masked due to alarm
273 * @intr_mask: interrupt configuration
274 * @ams_unmask_work: re-enables event once the event condition disappears
275 *
276 */
277 struct ams {
278 void __iomem *base;
279 void __iomem *ps_base;
280 void __iomem *pl_base;
281 struct clk *clk;
282 struct device *dev;
283 struct mutex lock;
284 spinlock_t intr_lock;
285 unsigned int alarm_mask;
286 unsigned int current_masked_alarm;
287 u64 intr_mask;
288 struct delayed_work ams_unmask_work;
289 };
290
ams_ps_update_reg(struct ams * ams,unsigned int offset,u32 mask,u32 data)291 static inline void ams_ps_update_reg(struct ams *ams, unsigned int offset,
292 u32 mask, u32 data)
293 {
294 u32 val, regval;
295
296 val = readl(ams->ps_base + offset);
297 regval = (val & ~mask) | (data & mask);
298 writel(regval, ams->ps_base + offset);
299 }
300
ams_pl_update_reg(struct ams * ams,unsigned int offset,u32 mask,u32 data)301 static inline void ams_pl_update_reg(struct ams *ams, unsigned int offset,
302 u32 mask, u32 data)
303 {
304 u32 val, regval;
305
306 val = readl(ams->pl_base + offset);
307 regval = (val & ~mask) | (data & mask);
308 writel(regval, ams->pl_base + offset);
309 }
310
ams_update_intrmask(struct ams * ams,u64 mask,u64 val)311 static void ams_update_intrmask(struct ams *ams, u64 mask, u64 val)
312 {
313 u32 regval;
314
315 ams->intr_mask = (ams->intr_mask & ~mask) | (val & mask);
316
317 regval = ~(ams->intr_mask | ams->current_masked_alarm);
318 writel(regval, ams->base + AMS_IER_0);
319
320 regval = ~(FIELD_GET(AMS_ISR1_INTR_MASK, ams->intr_mask));
321 writel(regval, ams->base + AMS_IER_1);
322
323 regval = ams->intr_mask | ams->current_masked_alarm;
324 writel(regval, ams->base + AMS_IDR_0);
325
326 regval = FIELD_GET(AMS_ISR1_INTR_MASK, ams->intr_mask);
327 writel(regval, ams->base + AMS_IDR_1);
328 }
329
ams_disable_all_alarms(struct ams * ams)330 static void ams_disable_all_alarms(struct ams *ams)
331 {
332 /* disable PS module alarm */
333 if (ams->ps_base) {
334 ams_ps_update_reg(ams, AMS_REG_CONFIG1, AMS_REGCFG1_ALARM_MASK,
335 AMS_REGCFG1_ALARM_MASK);
336 ams_ps_update_reg(ams, AMS_REG_CONFIG3, AMS_REGCFG3_ALARM_MASK,
337 AMS_REGCFG3_ALARM_MASK);
338 }
339
340 /* disable PL module alarm */
341 if (ams->pl_base) {
342 ams_pl_update_reg(ams, AMS_REG_CONFIG1, AMS_REGCFG1_ALARM_MASK,
343 AMS_REGCFG1_ALARM_MASK);
344 ams_pl_update_reg(ams, AMS_REG_CONFIG3, AMS_REGCFG3_ALARM_MASK,
345 AMS_REGCFG3_ALARM_MASK);
346 }
347 }
348
ams_update_ps_alarm(struct ams * ams,unsigned long alarm_mask)349 static void ams_update_ps_alarm(struct ams *ams, unsigned long alarm_mask)
350 {
351 u32 cfg;
352 u32 val;
353
354 val = FIELD_GET(AMS_ISR0_ALARM_2_TO_0_MASK, alarm_mask);
355 cfg = ~(FIELD_PREP(AMS_CONF1_ALARM_2_TO_0_MASK, val));
356
357 val = FIELD_GET(AMS_ISR0_ALARM_6_TO_3_MASK, alarm_mask);
358 cfg &= ~(FIELD_PREP(AMS_CONF1_ALARM_6_TO_3_MASK, val));
359
360 ams_ps_update_reg(ams, AMS_REG_CONFIG1, AMS_REGCFG1_ALARM_MASK, cfg);
361
362 val = FIELD_GET(AMS_ISR0_ALARM_12_TO_7_MASK, alarm_mask);
363 cfg = ~(FIELD_PREP(AMS_CONF1_ALARM_12_TO_7_MASK, val));
364 ams_ps_update_reg(ams, AMS_REG_CONFIG3, AMS_REGCFG3_ALARM_MASK, cfg);
365 }
366
ams_update_pl_alarm(struct ams * ams,unsigned long alarm_mask)367 static void ams_update_pl_alarm(struct ams *ams, unsigned long alarm_mask)
368 {
369 unsigned long pl_alarm_mask;
370 u32 cfg;
371 u32 val;
372
373 pl_alarm_mask = FIELD_GET(AMS_PL_ALARM_MASK, alarm_mask);
374
375 val = FIELD_GET(AMS_ISR0_ALARM_2_TO_0_MASK, pl_alarm_mask);
376 cfg = ~(FIELD_PREP(AMS_CONF1_ALARM_2_TO_0_MASK, val));
377
378 val = FIELD_GET(AMS_ISR0_ALARM_6_TO_3_MASK, pl_alarm_mask);
379 cfg &= ~(FIELD_PREP(AMS_CONF1_ALARM_6_TO_3_MASK, val));
380
381 ams_pl_update_reg(ams, AMS_REG_CONFIG1, AMS_REGCFG1_ALARM_MASK, cfg);
382
383 val = FIELD_GET(AMS_ISR0_ALARM_12_TO_7_MASK, pl_alarm_mask);
384 cfg = ~(FIELD_PREP(AMS_CONF1_ALARM_12_TO_7_MASK, val));
385 ams_pl_update_reg(ams, AMS_REG_CONFIG3, AMS_REGCFG3_ALARM_MASK, cfg);
386 }
387
ams_update_alarm(struct ams * ams,unsigned long alarm_mask)388 static void ams_update_alarm(struct ams *ams, unsigned long alarm_mask)
389 {
390 unsigned long flags;
391
392 if (ams->ps_base)
393 ams_update_ps_alarm(ams, alarm_mask);
394
395 if (ams->pl_base)
396 ams_update_pl_alarm(ams, alarm_mask);
397
398 spin_lock_irqsave(&ams->intr_lock, flags);
399 ams_update_intrmask(ams, AMS_ISR0_ALARM_MASK, ~alarm_mask);
400 spin_unlock_irqrestore(&ams->intr_lock, flags);
401 }
402
ams_enable_channel_sequence(struct iio_dev * indio_dev)403 static void ams_enable_channel_sequence(struct iio_dev *indio_dev)
404 {
405 struct ams *ams = iio_priv(indio_dev);
406 unsigned long long scan_mask;
407 int i;
408 u32 regval;
409
410 /*
411 * Enable channel sequence. First 22 bits of scan_mask represent
412 * PS channels, and next remaining bits represent PL channels.
413 */
414
415 /* Run calibration of PS & PL as part of the sequence */
416 scan_mask = BIT(0) | BIT(AMS_PS_SEQ_MAX);
417 for (i = 0; i < indio_dev->num_channels; i++)
418 scan_mask |= BIT_ULL(indio_dev->channels[i].scan_index);
419
420 if (ams->ps_base) {
421 /* put sysmon in a soft reset to change the sequence */
422 ams_ps_update_reg(ams, AMS_REG_CONFIG1, AMS_CONF1_SEQ_MASK,
423 AMS_CONF1_SEQ_DEFAULT);
424
425 /* configure basic channels */
426 regval = FIELD_GET(AMS_REG_SEQ0_MASK, scan_mask);
427 writel(regval, ams->ps_base + AMS_REG_SEQ_CH0);
428
429 regval = FIELD_GET(AMS_REG_SEQ2_MASK, scan_mask);
430 writel(regval, ams->ps_base + AMS_REG_SEQ_CH2);
431
432 /* set continuous sequence mode */
433 ams_ps_update_reg(ams, AMS_REG_CONFIG1, AMS_CONF1_SEQ_MASK,
434 AMS_CONF1_SEQ_CONTINUOUS);
435 }
436
437 if (ams->pl_base) {
438 /* put sysmon in a soft reset to change the sequence */
439 ams_pl_update_reg(ams, AMS_REG_CONFIG1, AMS_CONF1_SEQ_MASK,
440 AMS_CONF1_SEQ_DEFAULT);
441
442 /* configure basic channels */
443 scan_mask = FIELD_GET(AMS_PL_SEQ_MASK, scan_mask);
444
445 regval = FIELD_GET(AMS_REG_SEQ0_MASK, scan_mask);
446 writel(regval, ams->pl_base + AMS_REG_SEQ_CH0);
447
448 regval = FIELD_GET(AMS_REG_SEQ1_MASK, scan_mask);
449 writel(regval, ams->pl_base + AMS_REG_SEQ_CH1);
450
451 regval = FIELD_GET(AMS_REG_SEQ2_MASK, scan_mask);
452 writel(regval, ams->pl_base + AMS_REG_SEQ_CH2);
453
454 /* set continuous sequence mode */
455 ams_pl_update_reg(ams, AMS_REG_CONFIG1, AMS_CONF1_SEQ_MASK,
456 AMS_CONF1_SEQ_CONTINUOUS);
457 }
458 }
459
ams_init_device(struct ams * ams)460 static int ams_init_device(struct ams *ams)
461 {
462 u32 expect = AMS_PS_CSTS_PS_READY;
463 u32 reg, value;
464 int ret;
465
466 /* reset AMS */
467 if (ams->ps_base) {
468 writel(AMS_PS_RESET_VALUE, ams->ps_base + AMS_VP_VN);
469
470 ret = readl_poll_timeout(ams->base + AMS_PS_CSTS, reg, (reg & expect),
471 AMS_INIT_POLL_TIME_US, AMS_INIT_TIMEOUT_US);
472 if (ret)
473 return ret;
474
475 /* put sysmon in a default state */
476 ams_ps_update_reg(ams, AMS_REG_CONFIG1, AMS_CONF1_SEQ_MASK,
477 AMS_CONF1_SEQ_DEFAULT);
478 }
479
480 if (ams->pl_base) {
481 value = readl(ams->base + AMS_PL_CSTS);
482 if (value == 0)
483 return 0;
484
485 writel(AMS_PL_RESET_VALUE, ams->pl_base + AMS_VP_VN);
486
487 /* put sysmon in a default state */
488 ams_pl_update_reg(ams, AMS_REG_CONFIG1, AMS_CONF1_SEQ_MASK,
489 AMS_CONF1_SEQ_DEFAULT);
490 }
491
492 ams_disable_all_alarms(ams);
493
494 /* Disable interrupt */
495 ams_update_intrmask(ams, AMS_ALARM_MASK, AMS_ALARM_MASK);
496
497 /* Clear any pending interrupt */
498 writel(AMS_ISR0_ALARM_MASK, ams->base + AMS_ISR_0);
499 writel(AMS_ISR1_ALARM_MASK, ams->base + AMS_ISR_1);
500
501 return 0;
502 }
503
ams_enable_single_channel(struct ams * ams,unsigned int offset)504 static int ams_enable_single_channel(struct ams *ams, unsigned int offset)
505 {
506 u8 channel_num;
507
508 switch (offset) {
509 case AMS_VCC_PSPLL0:
510 channel_num = AMS_VCC_PSPLL0_CH;
511 break;
512 case AMS_VCC_PSPLL3:
513 channel_num = AMS_VCC_PSPLL3_CH;
514 break;
515 case AMS_VCCINT:
516 channel_num = AMS_VCCINT_CH;
517 break;
518 case AMS_VCCBRAM:
519 channel_num = AMS_VCCBRAM_CH;
520 break;
521 case AMS_VCCAUX:
522 channel_num = AMS_VCCAUX_CH;
523 break;
524 case AMS_PSDDRPLL:
525 channel_num = AMS_PSDDRPLL_CH;
526 break;
527 case AMS_PSINTFPDDR:
528 channel_num = AMS_PSINTFPDDR_CH;
529 break;
530 default:
531 return -EINVAL;
532 }
533
534 /* put sysmon in a soft reset to change the sequence */
535 ams_ps_update_reg(ams, AMS_REG_CONFIG1, AMS_CONF1_SEQ_MASK,
536 AMS_CONF1_SEQ_DEFAULT);
537
538 /* write the channel number */
539 ams_ps_update_reg(ams, AMS_REG_CONFIG0, AMS_CONF0_CHANNEL_NUM_MASK,
540 channel_num);
541
542 /* set single channel, sequencer off mode */
543 ams_ps_update_reg(ams, AMS_REG_CONFIG1, AMS_CONF1_SEQ_MASK,
544 AMS_CONF1_SEQ_SINGLE_CHANNEL);
545
546 return 0;
547 }
548
ams_read_vcc_reg(struct ams * ams,unsigned int offset,u32 * data)549 static int ams_read_vcc_reg(struct ams *ams, unsigned int offset, u32 *data)
550 {
551 u32 expect = AMS_ISR1_EOC_MASK;
552 u32 reg;
553 int ret;
554
555 ret = ams_enable_single_channel(ams, offset);
556 if (ret)
557 return ret;
558
559 /* clear end-of-conversion flag, wait for next conversion to complete */
560 writel(expect, ams->base + AMS_ISR_1);
561 ret = readl_poll_timeout(ams->base + AMS_ISR_1, reg, (reg & expect),
562 AMS_INIT_POLL_TIME_US, AMS_INIT_TIMEOUT_US);
563 if (ret)
564 return ret;
565
566 *data = readl(ams->base + offset);
567
568 return 0;
569 }
570
ams_get_ps_scale(int address)571 static int ams_get_ps_scale(int address)
572 {
573 int val;
574
575 switch (address) {
576 case AMS_SUPPLY1:
577 case AMS_SUPPLY2:
578 case AMS_SUPPLY3:
579 case AMS_SUPPLY4:
580 case AMS_SUPPLY9:
581 case AMS_SUPPLY10:
582 case AMS_VCCAMS:
583 val = AMS_SUPPLY_SCALE_3VOLT_mV;
584 break;
585 case AMS_SUPPLY5:
586 case AMS_SUPPLY6:
587 case AMS_SUPPLY7:
588 case AMS_SUPPLY8:
589 val = AMS_SUPPLY_SCALE_6VOLT_mV;
590 break;
591 default:
592 val = AMS_SUPPLY_SCALE_1VOLT_mV;
593 break;
594 }
595
596 return val;
597 }
598
ams_get_pl_scale(struct ams * ams,int address)599 static int ams_get_pl_scale(struct ams *ams, int address)
600 {
601 int val, regval;
602
603 switch (address) {
604 case AMS_SUPPLY1:
605 case AMS_SUPPLY2:
606 case AMS_SUPPLY3:
607 case AMS_SUPPLY4:
608 case AMS_SUPPLY5:
609 case AMS_SUPPLY6:
610 case AMS_VCCAMS:
611 case AMS_VREFP:
612 case AMS_VREFN:
613 val = AMS_SUPPLY_SCALE_3VOLT_mV;
614 break;
615 case AMS_SUPPLY7:
616 regval = readl(ams->pl_base + AMS_REG_CONFIG4);
617 if (FIELD_GET(AMS_VUSER0_MASK, regval))
618 val = AMS_SUPPLY_SCALE_6VOLT_mV;
619 else
620 val = AMS_SUPPLY_SCALE_3VOLT_mV;
621 break;
622 case AMS_SUPPLY8:
623 regval = readl(ams->pl_base + AMS_REG_CONFIG4);
624 if (FIELD_GET(AMS_VUSER1_MASK, regval))
625 val = AMS_SUPPLY_SCALE_6VOLT_mV;
626 else
627 val = AMS_SUPPLY_SCALE_3VOLT_mV;
628 break;
629 case AMS_SUPPLY9:
630 regval = readl(ams->pl_base + AMS_REG_CONFIG4);
631 if (FIELD_GET(AMS_VUSER2_MASK, regval))
632 val = AMS_SUPPLY_SCALE_6VOLT_mV;
633 else
634 val = AMS_SUPPLY_SCALE_3VOLT_mV;
635 break;
636 case AMS_SUPPLY10:
637 regval = readl(ams->pl_base + AMS_REG_CONFIG4);
638 if (FIELD_GET(AMS_VUSER3_MASK, regval))
639 val = AMS_SUPPLY_SCALE_6VOLT_mV;
640 else
641 val = AMS_SUPPLY_SCALE_3VOLT_mV;
642 break;
643 case AMS_VP_VN:
644 case AMS_REG_VAUX(0) ... AMS_REG_VAUX(15):
645 val = AMS_SUPPLY_SCALE_1VOLT_mV;
646 break;
647 default:
648 val = AMS_SUPPLY_SCALE_1VOLT_mV;
649 break;
650 }
651
652 return val;
653 }
654
ams_get_ctrl_scale(int address)655 static int ams_get_ctrl_scale(int address)
656 {
657 int val;
658
659 switch (address) {
660 case AMS_VCC_PSPLL0:
661 case AMS_VCC_PSPLL3:
662 case AMS_VCCINT:
663 case AMS_VCCBRAM:
664 case AMS_VCCAUX:
665 case AMS_PSDDRPLL:
666 case AMS_PSINTFPDDR:
667 val = AMS_SUPPLY_SCALE_3VOLT_mV;
668 break;
669 default:
670 val = AMS_SUPPLY_SCALE_1VOLT_mV;
671 break;
672 }
673
674 return val;
675 }
676
ams_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long mask)677 static int ams_read_raw(struct iio_dev *indio_dev,
678 struct iio_chan_spec const *chan,
679 int *val, int *val2, long mask)
680 {
681 struct ams *ams = iio_priv(indio_dev);
682 int ret;
683
684 switch (mask) {
685 case IIO_CHAN_INFO_RAW:
686 mutex_lock(&ams->lock);
687 if (chan->scan_index >= AMS_CTRL_SEQ_BASE) {
688 ret = ams_read_vcc_reg(ams, chan->address, val);
689 if (ret)
690 goto unlock_mutex;
691 ams_enable_channel_sequence(indio_dev);
692 } else if (chan->scan_index >= AMS_PS_SEQ_MAX)
693 *val = readl(ams->pl_base + chan->address);
694 else
695 *val = readl(ams->ps_base + chan->address);
696
697 ret = IIO_VAL_INT;
698 unlock_mutex:
699 mutex_unlock(&ams->lock);
700 return ret;
701 case IIO_CHAN_INFO_SCALE:
702 switch (chan->type) {
703 case IIO_VOLTAGE:
704 if (chan->scan_index < AMS_PS_SEQ_MAX)
705 *val = ams_get_ps_scale(chan->address);
706 else if (chan->scan_index >= AMS_PS_SEQ_MAX &&
707 chan->scan_index < AMS_CTRL_SEQ_BASE)
708 *val = ams_get_pl_scale(ams, chan->address);
709 else
710 *val = ams_get_ctrl_scale(chan->address);
711
712 *val2 = AMS_SUPPLY_SCALE_DIV_BIT;
713 return IIO_VAL_FRACTIONAL_LOG2;
714 case IIO_TEMP:
715 *val = AMS_TEMP_SCALE;
716 *val2 = AMS_TEMP_SCALE_DIV_BIT;
717 return IIO_VAL_FRACTIONAL_LOG2;
718 default:
719 return -EINVAL;
720 }
721 case IIO_CHAN_INFO_OFFSET:
722 /* Only the temperature channel has an offset */
723 *val = AMS_TEMP_OFFSET;
724 return IIO_VAL_INT;
725 default:
726 return -EINVAL;
727 }
728 }
729
ams_get_alarm_offset(int scan_index,enum iio_event_direction dir)730 static int ams_get_alarm_offset(int scan_index, enum iio_event_direction dir)
731 {
732 int offset;
733
734 if (scan_index >= AMS_PS_SEQ_MAX)
735 scan_index -= AMS_PS_SEQ_MAX;
736
737 if (dir == IIO_EV_DIR_FALLING) {
738 if (scan_index < AMS_SEQ_SUPPLY7)
739 offset = AMS_ALARM_THRESHOLD_OFF_10;
740 else
741 offset = AMS_ALARM_THRESHOLD_OFF_20;
742 } else {
743 offset = 0;
744 }
745
746 switch (scan_index) {
747 case AMS_SEQ_TEMP:
748 return AMS_ALARM_TEMP + offset;
749 case AMS_SEQ_SUPPLY1:
750 return AMS_ALARM_SUPPLY1 + offset;
751 case AMS_SEQ_SUPPLY2:
752 return AMS_ALARM_SUPPLY2 + offset;
753 case AMS_SEQ_SUPPLY3:
754 return AMS_ALARM_SUPPLY3 + offset;
755 case AMS_SEQ_SUPPLY4:
756 return AMS_ALARM_SUPPLY4 + offset;
757 case AMS_SEQ_SUPPLY5:
758 return AMS_ALARM_SUPPLY5 + offset;
759 case AMS_SEQ_SUPPLY6:
760 return AMS_ALARM_SUPPLY6 + offset;
761 case AMS_SEQ_SUPPLY7:
762 return AMS_ALARM_SUPPLY7 + offset;
763 case AMS_SEQ_SUPPLY8:
764 return AMS_ALARM_SUPPLY8 + offset;
765 case AMS_SEQ_SUPPLY9:
766 return AMS_ALARM_SUPPLY9 + offset;
767 case AMS_SEQ_SUPPLY10:
768 return AMS_ALARM_SUPPLY10 + offset;
769 case AMS_SEQ_VCCAMS:
770 return AMS_ALARM_VCCAMS + offset;
771 case AMS_SEQ_TEMP_REMOTE:
772 return AMS_ALARM_TEMP_REMOTE + offset;
773 default:
774 return 0;
775 }
776 }
777
ams_event_to_channel(struct iio_dev * dev,u32 event)778 static const struct iio_chan_spec *ams_event_to_channel(struct iio_dev *dev,
779 u32 event)
780 {
781 int scan_index = 0, i;
782
783 if (event >= AMS_PL_ALARM_START) {
784 event -= AMS_PL_ALARM_START;
785 scan_index = AMS_PS_SEQ_MAX;
786 }
787
788 switch (event) {
789 case AMS_ALARM_BIT_TEMP:
790 scan_index += AMS_SEQ_TEMP;
791 break;
792 case AMS_ALARM_BIT_SUPPLY1:
793 scan_index += AMS_SEQ_SUPPLY1;
794 break;
795 case AMS_ALARM_BIT_SUPPLY2:
796 scan_index += AMS_SEQ_SUPPLY2;
797 break;
798 case AMS_ALARM_BIT_SUPPLY3:
799 scan_index += AMS_SEQ_SUPPLY3;
800 break;
801 case AMS_ALARM_BIT_SUPPLY4:
802 scan_index += AMS_SEQ_SUPPLY4;
803 break;
804 case AMS_ALARM_BIT_SUPPLY5:
805 scan_index += AMS_SEQ_SUPPLY5;
806 break;
807 case AMS_ALARM_BIT_SUPPLY6:
808 scan_index += AMS_SEQ_SUPPLY6;
809 break;
810 case AMS_ALARM_BIT_SUPPLY7:
811 scan_index += AMS_SEQ_SUPPLY7;
812 break;
813 case AMS_ALARM_BIT_SUPPLY8:
814 scan_index += AMS_SEQ_SUPPLY8;
815 break;
816 case AMS_ALARM_BIT_SUPPLY9:
817 scan_index += AMS_SEQ_SUPPLY9;
818 break;
819 case AMS_ALARM_BIT_SUPPLY10:
820 scan_index += AMS_SEQ_SUPPLY10;
821 break;
822 case AMS_ALARM_BIT_VCCAMS:
823 scan_index += AMS_SEQ_VCCAMS;
824 break;
825 case AMS_ALARM_BIT_TEMP_REMOTE:
826 scan_index += AMS_SEQ_TEMP_REMOTE;
827 break;
828 default:
829 break;
830 }
831
832 for (i = 0; i < dev->num_channels; i++)
833 if (dev->channels[i].scan_index == scan_index)
834 break;
835
836 return &dev->channels[i];
837 }
838
ams_get_alarm_mask(int scan_index)839 static int ams_get_alarm_mask(int scan_index)
840 {
841 int bit = 0;
842
843 if (scan_index >= AMS_PS_SEQ_MAX) {
844 bit = AMS_PL_ALARM_START;
845 scan_index -= AMS_PS_SEQ_MAX;
846 }
847
848 switch (scan_index) {
849 case AMS_SEQ_TEMP:
850 return BIT(AMS_ALARM_BIT_TEMP + bit);
851 case AMS_SEQ_SUPPLY1:
852 return BIT(AMS_ALARM_BIT_SUPPLY1 + bit);
853 case AMS_SEQ_SUPPLY2:
854 return BIT(AMS_ALARM_BIT_SUPPLY2 + bit);
855 case AMS_SEQ_SUPPLY3:
856 return BIT(AMS_ALARM_BIT_SUPPLY3 + bit);
857 case AMS_SEQ_SUPPLY4:
858 return BIT(AMS_ALARM_BIT_SUPPLY4 + bit);
859 case AMS_SEQ_SUPPLY5:
860 return BIT(AMS_ALARM_BIT_SUPPLY5 + bit);
861 case AMS_SEQ_SUPPLY6:
862 return BIT(AMS_ALARM_BIT_SUPPLY6 + bit);
863 case AMS_SEQ_SUPPLY7:
864 return BIT(AMS_ALARM_BIT_SUPPLY7 + bit);
865 case AMS_SEQ_SUPPLY8:
866 return BIT(AMS_ALARM_BIT_SUPPLY8 + bit);
867 case AMS_SEQ_SUPPLY9:
868 return BIT(AMS_ALARM_BIT_SUPPLY9 + bit);
869 case AMS_SEQ_SUPPLY10:
870 return BIT(AMS_ALARM_BIT_SUPPLY10 + bit);
871 case AMS_SEQ_VCCAMS:
872 return BIT(AMS_ALARM_BIT_VCCAMS + bit);
873 case AMS_SEQ_TEMP_REMOTE:
874 return BIT(AMS_ALARM_BIT_TEMP_REMOTE + bit);
875 default:
876 return 0;
877 }
878 }
879
ams_read_event_config(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir)880 static int ams_read_event_config(struct iio_dev *indio_dev,
881 const struct iio_chan_spec *chan,
882 enum iio_event_type type,
883 enum iio_event_direction dir)
884 {
885 struct ams *ams = iio_priv(indio_dev);
886
887 return !!(ams->alarm_mask & ams_get_alarm_mask(chan->scan_index));
888 }
889
ams_write_event_config(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,int state)890 static int ams_write_event_config(struct iio_dev *indio_dev,
891 const struct iio_chan_spec *chan,
892 enum iio_event_type type,
893 enum iio_event_direction dir,
894 int state)
895 {
896 struct ams *ams = iio_priv(indio_dev);
897 unsigned int alarm;
898
899 alarm = ams_get_alarm_mask(chan->scan_index);
900
901 mutex_lock(&ams->lock);
902
903 if (state)
904 ams->alarm_mask |= alarm;
905 else
906 ams->alarm_mask &= ~alarm;
907
908 ams_update_alarm(ams, ams->alarm_mask);
909
910 mutex_unlock(&ams->lock);
911
912 return 0;
913 }
914
ams_read_event_value(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,enum iio_event_info info,int * val,int * val2)915 static int ams_read_event_value(struct iio_dev *indio_dev,
916 const struct iio_chan_spec *chan,
917 enum iio_event_type type,
918 enum iio_event_direction dir,
919 enum iio_event_info info, int *val, int *val2)
920 {
921 struct ams *ams = iio_priv(indio_dev);
922 unsigned int offset = ams_get_alarm_offset(chan->scan_index, dir);
923
924 mutex_lock(&ams->lock);
925
926 if (chan->scan_index >= AMS_PS_SEQ_MAX)
927 *val = readl(ams->pl_base + offset);
928 else
929 *val = readl(ams->ps_base + offset);
930
931 mutex_unlock(&ams->lock);
932
933 return IIO_VAL_INT;
934 }
935
ams_write_event_value(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,enum iio_event_info info,int val,int val2)936 static int ams_write_event_value(struct iio_dev *indio_dev,
937 const struct iio_chan_spec *chan,
938 enum iio_event_type type,
939 enum iio_event_direction dir,
940 enum iio_event_info info, int val, int val2)
941 {
942 struct ams *ams = iio_priv(indio_dev);
943 unsigned int offset;
944
945 mutex_lock(&ams->lock);
946
947 /* Set temperature channel threshold to direct threshold */
948 if (chan->type == IIO_TEMP) {
949 offset = ams_get_alarm_offset(chan->scan_index, IIO_EV_DIR_FALLING);
950
951 if (chan->scan_index >= AMS_PS_SEQ_MAX)
952 ams_pl_update_reg(ams, offset,
953 AMS_ALARM_THR_DIRECT_MASK,
954 AMS_ALARM_THR_DIRECT_MASK);
955 else
956 ams_ps_update_reg(ams, offset,
957 AMS_ALARM_THR_DIRECT_MASK,
958 AMS_ALARM_THR_DIRECT_MASK);
959 }
960
961 offset = ams_get_alarm_offset(chan->scan_index, dir);
962 if (chan->scan_index >= AMS_PS_SEQ_MAX)
963 writel(val, ams->pl_base + offset);
964 else
965 writel(val, ams->ps_base + offset);
966
967 mutex_unlock(&ams->lock);
968
969 return 0;
970 }
971
ams_handle_event(struct iio_dev * indio_dev,u32 event)972 static void ams_handle_event(struct iio_dev *indio_dev, u32 event)
973 {
974 const struct iio_chan_spec *chan;
975
976 chan = ams_event_to_channel(indio_dev, event);
977
978 if (chan->type == IIO_TEMP) {
979 /*
980 * The temperature channel only supports over-temperature
981 * events.
982 */
983 iio_push_event(indio_dev,
984 IIO_UNMOD_EVENT_CODE(chan->type, chan->channel,
985 IIO_EV_TYPE_THRESH,
986 IIO_EV_DIR_RISING),
987 iio_get_time_ns(indio_dev));
988 } else {
989 /*
990 * For other channels we don't know whether it is a upper or
991 * lower threshold event. Userspace will have to check the
992 * channel value if it wants to know.
993 */
994 iio_push_event(indio_dev,
995 IIO_UNMOD_EVENT_CODE(chan->type, chan->channel,
996 IIO_EV_TYPE_THRESH,
997 IIO_EV_DIR_EITHER),
998 iio_get_time_ns(indio_dev));
999 }
1000 }
1001
ams_handle_events(struct iio_dev * indio_dev,unsigned long events)1002 static void ams_handle_events(struct iio_dev *indio_dev, unsigned long events)
1003 {
1004 unsigned int bit;
1005
1006 for_each_set_bit(bit, &events, AMS_NO_OF_ALARMS)
1007 ams_handle_event(indio_dev, bit);
1008 }
1009
1010 /**
1011 * ams_unmask_worker - ams alarm interrupt unmask worker
1012 * @work: work to be done
1013 *
1014 * The ZynqMP threshold interrupts are level sensitive. Since we can't make the
1015 * threshold condition go way from within the interrupt handler, this means as
1016 * soon as a threshold condition is present we would enter the interrupt handler
1017 * again and again. To work around this we mask all active threshold interrupts
1018 * in the interrupt handler and start a timer. In this timer we poll the
1019 * interrupt status and only if the interrupt is inactive we unmask it again.
1020 */
ams_unmask_worker(struct work_struct * work)1021 static void ams_unmask_worker(struct work_struct *work)
1022 {
1023 struct ams *ams = container_of(work, struct ams, ams_unmask_work.work);
1024 unsigned int status, unmask;
1025
1026 spin_lock_irq(&ams->intr_lock);
1027
1028 status = readl(ams->base + AMS_ISR_0);
1029
1030 /* Clear those bits which are not active anymore */
1031 unmask = (ams->current_masked_alarm ^ status) & ams->current_masked_alarm;
1032
1033 /* Clear status of disabled alarm */
1034 unmask |= ams->intr_mask;
1035
1036 ams->current_masked_alarm &= status;
1037
1038 /* Also clear those which are masked out anyway */
1039 ams->current_masked_alarm &= ~ams->intr_mask;
1040
1041 /* Clear the interrupts before we unmask them */
1042 writel(unmask, ams->base + AMS_ISR_0);
1043
1044 ams_update_intrmask(ams, ~AMS_ALARM_MASK, ~AMS_ALARM_MASK);
1045
1046 spin_unlock_irq(&ams->intr_lock);
1047
1048 /* If still pending some alarm re-trigger the timer */
1049 if (ams->current_masked_alarm)
1050 schedule_delayed_work(&ams->ams_unmask_work,
1051 msecs_to_jiffies(AMS_UNMASK_TIMEOUT_MS));
1052 }
1053
ams_irq(int irq,void * data)1054 static irqreturn_t ams_irq(int irq, void *data)
1055 {
1056 struct iio_dev *indio_dev = data;
1057 struct ams *ams = iio_priv(indio_dev);
1058 u32 isr0;
1059
1060 spin_lock(&ams->intr_lock);
1061
1062 isr0 = readl(ams->base + AMS_ISR_0);
1063
1064 /* Only process alarms that are not masked */
1065 isr0 &= ~((ams->intr_mask & AMS_ISR0_ALARM_MASK) | ams->current_masked_alarm);
1066 if (!isr0) {
1067 spin_unlock(&ams->intr_lock);
1068 return IRQ_NONE;
1069 }
1070
1071 /* Clear interrupt */
1072 writel(isr0, ams->base + AMS_ISR_0);
1073
1074 /* Mask the alarm interrupts until cleared */
1075 ams->current_masked_alarm |= isr0;
1076 ams_update_intrmask(ams, ~AMS_ALARM_MASK, ~AMS_ALARM_MASK);
1077
1078 ams_handle_events(indio_dev, isr0);
1079
1080 schedule_delayed_work(&ams->ams_unmask_work,
1081 msecs_to_jiffies(AMS_UNMASK_TIMEOUT_MS));
1082
1083 spin_unlock(&ams->intr_lock);
1084
1085 return IRQ_HANDLED;
1086 }
1087
1088 static const struct iio_event_spec ams_temp_events[] = {
1089 {
1090 .type = IIO_EV_TYPE_THRESH,
1091 .dir = IIO_EV_DIR_RISING,
1092 .mask_separate = BIT(IIO_EV_INFO_ENABLE) | BIT(IIO_EV_INFO_VALUE),
1093 },
1094 };
1095
1096 static const struct iio_event_spec ams_voltage_events[] = {
1097 {
1098 .type = IIO_EV_TYPE_THRESH,
1099 .dir = IIO_EV_DIR_RISING,
1100 .mask_separate = BIT(IIO_EV_INFO_VALUE),
1101 },
1102 {
1103 .type = IIO_EV_TYPE_THRESH,
1104 .dir = IIO_EV_DIR_FALLING,
1105 .mask_separate = BIT(IIO_EV_INFO_VALUE),
1106 },
1107 {
1108 .type = IIO_EV_TYPE_THRESH,
1109 .dir = IIO_EV_DIR_EITHER,
1110 .mask_separate = BIT(IIO_EV_INFO_ENABLE),
1111 },
1112 };
1113
1114 static const struct iio_chan_spec ams_ps_channels[] = {
1115 AMS_PS_CHAN_TEMP(AMS_SEQ_TEMP, AMS_TEMP),
1116 AMS_PS_CHAN_TEMP(AMS_SEQ_TEMP_REMOTE, AMS_TEMP_REMOTE),
1117 AMS_PS_CHAN_VOLTAGE(AMS_SEQ_SUPPLY1, AMS_SUPPLY1),
1118 AMS_PS_CHAN_VOLTAGE(AMS_SEQ_SUPPLY2, AMS_SUPPLY2),
1119 AMS_PS_CHAN_VOLTAGE(AMS_SEQ_SUPPLY3, AMS_SUPPLY3),
1120 AMS_PS_CHAN_VOLTAGE(AMS_SEQ_SUPPLY4, AMS_SUPPLY4),
1121 AMS_PS_CHAN_VOLTAGE(AMS_SEQ_SUPPLY5, AMS_SUPPLY5),
1122 AMS_PS_CHAN_VOLTAGE(AMS_SEQ_SUPPLY6, AMS_SUPPLY6),
1123 AMS_PS_CHAN_VOLTAGE(AMS_SEQ_SUPPLY7, AMS_SUPPLY7),
1124 AMS_PS_CHAN_VOLTAGE(AMS_SEQ_SUPPLY8, AMS_SUPPLY8),
1125 AMS_PS_CHAN_VOLTAGE(AMS_SEQ_SUPPLY9, AMS_SUPPLY9),
1126 AMS_PS_CHAN_VOLTAGE(AMS_SEQ_SUPPLY10, AMS_SUPPLY10),
1127 AMS_PS_CHAN_VOLTAGE(AMS_SEQ_VCCAMS, AMS_VCCAMS),
1128 };
1129
1130 static const struct iio_chan_spec ams_pl_channels[] = {
1131 AMS_PL_CHAN_TEMP(AMS_SEQ_TEMP, AMS_TEMP),
1132 AMS_PL_CHAN_VOLTAGE(AMS_SEQ_SUPPLY1, AMS_SUPPLY1, true),
1133 AMS_PL_CHAN_VOLTAGE(AMS_SEQ_SUPPLY2, AMS_SUPPLY2, true),
1134 AMS_PL_CHAN_VOLTAGE(AMS_SEQ_VREFP, AMS_VREFP, false),
1135 AMS_PL_CHAN_VOLTAGE(AMS_SEQ_VREFN, AMS_VREFN, false),
1136 AMS_PL_CHAN_VOLTAGE(AMS_SEQ_SUPPLY3, AMS_SUPPLY3, true),
1137 AMS_PL_CHAN_VOLTAGE(AMS_SEQ_SUPPLY4, AMS_SUPPLY4, true),
1138 AMS_PL_CHAN_VOLTAGE(AMS_SEQ_SUPPLY5, AMS_SUPPLY5, true),
1139 AMS_PL_CHAN_VOLTAGE(AMS_SEQ_SUPPLY6, AMS_SUPPLY6, true),
1140 AMS_PL_CHAN_VOLTAGE(AMS_SEQ_VCCAMS, AMS_VCCAMS, true),
1141 AMS_PL_CHAN_VOLTAGE(AMS_SEQ_VP_VN, AMS_VP_VN, false),
1142 AMS_PL_CHAN_VOLTAGE(AMS_SEQ_SUPPLY7, AMS_SUPPLY7, true),
1143 AMS_PL_CHAN_VOLTAGE(AMS_SEQ_SUPPLY8, AMS_SUPPLY8, true),
1144 AMS_PL_CHAN_VOLTAGE(AMS_SEQ_SUPPLY9, AMS_SUPPLY9, true),
1145 AMS_PL_CHAN_VOLTAGE(AMS_SEQ_SUPPLY10, AMS_SUPPLY10, true),
1146 AMS_PL_AUX_CHAN_VOLTAGE(0),
1147 AMS_PL_AUX_CHAN_VOLTAGE(1),
1148 AMS_PL_AUX_CHAN_VOLTAGE(2),
1149 AMS_PL_AUX_CHAN_VOLTAGE(3),
1150 AMS_PL_AUX_CHAN_VOLTAGE(4),
1151 AMS_PL_AUX_CHAN_VOLTAGE(5),
1152 AMS_PL_AUX_CHAN_VOLTAGE(6),
1153 AMS_PL_AUX_CHAN_VOLTAGE(7),
1154 AMS_PL_AUX_CHAN_VOLTAGE(8),
1155 AMS_PL_AUX_CHAN_VOLTAGE(9),
1156 AMS_PL_AUX_CHAN_VOLTAGE(10),
1157 AMS_PL_AUX_CHAN_VOLTAGE(11),
1158 AMS_PL_AUX_CHAN_VOLTAGE(12),
1159 AMS_PL_AUX_CHAN_VOLTAGE(13),
1160 AMS_PL_AUX_CHAN_VOLTAGE(14),
1161 AMS_PL_AUX_CHAN_VOLTAGE(15),
1162 };
1163
1164 static const struct iio_chan_spec ams_ctrl_channels[] = {
1165 AMS_CTRL_CHAN_VOLTAGE(AMS_SEQ_VCC_PSPLL, AMS_VCC_PSPLL0),
1166 AMS_CTRL_CHAN_VOLTAGE(AMS_SEQ_VCC_PSBATT, AMS_VCC_PSPLL3),
1167 AMS_CTRL_CHAN_VOLTAGE(AMS_SEQ_VCCINT, AMS_VCCINT),
1168 AMS_CTRL_CHAN_VOLTAGE(AMS_SEQ_VCCBRAM, AMS_VCCBRAM),
1169 AMS_CTRL_CHAN_VOLTAGE(AMS_SEQ_VCCAUX, AMS_VCCAUX),
1170 AMS_CTRL_CHAN_VOLTAGE(AMS_SEQ_PSDDRPLL, AMS_PSDDRPLL),
1171 AMS_CTRL_CHAN_VOLTAGE(AMS_SEQ_INTDDR, AMS_PSINTFPDDR),
1172 };
1173
ams_get_ext_chan(struct fwnode_handle * chan_node,struct iio_chan_spec * channels,int num_channels)1174 static int ams_get_ext_chan(struct fwnode_handle *chan_node,
1175 struct iio_chan_spec *channels, int num_channels)
1176 {
1177 struct iio_chan_spec *chan;
1178 struct fwnode_handle *child;
1179 unsigned int reg, ext_chan;
1180 int ret;
1181
1182 fwnode_for_each_child_node(chan_node, child) {
1183 ret = fwnode_property_read_u32(child, "reg", ®);
1184 if (ret || reg > AMS_PL_MAX_EXT_CHANNEL + 30)
1185 continue;
1186
1187 chan = &channels[num_channels];
1188 ext_chan = reg + AMS_PL_MAX_FIXED_CHANNEL - 30;
1189 memcpy(chan, &ams_pl_channels[ext_chan], sizeof(*channels));
1190
1191 if (fwnode_property_read_bool(child, "xlnx,bipolar"))
1192 chan->scan_type.sign = 's';
1193
1194 num_channels++;
1195 }
1196
1197 return num_channels;
1198 }
1199
ams_iounmap_ps(void * data)1200 static void ams_iounmap_ps(void *data)
1201 {
1202 struct ams *ams = data;
1203
1204 iounmap(ams->ps_base);
1205 }
1206
ams_iounmap_pl(void * data)1207 static void ams_iounmap_pl(void *data)
1208 {
1209 struct ams *ams = data;
1210
1211 iounmap(ams->pl_base);
1212 }
1213
ams_init_module(struct iio_dev * indio_dev,struct fwnode_handle * fwnode,struct iio_chan_spec * channels)1214 static int ams_init_module(struct iio_dev *indio_dev,
1215 struct fwnode_handle *fwnode,
1216 struct iio_chan_spec *channels)
1217 {
1218 struct device *dev = indio_dev->dev.parent;
1219 struct ams *ams = iio_priv(indio_dev);
1220 int num_channels = 0;
1221 int ret;
1222
1223 if (fwnode_device_is_compatible(fwnode, "xlnx,zynqmp-ams-ps")) {
1224 ams->ps_base = fwnode_iomap(fwnode, 0);
1225 if (!ams->ps_base)
1226 return -ENXIO;
1227 ret = devm_add_action_or_reset(dev, ams_iounmap_ps, ams);
1228 if (ret < 0)
1229 return ret;
1230
1231 /* add PS channels to iio device channels */
1232 memcpy(channels, ams_ps_channels, sizeof(ams_ps_channels));
1233 num_channels = ARRAY_SIZE(ams_ps_channels);
1234 } else if (fwnode_device_is_compatible(fwnode, "xlnx,zynqmp-ams-pl")) {
1235 ams->pl_base = fwnode_iomap(fwnode, 0);
1236 if (!ams->pl_base)
1237 return -ENXIO;
1238
1239 ret = devm_add_action_or_reset(dev, ams_iounmap_pl, ams);
1240 if (ret < 0)
1241 return ret;
1242
1243 /* Copy only first 10 fix channels */
1244 memcpy(channels, ams_pl_channels, AMS_PL_MAX_FIXED_CHANNEL * sizeof(*channels));
1245 num_channels += AMS_PL_MAX_FIXED_CHANNEL;
1246 num_channels = ams_get_ext_chan(fwnode, channels,
1247 num_channels);
1248 } else if (fwnode_device_is_compatible(fwnode, "xlnx,zynqmp-ams")) {
1249 /* add AMS channels to iio device channels */
1250 memcpy(channels, ams_ctrl_channels, sizeof(ams_ctrl_channels));
1251 num_channels += ARRAY_SIZE(ams_ctrl_channels);
1252 } else {
1253 return -EINVAL;
1254 }
1255
1256 return num_channels;
1257 }
1258
ams_parse_firmware(struct iio_dev * indio_dev)1259 static int ams_parse_firmware(struct iio_dev *indio_dev)
1260 {
1261 struct ams *ams = iio_priv(indio_dev);
1262 struct iio_chan_spec *ams_channels, *dev_channels;
1263 struct device *dev = indio_dev->dev.parent;
1264 struct fwnode_handle *child = NULL;
1265 struct fwnode_handle *fwnode = dev_fwnode(dev);
1266 size_t ams_size;
1267 int ret, ch_cnt = 0, i, rising_off, falling_off;
1268 unsigned int num_channels = 0;
1269
1270 ams_size = ARRAY_SIZE(ams_ps_channels) + ARRAY_SIZE(ams_pl_channels) +
1271 ARRAY_SIZE(ams_ctrl_channels);
1272
1273 /* Initialize buffer for channel specification */
1274 ams_channels = devm_kcalloc(dev, ams_size, sizeof(*ams_channels), GFP_KERNEL);
1275 if (!ams_channels)
1276 return -ENOMEM;
1277
1278 if (fwnode_device_is_available(fwnode)) {
1279 ret = ams_init_module(indio_dev, fwnode, ams_channels);
1280 if (ret < 0)
1281 return ret;
1282
1283 num_channels += ret;
1284 }
1285
1286 fwnode_for_each_child_node(fwnode, child) {
1287 if (fwnode_device_is_available(child)) {
1288 ret = ams_init_module(indio_dev, child, ams_channels + num_channels);
1289 if (ret < 0) {
1290 fwnode_handle_put(child);
1291 return ret;
1292 }
1293
1294 num_channels += ret;
1295 }
1296 }
1297
1298 for (i = 0; i < num_channels; i++) {
1299 ams_channels[i].channel = ch_cnt++;
1300
1301 if (ams_channels[i].scan_index < AMS_CTRL_SEQ_BASE) {
1302 /* set threshold to max and min for each channel */
1303 falling_off =
1304 ams_get_alarm_offset(ams_channels[i].scan_index,
1305 IIO_EV_DIR_FALLING);
1306 rising_off =
1307 ams_get_alarm_offset(ams_channels[i].scan_index,
1308 IIO_EV_DIR_RISING);
1309 if (ams_channels[i].scan_index >= AMS_PS_SEQ_MAX) {
1310 writel(AMS_ALARM_THR_MIN,
1311 ams->pl_base + falling_off);
1312 writel(AMS_ALARM_THR_MAX,
1313 ams->pl_base + rising_off);
1314 } else {
1315 writel(AMS_ALARM_THR_MIN,
1316 ams->ps_base + falling_off);
1317 writel(AMS_ALARM_THR_MAX,
1318 ams->ps_base + rising_off);
1319 }
1320 }
1321 }
1322
1323 dev_channels = devm_krealloc_array(dev, ams_channels, num_channels,
1324 sizeof(*dev_channels), GFP_KERNEL);
1325 if (!dev_channels)
1326 return -ENOMEM;
1327
1328 indio_dev->channels = dev_channels;
1329 indio_dev->num_channels = num_channels;
1330
1331 return 0;
1332 }
1333
1334 static const struct iio_info iio_ams_info = {
1335 .read_raw = &ams_read_raw,
1336 .read_event_config = &ams_read_event_config,
1337 .write_event_config = &ams_write_event_config,
1338 .read_event_value = &ams_read_event_value,
1339 .write_event_value = &ams_write_event_value,
1340 };
1341
1342 static const struct of_device_id ams_of_match_table[] = {
1343 { .compatible = "xlnx,zynqmp-ams" },
1344 { }
1345 };
1346 MODULE_DEVICE_TABLE(of, ams_of_match_table);
1347
ams_probe(struct platform_device * pdev)1348 static int ams_probe(struct platform_device *pdev)
1349 {
1350 struct iio_dev *indio_dev;
1351 struct ams *ams;
1352 int ret;
1353 int irq;
1354
1355 indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*ams));
1356 if (!indio_dev)
1357 return -ENOMEM;
1358
1359 ams = iio_priv(indio_dev);
1360 mutex_init(&ams->lock);
1361 spin_lock_init(&ams->intr_lock);
1362
1363 indio_dev->name = "xilinx-ams";
1364
1365 indio_dev->info = &iio_ams_info;
1366 indio_dev->modes = INDIO_DIRECT_MODE;
1367
1368 ams->base = devm_platform_ioremap_resource(pdev, 0);
1369 if (IS_ERR(ams->base))
1370 return PTR_ERR(ams->base);
1371
1372 ams->clk = devm_clk_get_enabled(&pdev->dev, NULL);
1373 if (IS_ERR(ams->clk))
1374 return PTR_ERR(ams->clk);
1375
1376 ret = devm_delayed_work_autocancel(&pdev->dev, &ams->ams_unmask_work,
1377 ams_unmask_worker);
1378 if (ret < 0)
1379 return ret;
1380
1381 ret = ams_parse_firmware(indio_dev);
1382 if (ret)
1383 return dev_err_probe(&pdev->dev, ret, "failure in parsing DT\n");
1384
1385 ret = ams_init_device(ams);
1386 if (ret)
1387 return dev_err_probe(&pdev->dev, ret, "failed to initialize AMS\n");
1388
1389 ams_enable_channel_sequence(indio_dev);
1390
1391 irq = platform_get_irq(pdev, 0);
1392 if (irq < 0)
1393 return irq;
1394
1395 ret = devm_request_irq(&pdev->dev, irq, &ams_irq, 0, "ams-irq",
1396 indio_dev);
1397 if (ret < 0)
1398 return dev_err_probe(&pdev->dev, ret, "failed to register interrupt\n");
1399
1400 platform_set_drvdata(pdev, indio_dev);
1401
1402 return devm_iio_device_register(&pdev->dev, indio_dev);
1403 }
1404
ams_suspend(struct device * dev)1405 static int ams_suspend(struct device *dev)
1406 {
1407 struct ams *ams = iio_priv(dev_get_drvdata(dev));
1408
1409 clk_disable_unprepare(ams->clk);
1410
1411 return 0;
1412 }
1413
ams_resume(struct device * dev)1414 static int ams_resume(struct device *dev)
1415 {
1416 struct ams *ams = iio_priv(dev_get_drvdata(dev));
1417
1418 return clk_prepare_enable(ams->clk);
1419 }
1420
1421 static DEFINE_SIMPLE_DEV_PM_OPS(ams_pm_ops, ams_suspend, ams_resume);
1422
1423 static struct platform_driver ams_driver = {
1424 .probe = ams_probe,
1425 .driver = {
1426 .name = "xilinx-ams",
1427 .pm = pm_sleep_ptr(&ams_pm_ops),
1428 .of_match_table = ams_of_match_table,
1429 },
1430 };
1431 module_platform_driver(ams_driver);
1432
1433 MODULE_LICENSE("GPL v2");
1434 MODULE_AUTHOR("Xilinx, Inc.");
1435
