1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Driver for Microchip MCP3911, Two-channel Analog Front End
4 *
5 * Copyright (C) 2018 Marcus Folkesson <marcus.folkesson@gmail.com>
6 * Copyright (C) 2018 Kent Gustavsson <kent@minoris.se>
7 */
8 #include <linux/bitfield.h>
9 #include <linux/bits.h>
10 #include <linux/clk.h>
11 #include <linux/delay.h>
12 #include <linux/err.h>
13 #include <linux/module.h>
14 #include <linux/mod_devicetable.h>
15 #include <linux/property.h>
16 #include <linux/regulator/consumer.h>
17 #include <linux/spi/spi.h>
18
19 #include <linux/iio/iio.h>
20 #include <linux/iio/buffer.h>
21 #include <linux/iio/triggered_buffer.h>
22 #include <linux/iio/trigger_consumer.h>
23 #include <linux/iio/trigger.h>
24
25 #include <asm/unaligned.h>
26
27 #define MCP3911_REG_CHANNEL0 0x00
28 #define MCP3911_REG_CHANNEL1 0x03
29 #define MCP3911_REG_MOD 0x06
30 #define MCP3911_REG_PHASE 0x07
31 #define MCP3911_REG_GAIN 0x09
32
33 #define MCP3911_REG_STATUSCOM 0x0a
34 #define MCP3911_STATUSCOM_DRHIZ BIT(12)
35 #define MCP3911_STATUSCOM_READ GENMASK(7, 6)
36 #define MCP3911_STATUSCOM_CH1_24WIDTH BIT(4)
37 #define MCP3911_STATUSCOM_CH0_24WIDTH BIT(3)
38 #define MCP3911_STATUSCOM_EN_OFFCAL BIT(2)
39 #define MCP3911_STATUSCOM_EN_GAINCAL BIT(1)
40
41 #define MCP3911_REG_CONFIG 0x0c
42 #define MCP3911_CONFIG_CLKEXT BIT(1)
43 #define MCP3911_CONFIG_VREFEXT BIT(2)
44 #define MCP3911_CONFIG_OSR GENMASK(13, 11)
45
46 #define MCP3911_REG_OFFCAL_CH0 0x0e
47 #define MCP3911_REG_GAINCAL_CH0 0x11
48 #define MCP3911_REG_OFFCAL_CH1 0x14
49 #define MCP3911_REG_GAINCAL_CH1 0x17
50 #define MCP3911_REG_VREFCAL 0x1a
51
52 #define MCP3911_CHANNEL(x) (MCP3911_REG_CHANNEL0 + x * 3)
53 #define MCP3911_OFFCAL(x) (MCP3911_REG_OFFCAL_CH0 + x * 6)
54
55 /* Internal voltage reference in mV */
56 #define MCP3911_INT_VREF_MV 1200
57
58 #define MCP3911_REG_READ(reg, id) ((((reg) << 1) | ((id) << 6) | (1 << 0)) & 0xff)
59 #define MCP3911_REG_WRITE(reg, id) ((((reg) << 1) | ((id) << 6) | (0 << 0)) & 0xff)
60 #define MCP3911_REG_MASK GENMASK(4, 1)
61
62 #define MCP3911_NUM_CHANNELS 2
63
64 static const int mcp3911_osr_table[] = { 32, 64, 128, 256, 512, 1024, 2048, 4096 };
65
66 struct mcp3911 {
67 struct spi_device *spi;
68 struct mutex lock;
69 struct regulator *vref;
70 struct clk *clki;
71 u32 dev_addr;
72 struct iio_trigger *trig;
73 struct {
74 u32 channels[MCP3911_NUM_CHANNELS];
75 s64 ts __aligned(8);
76 } scan;
77
78 u8 tx_buf __aligned(IIO_DMA_MINALIGN);
79 u8 rx_buf[MCP3911_NUM_CHANNELS * 3];
80 };
81
mcp3911_read(struct mcp3911 * adc,u8 reg,u32 * val,u8 len)82 static int mcp3911_read(struct mcp3911 *adc, u8 reg, u32 *val, u8 len)
83 {
84 int ret;
85
86 reg = MCP3911_REG_READ(reg, adc->dev_addr);
87 ret = spi_write_then_read(adc->spi, ®, 1, val, len);
88 if (ret < 0)
89 return ret;
90
91 be32_to_cpus(val);
92 *val >>= ((4 - len) * 8);
93 dev_dbg(&adc->spi->dev, "reading 0x%x from register 0x%lx\n", *val,
94 FIELD_GET(MCP3911_REG_MASK, reg));
95 return ret;
96 }
97
mcp3911_write(struct mcp3911 * adc,u8 reg,u32 val,u8 len)98 static int mcp3911_write(struct mcp3911 *adc, u8 reg, u32 val, u8 len)
99 {
100 dev_dbg(&adc->spi->dev, "writing 0x%x to register 0x%x\n", val, reg);
101
102 val <<= (3 - len) * 8;
103 cpu_to_be32s(&val);
104 val |= MCP3911_REG_WRITE(reg, adc->dev_addr);
105
106 return spi_write(adc->spi, &val, len + 1);
107 }
108
mcp3911_update(struct mcp3911 * adc,u8 reg,u32 mask,u32 val,u8 len)109 static int mcp3911_update(struct mcp3911 *adc, u8 reg, u32 mask,
110 u32 val, u8 len)
111 {
112 u32 tmp;
113 int ret;
114
115 ret = mcp3911_read(adc, reg, &tmp, len);
116 if (ret)
117 return ret;
118
119 val &= mask;
120 val |= tmp & ~mask;
121 return mcp3911_write(adc, reg, val, len);
122 }
123
mcp3911_write_raw_get_fmt(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,long mask)124 static int mcp3911_write_raw_get_fmt(struct iio_dev *indio_dev,
125 struct iio_chan_spec const *chan,
126 long mask)
127 {
128 switch (mask) {
129 case IIO_CHAN_INFO_SCALE:
130 return IIO_VAL_INT_PLUS_NANO;
131 case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
132 return IIO_VAL_INT;
133 default:
134 return IIO_VAL_INT_PLUS_NANO;
135 }
136 }
137
mcp3911_read_avail(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,const int ** vals,int * type,int * length,long info)138 static int mcp3911_read_avail(struct iio_dev *indio_dev,
139 struct iio_chan_spec const *chan,
140 const int **vals, int *type, int *length,
141 long info)
142 {
143 switch (info) {
144 case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
145 *type = IIO_VAL_INT;
146 *vals = mcp3911_osr_table;
147 *length = ARRAY_SIZE(mcp3911_osr_table);
148 return IIO_AVAIL_LIST;
149 default:
150 return -EINVAL;
151 }
152 }
153
mcp3911_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * channel,int * val,int * val2,long mask)154 static int mcp3911_read_raw(struct iio_dev *indio_dev,
155 struct iio_chan_spec const *channel, int *val,
156 int *val2, long mask)
157 {
158 struct mcp3911 *adc = iio_priv(indio_dev);
159 int ret = -EINVAL;
160
161 mutex_lock(&adc->lock);
162 switch (mask) {
163 case IIO_CHAN_INFO_RAW:
164 ret = mcp3911_read(adc,
165 MCP3911_CHANNEL(channel->channel), val, 3);
166 if (ret)
167 goto out;
168
169 *val = sign_extend32(*val, 23);
170
171 ret = IIO_VAL_INT;
172 break;
173
174 case IIO_CHAN_INFO_OFFSET:
175 ret = mcp3911_read(adc,
176 MCP3911_OFFCAL(channel->channel), val, 3);
177 if (ret)
178 goto out;
179
180 ret = IIO_VAL_INT;
181 break;
182 case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
183 ret = mcp3911_read(adc, MCP3911_REG_CONFIG, val, 2);
184 if (ret)
185 goto out;
186
187 *val = FIELD_GET(MCP3911_CONFIG_OSR, *val);
188 *val = 32 << *val;
189 ret = IIO_VAL_INT;
190 break;
191
192 case IIO_CHAN_INFO_SCALE:
193 if (adc->vref) {
194 ret = regulator_get_voltage(adc->vref);
195 if (ret < 0) {
196 dev_err(indio_dev->dev.parent,
197 "failed to get vref voltage: %d\n",
198 ret);
199 goto out;
200 }
201
202 *val = ret / 1000;
203 } else {
204 *val = MCP3911_INT_VREF_MV;
205 }
206
207 /*
208 * For 24bit Conversion
209 * Raw = ((Voltage)/(Vref) * 2^23 * Gain * 1.5
210 * Voltage = Raw * (Vref)/(2^23 * Gain * 1.5)
211 */
212
213 /* val2 = (2^23 * 1.5) */
214 *val2 = 12582912;
215 ret = IIO_VAL_FRACTIONAL;
216 break;
217 }
218
219 out:
220 mutex_unlock(&adc->lock);
221 return ret;
222 }
223
mcp3911_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * channel,int val,int val2,long mask)224 static int mcp3911_write_raw(struct iio_dev *indio_dev,
225 struct iio_chan_spec const *channel, int val,
226 int val2, long mask)
227 {
228 struct mcp3911 *adc = iio_priv(indio_dev);
229 int ret = -EINVAL;
230
231 mutex_lock(&adc->lock);
232 switch (mask) {
233 case IIO_CHAN_INFO_OFFSET:
234 if (val2 != 0) {
235 ret = -EINVAL;
236 goto out;
237 }
238
239 /* Write offset */
240 ret = mcp3911_write(adc, MCP3911_OFFCAL(channel->channel), val,
241 3);
242 if (ret)
243 goto out;
244
245 /* Enable offset*/
246 ret = mcp3911_update(adc, MCP3911_REG_STATUSCOM,
247 MCP3911_STATUSCOM_EN_OFFCAL,
248 MCP3911_STATUSCOM_EN_OFFCAL, 2);
249 break;
250
251 case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
252 for (int i = 0; i < ARRAY_SIZE(mcp3911_osr_table); i++) {
253 if (val == mcp3911_osr_table[i]) {
254 val = FIELD_PREP(MCP3911_CONFIG_OSR, i);
255 ret = mcp3911_update(adc, MCP3911_REG_CONFIG, MCP3911_CONFIG_OSR,
256 val, 2);
257 break;
258 }
259 }
260 break;
261 }
262
263 out:
264 mutex_unlock(&adc->lock);
265 return ret;
266 }
267
268 #define MCP3911_CHAN(idx) { \
269 .type = IIO_VOLTAGE, \
270 .indexed = 1, \
271 .channel = idx, \
272 .scan_index = idx, \
273 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \
274 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
275 BIT(IIO_CHAN_INFO_OFFSET) | \
276 BIT(IIO_CHAN_INFO_SCALE), \
277 .info_mask_shared_by_type_available = \
278 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \
279 .scan_type = { \
280 .sign = 's', \
281 .realbits = 24, \
282 .storagebits = 32, \
283 .endianness = IIO_BE, \
284 }, \
285 }
286
287 static const struct iio_chan_spec mcp3911_channels[] = {
288 MCP3911_CHAN(0),
289 MCP3911_CHAN(1),
290 IIO_CHAN_SOFT_TIMESTAMP(2),
291 };
292
mcp3911_trigger_handler(int irq,void * p)293 static irqreturn_t mcp3911_trigger_handler(int irq, void *p)
294 {
295 struct iio_poll_func *pf = p;
296 struct iio_dev *indio_dev = pf->indio_dev;
297 struct mcp3911 *adc = iio_priv(indio_dev);
298 struct spi_transfer xfer[] = {
299 {
300 .tx_buf = &adc->tx_buf,
301 .len = 1,
302 }, {
303 .rx_buf = adc->rx_buf,
304 .len = sizeof(adc->rx_buf),
305 },
306 };
307 int scan_index;
308 int i = 0;
309 int ret;
310
311 mutex_lock(&adc->lock);
312 adc->tx_buf = MCP3911_REG_READ(MCP3911_CHANNEL(0), adc->dev_addr);
313 ret = spi_sync_transfer(adc->spi, xfer, ARRAY_SIZE(xfer));
314 if (ret < 0) {
315 dev_warn(&adc->spi->dev,
316 "failed to get conversion data\n");
317 goto out;
318 }
319
320 for_each_set_bit(scan_index, indio_dev->active_scan_mask, indio_dev->masklength) {
321 const struct iio_chan_spec *scan_chan = &indio_dev->channels[scan_index];
322
323 adc->scan.channels[i] = get_unaligned_be24(&adc->rx_buf[scan_chan->channel * 3]);
324 i++;
325 }
326 iio_push_to_buffers_with_timestamp(indio_dev, &adc->scan,
327 iio_get_time_ns(indio_dev));
328 out:
329 mutex_unlock(&adc->lock);
330 iio_trigger_notify_done(indio_dev->trig);
331
332 return IRQ_HANDLED;
333 }
334
335 static const struct iio_info mcp3911_info = {
336 .read_raw = mcp3911_read_raw,
337 .write_raw = mcp3911_write_raw,
338 .read_avail = mcp3911_read_avail,
339 .write_raw_get_fmt = mcp3911_write_raw_get_fmt,
340 };
341
mcp3911_config(struct mcp3911 * adc)342 static int mcp3911_config(struct mcp3911 *adc)
343 {
344 struct device *dev = &adc->spi->dev;
345 u32 regval;
346 int ret;
347
348 ret = device_property_read_u32(dev, "microchip,device-addr", &adc->dev_addr);
349
350 /*
351 * Fallback to "device-addr" due to historical mismatch between
352 * dt-bindings and implementation
353 */
354 if (ret)
355 device_property_read_u32(dev, "device-addr", &adc->dev_addr);
356 if (adc->dev_addr > 3) {
357 dev_err(&adc->spi->dev,
358 "invalid device address (%i). Must be in range 0-3.\n",
359 adc->dev_addr);
360 return -EINVAL;
361 }
362 dev_dbg(&adc->spi->dev, "use device address %i\n", adc->dev_addr);
363
364 ret = mcp3911_read(adc, MCP3911_REG_CONFIG, ®val, 2);
365 if (ret)
366 return ret;
367
368 regval &= ~MCP3911_CONFIG_VREFEXT;
369 if (adc->vref) {
370 dev_dbg(&adc->spi->dev, "use external voltage reference\n");
371 regval |= FIELD_PREP(MCP3911_CONFIG_VREFEXT, 1);
372 } else {
373 dev_dbg(&adc->spi->dev,
374 "use internal voltage reference (1.2V)\n");
375 regval |= FIELD_PREP(MCP3911_CONFIG_VREFEXT, 0);
376 }
377
378 regval &= ~MCP3911_CONFIG_CLKEXT;
379 if (adc->clki) {
380 dev_dbg(&adc->spi->dev, "use external clock as clocksource\n");
381 regval |= FIELD_PREP(MCP3911_CONFIG_CLKEXT, 1);
382 } else {
383 dev_dbg(&adc->spi->dev,
384 "use crystal oscillator as clocksource\n");
385 regval |= FIELD_PREP(MCP3911_CONFIG_CLKEXT, 0);
386 }
387
388 ret = mcp3911_write(adc, MCP3911_REG_CONFIG, regval, 2);
389 if (ret)
390 return ret;
391
392 ret = mcp3911_read(adc, MCP3911_REG_STATUSCOM, ®val, 2);
393 if (ret)
394 return ret;
395
396 /* Address counter incremented, cycle through register types */
397 regval &= ~MCP3911_STATUSCOM_READ;
398 regval |= FIELD_PREP(MCP3911_STATUSCOM_READ, 0x02);
399
400 return mcp3911_write(adc, MCP3911_REG_STATUSCOM, regval, 2);
401 }
402
mcp3911_cleanup_regulator(void * vref)403 static void mcp3911_cleanup_regulator(void *vref)
404 {
405 regulator_disable(vref);
406 }
407
mcp3911_set_trigger_state(struct iio_trigger * trig,bool enable)408 static int mcp3911_set_trigger_state(struct iio_trigger *trig, bool enable)
409 {
410 struct mcp3911 *adc = iio_trigger_get_drvdata(trig);
411
412 if (enable)
413 enable_irq(adc->spi->irq);
414 else
415 disable_irq(adc->spi->irq);
416
417 return 0;
418 }
419
420 static const struct iio_trigger_ops mcp3911_trigger_ops = {
421 .validate_device = iio_trigger_validate_own_device,
422 .set_trigger_state = mcp3911_set_trigger_state,
423 };
424
mcp3911_probe(struct spi_device * spi)425 static int mcp3911_probe(struct spi_device *spi)
426 {
427 struct iio_dev *indio_dev;
428 struct mcp3911 *adc;
429 int ret;
430
431 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*adc));
432 if (!indio_dev)
433 return -ENOMEM;
434
435 adc = iio_priv(indio_dev);
436 adc->spi = spi;
437
438 adc->vref = devm_regulator_get_optional(&adc->spi->dev, "vref");
439 if (IS_ERR(adc->vref)) {
440 if (PTR_ERR(adc->vref) == -ENODEV) {
441 adc->vref = NULL;
442 } else {
443 dev_err(&adc->spi->dev,
444 "failed to get regulator (%ld)\n",
445 PTR_ERR(adc->vref));
446 return PTR_ERR(adc->vref);
447 }
448
449 } else {
450 ret = regulator_enable(adc->vref);
451 if (ret)
452 return ret;
453
454 ret = devm_add_action_or_reset(&spi->dev,
455 mcp3911_cleanup_regulator, adc->vref);
456 if (ret)
457 return ret;
458 }
459
460 adc->clki = devm_clk_get_enabled(&adc->spi->dev, NULL);
461 if (IS_ERR(adc->clki)) {
462 if (PTR_ERR(adc->clki) == -ENOENT) {
463 adc->clki = NULL;
464 } else {
465 dev_err(&adc->spi->dev,
466 "failed to get adc clk (%ld)\n",
467 PTR_ERR(adc->clki));
468 return PTR_ERR(adc->clki);
469 }
470 }
471
472 ret = mcp3911_config(adc);
473 if (ret)
474 return ret;
475
476 if (device_property_read_bool(&adc->spi->dev, "microchip,data-ready-hiz"))
477 ret = mcp3911_update(adc, MCP3911_REG_STATUSCOM, MCP3911_STATUSCOM_DRHIZ,
478 0, 2);
479 else
480 ret = mcp3911_update(adc, MCP3911_REG_STATUSCOM, MCP3911_STATUSCOM_DRHIZ,
481 MCP3911_STATUSCOM_DRHIZ, 2);
482 if (ret)
483 return ret;
484
485 indio_dev->name = spi_get_device_id(spi)->name;
486 indio_dev->modes = INDIO_DIRECT_MODE;
487 indio_dev->info = &mcp3911_info;
488 spi_set_drvdata(spi, indio_dev);
489
490 indio_dev->channels = mcp3911_channels;
491 indio_dev->num_channels = ARRAY_SIZE(mcp3911_channels);
492
493 mutex_init(&adc->lock);
494
495 if (spi->irq > 0) {
496 adc->trig = devm_iio_trigger_alloc(&spi->dev, "%s-dev%d",
497 indio_dev->name,
498 iio_device_id(indio_dev));
499 if (!adc->trig)
500 return -ENOMEM;
501
502 adc->trig->ops = &mcp3911_trigger_ops;
503 iio_trigger_set_drvdata(adc->trig, adc);
504 ret = devm_iio_trigger_register(&spi->dev, adc->trig);
505 if (ret)
506 return ret;
507
508 /*
509 * The device generates interrupts as long as it is powered up.
510 * Some platforms might not allow the option to power it down so
511 * don't enable the interrupt to avoid extra load on the system.
512 */
513 ret = devm_request_irq(&spi->dev, spi->irq,
514 &iio_trigger_generic_data_rdy_poll, IRQF_NO_AUTOEN | IRQF_ONESHOT,
515 indio_dev->name, adc->trig);
516 if (ret)
517 return ret;
518 }
519
520 ret = devm_iio_triggered_buffer_setup(&spi->dev, indio_dev,
521 NULL,
522 mcp3911_trigger_handler, NULL);
523 if (ret)
524 return ret;
525
526 return devm_iio_device_register(&adc->spi->dev, indio_dev);
527 }
528
529 static const struct of_device_id mcp3911_dt_ids[] = {
530 { .compatible = "microchip,mcp3911" },
531 { }
532 };
533 MODULE_DEVICE_TABLE(of, mcp3911_dt_ids);
534
535 static const struct spi_device_id mcp3911_id[] = {
536 { "mcp3911", 0 },
537 { }
538 };
539 MODULE_DEVICE_TABLE(spi, mcp3911_id);
540
541 static struct spi_driver mcp3911_driver = {
542 .driver = {
543 .name = "mcp3911",
544 .of_match_table = mcp3911_dt_ids,
545 },
546 .probe = mcp3911_probe,
547 .id_table = mcp3911_id,
548 };
549 module_spi_driver(mcp3911_driver);
550
551 MODULE_AUTHOR("Marcus Folkesson <marcus.folkesson@gmail.com>");
552 MODULE_AUTHOR("Kent Gustavsson <kent@minoris.se>");
553 MODULE_DESCRIPTION("Microchip Technology MCP3911");
554 MODULE_LICENSE("GPL v2");
555
