1 /*
2 * Atmel ADC driver for SAMA5D2 devices and compatible.
3 *
4 * Copyright (C) 2015 Atmel,
5 * 2015 Ludovic Desroches <ludovic.desroches@atmel.com>
6 *
7 * This software is licensed under the terms of the GNU General Public
8 * License version 2, as published by the Free Software Foundation, and
9 * may be copied, distributed, and modified under those terms.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17 #include <linux/bitops.h>
18 #include <linux/clk.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/dmaengine.h>
21 #include <linux/interrupt.h>
22 #include <linux/io.h>
23 #include <linux/module.h>
24 #include <linux/of_device.h>
25 #include <linux/platform_device.h>
26 #include <linux/sched.h>
27 #include <linux/wait.h>
28 #include <linux/iio/iio.h>
29 #include <linux/iio/sysfs.h>
30 #include <linux/iio/buffer.h>
31 #include <linux/iio/trigger.h>
32 #include <linux/iio/trigger_consumer.h>
33 #include <linux/iio/triggered_buffer.h>
34 #include <linux/pinctrl/consumer.h>
35 #include <linux/regulator/consumer.h>
36
37 /* Control Register */
38 #define AT91_SAMA5D2_CR 0x00
39 /* Software Reset */
40 #define AT91_SAMA5D2_CR_SWRST BIT(0)
41 /* Start Conversion */
42 #define AT91_SAMA5D2_CR_START BIT(1)
43 /* Touchscreen Calibration */
44 #define AT91_SAMA5D2_CR_TSCALIB BIT(2)
45 /* Comparison Restart */
46 #define AT91_SAMA5D2_CR_CMPRST BIT(4)
47
48 /* Mode Register */
49 #define AT91_SAMA5D2_MR 0x04
50 /* Trigger Selection */
51 #define AT91_SAMA5D2_MR_TRGSEL(v) ((v) << 1)
52 /* ADTRG */
53 #define AT91_SAMA5D2_MR_TRGSEL_TRIG0 0
54 /* TIOA0 */
55 #define AT91_SAMA5D2_MR_TRGSEL_TRIG1 1
56 /* TIOA1 */
57 #define AT91_SAMA5D2_MR_TRGSEL_TRIG2 2
58 /* TIOA2 */
59 #define AT91_SAMA5D2_MR_TRGSEL_TRIG3 3
60 /* PWM event line 0 */
61 #define AT91_SAMA5D2_MR_TRGSEL_TRIG4 4
62 /* PWM event line 1 */
63 #define AT91_SAMA5D2_MR_TRGSEL_TRIG5 5
64 /* TIOA3 */
65 #define AT91_SAMA5D2_MR_TRGSEL_TRIG6 6
66 /* RTCOUT0 */
67 #define AT91_SAMA5D2_MR_TRGSEL_TRIG7 7
68 /* Sleep Mode */
69 #define AT91_SAMA5D2_MR_SLEEP BIT(5)
70 /* Fast Wake Up */
71 #define AT91_SAMA5D2_MR_FWUP BIT(6)
72 /* Prescaler Rate Selection */
73 #define AT91_SAMA5D2_MR_PRESCAL(v) ((v) << AT91_SAMA5D2_MR_PRESCAL_OFFSET)
74 #define AT91_SAMA5D2_MR_PRESCAL_OFFSET 8
75 #define AT91_SAMA5D2_MR_PRESCAL_MAX 0xff
76 #define AT91_SAMA5D2_MR_PRESCAL_MASK GENMASK(15, 8)
77 /* Startup Time */
78 #define AT91_SAMA5D2_MR_STARTUP(v) ((v) << 16)
79 #define AT91_SAMA5D2_MR_STARTUP_MASK GENMASK(19, 16)
80 /* Analog Change */
81 #define AT91_SAMA5D2_MR_ANACH BIT(23)
82 /* Tracking Time */
83 #define AT91_SAMA5D2_MR_TRACKTIM(v) ((v) << 24)
84 #define AT91_SAMA5D2_MR_TRACKTIM_MAX 0xff
85 /* Transfer Time */
86 #define AT91_SAMA5D2_MR_TRANSFER(v) ((v) << 28)
87 #define AT91_SAMA5D2_MR_TRANSFER_MAX 0x3
88 /* Use Sequence Enable */
89 #define AT91_SAMA5D2_MR_USEQ BIT(31)
90
91 /* Channel Sequence Register 1 */
92 #define AT91_SAMA5D2_SEQR1 0x08
93 /* Channel Sequence Register 2 */
94 #define AT91_SAMA5D2_SEQR2 0x0c
95 /* Channel Enable Register */
96 #define AT91_SAMA5D2_CHER 0x10
97 /* Channel Disable Register */
98 #define AT91_SAMA5D2_CHDR 0x14
99 /* Channel Status Register */
100 #define AT91_SAMA5D2_CHSR 0x18
101 /* Last Converted Data Register */
102 #define AT91_SAMA5D2_LCDR 0x20
103 /* Interrupt Enable Register */
104 #define AT91_SAMA5D2_IER 0x24
105 /* Interrupt Enable Register - TS X measurement ready */
106 #define AT91_SAMA5D2_IER_XRDY BIT(20)
107 /* Interrupt Enable Register - TS Y measurement ready */
108 #define AT91_SAMA5D2_IER_YRDY BIT(21)
109 /* Interrupt Enable Register - TS pressure measurement ready */
110 #define AT91_SAMA5D2_IER_PRDY BIT(22)
111 /* Interrupt Enable Register - general overrun error */
112 #define AT91_SAMA5D2_IER_GOVRE BIT(25)
113 /* Interrupt Enable Register - Pen detect */
114 #define AT91_SAMA5D2_IER_PEN BIT(29)
115 /* Interrupt Enable Register - No pen detect */
116 #define AT91_SAMA5D2_IER_NOPEN BIT(30)
117 /* Interrupt Disable Register */
118 #define AT91_SAMA5D2_IDR 0x28
119 /* Interrupt Mask Register */
120 #define AT91_SAMA5D2_IMR 0x2c
121 /* Interrupt Status Register */
122 #define AT91_SAMA5D2_ISR 0x30
123 /* Interrupt Status Register - Pen touching sense status */
124 #define AT91_SAMA5D2_ISR_PENS BIT(31)
125 /* Last Channel Trigger Mode Register */
126 #define AT91_SAMA5D2_LCTMR 0x34
127 /* Last Channel Compare Window Register */
128 #define AT91_SAMA5D2_LCCWR 0x38
129 /* Overrun Status Register */
130 #define AT91_SAMA5D2_OVER 0x3c
131 /* Extended Mode Register */
132 #define AT91_SAMA5D2_EMR 0x40
133 /* Extended Mode Register - Oversampling rate */
134 #define AT91_SAMA5D2_EMR_OSR(V) ((V) << 16)
135 #define AT91_SAMA5D2_EMR_OSR_MASK GENMASK(17, 16)
136 #define AT91_SAMA5D2_EMR_OSR_1SAMPLES 0
137 #define AT91_SAMA5D2_EMR_OSR_4SAMPLES 1
138 #define AT91_SAMA5D2_EMR_OSR_16SAMPLES 2
139
140 /* Extended Mode Register - Averaging on single trigger event */
141 #define AT91_SAMA5D2_EMR_ASTE(V) ((V) << 20)
142 /* Compare Window Register */
143 #define AT91_SAMA5D2_CWR 0x44
144 /* Channel Gain Register */
145 #define AT91_SAMA5D2_CGR 0x48
146
147 /* Channel Offset Register */
148 #define AT91_SAMA5D2_COR 0x4c
149 #define AT91_SAMA5D2_COR_DIFF_OFFSET 16
150
151 /* Channel Data Register 0 */
152 #define AT91_SAMA5D2_CDR0 0x50
153 /* Analog Control Register */
154 #define AT91_SAMA5D2_ACR 0x94
155 /* Analog Control Register - Pen detect sensitivity mask */
156 #define AT91_SAMA5D2_ACR_PENDETSENS_MASK GENMASK(1, 0)
157
158 /* Touchscreen Mode Register */
159 #define AT91_SAMA5D2_TSMR 0xb0
160 /* Touchscreen Mode Register - No touch mode */
161 #define AT91_SAMA5D2_TSMR_TSMODE_NONE 0
162 /* Touchscreen Mode Register - 4 wire screen, no pressure measurement */
163 #define AT91_SAMA5D2_TSMR_TSMODE_4WIRE_NO_PRESS 1
164 /* Touchscreen Mode Register - 4 wire screen, pressure measurement */
165 #define AT91_SAMA5D2_TSMR_TSMODE_4WIRE_PRESS 2
166 /* Touchscreen Mode Register - 5 wire screen */
167 #define AT91_SAMA5D2_TSMR_TSMODE_5WIRE 3
168 /* Touchscreen Mode Register - Average samples mask */
169 #define AT91_SAMA5D2_TSMR_TSAV_MASK GENMASK(5, 4)
170 /* Touchscreen Mode Register - Average samples */
171 #define AT91_SAMA5D2_TSMR_TSAV(x) ((x) << 4)
172 /* Touchscreen Mode Register - Touch/trigger frequency ratio mask */
173 #define AT91_SAMA5D2_TSMR_TSFREQ_MASK GENMASK(11, 8)
174 /* Touchscreen Mode Register - Touch/trigger frequency ratio */
175 #define AT91_SAMA5D2_TSMR_TSFREQ(x) ((x) << 8)
176 /* Touchscreen Mode Register - Pen Debounce Time mask */
177 #define AT91_SAMA5D2_TSMR_PENDBC_MASK GENMASK(31, 28)
178 /* Touchscreen Mode Register - Pen Debounce Time */
179 #define AT91_SAMA5D2_TSMR_PENDBC(x) ((x) << 28)
180 /* Touchscreen Mode Register - No DMA for touch measurements */
181 #define AT91_SAMA5D2_TSMR_NOTSDMA BIT(22)
182 /* Touchscreen Mode Register - Disable pen detection */
183 #define AT91_SAMA5D2_TSMR_PENDET_DIS (0 << 24)
184 /* Touchscreen Mode Register - Enable pen detection */
185 #define AT91_SAMA5D2_TSMR_PENDET_ENA BIT(24)
186
187 /* Touchscreen X Position Register */
188 #define AT91_SAMA5D2_XPOSR 0xb4
189 /* Touchscreen Y Position Register */
190 #define AT91_SAMA5D2_YPOSR 0xb8
191 /* Touchscreen Pressure Register */
192 #define AT91_SAMA5D2_PRESSR 0xbc
193 /* Trigger Register */
194 #define AT91_SAMA5D2_TRGR 0xc0
195 /* Mask for TRGMOD field of TRGR register */
196 #define AT91_SAMA5D2_TRGR_TRGMOD_MASK GENMASK(2, 0)
197 /* No trigger, only software trigger can start conversions */
198 #define AT91_SAMA5D2_TRGR_TRGMOD_NO_TRIGGER 0
199 /* Trigger Mode external trigger rising edge */
200 #define AT91_SAMA5D2_TRGR_TRGMOD_EXT_TRIG_RISE 1
201 /* Trigger Mode external trigger falling edge */
202 #define AT91_SAMA5D2_TRGR_TRGMOD_EXT_TRIG_FALL 2
203 /* Trigger Mode external trigger any edge */
204 #define AT91_SAMA5D2_TRGR_TRGMOD_EXT_TRIG_ANY 3
205 /* Trigger Mode internal periodic */
206 #define AT91_SAMA5D2_TRGR_TRGMOD_PERIODIC 5
207 /* Trigger Mode - trigger period mask */
208 #define AT91_SAMA5D2_TRGR_TRGPER_MASK GENMASK(31, 16)
209 /* Trigger Mode - trigger period */
210 #define AT91_SAMA5D2_TRGR_TRGPER(x) ((x) << 16)
211
212 /* Correction Select Register */
213 #define AT91_SAMA5D2_COSR 0xd0
214 /* Correction Value Register */
215 #define AT91_SAMA5D2_CVR 0xd4
216 /* Channel Error Correction Register */
217 #define AT91_SAMA5D2_CECR 0xd8
218 /* Write Protection Mode Register */
219 #define AT91_SAMA5D2_WPMR 0xe4
220 /* Write Protection Status Register */
221 #define AT91_SAMA5D2_WPSR 0xe8
222 /* Version Register */
223 #define AT91_SAMA5D2_VERSION 0xfc
224
225 #define AT91_SAMA5D2_HW_TRIG_CNT 3
226 #define AT91_SAMA5D2_SINGLE_CHAN_CNT 12
227 #define AT91_SAMA5D2_DIFF_CHAN_CNT 6
228
229 #define AT91_SAMA5D2_TIMESTAMP_CHAN_IDX (AT91_SAMA5D2_SINGLE_CHAN_CNT + \
230 AT91_SAMA5D2_DIFF_CHAN_CNT + 1)
231
232 #define AT91_SAMA5D2_TOUCH_X_CHAN_IDX (AT91_SAMA5D2_SINGLE_CHAN_CNT + \
233 AT91_SAMA5D2_DIFF_CHAN_CNT * 2)
234 #define AT91_SAMA5D2_TOUCH_Y_CHAN_IDX (AT91_SAMA5D2_TOUCH_X_CHAN_IDX + 1)
235 #define AT91_SAMA5D2_TOUCH_P_CHAN_IDX (AT91_SAMA5D2_TOUCH_Y_CHAN_IDX + 1)
236 #define AT91_SAMA5D2_MAX_CHAN_IDX AT91_SAMA5D2_TOUCH_P_CHAN_IDX
237
238 #define AT91_SAMA5D2_TOUCH_SAMPLE_PERIOD_US 2000 /* 2ms */
239 #define AT91_SAMA5D2_TOUCH_PEN_DETECT_DEBOUNCE_US 200
240
241 #define AT91_SAMA5D2_XYZ_MASK GENMASK(11, 0)
242
243 #define AT91_SAMA5D2_MAX_POS_BITS 12
244
245 /*
246 * Maximum number of bytes to hold conversion from all channels
247 * without the timestamp.
248 */
249 #define AT91_BUFFER_MAX_CONVERSION_BYTES ((AT91_SAMA5D2_SINGLE_CHAN_CNT + \
250 AT91_SAMA5D2_DIFF_CHAN_CNT) * 2)
251
252 /* This total must also include the timestamp */
253 #define AT91_BUFFER_MAX_BYTES (AT91_BUFFER_MAX_CONVERSION_BYTES + 8)
254
255 #define AT91_BUFFER_MAX_HWORDS (AT91_BUFFER_MAX_BYTES / 2)
256
257 #define AT91_HWFIFO_MAX_SIZE_STR "128"
258 #define AT91_HWFIFO_MAX_SIZE 128
259
260 /* Possible values for oversampling ratio */
261 #define AT91_OSR_1SAMPLES 1
262 #define AT91_OSR_4SAMPLES 4
263 #define AT91_OSR_16SAMPLES 16
264
265 #define AT91_SAMA5D2_CHAN_SINGLE(num, addr) \
266 { \
267 .type = IIO_VOLTAGE, \
268 .channel = num, \
269 .address = addr, \
270 .scan_index = num, \
271 .scan_type = { \
272 .sign = 'u', \
273 .realbits = 14, \
274 .storagebits = 16, \
275 }, \
276 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
277 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
278 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ)|\
279 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \
280 .datasheet_name = "CH"#num, \
281 .indexed = 1, \
282 }
283
284 #define AT91_SAMA5D2_CHAN_DIFF(num, num2, addr) \
285 { \
286 .type = IIO_VOLTAGE, \
287 .differential = 1, \
288 .channel = num, \
289 .channel2 = num2, \
290 .address = addr, \
291 .scan_index = num + AT91_SAMA5D2_SINGLE_CHAN_CNT, \
292 .scan_type = { \
293 .sign = 's', \
294 .realbits = 14, \
295 .storagebits = 16, \
296 }, \
297 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
298 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
299 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ)|\
300 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \
301 .datasheet_name = "CH"#num"-CH"#num2, \
302 .indexed = 1, \
303 }
304
305 #define AT91_SAMA5D2_CHAN_TOUCH(num, name, mod) \
306 { \
307 .type = IIO_POSITIONRELATIVE, \
308 .modified = 1, \
309 .channel = num, \
310 .channel2 = mod, \
311 .scan_index = num, \
312 .scan_type = { \
313 .sign = 'u', \
314 .realbits = 12, \
315 .storagebits = 16, \
316 }, \
317 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
318 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ)|\
319 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \
320 .datasheet_name = name, \
321 }
322 #define AT91_SAMA5D2_CHAN_PRESSURE(num, name) \
323 { \
324 .type = IIO_PRESSURE, \
325 .channel = num, \
326 .scan_index = num, \
327 .scan_type = { \
328 .sign = 'u', \
329 .realbits = 12, \
330 .storagebits = 16, \
331 }, \
332 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
333 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ)|\
334 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \
335 .datasheet_name = name, \
336 }
337
338 #define at91_adc_readl(st, reg) readl_relaxed(st->base + reg)
339 #define at91_adc_writel(st, reg, val) writel_relaxed(val, st->base + reg)
340
341 struct at91_adc_soc_info {
342 unsigned startup_time;
343 unsigned min_sample_rate;
344 unsigned max_sample_rate;
345 };
346
347 struct at91_adc_trigger {
348 char *name;
349 unsigned int trgmod_value;
350 unsigned int edge_type;
351 bool hw_trig;
352 };
353
354 /**
355 * at91_adc_dma - at91-sama5d2 dma information struct
356 * @dma_chan: the dma channel acquired
357 * @rx_buf: dma coherent allocated area
358 * @rx_dma_buf: dma handler for the buffer
359 * @phys_addr: physical address of the ADC base register
360 * @buf_idx: index inside the dma buffer where reading was last done
361 * @rx_buf_sz: size of buffer used by DMA operation
362 * @watermark: number of conversions to copy before DMA triggers irq
363 * @dma_ts: hold the start timestamp of dma operation
364 */
365 struct at91_adc_dma {
366 struct dma_chan *dma_chan;
367 u8 *rx_buf;
368 dma_addr_t rx_dma_buf;
369 phys_addr_t phys_addr;
370 int buf_idx;
371 int rx_buf_sz;
372 int watermark;
373 s64 dma_ts;
374 };
375
376 /**
377 * at91_adc_touch - at91-sama5d2 touchscreen information struct
378 * @sample_period_val: the value for periodic trigger interval
379 * @touching: is the pen touching the screen or not
380 * @x_pos: temporary placeholder for pressure computation
381 * @channels_bitmask: bitmask with the touchscreen channels enabled
382 * @workq: workqueue for buffer data pushing
383 */
384 struct at91_adc_touch {
385 u16 sample_period_val;
386 bool touching;
387 u16 x_pos;
388 unsigned long channels_bitmask;
389 struct work_struct workq;
390 };
391
392 struct at91_adc_state {
393 void __iomem *base;
394 int irq;
395 struct clk *per_clk;
396 struct regulator *reg;
397 struct regulator *vref;
398 int vref_uv;
399 unsigned int current_sample_rate;
400 struct iio_trigger *trig;
401 const struct at91_adc_trigger *selected_trig;
402 const struct iio_chan_spec *chan;
403 bool conversion_done;
404 u32 conversion_value;
405 unsigned int oversampling_ratio;
406 struct at91_adc_soc_info soc_info;
407 wait_queue_head_t wq_data_available;
408 struct at91_adc_dma dma_st;
409 struct at91_adc_touch touch_st;
410 u16 buffer[AT91_BUFFER_MAX_HWORDS];
411 /*
412 * lock to prevent concurrent 'single conversion' requests through
413 * sysfs.
414 */
415 struct mutex lock;
416 };
417
418 static const struct at91_adc_trigger at91_adc_trigger_list[] = {
419 {
420 .name = "external_rising",
421 .trgmod_value = AT91_SAMA5D2_TRGR_TRGMOD_EXT_TRIG_RISE,
422 .edge_type = IRQ_TYPE_EDGE_RISING,
423 .hw_trig = true,
424 },
425 {
426 .name = "external_falling",
427 .trgmod_value = AT91_SAMA5D2_TRGR_TRGMOD_EXT_TRIG_FALL,
428 .edge_type = IRQ_TYPE_EDGE_FALLING,
429 .hw_trig = true,
430 },
431 {
432 .name = "external_any",
433 .trgmod_value = AT91_SAMA5D2_TRGR_TRGMOD_EXT_TRIG_ANY,
434 .edge_type = IRQ_TYPE_EDGE_BOTH,
435 .hw_trig = true,
436 },
437 {
438 .name = "software",
439 .trgmod_value = AT91_SAMA5D2_TRGR_TRGMOD_NO_TRIGGER,
440 .edge_type = IRQ_TYPE_NONE,
441 .hw_trig = false,
442 },
443 };
444
445 static const struct iio_chan_spec at91_adc_channels[] = {
446 AT91_SAMA5D2_CHAN_SINGLE(0, 0x50),
447 AT91_SAMA5D2_CHAN_SINGLE(1, 0x54),
448 AT91_SAMA5D2_CHAN_SINGLE(2, 0x58),
449 AT91_SAMA5D2_CHAN_SINGLE(3, 0x5c),
450 AT91_SAMA5D2_CHAN_SINGLE(4, 0x60),
451 AT91_SAMA5D2_CHAN_SINGLE(5, 0x64),
452 AT91_SAMA5D2_CHAN_SINGLE(6, 0x68),
453 AT91_SAMA5D2_CHAN_SINGLE(7, 0x6c),
454 AT91_SAMA5D2_CHAN_SINGLE(8, 0x70),
455 AT91_SAMA5D2_CHAN_SINGLE(9, 0x74),
456 AT91_SAMA5D2_CHAN_SINGLE(10, 0x78),
457 AT91_SAMA5D2_CHAN_SINGLE(11, 0x7c),
458 AT91_SAMA5D2_CHAN_DIFF(0, 1, 0x50),
459 AT91_SAMA5D2_CHAN_DIFF(2, 3, 0x58),
460 AT91_SAMA5D2_CHAN_DIFF(4, 5, 0x60),
461 AT91_SAMA5D2_CHAN_DIFF(6, 7, 0x68),
462 AT91_SAMA5D2_CHAN_DIFF(8, 9, 0x70),
463 AT91_SAMA5D2_CHAN_DIFF(10, 11, 0x78),
464 IIO_CHAN_SOFT_TIMESTAMP(AT91_SAMA5D2_TIMESTAMP_CHAN_IDX),
465 AT91_SAMA5D2_CHAN_TOUCH(AT91_SAMA5D2_TOUCH_X_CHAN_IDX, "x", IIO_MOD_X),
466 AT91_SAMA5D2_CHAN_TOUCH(AT91_SAMA5D2_TOUCH_Y_CHAN_IDX, "y", IIO_MOD_Y),
467 AT91_SAMA5D2_CHAN_PRESSURE(AT91_SAMA5D2_TOUCH_P_CHAN_IDX, "pressure"),
468 };
469
at91_adc_chan_xlate(struct iio_dev * indio_dev,int chan)470 static int at91_adc_chan_xlate(struct iio_dev *indio_dev, int chan)
471 {
472 int i;
473
474 for (i = 0; i < indio_dev->num_channels; i++) {
475 if (indio_dev->channels[i].scan_index == chan)
476 return i;
477 }
478 return -EINVAL;
479 }
480
481 static inline struct iio_chan_spec const *
at91_adc_chan_get(struct iio_dev * indio_dev,int chan)482 at91_adc_chan_get(struct iio_dev *indio_dev, int chan)
483 {
484 int index = at91_adc_chan_xlate(indio_dev, chan);
485
486 if (index < 0)
487 return NULL;
488 return indio_dev->channels + index;
489 }
490
at91_adc_of_xlate(struct iio_dev * indio_dev,const struct of_phandle_args * iiospec)491 static inline int at91_adc_of_xlate(struct iio_dev *indio_dev,
492 const struct of_phandle_args *iiospec)
493 {
494 return at91_adc_chan_xlate(indio_dev, iiospec->args[0]);
495 }
496
at91_adc_config_emr(struct at91_adc_state * st)497 static void at91_adc_config_emr(struct at91_adc_state *st)
498 {
499 /* configure the extended mode register */
500 unsigned int emr = at91_adc_readl(st, AT91_SAMA5D2_EMR);
501
502 /* select oversampling per single trigger event */
503 emr |= AT91_SAMA5D2_EMR_ASTE(1);
504
505 /* delete leftover content if it's the case */
506 emr &= ~AT91_SAMA5D2_EMR_OSR_MASK;
507
508 /* select oversampling ratio from configuration */
509 switch (st->oversampling_ratio) {
510 case AT91_OSR_1SAMPLES:
511 emr |= AT91_SAMA5D2_EMR_OSR(AT91_SAMA5D2_EMR_OSR_1SAMPLES) &
512 AT91_SAMA5D2_EMR_OSR_MASK;
513 break;
514 case AT91_OSR_4SAMPLES:
515 emr |= AT91_SAMA5D2_EMR_OSR(AT91_SAMA5D2_EMR_OSR_4SAMPLES) &
516 AT91_SAMA5D2_EMR_OSR_MASK;
517 break;
518 case AT91_OSR_16SAMPLES:
519 emr |= AT91_SAMA5D2_EMR_OSR(AT91_SAMA5D2_EMR_OSR_16SAMPLES) &
520 AT91_SAMA5D2_EMR_OSR_MASK;
521 break;
522 }
523
524 at91_adc_writel(st, AT91_SAMA5D2_EMR, emr);
525 }
526
at91_adc_adjust_val_osr(struct at91_adc_state * st,int * val)527 static int at91_adc_adjust_val_osr(struct at91_adc_state *st, int *val)
528 {
529 if (st->oversampling_ratio == AT91_OSR_1SAMPLES) {
530 /*
531 * in this case we only have 12 bits of real data, but channel
532 * is registered as 14 bits, so shift left two bits
533 */
534 *val <<= 2;
535 } else if (st->oversampling_ratio == AT91_OSR_4SAMPLES) {
536 /*
537 * in this case we have 13 bits of real data, but channel
538 * is registered as 14 bits, so left shift one bit
539 */
540 *val <<= 1;
541 }
542
543 return IIO_VAL_INT;
544 }
545
at91_adc_adjust_val_osr_array(struct at91_adc_state * st,void * buf,int len)546 static void at91_adc_adjust_val_osr_array(struct at91_adc_state *st, void *buf,
547 int len)
548 {
549 int i = 0, val;
550 u16 *buf_u16 = (u16 *) buf;
551
552 /*
553 * We are converting each two bytes (each sample).
554 * First convert the byte based array to u16, and convert each sample
555 * separately.
556 * Each value is two bytes in an array of chars, so to not shift
557 * more than we need, save the value separately.
558 * len is in bytes, so divide by two to get number of samples.
559 */
560 while (i < len / 2) {
561 val = buf_u16[i];
562 at91_adc_adjust_val_osr(st, &val);
563 buf_u16[i] = val;
564 i++;
565 }
566 }
567
at91_adc_configure_touch(struct at91_adc_state * st,bool state)568 static int at91_adc_configure_touch(struct at91_adc_state *st, bool state)
569 {
570 u32 clk_khz = st->current_sample_rate / 1000;
571 int i = 0;
572 u16 pendbc;
573 u32 tsmr, acr;
574
575 if (!state) {
576 /* disabling touch IRQs and setting mode to no touch enabled */
577 at91_adc_writel(st, AT91_SAMA5D2_IDR,
578 AT91_SAMA5D2_IER_PEN | AT91_SAMA5D2_IER_NOPEN);
579 at91_adc_writel(st, AT91_SAMA5D2_TSMR, 0);
580 return 0;
581 }
582 /*
583 * debounce time is in microseconds, we need it in milliseconds to
584 * multiply with kilohertz, so, divide by 1000, but after the multiply.
585 * round up to make sure pendbc is at least 1
586 */
587 pendbc = round_up(AT91_SAMA5D2_TOUCH_PEN_DETECT_DEBOUNCE_US *
588 clk_khz / 1000, 1);
589
590 /* get the required exponent */
591 while (pendbc >> i++)
592 ;
593
594 pendbc = i;
595
596 tsmr = AT91_SAMA5D2_TSMR_TSMODE_4WIRE_PRESS;
597
598 tsmr |= AT91_SAMA5D2_TSMR_TSAV(2) & AT91_SAMA5D2_TSMR_TSAV_MASK;
599 tsmr |= AT91_SAMA5D2_TSMR_PENDBC(pendbc) &
600 AT91_SAMA5D2_TSMR_PENDBC_MASK;
601 tsmr |= AT91_SAMA5D2_TSMR_NOTSDMA;
602 tsmr |= AT91_SAMA5D2_TSMR_PENDET_ENA;
603 tsmr |= AT91_SAMA5D2_TSMR_TSFREQ(2) & AT91_SAMA5D2_TSMR_TSFREQ_MASK;
604
605 at91_adc_writel(st, AT91_SAMA5D2_TSMR, tsmr);
606
607 acr = at91_adc_readl(st, AT91_SAMA5D2_ACR);
608 acr &= ~AT91_SAMA5D2_ACR_PENDETSENS_MASK;
609 acr |= 0x02 & AT91_SAMA5D2_ACR_PENDETSENS_MASK;
610 at91_adc_writel(st, AT91_SAMA5D2_ACR, acr);
611
612 /* Sample Period Time = (TRGPER + 1) / ADCClock */
613 st->touch_st.sample_period_val =
614 round_up((AT91_SAMA5D2_TOUCH_SAMPLE_PERIOD_US *
615 clk_khz / 1000) - 1, 1);
616 /* enable pen detect IRQ */
617 at91_adc_writel(st, AT91_SAMA5D2_IER, AT91_SAMA5D2_IER_PEN);
618
619 return 0;
620 }
621
at91_adc_touch_pos(struct at91_adc_state * st,int reg)622 static u16 at91_adc_touch_pos(struct at91_adc_state *st, int reg)
623 {
624 u32 val;
625 u32 scale, result, pos;
626
627 /*
628 * to obtain the actual position we must divide by scale
629 * and multiply with max, where
630 * max = 2^AT91_SAMA5D2_MAX_POS_BITS - 1
631 */
632 /* first half of register is the x or y, second half is the scale */
633 val = at91_adc_readl(st, reg);
634 if (!val)
635 dev_dbg(&iio_priv_to_dev(st)->dev, "pos is 0\n");
636
637 pos = val & AT91_SAMA5D2_XYZ_MASK;
638 result = (pos << AT91_SAMA5D2_MAX_POS_BITS) - pos;
639 scale = (val >> 16) & AT91_SAMA5D2_XYZ_MASK;
640 if (scale == 0) {
641 dev_err(&iio_priv_to_dev(st)->dev, "scale is 0\n");
642 return 0;
643 }
644 result /= scale;
645
646 return result;
647 }
648
at91_adc_touch_x_pos(struct at91_adc_state * st)649 static u16 at91_adc_touch_x_pos(struct at91_adc_state *st)
650 {
651 st->touch_st.x_pos = at91_adc_touch_pos(st, AT91_SAMA5D2_XPOSR);
652 return st->touch_st.x_pos;
653 }
654
at91_adc_touch_y_pos(struct at91_adc_state * st)655 static u16 at91_adc_touch_y_pos(struct at91_adc_state *st)
656 {
657 return at91_adc_touch_pos(st, AT91_SAMA5D2_YPOSR);
658 }
659
at91_adc_touch_pressure(struct at91_adc_state * st)660 static u16 at91_adc_touch_pressure(struct at91_adc_state *st)
661 {
662 u32 val;
663 u32 z1, z2;
664 u32 pres;
665 u32 rxp = 1;
666 u32 factor = 1000;
667
668 /* calculate the pressure */
669 val = at91_adc_readl(st, AT91_SAMA5D2_PRESSR);
670 z1 = val & AT91_SAMA5D2_XYZ_MASK;
671 z2 = (val >> 16) & AT91_SAMA5D2_XYZ_MASK;
672
673 if (z1 != 0)
674 pres = rxp * (st->touch_st.x_pos * factor / 1024) *
675 (z2 * factor / z1 - factor) /
676 factor;
677 else
678 pres = 0xFFFF; /* no pen contact */
679
680 /*
681 * The pressure from device grows down, minimum is 0xFFFF, maximum 0x0.
682 * We compute it this way, but let's return it in the expected way,
683 * growing from 0 to 0xFFFF.
684 */
685 return 0xFFFF - pres;
686 }
687
at91_adc_read_position(struct at91_adc_state * st,int chan,u16 * val)688 static int at91_adc_read_position(struct at91_adc_state *st, int chan, u16 *val)
689 {
690 *val = 0;
691 if (!st->touch_st.touching)
692 return -ENODATA;
693 if (chan == AT91_SAMA5D2_TOUCH_X_CHAN_IDX)
694 *val = at91_adc_touch_x_pos(st);
695 else if (chan == AT91_SAMA5D2_TOUCH_Y_CHAN_IDX)
696 *val = at91_adc_touch_y_pos(st);
697 else
698 return -ENODATA;
699
700 return IIO_VAL_INT;
701 }
702
at91_adc_read_pressure(struct at91_adc_state * st,int chan,u16 * val)703 static int at91_adc_read_pressure(struct at91_adc_state *st, int chan, u16 *val)
704 {
705 *val = 0;
706 if (!st->touch_st.touching)
707 return -ENODATA;
708 if (chan == AT91_SAMA5D2_TOUCH_P_CHAN_IDX)
709 *val = at91_adc_touch_pressure(st);
710 else
711 return -ENODATA;
712
713 return IIO_VAL_INT;
714 }
715
at91_adc_configure_trigger(struct iio_trigger * trig,bool state)716 static int at91_adc_configure_trigger(struct iio_trigger *trig, bool state)
717 {
718 struct iio_dev *indio = iio_trigger_get_drvdata(trig);
719 struct at91_adc_state *st = iio_priv(indio);
720 u32 status = at91_adc_readl(st, AT91_SAMA5D2_TRGR);
721 u8 bit;
722
723 /* clear TRGMOD */
724 status &= ~AT91_SAMA5D2_TRGR_TRGMOD_MASK;
725
726 if (state)
727 status |= st->selected_trig->trgmod_value;
728
729 /* set/unset hw trigger */
730 at91_adc_writel(st, AT91_SAMA5D2_TRGR, status);
731
732 for_each_set_bit(bit, indio->active_scan_mask, indio->num_channels) {
733 struct iio_chan_spec const *chan = at91_adc_chan_get(indio, bit);
734
735 if (!chan)
736 continue;
737 /* these channel types cannot be handled by this trigger */
738 if (chan->type == IIO_POSITIONRELATIVE ||
739 chan->type == IIO_PRESSURE)
740 continue;
741
742 if (state) {
743 at91_adc_writel(st, AT91_SAMA5D2_CHER,
744 BIT(chan->channel));
745 /* enable irq only if not using DMA */
746 if (!st->dma_st.dma_chan) {
747 at91_adc_writel(st, AT91_SAMA5D2_IER,
748 BIT(chan->channel));
749 }
750 } else {
751 /* disable irq only if not using DMA */
752 if (!st->dma_st.dma_chan) {
753 at91_adc_writel(st, AT91_SAMA5D2_IDR,
754 BIT(chan->channel));
755 }
756 at91_adc_writel(st, AT91_SAMA5D2_CHDR,
757 BIT(chan->channel));
758 }
759 }
760
761 return 0;
762 }
763
at91_adc_reenable_trigger(struct iio_trigger * trig)764 static int at91_adc_reenable_trigger(struct iio_trigger *trig)
765 {
766 struct iio_dev *indio = iio_trigger_get_drvdata(trig);
767 struct at91_adc_state *st = iio_priv(indio);
768
769 /* if we are using DMA, we must not reenable irq after each trigger */
770 if (st->dma_st.dma_chan)
771 return 0;
772
773 enable_irq(st->irq);
774
775 /* Needed to ACK the DRDY interruption */
776 at91_adc_readl(st, AT91_SAMA5D2_LCDR);
777 return 0;
778 }
779
780 static const struct iio_trigger_ops at91_adc_trigger_ops = {
781 .set_trigger_state = &at91_adc_configure_trigger,
782 .try_reenable = &at91_adc_reenable_trigger,
783 .validate_device = iio_trigger_validate_own_device,
784 };
785
at91_adc_dma_size_done(struct at91_adc_state * st)786 static int at91_adc_dma_size_done(struct at91_adc_state *st)
787 {
788 struct dma_tx_state state;
789 enum dma_status status;
790 int i, size;
791
792 status = dmaengine_tx_status(st->dma_st.dma_chan,
793 st->dma_st.dma_chan->cookie,
794 &state);
795 if (status != DMA_IN_PROGRESS)
796 return 0;
797
798 /* Transferred length is size in bytes from end of buffer */
799 i = st->dma_st.rx_buf_sz - state.residue;
800
801 /* Return available bytes */
802 if (i >= st->dma_st.buf_idx)
803 size = i - st->dma_st.buf_idx;
804 else
805 size = st->dma_st.rx_buf_sz + i - st->dma_st.buf_idx;
806 return size;
807 }
808
at91_dma_buffer_done(void * data)809 static void at91_dma_buffer_done(void *data)
810 {
811 struct iio_dev *indio_dev = data;
812
813 iio_trigger_poll_chained(indio_dev->trig);
814 }
815
at91_adc_dma_start(struct iio_dev * indio_dev)816 static int at91_adc_dma_start(struct iio_dev *indio_dev)
817 {
818 struct at91_adc_state *st = iio_priv(indio_dev);
819 struct dma_async_tx_descriptor *desc;
820 dma_cookie_t cookie;
821 int ret;
822 u8 bit;
823
824 if (!st->dma_st.dma_chan)
825 return 0;
826
827 /* we start a new DMA, so set buffer index to start */
828 st->dma_st.buf_idx = 0;
829
830 /*
831 * compute buffer size w.r.t. watermark and enabled channels.
832 * scan_bytes is aligned so we need an exact size for DMA
833 */
834 st->dma_st.rx_buf_sz = 0;
835
836 for_each_set_bit(bit, indio_dev->active_scan_mask,
837 indio_dev->num_channels) {
838 struct iio_chan_spec const *chan =
839 at91_adc_chan_get(indio_dev, bit);
840
841 if (!chan)
842 continue;
843
844 st->dma_st.rx_buf_sz += chan->scan_type.storagebits / 8;
845 }
846 st->dma_st.rx_buf_sz *= st->dma_st.watermark;
847
848 /* Prepare a DMA cyclic transaction */
849 desc = dmaengine_prep_dma_cyclic(st->dma_st.dma_chan,
850 st->dma_st.rx_dma_buf,
851 st->dma_st.rx_buf_sz,
852 st->dma_st.rx_buf_sz / 2,
853 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT);
854
855 if (!desc) {
856 dev_err(&indio_dev->dev, "cannot prepare DMA cyclic\n");
857 return -EBUSY;
858 }
859
860 desc->callback = at91_dma_buffer_done;
861 desc->callback_param = indio_dev;
862
863 cookie = dmaengine_submit(desc);
864 ret = dma_submit_error(cookie);
865 if (ret) {
866 dev_err(&indio_dev->dev, "cannot submit DMA cyclic\n");
867 dmaengine_terminate_async(st->dma_st.dma_chan);
868 return ret;
869 }
870
871 /* enable general overrun error signaling */
872 at91_adc_writel(st, AT91_SAMA5D2_IER, AT91_SAMA5D2_IER_GOVRE);
873 /* Issue pending DMA requests */
874 dma_async_issue_pending(st->dma_st.dma_chan);
875
876 /* consider current time as DMA start time for timestamps */
877 st->dma_st.dma_ts = iio_get_time_ns(indio_dev);
878
879 dev_dbg(&indio_dev->dev, "DMA cyclic started\n");
880
881 return 0;
882 }
883
at91_adc_buffer_postenable(struct iio_dev * indio_dev)884 static int at91_adc_buffer_postenable(struct iio_dev *indio_dev)
885 {
886 int ret;
887 struct at91_adc_state *st = iio_priv(indio_dev);
888
889 /* check if we are enabling triggered buffer or the touchscreen */
890 if (bitmap_subset(indio_dev->active_scan_mask,
891 &st->touch_st.channels_bitmask,
892 AT91_SAMA5D2_MAX_CHAN_IDX + 1)) {
893 /* touchscreen enabling */
894 return at91_adc_configure_touch(st, true);
895 }
896 /* if we are not in triggered mode, we cannot enable the buffer. */
897 if (!(indio_dev->currentmode & INDIO_ALL_TRIGGERED_MODES))
898 return -EINVAL;
899
900 /* we continue with the triggered buffer */
901 ret = at91_adc_dma_start(indio_dev);
902 if (ret) {
903 dev_err(&indio_dev->dev, "buffer postenable failed\n");
904 return ret;
905 }
906
907 return iio_triggered_buffer_postenable(indio_dev);
908 }
909
at91_adc_buffer_predisable(struct iio_dev * indio_dev)910 static int at91_adc_buffer_predisable(struct iio_dev *indio_dev)
911 {
912 struct at91_adc_state *st = iio_priv(indio_dev);
913 int ret;
914 u8 bit;
915
916 /* check if we are disabling triggered buffer or the touchscreen */
917 if (bitmap_subset(indio_dev->active_scan_mask,
918 &st->touch_st.channels_bitmask,
919 AT91_SAMA5D2_MAX_CHAN_IDX + 1)) {
920 /* touchscreen disable */
921 return at91_adc_configure_touch(st, false);
922 }
923 /* if we are not in triggered mode, nothing to do here */
924 if (!(indio_dev->currentmode & INDIO_ALL_TRIGGERED_MODES))
925 return -EINVAL;
926
927 /* continue with the triggered buffer */
928 ret = iio_triggered_buffer_predisable(indio_dev);
929 if (ret < 0)
930 dev_err(&indio_dev->dev, "buffer predisable failed\n");
931
932 if (!st->dma_st.dma_chan)
933 return ret;
934
935 /* if we are using DMA we must clear registers and end DMA */
936 dmaengine_terminate_sync(st->dma_st.dma_chan);
937
938 /*
939 * For each enabled channel we must read the last converted value
940 * to clear EOC status and not get a possible interrupt later.
941 * This value is being read by DMA from LCDR anyway
942 */
943 for_each_set_bit(bit, indio_dev->active_scan_mask,
944 indio_dev->num_channels) {
945 struct iio_chan_spec const *chan =
946 at91_adc_chan_get(indio_dev, bit);
947
948 if (!chan)
949 continue;
950 /* these channel types are virtual, no need to do anything */
951 if (chan->type == IIO_POSITIONRELATIVE ||
952 chan->type == IIO_PRESSURE)
953 continue;
954 if (st->dma_st.dma_chan)
955 at91_adc_readl(st, chan->address);
956 }
957
958 /* read overflow register to clear possible overflow status */
959 at91_adc_readl(st, AT91_SAMA5D2_OVER);
960 return ret;
961 }
962
963 static const struct iio_buffer_setup_ops at91_buffer_setup_ops = {
964 .postenable = &at91_adc_buffer_postenable,
965 .predisable = &at91_adc_buffer_predisable,
966 };
967
at91_adc_allocate_trigger(struct iio_dev * indio,char * trigger_name)968 static struct iio_trigger *at91_adc_allocate_trigger(struct iio_dev *indio,
969 char *trigger_name)
970 {
971 struct iio_trigger *trig;
972 int ret;
973
974 trig = devm_iio_trigger_alloc(&indio->dev, "%s-dev%d-%s", indio->name,
975 indio->id, trigger_name);
976 if (!trig)
977 return NULL;
978
979 trig->dev.parent = indio->dev.parent;
980 iio_trigger_set_drvdata(trig, indio);
981 trig->ops = &at91_adc_trigger_ops;
982
983 ret = devm_iio_trigger_register(&indio->dev, trig);
984 if (ret)
985 return ERR_PTR(ret);
986
987 return trig;
988 }
989
at91_adc_trigger_init(struct iio_dev * indio)990 static int at91_adc_trigger_init(struct iio_dev *indio)
991 {
992 struct at91_adc_state *st = iio_priv(indio);
993
994 st->trig = at91_adc_allocate_trigger(indio, st->selected_trig->name);
995 if (IS_ERR(st->trig)) {
996 dev_err(&indio->dev,
997 "could not allocate trigger\n");
998 return PTR_ERR(st->trig);
999 }
1000
1001 return 0;
1002 }
1003
at91_adc_trigger_handler_nodma(struct iio_dev * indio_dev,struct iio_poll_func * pf)1004 static void at91_adc_trigger_handler_nodma(struct iio_dev *indio_dev,
1005 struct iio_poll_func *pf)
1006 {
1007 struct at91_adc_state *st = iio_priv(indio_dev);
1008 int i = 0;
1009 int val;
1010 u8 bit;
1011
1012 for_each_set_bit(bit, indio_dev->active_scan_mask,
1013 indio_dev->num_channels) {
1014 struct iio_chan_spec const *chan =
1015 at91_adc_chan_get(indio_dev, bit);
1016
1017 if (!chan)
1018 continue;
1019 /*
1020 * Our external trigger only supports the voltage channels.
1021 * In case someone requested a different type of channel
1022 * just put zeroes to buffer.
1023 * This should not happen because we check the scan mode
1024 * and scan mask when we enable the buffer, and we don't allow
1025 * the buffer to start with a mixed mask (voltage and something
1026 * else).
1027 * Thus, emit a warning.
1028 */
1029 if (chan->type == IIO_VOLTAGE) {
1030 val = at91_adc_readl(st, chan->address);
1031 at91_adc_adjust_val_osr(st, &val);
1032 st->buffer[i] = val;
1033 } else {
1034 st->buffer[i] = 0;
1035 WARN(true, "This trigger cannot handle this type of channel");
1036 }
1037 i++;
1038 }
1039 iio_push_to_buffers_with_timestamp(indio_dev, st->buffer,
1040 pf->timestamp);
1041 }
1042
at91_adc_trigger_handler_dma(struct iio_dev * indio_dev)1043 static void at91_adc_trigger_handler_dma(struct iio_dev *indio_dev)
1044 {
1045 struct at91_adc_state *st = iio_priv(indio_dev);
1046 int transferred_len = at91_adc_dma_size_done(st);
1047 s64 ns = iio_get_time_ns(indio_dev);
1048 s64 interval;
1049 int sample_index = 0, sample_count, sample_size;
1050
1051 u32 status = at91_adc_readl(st, AT91_SAMA5D2_ISR);
1052 /* if we reached this point, we cannot sample faster */
1053 if (status & AT91_SAMA5D2_IER_GOVRE)
1054 pr_info_ratelimited("%s: conversion overrun detected\n",
1055 indio_dev->name);
1056
1057 sample_size = div_s64(st->dma_st.rx_buf_sz, st->dma_st.watermark);
1058
1059 sample_count = div_s64(transferred_len, sample_size);
1060
1061 /*
1062 * interval between samples is total time since last transfer handling
1063 * divided by the number of samples (total size divided by sample size)
1064 */
1065 interval = div_s64((ns - st->dma_st.dma_ts), sample_count);
1066
1067 while (transferred_len >= sample_size) {
1068 /*
1069 * for all the values in the current sample,
1070 * adjust the values inside the buffer for oversampling
1071 */
1072 at91_adc_adjust_val_osr_array(st,
1073 &st->dma_st.rx_buf[st->dma_st.buf_idx],
1074 sample_size);
1075
1076 iio_push_to_buffers_with_timestamp(indio_dev,
1077 (st->dma_st.rx_buf + st->dma_st.buf_idx),
1078 (st->dma_st.dma_ts + interval * sample_index));
1079 /* adjust remaining length */
1080 transferred_len -= sample_size;
1081 /* adjust buffer index */
1082 st->dma_st.buf_idx += sample_size;
1083 /* in case of reaching end of buffer, reset index */
1084 if (st->dma_st.buf_idx >= st->dma_st.rx_buf_sz)
1085 st->dma_st.buf_idx = 0;
1086 sample_index++;
1087 }
1088 /* adjust saved time for next transfer handling */
1089 st->dma_st.dma_ts = iio_get_time_ns(indio_dev);
1090 }
1091
at91_adc_trigger_handler(int irq,void * p)1092 static irqreturn_t at91_adc_trigger_handler(int irq, void *p)
1093 {
1094 struct iio_poll_func *pf = p;
1095 struct iio_dev *indio_dev = pf->indio_dev;
1096 struct at91_adc_state *st = iio_priv(indio_dev);
1097
1098 if (st->dma_st.dma_chan)
1099 at91_adc_trigger_handler_dma(indio_dev);
1100 else
1101 at91_adc_trigger_handler_nodma(indio_dev, pf);
1102
1103 iio_trigger_notify_done(indio_dev->trig);
1104
1105 return IRQ_HANDLED;
1106 }
1107
at91_adc_buffer_init(struct iio_dev * indio)1108 static int at91_adc_buffer_init(struct iio_dev *indio)
1109 {
1110 struct at91_adc_state *st = iio_priv(indio);
1111
1112 if (st->selected_trig->hw_trig) {
1113 return devm_iio_triggered_buffer_setup(&indio->dev, indio,
1114 &iio_pollfunc_store_time,
1115 &at91_adc_trigger_handler, &at91_buffer_setup_ops);
1116 }
1117 /*
1118 * we need to prepare the buffer ops in case we will get
1119 * another buffer attached (like a callback buffer for the touchscreen)
1120 */
1121 indio->setup_ops = &at91_buffer_setup_ops;
1122
1123 return 0;
1124 }
1125
at91_adc_startup_time(unsigned startup_time_min,unsigned adc_clk_khz)1126 static unsigned at91_adc_startup_time(unsigned startup_time_min,
1127 unsigned adc_clk_khz)
1128 {
1129 static const unsigned int startup_lookup[] = {
1130 0, 8, 16, 24,
1131 64, 80, 96, 112,
1132 512, 576, 640, 704,
1133 768, 832, 896, 960
1134 };
1135 unsigned ticks_min, i;
1136
1137 /*
1138 * Since the adc frequency is checked before, there is no reason
1139 * to not meet the startup time constraint.
1140 */
1141
1142 ticks_min = startup_time_min * adc_clk_khz / 1000;
1143 for (i = 0; i < ARRAY_SIZE(startup_lookup); i++)
1144 if (startup_lookup[i] > ticks_min)
1145 break;
1146
1147 return i;
1148 }
1149
at91_adc_setup_samp_freq(struct at91_adc_state * st,unsigned freq)1150 static void at91_adc_setup_samp_freq(struct at91_adc_state *st, unsigned freq)
1151 {
1152 struct iio_dev *indio_dev = iio_priv_to_dev(st);
1153 unsigned f_per, prescal, startup, mr;
1154
1155 f_per = clk_get_rate(st->per_clk);
1156 prescal = (f_per / (2 * freq)) - 1;
1157
1158 startup = at91_adc_startup_time(st->soc_info.startup_time,
1159 freq / 1000);
1160
1161 mr = at91_adc_readl(st, AT91_SAMA5D2_MR);
1162 mr &= ~(AT91_SAMA5D2_MR_STARTUP_MASK | AT91_SAMA5D2_MR_PRESCAL_MASK);
1163 mr |= AT91_SAMA5D2_MR_STARTUP(startup);
1164 mr |= AT91_SAMA5D2_MR_PRESCAL(prescal);
1165 at91_adc_writel(st, AT91_SAMA5D2_MR, mr);
1166
1167 dev_dbg(&indio_dev->dev, "freq: %u, startup: %u, prescal: %u\n",
1168 freq, startup, prescal);
1169 st->current_sample_rate = freq;
1170 }
1171
at91_adc_get_sample_freq(struct at91_adc_state * st)1172 static inline unsigned at91_adc_get_sample_freq(struct at91_adc_state *st)
1173 {
1174 return st->current_sample_rate;
1175 }
1176
at91_adc_touch_data_handler(struct iio_dev * indio_dev)1177 static void at91_adc_touch_data_handler(struct iio_dev *indio_dev)
1178 {
1179 struct at91_adc_state *st = iio_priv(indio_dev);
1180 u8 bit;
1181 u16 val;
1182 int i = 0;
1183
1184 for_each_set_bit(bit, indio_dev->active_scan_mask,
1185 AT91_SAMA5D2_MAX_CHAN_IDX + 1) {
1186 struct iio_chan_spec const *chan =
1187 at91_adc_chan_get(indio_dev, bit);
1188
1189 if (chan->type == IIO_POSITIONRELATIVE)
1190 at91_adc_read_position(st, chan->channel, &val);
1191 else if (chan->type == IIO_PRESSURE)
1192 at91_adc_read_pressure(st, chan->channel, &val);
1193 else
1194 continue;
1195 st->buffer[i] = val;
1196 i++;
1197 }
1198 /*
1199 * Schedule work to push to buffers.
1200 * This is intended to push to the callback buffer that another driver
1201 * registered. We are still in a handler from our IRQ. If we push
1202 * directly, it means the other driver has it's callback called
1203 * from our IRQ context. Which is something we better avoid.
1204 * Let's schedule it after our IRQ is completed.
1205 */
1206 schedule_work(&st->touch_st.workq);
1207 }
1208
at91_adc_pen_detect_interrupt(struct at91_adc_state * st)1209 static void at91_adc_pen_detect_interrupt(struct at91_adc_state *st)
1210 {
1211 at91_adc_writel(st, AT91_SAMA5D2_IDR, AT91_SAMA5D2_IER_PEN);
1212 at91_adc_writel(st, AT91_SAMA5D2_IER, AT91_SAMA5D2_IER_NOPEN |
1213 AT91_SAMA5D2_IER_XRDY | AT91_SAMA5D2_IER_YRDY |
1214 AT91_SAMA5D2_IER_PRDY);
1215 at91_adc_writel(st, AT91_SAMA5D2_TRGR,
1216 AT91_SAMA5D2_TRGR_TRGMOD_PERIODIC |
1217 AT91_SAMA5D2_TRGR_TRGPER(st->touch_st.sample_period_val));
1218 st->touch_st.touching = true;
1219 }
1220
at91_adc_no_pen_detect_interrupt(struct at91_adc_state * st)1221 static void at91_adc_no_pen_detect_interrupt(struct at91_adc_state *st)
1222 {
1223 struct iio_dev *indio_dev = iio_priv_to_dev(st);
1224
1225 at91_adc_writel(st, AT91_SAMA5D2_TRGR,
1226 AT91_SAMA5D2_TRGR_TRGMOD_NO_TRIGGER);
1227 at91_adc_writel(st, AT91_SAMA5D2_IDR, AT91_SAMA5D2_IER_NOPEN |
1228 AT91_SAMA5D2_IER_XRDY | AT91_SAMA5D2_IER_YRDY |
1229 AT91_SAMA5D2_IER_PRDY);
1230 st->touch_st.touching = false;
1231
1232 at91_adc_touch_data_handler(indio_dev);
1233
1234 at91_adc_writel(st, AT91_SAMA5D2_IER, AT91_SAMA5D2_IER_PEN);
1235 }
1236
at91_adc_workq_handler(struct work_struct * workq)1237 static void at91_adc_workq_handler(struct work_struct *workq)
1238 {
1239 struct at91_adc_touch *touch_st = container_of(workq,
1240 struct at91_adc_touch, workq);
1241 struct at91_adc_state *st = container_of(touch_st,
1242 struct at91_adc_state, touch_st);
1243 struct iio_dev *indio_dev = iio_priv_to_dev(st);
1244
1245 iio_push_to_buffers(indio_dev, st->buffer);
1246 }
1247
at91_adc_interrupt(int irq,void * private)1248 static irqreturn_t at91_adc_interrupt(int irq, void *private)
1249 {
1250 struct iio_dev *indio = private;
1251 struct at91_adc_state *st = iio_priv(indio);
1252 u32 status = at91_adc_readl(st, AT91_SAMA5D2_ISR);
1253 u32 imr = at91_adc_readl(st, AT91_SAMA5D2_IMR);
1254 u32 rdy_mask = AT91_SAMA5D2_IER_XRDY | AT91_SAMA5D2_IER_YRDY |
1255 AT91_SAMA5D2_IER_PRDY;
1256
1257 if (!(status & imr))
1258 return IRQ_NONE;
1259 if (status & AT91_SAMA5D2_IER_PEN) {
1260 /* pen detected IRQ */
1261 at91_adc_pen_detect_interrupt(st);
1262 } else if ((status & AT91_SAMA5D2_IER_NOPEN)) {
1263 /* nopen detected IRQ */
1264 at91_adc_no_pen_detect_interrupt(st);
1265 } else if ((status & AT91_SAMA5D2_ISR_PENS) &&
1266 ((status & rdy_mask) == rdy_mask)) {
1267 /* periodic trigger IRQ - during pen sense */
1268 at91_adc_touch_data_handler(indio);
1269 } else if (status & AT91_SAMA5D2_ISR_PENS) {
1270 /*
1271 * touching, but the measurements are not ready yet.
1272 * read and ignore.
1273 */
1274 status = at91_adc_readl(st, AT91_SAMA5D2_XPOSR);
1275 status = at91_adc_readl(st, AT91_SAMA5D2_YPOSR);
1276 status = at91_adc_readl(st, AT91_SAMA5D2_PRESSR);
1277 } else if (iio_buffer_enabled(indio) && !st->dma_st.dma_chan) {
1278 /* triggered buffer without DMA */
1279 disable_irq_nosync(irq);
1280 iio_trigger_poll(indio->trig);
1281 } else if (iio_buffer_enabled(indio) && st->dma_st.dma_chan) {
1282 /* triggered buffer with DMA - should not happen */
1283 disable_irq_nosync(irq);
1284 WARN(true, "Unexpected irq occurred\n");
1285 } else if (!iio_buffer_enabled(indio)) {
1286 /* software requested conversion */
1287 st->conversion_value = at91_adc_readl(st, st->chan->address);
1288 st->conversion_done = true;
1289 wake_up_interruptible(&st->wq_data_available);
1290 }
1291 return IRQ_HANDLED;
1292 }
1293
at91_adc_read_info_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val)1294 static int at91_adc_read_info_raw(struct iio_dev *indio_dev,
1295 struct iio_chan_spec const *chan, int *val)
1296 {
1297 struct at91_adc_state *st = iio_priv(indio_dev);
1298 u32 cor = 0;
1299 u16 tmp_val;
1300 int ret;
1301
1302 /*
1303 * Keep in mind that we cannot use software trigger or touchscreen
1304 * if external trigger is enabled
1305 */
1306 if (chan->type == IIO_POSITIONRELATIVE) {
1307 ret = iio_device_claim_direct_mode(indio_dev);
1308 if (ret)
1309 return ret;
1310 mutex_lock(&st->lock);
1311
1312 ret = at91_adc_read_position(st, chan->channel,
1313 &tmp_val);
1314 *val = tmp_val;
1315 mutex_unlock(&st->lock);
1316 iio_device_release_direct_mode(indio_dev);
1317
1318 return at91_adc_adjust_val_osr(st, val);
1319 }
1320 if (chan->type == IIO_PRESSURE) {
1321 ret = iio_device_claim_direct_mode(indio_dev);
1322 if (ret)
1323 return ret;
1324 mutex_lock(&st->lock);
1325
1326 ret = at91_adc_read_pressure(st, chan->channel,
1327 &tmp_val);
1328 *val = tmp_val;
1329 mutex_unlock(&st->lock);
1330 iio_device_release_direct_mode(indio_dev);
1331
1332 return at91_adc_adjust_val_osr(st, val);
1333 }
1334
1335 /* in this case we have a voltage channel */
1336
1337 ret = iio_device_claim_direct_mode(indio_dev);
1338 if (ret)
1339 return ret;
1340 mutex_lock(&st->lock);
1341
1342 st->chan = chan;
1343
1344 if (chan->differential)
1345 cor = (BIT(chan->channel) | BIT(chan->channel2)) <<
1346 AT91_SAMA5D2_COR_DIFF_OFFSET;
1347
1348 at91_adc_writel(st, AT91_SAMA5D2_COR, cor);
1349 at91_adc_writel(st, AT91_SAMA5D2_CHER, BIT(chan->channel));
1350 at91_adc_writel(st, AT91_SAMA5D2_IER, BIT(chan->channel));
1351 at91_adc_writel(st, AT91_SAMA5D2_CR, AT91_SAMA5D2_CR_START);
1352
1353 ret = wait_event_interruptible_timeout(st->wq_data_available,
1354 st->conversion_done,
1355 msecs_to_jiffies(1000));
1356 if (ret == 0)
1357 ret = -ETIMEDOUT;
1358
1359 if (ret > 0) {
1360 *val = st->conversion_value;
1361 ret = at91_adc_adjust_val_osr(st, val);
1362 if (chan->scan_type.sign == 's')
1363 *val = sign_extend32(*val, 11);
1364 st->conversion_done = false;
1365 }
1366
1367 at91_adc_writel(st, AT91_SAMA5D2_IDR, BIT(chan->channel));
1368 at91_adc_writel(st, AT91_SAMA5D2_CHDR, BIT(chan->channel));
1369
1370 /* Needed to ACK the DRDY interruption */
1371 at91_adc_readl(st, AT91_SAMA5D2_LCDR);
1372
1373 mutex_unlock(&st->lock);
1374
1375 iio_device_release_direct_mode(indio_dev);
1376 return ret;
1377 }
1378
at91_adc_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long mask)1379 static int at91_adc_read_raw(struct iio_dev *indio_dev,
1380 struct iio_chan_spec const *chan,
1381 int *val, int *val2, long mask)
1382 {
1383 struct at91_adc_state *st = iio_priv(indio_dev);
1384
1385 switch (mask) {
1386 case IIO_CHAN_INFO_RAW:
1387 return at91_adc_read_info_raw(indio_dev, chan, val);
1388 case IIO_CHAN_INFO_SCALE:
1389 *val = st->vref_uv / 1000;
1390 if (chan->differential)
1391 *val *= 2;
1392 *val2 = chan->scan_type.realbits;
1393 return IIO_VAL_FRACTIONAL_LOG2;
1394
1395 case IIO_CHAN_INFO_SAMP_FREQ:
1396 *val = at91_adc_get_sample_freq(st);
1397 return IIO_VAL_INT;
1398
1399 case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
1400 *val = st->oversampling_ratio;
1401 return IIO_VAL_INT;
1402
1403 default:
1404 return -EINVAL;
1405 }
1406 }
1407
at91_adc_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long mask)1408 static int at91_adc_write_raw(struct iio_dev *indio_dev,
1409 struct iio_chan_spec const *chan,
1410 int val, int val2, long mask)
1411 {
1412 struct at91_adc_state *st = iio_priv(indio_dev);
1413
1414 switch (mask) {
1415 case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
1416 if ((val != AT91_OSR_1SAMPLES) && (val != AT91_OSR_4SAMPLES) &&
1417 (val != AT91_OSR_16SAMPLES))
1418 return -EINVAL;
1419 /* if no change, optimize out */
1420 if (val == st->oversampling_ratio)
1421 return 0;
1422 st->oversampling_ratio = val;
1423 /* update ratio */
1424 at91_adc_config_emr(st);
1425 return 0;
1426 case IIO_CHAN_INFO_SAMP_FREQ:
1427 if (val < st->soc_info.min_sample_rate ||
1428 val > st->soc_info.max_sample_rate)
1429 return -EINVAL;
1430
1431 at91_adc_setup_samp_freq(st, val);
1432 return 0;
1433 default:
1434 return -EINVAL;
1435 };
1436 }
1437
at91_adc_dma_init(struct platform_device * pdev)1438 static void at91_adc_dma_init(struct platform_device *pdev)
1439 {
1440 struct iio_dev *indio_dev = platform_get_drvdata(pdev);
1441 struct at91_adc_state *st = iio_priv(indio_dev);
1442 struct dma_slave_config config = {0};
1443 /*
1444 * We make the buffer double the size of the fifo,
1445 * such that DMA uses one half of the buffer (full fifo size)
1446 * and the software uses the other half to read/write.
1447 */
1448 unsigned int pages = DIV_ROUND_UP(AT91_HWFIFO_MAX_SIZE *
1449 AT91_BUFFER_MAX_CONVERSION_BYTES * 2,
1450 PAGE_SIZE);
1451
1452 if (st->dma_st.dma_chan)
1453 return;
1454
1455 st->dma_st.dma_chan = dma_request_slave_channel(&pdev->dev, "rx");
1456
1457 if (!st->dma_st.dma_chan) {
1458 dev_info(&pdev->dev, "can't get DMA channel\n");
1459 goto dma_exit;
1460 }
1461
1462 st->dma_st.rx_buf = dma_alloc_coherent(st->dma_st.dma_chan->device->dev,
1463 pages * PAGE_SIZE,
1464 &st->dma_st.rx_dma_buf,
1465 GFP_KERNEL);
1466 if (!st->dma_st.rx_buf) {
1467 dev_info(&pdev->dev, "can't allocate coherent DMA area\n");
1468 goto dma_chan_disable;
1469 }
1470
1471 /* Configure DMA channel to read data register */
1472 config.direction = DMA_DEV_TO_MEM;
1473 config.src_addr = (phys_addr_t)(st->dma_st.phys_addr
1474 + AT91_SAMA5D2_LCDR);
1475 config.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
1476 config.src_maxburst = 1;
1477 config.dst_maxburst = 1;
1478
1479 if (dmaengine_slave_config(st->dma_st.dma_chan, &config)) {
1480 dev_info(&pdev->dev, "can't configure DMA slave\n");
1481 goto dma_free_area;
1482 }
1483
1484 dev_info(&pdev->dev, "using %s for rx DMA transfers\n",
1485 dma_chan_name(st->dma_st.dma_chan));
1486
1487 return;
1488
1489 dma_free_area:
1490 dma_free_coherent(st->dma_st.dma_chan->device->dev, pages * PAGE_SIZE,
1491 st->dma_st.rx_buf, st->dma_st.rx_dma_buf);
1492 dma_chan_disable:
1493 dma_release_channel(st->dma_st.dma_chan);
1494 st->dma_st.dma_chan = 0;
1495 dma_exit:
1496 dev_info(&pdev->dev, "continuing without DMA support\n");
1497 }
1498
at91_adc_dma_disable(struct platform_device * pdev)1499 static void at91_adc_dma_disable(struct platform_device *pdev)
1500 {
1501 struct iio_dev *indio_dev = platform_get_drvdata(pdev);
1502 struct at91_adc_state *st = iio_priv(indio_dev);
1503 unsigned int pages = DIV_ROUND_UP(AT91_HWFIFO_MAX_SIZE *
1504 AT91_BUFFER_MAX_CONVERSION_BYTES * 2,
1505 PAGE_SIZE);
1506
1507 /* if we are not using DMA, just return */
1508 if (!st->dma_st.dma_chan)
1509 return;
1510
1511 /* wait for all transactions to be terminated first*/
1512 dmaengine_terminate_sync(st->dma_st.dma_chan);
1513
1514 dma_free_coherent(st->dma_st.dma_chan->device->dev, pages * PAGE_SIZE,
1515 st->dma_st.rx_buf, st->dma_st.rx_dma_buf);
1516 dma_release_channel(st->dma_st.dma_chan);
1517 st->dma_st.dma_chan = 0;
1518
1519 dev_info(&pdev->dev, "continuing without DMA support\n");
1520 }
1521
at91_adc_set_watermark(struct iio_dev * indio_dev,unsigned int val)1522 static int at91_adc_set_watermark(struct iio_dev *indio_dev, unsigned int val)
1523 {
1524 struct at91_adc_state *st = iio_priv(indio_dev);
1525
1526 if (val > AT91_HWFIFO_MAX_SIZE)
1527 return -EINVAL;
1528
1529 if (!st->selected_trig->hw_trig) {
1530 dev_dbg(&indio_dev->dev, "we need hw trigger for DMA\n");
1531 return 0;
1532 }
1533
1534 dev_dbg(&indio_dev->dev, "new watermark is %u\n", val);
1535 st->dma_st.watermark = val;
1536
1537 /*
1538 * The logic here is: if we have watermark 1, it means we do
1539 * each conversion with it's own IRQ, thus we don't need DMA.
1540 * If the watermark is higher, we do DMA to do all the transfers in bulk
1541 */
1542
1543 if (val == 1)
1544 at91_adc_dma_disable(to_platform_device(&indio_dev->dev));
1545 else if (val > 1)
1546 at91_adc_dma_init(to_platform_device(&indio_dev->dev));
1547
1548 return 0;
1549 }
1550
at91_adc_update_scan_mode(struct iio_dev * indio_dev,const unsigned long * scan_mask)1551 static int at91_adc_update_scan_mode(struct iio_dev *indio_dev,
1552 const unsigned long *scan_mask)
1553 {
1554 struct at91_adc_state *st = iio_priv(indio_dev);
1555
1556 if (bitmap_subset(scan_mask, &st->touch_st.channels_bitmask,
1557 AT91_SAMA5D2_MAX_CHAN_IDX + 1))
1558 return 0;
1559 /*
1560 * if the new bitmap is a combination of touchscreen and regular
1561 * channels, then we are not fine
1562 */
1563 if (bitmap_intersects(&st->touch_st.channels_bitmask, scan_mask,
1564 AT91_SAMA5D2_MAX_CHAN_IDX + 1))
1565 return -EINVAL;
1566 return 0;
1567 }
1568
at91_adc_hw_init(struct at91_adc_state * st)1569 static void at91_adc_hw_init(struct at91_adc_state *st)
1570 {
1571 at91_adc_writel(st, AT91_SAMA5D2_CR, AT91_SAMA5D2_CR_SWRST);
1572 at91_adc_writel(st, AT91_SAMA5D2_IDR, 0xffffffff);
1573 /*
1574 * Transfer field must be set to 2 according to the datasheet and
1575 * allows different analog settings for each channel.
1576 */
1577 at91_adc_writel(st, AT91_SAMA5D2_MR,
1578 AT91_SAMA5D2_MR_TRANSFER(2) | AT91_SAMA5D2_MR_ANACH);
1579
1580 at91_adc_setup_samp_freq(st, st->soc_info.min_sample_rate);
1581
1582 /* configure extended mode register */
1583 at91_adc_config_emr(st);
1584 }
1585
at91_adc_get_fifo_state(struct device * dev,struct device_attribute * attr,char * buf)1586 static ssize_t at91_adc_get_fifo_state(struct device *dev,
1587 struct device_attribute *attr, char *buf)
1588 {
1589 struct iio_dev *indio_dev =
1590 platform_get_drvdata(to_platform_device(dev));
1591 struct at91_adc_state *st = iio_priv(indio_dev);
1592
1593 return scnprintf(buf, PAGE_SIZE, "%d\n", !!st->dma_st.dma_chan);
1594 }
1595
at91_adc_get_watermark(struct device * dev,struct device_attribute * attr,char * buf)1596 static ssize_t at91_adc_get_watermark(struct device *dev,
1597 struct device_attribute *attr, char *buf)
1598 {
1599 struct iio_dev *indio_dev =
1600 platform_get_drvdata(to_platform_device(dev));
1601 struct at91_adc_state *st = iio_priv(indio_dev);
1602
1603 return scnprintf(buf, PAGE_SIZE, "%d\n", st->dma_st.watermark);
1604 }
1605
1606 static IIO_DEVICE_ATTR(hwfifo_enabled, 0444,
1607 at91_adc_get_fifo_state, NULL, 0);
1608 static IIO_DEVICE_ATTR(hwfifo_watermark, 0444,
1609 at91_adc_get_watermark, NULL, 0);
1610
1611 static IIO_CONST_ATTR(hwfifo_watermark_min, "2");
1612 static IIO_CONST_ATTR(hwfifo_watermark_max, AT91_HWFIFO_MAX_SIZE_STR);
1613
1614 static IIO_CONST_ATTR(oversampling_ratio_available,
1615 __stringify(AT91_OSR_1SAMPLES) " "
1616 __stringify(AT91_OSR_4SAMPLES) " "
1617 __stringify(AT91_OSR_16SAMPLES));
1618
1619 static struct attribute *at91_adc_attributes[] = {
1620 &iio_const_attr_oversampling_ratio_available.dev_attr.attr,
1621 NULL,
1622 };
1623
1624 static const struct attribute_group at91_adc_attribute_group = {
1625 .attrs = at91_adc_attributes,
1626 };
1627
1628 static const struct attribute *at91_adc_fifo_attributes[] = {
1629 &iio_const_attr_hwfifo_watermark_min.dev_attr.attr,
1630 &iio_const_attr_hwfifo_watermark_max.dev_attr.attr,
1631 &iio_dev_attr_hwfifo_watermark.dev_attr.attr,
1632 &iio_dev_attr_hwfifo_enabled.dev_attr.attr,
1633 NULL,
1634 };
1635
1636 static const struct iio_info at91_adc_info = {
1637 .attrs = &at91_adc_attribute_group,
1638 .read_raw = &at91_adc_read_raw,
1639 .write_raw = &at91_adc_write_raw,
1640 .update_scan_mode = &at91_adc_update_scan_mode,
1641 .of_xlate = &at91_adc_of_xlate,
1642 .hwfifo_set_watermark = &at91_adc_set_watermark,
1643 };
1644
at91_adc_probe(struct platform_device * pdev)1645 static int at91_adc_probe(struct platform_device *pdev)
1646 {
1647 struct iio_dev *indio_dev;
1648 struct at91_adc_state *st;
1649 struct resource *res;
1650 int ret, i;
1651 u32 edge_type = IRQ_TYPE_NONE;
1652
1653 indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*st));
1654 if (!indio_dev)
1655 return -ENOMEM;
1656
1657 indio_dev->dev.parent = &pdev->dev;
1658 indio_dev->name = dev_name(&pdev->dev);
1659 indio_dev->modes = INDIO_DIRECT_MODE | INDIO_BUFFER_SOFTWARE;
1660 indio_dev->info = &at91_adc_info;
1661 indio_dev->channels = at91_adc_channels;
1662 indio_dev->num_channels = ARRAY_SIZE(at91_adc_channels);
1663
1664 st = iio_priv(indio_dev);
1665
1666 bitmap_set(&st->touch_st.channels_bitmask,
1667 AT91_SAMA5D2_TOUCH_X_CHAN_IDX, 1);
1668 bitmap_set(&st->touch_st.channels_bitmask,
1669 AT91_SAMA5D2_TOUCH_Y_CHAN_IDX, 1);
1670 bitmap_set(&st->touch_st.channels_bitmask,
1671 AT91_SAMA5D2_TOUCH_P_CHAN_IDX, 1);
1672
1673 st->oversampling_ratio = AT91_OSR_1SAMPLES;
1674
1675 ret = of_property_read_u32(pdev->dev.of_node,
1676 "atmel,min-sample-rate-hz",
1677 &st->soc_info.min_sample_rate);
1678 if (ret) {
1679 dev_err(&pdev->dev,
1680 "invalid or missing value for atmel,min-sample-rate-hz\n");
1681 return ret;
1682 }
1683
1684 ret = of_property_read_u32(pdev->dev.of_node,
1685 "atmel,max-sample-rate-hz",
1686 &st->soc_info.max_sample_rate);
1687 if (ret) {
1688 dev_err(&pdev->dev,
1689 "invalid or missing value for atmel,max-sample-rate-hz\n");
1690 return ret;
1691 }
1692
1693 ret = of_property_read_u32(pdev->dev.of_node, "atmel,startup-time-ms",
1694 &st->soc_info.startup_time);
1695 if (ret) {
1696 dev_err(&pdev->dev,
1697 "invalid or missing value for atmel,startup-time-ms\n");
1698 return ret;
1699 }
1700
1701 ret = of_property_read_u32(pdev->dev.of_node,
1702 "atmel,trigger-edge-type", &edge_type);
1703 if (ret) {
1704 dev_dbg(&pdev->dev,
1705 "atmel,trigger-edge-type not specified, only software trigger available\n");
1706 }
1707
1708 st->selected_trig = NULL;
1709
1710 /* find the right trigger, or no trigger at all */
1711 for (i = 0; i < AT91_SAMA5D2_HW_TRIG_CNT + 1; i++)
1712 if (at91_adc_trigger_list[i].edge_type == edge_type) {
1713 st->selected_trig = &at91_adc_trigger_list[i];
1714 break;
1715 }
1716
1717 if (!st->selected_trig) {
1718 dev_err(&pdev->dev, "invalid external trigger edge value\n");
1719 return -EINVAL;
1720 }
1721
1722 init_waitqueue_head(&st->wq_data_available);
1723 mutex_init(&st->lock);
1724 INIT_WORK(&st->touch_st.workq, at91_adc_workq_handler);
1725
1726 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1727 if (!res)
1728 return -EINVAL;
1729
1730 /* if we plan to use DMA, we need the physical address of the regs */
1731 st->dma_st.phys_addr = res->start;
1732
1733 st->base = devm_ioremap_resource(&pdev->dev, res);
1734 if (IS_ERR(st->base))
1735 return PTR_ERR(st->base);
1736
1737 st->irq = platform_get_irq(pdev, 0);
1738 if (st->irq <= 0) {
1739 if (!st->irq)
1740 st->irq = -ENXIO;
1741
1742 return st->irq;
1743 }
1744
1745 st->per_clk = devm_clk_get(&pdev->dev, "adc_clk");
1746 if (IS_ERR(st->per_clk))
1747 return PTR_ERR(st->per_clk);
1748
1749 st->reg = devm_regulator_get(&pdev->dev, "vddana");
1750 if (IS_ERR(st->reg))
1751 return PTR_ERR(st->reg);
1752
1753 st->vref = devm_regulator_get(&pdev->dev, "vref");
1754 if (IS_ERR(st->vref))
1755 return PTR_ERR(st->vref);
1756
1757 ret = devm_request_irq(&pdev->dev, st->irq, at91_adc_interrupt, 0,
1758 pdev->dev.driver->name, indio_dev);
1759 if (ret)
1760 return ret;
1761
1762 ret = regulator_enable(st->reg);
1763 if (ret)
1764 return ret;
1765
1766 ret = regulator_enable(st->vref);
1767 if (ret)
1768 goto reg_disable;
1769
1770 st->vref_uv = regulator_get_voltage(st->vref);
1771 if (st->vref_uv <= 0) {
1772 ret = -EINVAL;
1773 goto vref_disable;
1774 }
1775
1776 at91_adc_hw_init(st);
1777
1778 ret = clk_prepare_enable(st->per_clk);
1779 if (ret)
1780 goto vref_disable;
1781
1782 platform_set_drvdata(pdev, indio_dev);
1783
1784 ret = at91_adc_buffer_init(indio_dev);
1785 if (ret < 0) {
1786 dev_err(&pdev->dev, "couldn't initialize the buffer.\n");
1787 goto per_clk_disable_unprepare;
1788 }
1789
1790 if (st->selected_trig->hw_trig) {
1791 ret = at91_adc_trigger_init(indio_dev);
1792 if (ret < 0) {
1793 dev_err(&pdev->dev, "couldn't setup the triggers.\n");
1794 goto per_clk_disable_unprepare;
1795 }
1796 /*
1797 * Initially the iio buffer has a length of 2 and
1798 * a watermark of 1
1799 */
1800 st->dma_st.watermark = 1;
1801
1802 iio_buffer_set_attrs(indio_dev->buffer,
1803 at91_adc_fifo_attributes);
1804 }
1805
1806 if (dma_coerce_mask_and_coherent(&indio_dev->dev, DMA_BIT_MASK(32)))
1807 dev_info(&pdev->dev, "cannot set DMA mask to 32-bit\n");
1808
1809 ret = iio_device_register(indio_dev);
1810 if (ret < 0)
1811 goto dma_disable;
1812
1813 if (st->selected_trig->hw_trig)
1814 dev_info(&pdev->dev, "setting up trigger as %s\n",
1815 st->selected_trig->name);
1816
1817 dev_info(&pdev->dev, "version: %x\n",
1818 readl_relaxed(st->base + AT91_SAMA5D2_VERSION));
1819
1820 return 0;
1821
1822 dma_disable:
1823 at91_adc_dma_disable(pdev);
1824 per_clk_disable_unprepare:
1825 clk_disable_unprepare(st->per_clk);
1826 vref_disable:
1827 regulator_disable(st->vref);
1828 reg_disable:
1829 regulator_disable(st->reg);
1830 return ret;
1831 }
1832
at91_adc_remove(struct platform_device * pdev)1833 static int at91_adc_remove(struct platform_device *pdev)
1834 {
1835 struct iio_dev *indio_dev = platform_get_drvdata(pdev);
1836 struct at91_adc_state *st = iio_priv(indio_dev);
1837
1838 iio_device_unregister(indio_dev);
1839
1840 at91_adc_dma_disable(pdev);
1841
1842 clk_disable_unprepare(st->per_clk);
1843
1844 regulator_disable(st->vref);
1845 regulator_disable(st->reg);
1846
1847 return 0;
1848 }
1849
at91_adc_suspend(struct device * dev)1850 static __maybe_unused int at91_adc_suspend(struct device *dev)
1851 {
1852 struct iio_dev *indio_dev =
1853 platform_get_drvdata(to_platform_device(dev));
1854 struct at91_adc_state *st = iio_priv(indio_dev);
1855
1856 /*
1857 * Do a sofware reset of the ADC before we go to suspend.
1858 * this will ensure that all pins are free from being muxed by the ADC
1859 * and can be used by for other devices.
1860 * Otherwise, ADC will hog them and we can't go to suspend mode.
1861 */
1862 at91_adc_writel(st, AT91_SAMA5D2_CR, AT91_SAMA5D2_CR_SWRST);
1863
1864 clk_disable_unprepare(st->per_clk);
1865 regulator_disable(st->vref);
1866 regulator_disable(st->reg);
1867
1868 return pinctrl_pm_select_sleep_state(dev);
1869 }
1870
at91_adc_resume(struct device * dev)1871 static __maybe_unused int at91_adc_resume(struct device *dev)
1872 {
1873 struct iio_dev *indio_dev =
1874 platform_get_drvdata(to_platform_device(dev));
1875 struct at91_adc_state *st = iio_priv(indio_dev);
1876 int ret;
1877
1878 ret = pinctrl_pm_select_default_state(dev);
1879 if (ret)
1880 goto resume_failed;
1881
1882 ret = regulator_enable(st->reg);
1883 if (ret)
1884 goto resume_failed;
1885
1886 ret = regulator_enable(st->vref);
1887 if (ret)
1888 goto reg_disable_resume;
1889
1890 ret = clk_prepare_enable(st->per_clk);
1891 if (ret)
1892 goto vref_disable_resume;
1893
1894 at91_adc_hw_init(st);
1895
1896 /* reconfiguring trigger hardware state */
1897 if (!iio_buffer_enabled(indio_dev))
1898 return 0;
1899
1900 /* check if we are enabling triggered buffer or the touchscreen */
1901 if (bitmap_subset(indio_dev->active_scan_mask,
1902 &st->touch_st.channels_bitmask,
1903 AT91_SAMA5D2_MAX_CHAN_IDX + 1)) {
1904 /* touchscreen enabling */
1905 return at91_adc_configure_touch(st, true);
1906 } else {
1907 return at91_adc_configure_trigger(st->trig, true);
1908 }
1909
1910 /* not needed but more explicit */
1911 return 0;
1912
1913 vref_disable_resume:
1914 regulator_disable(st->vref);
1915 reg_disable_resume:
1916 regulator_disable(st->reg);
1917 resume_failed:
1918 dev_err(&indio_dev->dev, "failed to resume\n");
1919 return ret;
1920 }
1921
1922 static SIMPLE_DEV_PM_OPS(at91_adc_pm_ops, at91_adc_suspend, at91_adc_resume);
1923
1924 static const struct of_device_id at91_adc_dt_match[] = {
1925 {
1926 .compatible = "atmel,sama5d2-adc",
1927 }, {
1928 /* sentinel */
1929 }
1930 };
1931 MODULE_DEVICE_TABLE(of, at91_adc_dt_match);
1932
1933 static struct platform_driver at91_adc_driver = {
1934 .probe = at91_adc_probe,
1935 .remove = at91_adc_remove,
1936 .driver = {
1937 .name = "at91-sama5d2_adc",
1938 .of_match_table = at91_adc_dt_match,
1939 .pm = &at91_adc_pm_ops,
1940 },
1941 };
1942 module_platform_driver(at91_adc_driver)
1943
1944 MODULE_AUTHOR("Ludovic Desroches <ludovic.desroches@atmel.com>");
1945 MODULE_DESCRIPTION("Atmel AT91 SAMA5D2 ADC");
1946 MODULE_LICENSE("GPL v2");
1947
