1 /*
2 * Copyright (c) 2003-2015 Broadcom Corporation
3 *
4 * This file is licensed under the terms of the GNU General Public
5 * License version 2. This program is licensed "as is" without any
6 * warranty of any kind, whether express or implied.
7 */
8
9 #include <linux/acpi.h>
10 #include <linux/clk.h>
11 #include <linux/completion.h>
12 #include <linux/i2c.h>
13 #include <linux/i2c-smbus.h>
14 #include <linux/init.h>
15 #include <linux/interrupt.h>
16 #include <linux/io.h>
17 #include <linux/kernel.h>
18 #include <linux/module.h>
19 #include <linux/platform_device.h>
20 #include <linux/delay.h>
21
22 #define XLP9XX_I2C_DIV 0x0
23 #define XLP9XX_I2C_CTRL 0x1
24 #define XLP9XX_I2C_CMD 0x2
25 #define XLP9XX_I2C_STATUS 0x3
26 #define XLP9XX_I2C_MTXFIFO 0x4
27 #define XLP9XX_I2C_MRXFIFO 0x5
28 #define XLP9XX_I2C_MFIFOCTRL 0x6
29 #define XLP9XX_I2C_STXFIFO 0x7
30 #define XLP9XX_I2C_SRXFIFO 0x8
31 #define XLP9XX_I2C_SFIFOCTRL 0x9
32 #define XLP9XX_I2C_SLAVEADDR 0xA
33 #define XLP9XX_I2C_OWNADDR 0xB
34 #define XLP9XX_I2C_FIFOWCNT 0xC
35 #define XLP9XX_I2C_INTEN 0xD
36 #define XLP9XX_I2C_INTST 0xE
37 #define XLP9XX_I2C_WAITCNT 0xF
38 #define XLP9XX_I2C_TIMEOUT 0X10
39 #define XLP9XX_I2C_GENCALLADDR 0x11
40
41 #define XLP9XX_I2C_STATUS_BUSY BIT(0)
42
43 #define XLP9XX_I2C_CMD_START BIT(7)
44 #define XLP9XX_I2C_CMD_STOP BIT(6)
45 #define XLP9XX_I2C_CMD_READ BIT(5)
46 #define XLP9XX_I2C_CMD_WRITE BIT(4)
47 #define XLP9XX_I2C_CMD_ACK BIT(3)
48
49 #define XLP9XX_I2C_CTRL_MCTLEN_SHIFT 16
50 #define XLP9XX_I2C_CTRL_MCTLEN_MASK 0xffff0000
51 #define XLP9XX_I2C_CTRL_RST BIT(8)
52 #define XLP9XX_I2C_CTRL_EN BIT(6)
53 #define XLP9XX_I2C_CTRL_MASTER BIT(4)
54 #define XLP9XX_I2C_CTRL_FIFORD BIT(1)
55 #define XLP9XX_I2C_CTRL_ADDMODE BIT(0)
56
57 #define XLP9XX_I2C_INTEN_NACKADDR BIT(25)
58 #define XLP9XX_I2C_INTEN_SADDR BIT(13)
59 #define XLP9XX_I2C_INTEN_DATADONE BIT(12)
60 #define XLP9XX_I2C_INTEN_ARLOST BIT(11)
61 #define XLP9XX_I2C_INTEN_MFIFOFULL BIT(4)
62 #define XLP9XX_I2C_INTEN_MFIFOEMTY BIT(3)
63 #define XLP9XX_I2C_INTEN_MFIFOHI BIT(2)
64 #define XLP9XX_I2C_INTEN_BUSERR BIT(0)
65
66 #define XLP9XX_I2C_MFIFOCTRL_HITH_SHIFT 8
67 #define XLP9XX_I2C_MFIFOCTRL_LOTH_SHIFT 0
68 #define XLP9XX_I2C_MFIFOCTRL_RST BIT(16)
69
70 #define XLP9XX_I2C_SLAVEADDR_RW BIT(0)
71 #define XLP9XX_I2C_SLAVEADDR_ADDR_SHIFT 1
72
73 #define XLP9XX_I2C_IP_CLK_FREQ 133000000UL
74 #define XLP9XX_I2C_DEFAULT_FREQ 100000
75 #define XLP9XX_I2C_HIGH_FREQ 400000
76 #define XLP9XX_I2C_FIFO_SIZE 0x80U
77 #define XLP9XX_I2C_TIMEOUT_MS 1000
78 #define XLP9XX_I2C_BUSY_TIMEOUT 50
79
80 #define XLP9XX_I2C_FIFO_WCNT_MASK 0xff
81 #define XLP9XX_I2C_STATUS_ERRMASK (XLP9XX_I2C_INTEN_ARLOST | \
82 XLP9XX_I2C_INTEN_NACKADDR | XLP9XX_I2C_INTEN_BUSERR)
83
84 struct xlp9xx_i2c_dev {
85 struct device *dev;
86 struct i2c_adapter adapter;
87 struct completion msg_complete;
88 struct i2c_smbus_alert_setup alert_data;
89 struct i2c_client *ara;
90 int irq;
91 bool msg_read;
92 bool len_recv;
93 bool client_pec;
94 u32 __iomem *base;
95 u32 msg_buf_remaining;
96 u32 msg_len;
97 u32 ip_clk_hz;
98 u32 clk_hz;
99 u32 msg_err;
100 u8 *msg_buf;
101 };
102
xlp9xx_write_i2c_reg(struct xlp9xx_i2c_dev * priv,unsigned long reg,u32 val)103 static inline void xlp9xx_write_i2c_reg(struct xlp9xx_i2c_dev *priv,
104 unsigned long reg, u32 val)
105 {
106 writel(val, priv->base + reg);
107 }
108
xlp9xx_read_i2c_reg(struct xlp9xx_i2c_dev * priv,unsigned long reg)109 static inline u32 xlp9xx_read_i2c_reg(struct xlp9xx_i2c_dev *priv,
110 unsigned long reg)
111 {
112 return readl(priv->base + reg);
113 }
114
xlp9xx_i2c_mask_irq(struct xlp9xx_i2c_dev * priv,u32 mask)115 static void xlp9xx_i2c_mask_irq(struct xlp9xx_i2c_dev *priv, u32 mask)
116 {
117 u32 inten;
118
119 inten = xlp9xx_read_i2c_reg(priv, XLP9XX_I2C_INTEN) & ~mask;
120 xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_INTEN, inten);
121 }
122
xlp9xx_i2c_unmask_irq(struct xlp9xx_i2c_dev * priv,u32 mask)123 static void xlp9xx_i2c_unmask_irq(struct xlp9xx_i2c_dev *priv, u32 mask)
124 {
125 u32 inten;
126
127 inten = xlp9xx_read_i2c_reg(priv, XLP9XX_I2C_INTEN) | mask;
128 xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_INTEN, inten);
129 }
130
xlp9xx_i2c_update_rx_fifo_thres(struct xlp9xx_i2c_dev * priv)131 static void xlp9xx_i2c_update_rx_fifo_thres(struct xlp9xx_i2c_dev *priv)
132 {
133 u32 thres;
134
135 if (priv->len_recv)
136 /* interrupt after the first read to examine
137 * the length byte before proceeding further
138 */
139 thres = 1;
140 else if (priv->msg_buf_remaining > XLP9XX_I2C_FIFO_SIZE)
141 thres = XLP9XX_I2C_FIFO_SIZE;
142 else
143 thres = priv->msg_buf_remaining;
144
145 xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_MFIFOCTRL,
146 thres << XLP9XX_I2C_MFIFOCTRL_HITH_SHIFT);
147 }
148
xlp9xx_i2c_fill_tx_fifo(struct xlp9xx_i2c_dev * priv)149 static void xlp9xx_i2c_fill_tx_fifo(struct xlp9xx_i2c_dev *priv)
150 {
151 u32 len, i;
152 u8 *buf = priv->msg_buf;
153
154 len = min(priv->msg_buf_remaining, XLP9XX_I2C_FIFO_SIZE);
155 for (i = 0; i < len; i++)
156 xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_MTXFIFO, buf[i]);
157 priv->msg_buf_remaining -= len;
158 priv->msg_buf += len;
159 }
160
xlp9xx_i2c_update_rlen(struct xlp9xx_i2c_dev * priv)161 static void xlp9xx_i2c_update_rlen(struct xlp9xx_i2c_dev *priv)
162 {
163 u32 val, len;
164
165 /*
166 * Update receive length. Re-read len to get the latest value,
167 * and then add 4 to have a minimum value that can be safely
168 * written. This is to account for the byte read above, the
169 * transfer in progress and any delays in the register I/O
170 */
171 val = xlp9xx_read_i2c_reg(priv, XLP9XX_I2C_CTRL);
172 len = xlp9xx_read_i2c_reg(priv, XLP9XX_I2C_FIFOWCNT) &
173 XLP9XX_I2C_FIFO_WCNT_MASK;
174 len = max_t(u32, priv->msg_len, len + 4);
175 if (len >= I2C_SMBUS_BLOCK_MAX + 2)
176 return;
177 val = (val & ~XLP9XX_I2C_CTRL_MCTLEN_MASK) |
178 (len << XLP9XX_I2C_CTRL_MCTLEN_SHIFT);
179 xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_CTRL, val);
180 }
181
xlp9xx_i2c_drain_rx_fifo(struct xlp9xx_i2c_dev * priv)182 static void xlp9xx_i2c_drain_rx_fifo(struct xlp9xx_i2c_dev *priv)
183 {
184 u32 len, i;
185 u8 rlen, *buf = priv->msg_buf;
186
187 len = xlp9xx_read_i2c_reg(priv, XLP9XX_I2C_FIFOWCNT) &
188 XLP9XX_I2C_FIFO_WCNT_MASK;
189 if (!len)
190 return;
191 if (priv->len_recv) {
192 /* read length byte */
193 rlen = xlp9xx_read_i2c_reg(priv, XLP9XX_I2C_MRXFIFO);
194
195 /*
196 * We expect at least 2 interrupts for I2C_M_RECV_LEN
197 * transactions. The length is updated during the first
198 * interrupt, and the buffer contents are only copied
199 * during subsequent interrupts. If in case the interrupts
200 * get merged we would complete the transaction without
201 * copying out the bytes from RX fifo. To avoid this now we
202 * drain the fifo as and when data is available.
203 * We drained the rlen byte already, decrement total length
204 * by one.
205 */
206
207 len--;
208 if (rlen > I2C_SMBUS_BLOCK_MAX || rlen == 0) {
209 rlen = 0; /*abort transfer */
210 priv->msg_buf_remaining = 0;
211 priv->msg_len = 0;
212 xlp9xx_i2c_update_rlen(priv);
213 return;
214 }
215
216 *buf++ = rlen;
217 if (priv->client_pec)
218 ++rlen; /* account for error check byte */
219 /* update remaining bytes and message length */
220 priv->msg_buf_remaining = rlen;
221 priv->msg_len = rlen + 1;
222 xlp9xx_i2c_update_rlen(priv);
223 priv->len_recv = false;
224 }
225
226 len = min(priv->msg_buf_remaining, len);
227 for (i = 0; i < len; i++, buf++)
228 *buf = xlp9xx_read_i2c_reg(priv, XLP9XX_I2C_MRXFIFO);
229
230 priv->msg_buf_remaining -= len;
231 priv->msg_buf = buf;
232
233 if (priv->msg_buf_remaining)
234 xlp9xx_i2c_update_rx_fifo_thres(priv);
235 }
236
xlp9xx_i2c_isr(int irq,void * dev_id)237 static irqreturn_t xlp9xx_i2c_isr(int irq, void *dev_id)
238 {
239 struct xlp9xx_i2c_dev *priv = dev_id;
240 u32 status;
241
242 status = xlp9xx_read_i2c_reg(priv, XLP9XX_I2C_INTST);
243 if (status == 0)
244 return IRQ_NONE;
245
246 xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_INTST, status);
247 if (status & XLP9XX_I2C_STATUS_ERRMASK) {
248 priv->msg_err = status;
249 goto xfer_done;
250 }
251
252 /* SADDR ACK for SMBUS_QUICK */
253 if ((status & XLP9XX_I2C_INTEN_SADDR) && (priv->msg_len == 0))
254 goto xfer_done;
255
256 if (!priv->msg_read) {
257 if (status & XLP9XX_I2C_INTEN_MFIFOEMTY) {
258 /* TX FIFO got empty, fill it up again */
259 if (priv->msg_buf_remaining)
260 xlp9xx_i2c_fill_tx_fifo(priv);
261 else
262 xlp9xx_i2c_mask_irq(priv,
263 XLP9XX_I2C_INTEN_MFIFOEMTY);
264 }
265 } else {
266 if (status & (XLP9XX_I2C_INTEN_DATADONE |
267 XLP9XX_I2C_INTEN_MFIFOHI)) {
268 /* data is in FIFO, read it */
269 if (priv->msg_buf_remaining)
270 xlp9xx_i2c_drain_rx_fifo(priv);
271 }
272 }
273
274 /* Transfer complete */
275 if (status & XLP9XX_I2C_INTEN_DATADONE)
276 goto xfer_done;
277
278 return IRQ_HANDLED;
279
280 xfer_done:
281 xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_INTEN, 0);
282 complete(&priv->msg_complete);
283 return IRQ_HANDLED;
284 }
285
xlp9xx_i2c_check_bus_status(struct xlp9xx_i2c_dev * priv)286 static int xlp9xx_i2c_check_bus_status(struct xlp9xx_i2c_dev *priv)
287 {
288 u32 status;
289 u32 busy_timeout = XLP9XX_I2C_BUSY_TIMEOUT;
290
291 while (busy_timeout) {
292 status = xlp9xx_read_i2c_reg(priv, XLP9XX_I2C_STATUS);
293 if ((status & XLP9XX_I2C_STATUS_BUSY) == 0)
294 break;
295
296 busy_timeout--;
297 usleep_range(1000, 1100);
298 }
299
300 if (!busy_timeout)
301 return -EIO;
302
303 return 0;
304 }
305
xlp9xx_i2c_init(struct xlp9xx_i2c_dev * priv)306 static int xlp9xx_i2c_init(struct xlp9xx_i2c_dev *priv)
307 {
308 u32 prescale;
309
310 /*
311 * The controller uses 5 * SCL clock internally.
312 * So prescale value should be divided by 5.
313 */
314 prescale = DIV_ROUND_UP(priv->ip_clk_hz, priv->clk_hz);
315 prescale = ((prescale - 8) / 5) - 1;
316 xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_CTRL, XLP9XX_I2C_CTRL_RST);
317 xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_CTRL, XLP9XX_I2C_CTRL_EN |
318 XLP9XX_I2C_CTRL_MASTER);
319 xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_DIV, prescale);
320 xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_INTEN, 0);
321
322 return 0;
323 }
324
xlp9xx_i2c_xfer_msg(struct xlp9xx_i2c_dev * priv,struct i2c_msg * msg,int last_msg)325 static int xlp9xx_i2c_xfer_msg(struct xlp9xx_i2c_dev *priv, struct i2c_msg *msg,
326 int last_msg)
327 {
328 unsigned long timeleft;
329 u32 intr_mask, cmd, val, len;
330
331 priv->msg_buf = msg->buf;
332 priv->msg_buf_remaining = priv->msg_len = msg->len;
333 priv->msg_err = 0;
334 priv->msg_read = (msg->flags & I2C_M_RD);
335 reinit_completion(&priv->msg_complete);
336
337 /* Reset FIFO */
338 xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_MFIFOCTRL,
339 XLP9XX_I2C_MFIFOCTRL_RST);
340
341 /* set slave addr */
342 xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_SLAVEADDR,
343 (msg->addr << XLP9XX_I2C_SLAVEADDR_ADDR_SHIFT) |
344 (priv->msg_read ? XLP9XX_I2C_SLAVEADDR_RW : 0));
345
346 /* Build control word for transfer */
347 val = xlp9xx_read_i2c_reg(priv, XLP9XX_I2C_CTRL);
348 if (!priv->msg_read)
349 val &= ~XLP9XX_I2C_CTRL_FIFORD;
350 else
351 val |= XLP9XX_I2C_CTRL_FIFORD; /* read */
352
353 if (msg->flags & I2C_M_TEN)
354 val |= XLP9XX_I2C_CTRL_ADDMODE; /* 10-bit address mode*/
355 else
356 val &= ~XLP9XX_I2C_CTRL_ADDMODE;
357
358 priv->len_recv = msg->flags & I2C_M_RECV_LEN;
359 len = priv->len_recv ? I2C_SMBUS_BLOCK_MAX + 2 : msg->len;
360 priv->client_pec = msg->flags & I2C_CLIENT_PEC;
361
362 /* set FIFO threshold if reading */
363 if (priv->msg_read)
364 xlp9xx_i2c_update_rx_fifo_thres(priv);
365
366 /* set data length to be transferred */
367 val = (val & ~XLP9XX_I2C_CTRL_MCTLEN_MASK) |
368 (len << XLP9XX_I2C_CTRL_MCTLEN_SHIFT);
369 xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_CTRL, val);
370
371 /* fill fifo during tx */
372 if (!priv->msg_read)
373 xlp9xx_i2c_fill_tx_fifo(priv);
374
375 /* set interrupt mask */
376 intr_mask = (XLP9XX_I2C_INTEN_ARLOST | XLP9XX_I2C_INTEN_BUSERR |
377 XLP9XX_I2C_INTEN_NACKADDR | XLP9XX_I2C_INTEN_DATADONE);
378
379 if (priv->msg_read) {
380 intr_mask |= XLP9XX_I2C_INTEN_MFIFOHI;
381 if (msg->len == 0)
382 intr_mask |= XLP9XX_I2C_INTEN_SADDR;
383 } else {
384 if (msg->len == 0)
385 intr_mask |= XLP9XX_I2C_INTEN_SADDR;
386 else
387 intr_mask |= XLP9XX_I2C_INTEN_MFIFOEMTY;
388 }
389 xlp9xx_i2c_unmask_irq(priv, intr_mask);
390
391 /* set cmd reg */
392 cmd = XLP9XX_I2C_CMD_START;
393 if (msg->len)
394 cmd |= (priv->msg_read ?
395 XLP9XX_I2C_CMD_READ : XLP9XX_I2C_CMD_WRITE);
396 if (last_msg)
397 cmd |= XLP9XX_I2C_CMD_STOP;
398
399 xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_CMD, cmd);
400
401 timeleft = msecs_to_jiffies(XLP9XX_I2C_TIMEOUT_MS);
402 timeleft = wait_for_completion_timeout(&priv->msg_complete, timeleft);
403
404 if (priv->msg_err & XLP9XX_I2C_INTEN_BUSERR) {
405 dev_dbg(priv->dev, "transfer error %x!\n", priv->msg_err);
406 xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_CMD, XLP9XX_I2C_CMD_STOP);
407 return -EIO;
408 } else if (priv->msg_err & XLP9XX_I2C_INTEN_NACKADDR) {
409 return -ENXIO;
410 }
411
412 if (timeleft == 0) {
413 dev_dbg(priv->dev, "i2c transfer timed out!\n");
414 xlp9xx_i2c_init(priv);
415 return -ETIMEDOUT;
416 }
417
418 /* update msg->len with actual received length */
419 if (msg->flags & I2C_M_RECV_LEN) {
420 if (!priv->msg_len)
421 return -EPROTO;
422 msg->len = priv->msg_len;
423 }
424 return 0;
425 }
426
xlp9xx_i2c_xfer(struct i2c_adapter * adap,struct i2c_msg * msgs,int num)427 static int xlp9xx_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
428 int num)
429 {
430 int i, ret;
431 struct xlp9xx_i2c_dev *priv = i2c_get_adapdata(adap);
432
433 ret = xlp9xx_i2c_check_bus_status(priv);
434 if (ret) {
435 xlp9xx_i2c_init(priv);
436 ret = xlp9xx_i2c_check_bus_status(priv);
437 if (ret)
438 return ret;
439 }
440
441 for (i = 0; i < num; i++) {
442 ret = xlp9xx_i2c_xfer_msg(priv, &msgs[i], i == num - 1);
443 if (ret != 0)
444 return ret;
445 }
446
447 return num;
448 }
449
xlp9xx_i2c_functionality(struct i2c_adapter * adapter)450 static u32 xlp9xx_i2c_functionality(struct i2c_adapter *adapter)
451 {
452 return I2C_FUNC_SMBUS_EMUL | I2C_FUNC_SMBUS_READ_BLOCK_DATA |
453 I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR;
454 }
455
456 static const struct i2c_algorithm xlp9xx_i2c_algo = {
457 .master_xfer = xlp9xx_i2c_xfer,
458 .functionality = xlp9xx_i2c_functionality,
459 };
460
xlp9xx_i2c_get_frequency(struct platform_device * pdev,struct xlp9xx_i2c_dev * priv)461 static int xlp9xx_i2c_get_frequency(struct platform_device *pdev,
462 struct xlp9xx_i2c_dev *priv)
463 {
464 struct clk *clk;
465 u32 freq;
466 int err;
467
468 clk = devm_clk_get(&pdev->dev, NULL);
469 if (IS_ERR(clk)) {
470 priv->ip_clk_hz = XLP9XX_I2C_IP_CLK_FREQ;
471 dev_dbg(&pdev->dev, "using default input frequency %u\n",
472 priv->ip_clk_hz);
473 } else {
474 priv->ip_clk_hz = clk_get_rate(clk);
475 }
476
477 err = device_property_read_u32(&pdev->dev, "clock-frequency", &freq);
478 if (err) {
479 freq = XLP9XX_I2C_DEFAULT_FREQ;
480 dev_dbg(&pdev->dev, "using default frequency %u\n", freq);
481 } else if (freq == 0 || freq > XLP9XX_I2C_HIGH_FREQ) {
482 dev_warn(&pdev->dev, "invalid frequency %u, using default\n",
483 freq);
484 freq = XLP9XX_I2C_DEFAULT_FREQ;
485 }
486 priv->clk_hz = freq;
487
488 return 0;
489 }
490
xlp9xx_i2c_smbus_setup(struct xlp9xx_i2c_dev * priv,struct platform_device * pdev)491 static int xlp9xx_i2c_smbus_setup(struct xlp9xx_i2c_dev *priv,
492 struct platform_device *pdev)
493 {
494 if (!priv->alert_data.irq)
495 return -EINVAL;
496
497 priv->ara = i2c_setup_smbus_alert(&priv->adapter, &priv->alert_data);
498 if (!priv->ara)
499 return -ENODEV;
500
501 return 0;
502 }
503
xlp9xx_i2c_probe(struct platform_device * pdev)504 static int xlp9xx_i2c_probe(struct platform_device *pdev)
505 {
506 struct xlp9xx_i2c_dev *priv;
507 struct resource *res;
508 int err = 0;
509
510 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
511 if (!priv)
512 return -ENOMEM;
513
514 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
515 priv->base = devm_ioremap_resource(&pdev->dev, res);
516 if (IS_ERR(priv->base))
517 return PTR_ERR(priv->base);
518
519 priv->irq = platform_get_irq(pdev, 0);
520 if (priv->irq <= 0) {
521 dev_err(&pdev->dev, "invalid irq!\n");
522 return priv->irq;
523 }
524 /* SMBAlert irq */
525 priv->alert_data.irq = platform_get_irq(pdev, 1);
526 if (priv->alert_data.irq <= 0)
527 priv->alert_data.irq = 0;
528
529 xlp9xx_i2c_get_frequency(pdev, priv);
530 xlp9xx_i2c_init(priv);
531
532 err = devm_request_irq(&pdev->dev, priv->irq, xlp9xx_i2c_isr, 0,
533 pdev->name, priv);
534 if (err) {
535 dev_err(&pdev->dev, "IRQ request failed!\n");
536 return err;
537 }
538
539 init_completion(&priv->msg_complete);
540 priv->adapter.dev.parent = &pdev->dev;
541 priv->adapter.algo = &xlp9xx_i2c_algo;
542 priv->adapter.class = I2C_CLASS_HWMON;
543 ACPI_COMPANION_SET(&priv->adapter.dev, ACPI_COMPANION(&pdev->dev));
544 priv->adapter.dev.of_node = pdev->dev.of_node;
545 priv->dev = &pdev->dev;
546
547 snprintf(priv->adapter.name, sizeof(priv->adapter.name), "xlp9xx-i2c");
548 i2c_set_adapdata(&priv->adapter, priv);
549
550 err = i2c_add_adapter(&priv->adapter);
551 if (err)
552 return err;
553
554 err = xlp9xx_i2c_smbus_setup(priv, pdev);
555 if (err)
556 dev_dbg(&pdev->dev, "No active SMBus alert %d\n", err);
557
558 platform_set_drvdata(pdev, priv);
559 dev_dbg(&pdev->dev, "I2C bus:%d added\n", priv->adapter.nr);
560
561 return 0;
562 }
563
xlp9xx_i2c_remove(struct platform_device * pdev)564 static int xlp9xx_i2c_remove(struct platform_device *pdev)
565 {
566 struct xlp9xx_i2c_dev *priv;
567
568 priv = platform_get_drvdata(pdev);
569 xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_INTEN, 0);
570 synchronize_irq(priv->irq);
571 i2c_del_adapter(&priv->adapter);
572 xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_CTRL, 0);
573
574 return 0;
575 }
576
577 static const struct of_device_id xlp9xx_i2c_of_match[] = {
578 { .compatible = "netlogic,xlp980-i2c", },
579 { /* sentinel */ },
580 };
581 MODULE_DEVICE_TABLE(of, xlp9xx_i2c_of_match);
582
583 #ifdef CONFIG_ACPI
584 static const struct acpi_device_id xlp9xx_i2c_acpi_ids[] = {
585 {"BRCM9007", 0},
586 {"CAV9007", 0},
587 {}
588 };
589 MODULE_DEVICE_TABLE(acpi, xlp9xx_i2c_acpi_ids);
590 #endif
591
592 static struct platform_driver xlp9xx_i2c_driver = {
593 .probe = xlp9xx_i2c_probe,
594 .remove = xlp9xx_i2c_remove,
595 .driver = {
596 .name = "xlp9xx-i2c",
597 .of_match_table = xlp9xx_i2c_of_match,
598 .acpi_match_table = ACPI_PTR(xlp9xx_i2c_acpi_ids),
599 },
600 };
601
602 module_platform_driver(xlp9xx_i2c_driver);
603
604 MODULE_AUTHOR("Subhendu Sekhar Behera <sbehera@broadcom.com>");
605 MODULE_DESCRIPTION("XLP9XX/5XX I2C Bus Controller Driver");
606 MODULE_LICENSE("GPL v2");
607
