1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) 2012 FUJITSU SEMICONDUCTOR LIMITED
4 */
5
6 #include <linux/acpi.h>
7 #include <linux/clk.h>
8 #include <linux/delay.h>
9 #include <linux/device.h>
10 #include <linux/err.h>
11 #include <linux/errno.h>
12 #include <linux/i2c.h>
13 #include <linux/interrupt.h>
14 #include <linux/io.h>
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/platform_device.h>
18 #include <linux/sched.h>
19 #include <linux/slab.h>
20 #include <linux/spinlock.h>
21
22 #define WAIT_PCLK(n, rate) \
23 ndelay(DIV_ROUND_UP(DIV_ROUND_UP(1000000000, rate), n) + 10)
24
25 /* I2C register address definitions */
26 #define SYNQUACER_I2C_REG_BSR (0x00 << 2) // Bus Status
27 #define SYNQUACER_I2C_REG_BCR (0x01 << 2) // Bus Control
28 #define SYNQUACER_I2C_REG_CCR (0x02 << 2) // Clock Control
29 #define SYNQUACER_I2C_REG_ADR (0x03 << 2) // Address
30 #define SYNQUACER_I2C_REG_DAR (0x04 << 2) // Data
31 #define SYNQUACER_I2C_REG_CSR (0x05 << 2) // Expansion CS
32 #define SYNQUACER_I2C_REG_FSR (0x06 << 2) // Bus Clock Freq
33 #define SYNQUACER_I2C_REG_BC2R (0x07 << 2) // Bus Control 2
34
35 /* I2C register bit definitions */
36 #define SYNQUACER_I2C_BSR_FBT BIT(0) // First Byte Transfer
37 #define SYNQUACER_I2C_BSR_GCA BIT(1) // General Call Address
38 #define SYNQUACER_I2C_BSR_AAS BIT(2) // Address as Slave
39 #define SYNQUACER_I2C_BSR_TRX BIT(3) // Transfer/Receive
40 #define SYNQUACER_I2C_BSR_LRB BIT(4) // Last Received Bit
41 #define SYNQUACER_I2C_BSR_AL BIT(5) // Arbitration Lost
42 #define SYNQUACER_I2C_BSR_RSC BIT(6) // Repeated Start Cond.
43 #define SYNQUACER_I2C_BSR_BB BIT(7) // Bus Busy
44
45 #define SYNQUACER_I2C_BCR_INT BIT(0) // Interrupt
46 #define SYNQUACER_I2C_BCR_INTE BIT(1) // Interrupt Enable
47 #define SYNQUACER_I2C_BCR_GCAA BIT(2) // Gen. Call Access Ack.
48 #define SYNQUACER_I2C_BCR_ACK BIT(3) // Acknowledge
49 #define SYNQUACER_I2C_BCR_MSS BIT(4) // Master Slave Select
50 #define SYNQUACER_I2C_BCR_SCC BIT(5) // Start Condition Cont.
51 #define SYNQUACER_I2C_BCR_BEIE BIT(6) // Bus Error Int Enable
52 #define SYNQUACER_I2C_BCR_BER BIT(7) // Bus Error
53
54 #define SYNQUACER_I2C_CCR_CS_MASK (0x1f) // CCR Clock Period Sel.
55 #define SYNQUACER_I2C_CCR_EN BIT(5) // Enable
56 #define SYNQUACER_I2C_CCR_FM BIT(6) // Speed Mode Select
57
58 #define SYNQUACER_I2C_CSR_CS_MASK (0x3f) // CSR Clock Period Sel.
59
60 #define SYNQUACER_I2C_BC2R_SCLL BIT(0) // SCL Low Drive
61 #define SYNQUACER_I2C_BC2R_SDAL BIT(1) // SDA Low Drive
62 #define SYNQUACER_I2C_BC2R_SCLS BIT(4) // SCL Status
63 #define SYNQUACER_I2C_BC2R_SDAS BIT(5) // SDA Status
64
65 /* PCLK frequency */
66 #define SYNQUACER_I2C_BUS_CLK_FR(rate) (((rate) / 20000000) + 1)
67
68 /* STANDARD MODE frequency */
69 #define SYNQUACER_I2C_CLK_MASTER_STD(rate) \
70 DIV_ROUND_UP(DIV_ROUND_UP((rate), 100000) - 2, 2)
71 /* FAST MODE frequency */
72 #define SYNQUACER_I2C_CLK_MASTER_FAST(rate) \
73 DIV_ROUND_UP((DIV_ROUND_UP((rate), 400000) - 2) * 2, 3)
74
75 /* (clkrate <= 18000000) */
76 /* calculate the value of CS bits in CCR register on standard mode */
77 #define SYNQUACER_I2C_CCR_CS_STD_MAX_18M(rate) \
78 ((SYNQUACER_I2C_CLK_MASTER_STD(rate) - 65) \
79 & SYNQUACER_I2C_CCR_CS_MASK)
80
81 /* calculate the value of CS bits in CSR register on standard mode */
82 #define SYNQUACER_I2C_CSR_CS_STD_MAX_18M(rate) 0x00
83
84 /* calculate the value of CS bits in CCR register on fast mode */
85 #define SYNQUACER_I2C_CCR_CS_FAST_MAX_18M(rate) \
86 ((SYNQUACER_I2C_CLK_MASTER_FAST(rate) - 1) \
87 & SYNQUACER_I2C_CCR_CS_MASK)
88
89 /* calculate the value of CS bits in CSR register on fast mode */
90 #define SYNQUACER_I2C_CSR_CS_FAST_MAX_18M(rate) 0x00
91
92 /* (clkrate > 18000000) */
93 /* calculate the value of CS bits in CCR register on standard mode */
94 #define SYNQUACER_I2C_CCR_CS_STD_MIN_18M(rate) \
95 ((SYNQUACER_I2C_CLK_MASTER_STD(rate) - 1) \
96 & SYNQUACER_I2C_CCR_CS_MASK)
97
98 /* calculate the value of CS bits in CSR register on standard mode */
99 #define SYNQUACER_I2C_CSR_CS_STD_MIN_18M(rate) \
100 (((SYNQUACER_I2C_CLK_MASTER_STD(rate) - 1) >> 5) \
101 & SYNQUACER_I2C_CSR_CS_MASK)
102
103 /* calculate the value of CS bits in CCR register on fast mode */
104 #define SYNQUACER_I2C_CCR_CS_FAST_MIN_18M(rate) \
105 ((SYNQUACER_I2C_CLK_MASTER_FAST(rate) - 1) \
106 & SYNQUACER_I2C_CCR_CS_MASK)
107
108 /* calculate the value of CS bits in CSR register on fast mode */
109 #define SYNQUACER_I2C_CSR_CS_FAST_MIN_18M(rate) \
110 (((SYNQUACER_I2C_CLK_MASTER_FAST(rate) - 1) >> 5) \
111 & SYNQUACER_I2C_CSR_CS_MASK)
112
113 /* min I2C clock frequency 14M */
114 #define SYNQUACER_I2C_MIN_CLK_RATE (14 * 1000000)
115 /* max I2C clock frequency 200M */
116 #define SYNQUACER_I2C_MAX_CLK_RATE (200 * 1000000)
117 /* I2C clock frequency 18M */
118 #define SYNQUACER_I2C_CLK_RATE_18M (18 * 1000000)
119
120 #define SYNQUACER_I2C_SPEED_FM 400 // Fast Mode
121 #define SYNQUACER_I2C_SPEED_SM 100 // Standard Mode
122
123 enum i2c_state {
124 STATE_IDLE,
125 STATE_START,
126 STATE_READ,
127 STATE_WRITE
128 };
129
130 struct synquacer_i2c {
131 struct completion completion;
132
133 struct i2c_msg *msg;
134 u32 msg_num;
135 u32 msg_idx;
136 u32 msg_ptr;
137
138 int irq;
139 struct device *dev;
140 void __iomem *base;
141 struct clk *pclk;
142 u32 pclkrate;
143 u32 speed_khz;
144 u32 timeout_ms;
145 enum i2c_state state;
146 struct i2c_adapter adapter;
147
148 bool is_suspended;
149 };
150
is_lastmsg(struct synquacer_i2c * i2c)151 static inline int is_lastmsg(struct synquacer_i2c *i2c)
152 {
153 return i2c->msg_idx >= (i2c->msg_num - 1);
154 }
155
is_msglast(struct synquacer_i2c * i2c)156 static inline int is_msglast(struct synquacer_i2c *i2c)
157 {
158 return i2c->msg_ptr == (i2c->msg->len - 1);
159 }
160
is_msgend(struct synquacer_i2c * i2c)161 static inline int is_msgend(struct synquacer_i2c *i2c)
162 {
163 return i2c->msg_ptr >= i2c->msg->len;
164 }
165
calc_timeout_ms(struct synquacer_i2c * i2c,struct i2c_msg * msgs,int num)166 static inline unsigned long calc_timeout_ms(struct synquacer_i2c *i2c,
167 struct i2c_msg *msgs,
168 int num)
169 {
170 unsigned long bit_count = 0;
171 int i;
172
173 for (i = 0; i < num; i++, msgs++)
174 bit_count += msgs->len;
175
176 return DIV_ROUND_UP((bit_count * 9 + num * 10) * 3, 200) + 10;
177 }
178
synquacer_i2c_stop(struct synquacer_i2c * i2c,int ret)179 static void synquacer_i2c_stop(struct synquacer_i2c *i2c, int ret)
180 {
181 /*
182 * clear IRQ (INT=0, BER=0)
183 * set Stop Condition (MSS=0)
184 * Interrupt Disable
185 */
186 writeb(0, i2c->base + SYNQUACER_I2C_REG_BCR);
187
188 i2c->state = STATE_IDLE;
189
190 i2c->msg_ptr = 0;
191 i2c->msg = NULL;
192 i2c->msg_idx++;
193 i2c->msg_num = 0;
194 if (ret)
195 i2c->msg_idx = ret;
196
197 complete(&i2c->completion);
198 }
199
synquacer_i2c_hw_init(struct synquacer_i2c * i2c)200 static void synquacer_i2c_hw_init(struct synquacer_i2c *i2c)
201 {
202 unsigned char ccr_cs, csr_cs;
203 u32 rt = i2c->pclkrate;
204
205 /* Set own Address */
206 writeb(0, i2c->base + SYNQUACER_I2C_REG_ADR);
207
208 /* Set PCLK frequency */
209 writeb(SYNQUACER_I2C_BUS_CLK_FR(i2c->pclkrate),
210 i2c->base + SYNQUACER_I2C_REG_FSR);
211
212 switch (i2c->speed_khz) {
213 case SYNQUACER_I2C_SPEED_FM:
214 if (i2c->pclkrate <= SYNQUACER_I2C_CLK_RATE_18M) {
215 ccr_cs = SYNQUACER_I2C_CCR_CS_FAST_MAX_18M(rt);
216 csr_cs = SYNQUACER_I2C_CSR_CS_FAST_MAX_18M(rt);
217 } else {
218 ccr_cs = SYNQUACER_I2C_CCR_CS_FAST_MIN_18M(rt);
219 csr_cs = SYNQUACER_I2C_CSR_CS_FAST_MIN_18M(rt);
220 }
221
222 /* Set Clock and enable, Set fast mode */
223 writeb(ccr_cs | SYNQUACER_I2C_CCR_FM |
224 SYNQUACER_I2C_CCR_EN,
225 i2c->base + SYNQUACER_I2C_REG_CCR);
226 writeb(csr_cs, i2c->base + SYNQUACER_I2C_REG_CSR);
227 break;
228 case SYNQUACER_I2C_SPEED_SM:
229 if (i2c->pclkrate <= SYNQUACER_I2C_CLK_RATE_18M) {
230 ccr_cs = SYNQUACER_I2C_CCR_CS_STD_MAX_18M(rt);
231 csr_cs = SYNQUACER_I2C_CSR_CS_STD_MAX_18M(rt);
232 } else {
233 ccr_cs = SYNQUACER_I2C_CCR_CS_STD_MIN_18M(rt);
234 csr_cs = SYNQUACER_I2C_CSR_CS_STD_MIN_18M(rt);
235 }
236
237 /* Set Clock and enable, Set standard mode */
238 writeb(ccr_cs | SYNQUACER_I2C_CCR_EN,
239 i2c->base + SYNQUACER_I2C_REG_CCR);
240 writeb(csr_cs, i2c->base + SYNQUACER_I2C_REG_CSR);
241 break;
242 default:
243 WARN_ON(1);
244 }
245
246 /* clear IRQ (INT=0, BER=0), Interrupt Disable */
247 writeb(0, i2c->base + SYNQUACER_I2C_REG_BCR);
248 writeb(0, i2c->base + SYNQUACER_I2C_REG_BC2R);
249 }
250
synquacer_i2c_hw_reset(struct synquacer_i2c * i2c)251 static void synquacer_i2c_hw_reset(struct synquacer_i2c *i2c)
252 {
253 /* Disable clock */
254 writeb(0, i2c->base + SYNQUACER_I2C_REG_CCR);
255 writeb(0, i2c->base + SYNQUACER_I2C_REG_CSR);
256
257 WAIT_PCLK(100, i2c->pclkrate);
258 }
259
synquacer_i2c_master_start(struct synquacer_i2c * i2c,struct i2c_msg * pmsg)260 static int synquacer_i2c_master_start(struct synquacer_i2c *i2c,
261 struct i2c_msg *pmsg)
262 {
263 unsigned char bsr, bcr;
264
265 writeb(i2c_8bit_addr_from_msg(pmsg), i2c->base + SYNQUACER_I2C_REG_DAR);
266
267 dev_dbg(i2c->dev, "slave:0x%02x\n", pmsg->addr);
268
269 /* Generate Start Condition */
270 bsr = readb(i2c->base + SYNQUACER_I2C_REG_BSR);
271 bcr = readb(i2c->base + SYNQUACER_I2C_REG_BCR);
272 dev_dbg(i2c->dev, "bsr:0x%02x, bcr:0x%02x\n", bsr, bcr);
273
274 if ((bsr & SYNQUACER_I2C_BSR_BB) &&
275 !(bcr & SYNQUACER_I2C_BCR_MSS)) {
276 dev_dbg(i2c->dev, "bus is busy");
277 return -EBUSY;
278 }
279
280 if (bsr & SYNQUACER_I2C_BSR_BB) { /* Bus is busy */
281 dev_dbg(i2c->dev, "Continuous Start");
282 writeb(bcr | SYNQUACER_I2C_BCR_SCC,
283 i2c->base + SYNQUACER_I2C_REG_BCR);
284 } else {
285 if (bcr & SYNQUACER_I2C_BCR_MSS) {
286 dev_dbg(i2c->dev, "not in master mode");
287 return -EAGAIN;
288 }
289 dev_dbg(i2c->dev, "Start Condition");
290 /* Start Condition + Enable Interrupts */
291 writeb(bcr | SYNQUACER_I2C_BCR_MSS |
292 SYNQUACER_I2C_BCR_INTE | SYNQUACER_I2C_BCR_BEIE,
293 i2c->base + SYNQUACER_I2C_REG_BCR);
294 }
295
296 WAIT_PCLK(10, i2c->pclkrate);
297
298 /* get BSR & BCR registers */
299 bsr = readb(i2c->base + SYNQUACER_I2C_REG_BSR);
300 bcr = readb(i2c->base + SYNQUACER_I2C_REG_BCR);
301 dev_dbg(i2c->dev, "bsr:0x%02x, bcr:0x%02x\n", bsr, bcr);
302
303 if ((bsr & SYNQUACER_I2C_BSR_AL) ||
304 !(bcr & SYNQUACER_I2C_BCR_MSS)) {
305 dev_dbg(i2c->dev, "arbitration lost\n");
306 return -EAGAIN;
307 }
308
309 return 0;
310 }
311
synquacer_i2c_doxfer(struct synquacer_i2c * i2c,struct i2c_msg * msgs,int num)312 static int synquacer_i2c_doxfer(struct synquacer_i2c *i2c,
313 struct i2c_msg *msgs, int num)
314 {
315 unsigned char bsr;
316 unsigned long timeout;
317 int ret;
318
319 if (i2c->is_suspended)
320 return -EBUSY;
321
322 synquacer_i2c_hw_init(i2c);
323 bsr = readb(i2c->base + SYNQUACER_I2C_REG_BSR);
324 if (bsr & SYNQUACER_I2C_BSR_BB) {
325 dev_err(i2c->dev, "cannot get bus (bus busy)\n");
326 return -EBUSY;
327 }
328
329 reinit_completion(&i2c->completion);
330
331 i2c->msg = msgs;
332 i2c->msg_num = num;
333 i2c->msg_ptr = 0;
334 i2c->msg_idx = 0;
335 i2c->state = STATE_START;
336
337 ret = synquacer_i2c_master_start(i2c, i2c->msg);
338 if (ret < 0) {
339 dev_dbg(i2c->dev, "Address failed: (%d)\n", ret);
340 return ret;
341 }
342
343 timeout = wait_for_completion_timeout(&i2c->completion,
344 msecs_to_jiffies(i2c->timeout_ms));
345 if (timeout == 0) {
346 dev_dbg(i2c->dev, "timeout\n");
347 return -EAGAIN;
348 }
349
350 ret = i2c->msg_idx;
351 if (ret != num) {
352 dev_dbg(i2c->dev, "incomplete xfer (%d)\n", ret);
353 return -EAGAIN;
354 }
355
356 /* wait 2 clock periods to ensure the stop has been through the bus */
357 udelay(DIV_ROUND_UP(2 * 1000, i2c->speed_khz));
358
359 return 0;
360 }
361
synquacer_i2c_isr(int irq,void * dev_id)362 static irqreturn_t synquacer_i2c_isr(int irq, void *dev_id)
363 {
364 struct synquacer_i2c *i2c = dev_id;
365
366 unsigned char byte;
367 unsigned char bsr, bcr;
368 int ret;
369
370 bcr = readb(i2c->base + SYNQUACER_I2C_REG_BCR);
371 bsr = readb(i2c->base + SYNQUACER_I2C_REG_BSR);
372 dev_dbg(i2c->dev, "bsr:0x%02x, bcr:0x%02x\n", bsr, bcr);
373
374 if (bcr & SYNQUACER_I2C_BCR_BER) {
375 dev_err(i2c->dev, "bus error\n");
376 synquacer_i2c_stop(i2c, -EAGAIN);
377 goto out;
378 }
379 if ((bsr & SYNQUACER_I2C_BSR_AL) ||
380 !(bcr & SYNQUACER_I2C_BCR_MSS)) {
381 dev_dbg(i2c->dev, "arbitration lost\n");
382 synquacer_i2c_stop(i2c, -EAGAIN);
383 goto out;
384 }
385
386 switch (i2c->state) {
387 case STATE_START:
388 if (bsr & SYNQUACER_I2C_BSR_LRB) {
389 dev_dbg(i2c->dev, "ack was not received\n");
390 synquacer_i2c_stop(i2c, -EAGAIN);
391 goto out;
392 }
393
394 if (i2c->msg->flags & I2C_M_RD)
395 i2c->state = STATE_READ;
396 else
397 i2c->state = STATE_WRITE;
398
399 if (is_lastmsg(i2c) && i2c->msg->len == 0) {
400 synquacer_i2c_stop(i2c, 0);
401 goto out;
402 }
403
404 if (i2c->state == STATE_READ)
405 goto prepare_read;
406
407 /* fallthru */
408
409 case STATE_WRITE:
410 if (bsr & SYNQUACER_I2C_BSR_LRB) {
411 dev_dbg(i2c->dev, "WRITE: No Ack\n");
412 synquacer_i2c_stop(i2c, -EAGAIN);
413 goto out;
414 }
415
416 if (!is_msgend(i2c)) {
417 writeb(i2c->msg->buf[i2c->msg_ptr++],
418 i2c->base + SYNQUACER_I2C_REG_DAR);
419
420 /* clear IRQ, and continue */
421 writeb(SYNQUACER_I2C_BCR_BEIE |
422 SYNQUACER_I2C_BCR_MSS |
423 SYNQUACER_I2C_BCR_INTE,
424 i2c->base + SYNQUACER_I2C_REG_BCR);
425 break;
426 }
427 if (is_lastmsg(i2c)) {
428 synquacer_i2c_stop(i2c, 0);
429 break;
430 }
431 dev_dbg(i2c->dev, "WRITE: Next Message\n");
432
433 i2c->msg_ptr = 0;
434 i2c->msg_idx++;
435 i2c->msg++;
436
437 /* send the new start */
438 ret = synquacer_i2c_master_start(i2c, i2c->msg);
439 if (ret < 0) {
440 dev_dbg(i2c->dev, "restart error (%d)\n", ret);
441 synquacer_i2c_stop(i2c, -EAGAIN);
442 break;
443 }
444 i2c->state = STATE_START;
445 break;
446
447 case STATE_READ:
448 byte = readb(i2c->base + SYNQUACER_I2C_REG_DAR);
449 if (!(bsr & SYNQUACER_I2C_BSR_FBT)) /* data */
450 i2c->msg->buf[i2c->msg_ptr++] = byte;
451 else /* address */
452 dev_dbg(i2c->dev, "address:0x%02x. ignore it.\n", byte);
453
454 prepare_read:
455 if (is_msglast(i2c)) {
456 writeb(SYNQUACER_I2C_BCR_MSS |
457 SYNQUACER_I2C_BCR_BEIE |
458 SYNQUACER_I2C_BCR_INTE,
459 i2c->base + SYNQUACER_I2C_REG_BCR);
460 break;
461 }
462 if (!is_msgend(i2c)) {
463 writeb(SYNQUACER_I2C_BCR_MSS |
464 SYNQUACER_I2C_BCR_BEIE |
465 SYNQUACER_I2C_BCR_INTE |
466 SYNQUACER_I2C_BCR_ACK,
467 i2c->base + SYNQUACER_I2C_REG_BCR);
468 break;
469 }
470 if (is_lastmsg(i2c)) {
471 /* last message, send stop and complete */
472 dev_dbg(i2c->dev, "READ: Send Stop\n");
473 synquacer_i2c_stop(i2c, 0);
474 break;
475 }
476 dev_dbg(i2c->dev, "READ: Next Transfer\n");
477
478 i2c->msg_ptr = 0;
479 i2c->msg_idx++;
480 i2c->msg++;
481
482 ret = synquacer_i2c_master_start(i2c, i2c->msg);
483 if (ret < 0) {
484 dev_dbg(i2c->dev, "restart error (%d)\n", ret);
485 synquacer_i2c_stop(i2c, -EAGAIN);
486 } else {
487 i2c->state = STATE_START;
488 }
489 break;
490 default:
491 dev_err(i2c->dev, "called in err STATE (%d)\n", i2c->state);
492 break;
493 }
494
495 out:
496 WAIT_PCLK(10, i2c->pclkrate);
497 return IRQ_HANDLED;
498 }
499
synquacer_i2c_xfer(struct i2c_adapter * adap,struct i2c_msg * msgs,int num)500 static int synquacer_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
501 int num)
502 {
503 struct synquacer_i2c *i2c;
504 int retry;
505 int ret;
506
507 i2c = i2c_get_adapdata(adap);
508 i2c->timeout_ms = calc_timeout_ms(i2c, msgs, num);
509
510 dev_dbg(i2c->dev, "calculated timeout %d ms\n", i2c->timeout_ms);
511
512 for (retry = 0; retry <= adap->retries; retry++) {
513 ret = synquacer_i2c_doxfer(i2c, msgs, num);
514 if (ret != -EAGAIN)
515 return ret;
516
517 dev_dbg(i2c->dev, "Retrying transmission (%d)\n", retry);
518
519 synquacer_i2c_hw_reset(i2c);
520 }
521 return -EIO;
522 }
523
synquacer_i2c_functionality(struct i2c_adapter * adap)524 static u32 synquacer_i2c_functionality(struct i2c_adapter *adap)
525 {
526 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
527 }
528
529 static const struct i2c_algorithm synquacer_i2c_algo = {
530 .master_xfer = synquacer_i2c_xfer,
531 .functionality = synquacer_i2c_functionality,
532 };
533
534 static struct i2c_adapter synquacer_i2c_ops = {
535 .owner = THIS_MODULE,
536 .name = "synquacer_i2c-adapter",
537 .algo = &synquacer_i2c_algo,
538 .retries = 5,
539 };
540
synquacer_i2c_probe(struct platform_device * pdev)541 static int synquacer_i2c_probe(struct platform_device *pdev)
542 {
543 struct synquacer_i2c *i2c;
544 struct resource *r;
545 u32 bus_speed;
546 int ret;
547
548 i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL);
549 if (!i2c)
550 return -ENOMEM;
551
552 bus_speed = i2c_acpi_find_bus_speed(&pdev->dev);
553 if (!bus_speed)
554 device_property_read_u32(&pdev->dev, "clock-frequency",
555 &bus_speed);
556
557 device_property_read_u32(&pdev->dev, "socionext,pclk-rate",
558 &i2c->pclkrate);
559
560 i2c->pclk = devm_clk_get(&pdev->dev, "pclk");
561 if (IS_ERR(i2c->pclk) && PTR_ERR(i2c->pclk) == -EPROBE_DEFER)
562 return -EPROBE_DEFER;
563 if (!IS_ERR_OR_NULL(i2c->pclk)) {
564 dev_dbg(&pdev->dev, "clock source %p\n", i2c->pclk);
565
566 ret = clk_prepare_enable(i2c->pclk);
567 if (ret) {
568 dev_err(&pdev->dev, "failed to enable clock (%d)\n",
569 ret);
570 return ret;
571 }
572 i2c->pclkrate = clk_get_rate(i2c->pclk);
573 }
574
575 if (i2c->pclkrate < SYNQUACER_I2C_MIN_CLK_RATE ||
576 i2c->pclkrate > SYNQUACER_I2C_MAX_CLK_RATE) {
577 dev_err(&pdev->dev, "PCLK missing or out of range (%d)\n",
578 i2c->pclkrate);
579 return -EINVAL;
580 }
581
582 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
583 i2c->base = devm_ioremap_resource(&pdev->dev, r);
584 if (IS_ERR(i2c->base))
585 return PTR_ERR(i2c->base);
586
587 i2c->irq = platform_get_irq(pdev, 0);
588 if (i2c->irq < 0) {
589 dev_err(&pdev->dev, "no IRQ resource found\n");
590 return -ENODEV;
591 }
592
593 ret = devm_request_irq(&pdev->dev, i2c->irq, synquacer_i2c_isr,
594 0, dev_name(&pdev->dev), i2c);
595 if (ret < 0) {
596 dev_err(&pdev->dev, "cannot claim IRQ %d\n", i2c->irq);
597 return ret;
598 }
599
600 i2c->state = STATE_IDLE;
601 i2c->dev = &pdev->dev;
602 i2c->adapter = synquacer_i2c_ops;
603 i2c_set_adapdata(&i2c->adapter, i2c);
604 i2c->adapter.dev.parent = &pdev->dev;
605 i2c->adapter.nr = pdev->id;
606 init_completion(&i2c->completion);
607
608 if (bus_speed < 400000)
609 i2c->speed_khz = SYNQUACER_I2C_SPEED_SM;
610 else
611 i2c->speed_khz = SYNQUACER_I2C_SPEED_FM;
612
613 synquacer_i2c_hw_init(i2c);
614
615 ret = i2c_add_numbered_adapter(&i2c->adapter);
616 if (ret) {
617 dev_err(&pdev->dev, "failed to add bus to i2c core\n");
618 return ret;
619 }
620
621 platform_set_drvdata(pdev, i2c);
622
623 dev_info(&pdev->dev, "%s: synquacer_i2c adapter\n",
624 dev_name(&i2c->adapter.dev));
625
626 return 0;
627 }
628
synquacer_i2c_remove(struct platform_device * pdev)629 static int synquacer_i2c_remove(struct platform_device *pdev)
630 {
631 struct synquacer_i2c *i2c = platform_get_drvdata(pdev);
632
633 i2c_del_adapter(&i2c->adapter);
634 if (!IS_ERR(i2c->pclk))
635 clk_disable_unprepare(i2c->pclk);
636
637 return 0;
638 };
639
640 static const struct of_device_id synquacer_i2c_dt_ids[] = {
641 { .compatible = "socionext,synquacer-i2c" },
642 { /* sentinel */ }
643 };
644 MODULE_DEVICE_TABLE(of, synquacer_i2c_dt_ids);
645
646 #ifdef CONFIG_ACPI
647 static const struct acpi_device_id synquacer_i2c_acpi_ids[] = {
648 { "SCX0003" },
649 { /* sentinel */ }
650 };
651 MODULE_DEVICE_TABLE(acpi, synquacer_i2c_acpi_ids);
652 #endif
653
654 static struct platform_driver synquacer_i2c_driver = {
655 .probe = synquacer_i2c_probe,
656 .remove = synquacer_i2c_remove,
657 .driver = {
658 .name = "synquacer_i2c",
659 .of_match_table = of_match_ptr(synquacer_i2c_dt_ids),
660 .acpi_match_table = ACPI_PTR(synquacer_i2c_acpi_ids),
661 },
662 };
663 module_platform_driver(synquacer_i2c_driver);
664
665 MODULE_AUTHOR("Fujitsu Semiconductor Ltd");
666 MODULE_DESCRIPTION("Socionext SynQuacer I2C Driver");
667 MODULE_LICENSE("GPL v2");
668
