1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
3
4 #include <linux/clk.h>
5 #include <linux/dma-mapping.h>
6 #include <linux/err.h>
7 #include <linux/i2c.h>
8 #include <linux/interrupt.h>
9 #include <linux/io.h>
10 #include <linux/module.h>
11 #include <linux/of.h>
12 #include <linux/of_platform.h>
13 #include <linux/platform_device.h>
14 #include <linux/pm_runtime.h>
15 #include <linux/qcom-geni-se.h>
16 #include <linux/spinlock.h>
17
18 #define SE_I2C_TX_TRANS_LEN 0x26c
19 #define SE_I2C_RX_TRANS_LEN 0x270
20 #define SE_I2C_SCL_COUNTERS 0x278
21
22 #define SE_I2C_ERR (M_CMD_OVERRUN_EN | M_ILLEGAL_CMD_EN | M_CMD_FAILURE_EN |\
23 M_GP_IRQ_1_EN | M_GP_IRQ_3_EN | M_GP_IRQ_4_EN)
24 #define SE_I2C_ABORT BIT(1)
25
26 /* M_CMD OP codes for I2C */
27 #define I2C_WRITE 0x1
28 #define I2C_READ 0x2
29 #define I2C_WRITE_READ 0x3
30 #define I2C_ADDR_ONLY 0x4
31 #define I2C_BUS_CLEAR 0x6
32 #define I2C_STOP_ON_BUS 0x7
33 /* M_CMD params for I2C */
34 #define PRE_CMD_DELAY BIT(0)
35 #define TIMESTAMP_BEFORE BIT(1)
36 #define STOP_STRETCH BIT(2)
37 #define TIMESTAMP_AFTER BIT(3)
38 #define POST_COMMAND_DELAY BIT(4)
39 #define IGNORE_ADD_NACK BIT(6)
40 #define READ_FINISHED_WITH_ACK BIT(7)
41 #define BYPASS_ADDR_PHASE BIT(8)
42 #define SLV_ADDR_MSK GENMASK(15, 9)
43 #define SLV_ADDR_SHFT 9
44 /* I2C SCL COUNTER fields */
45 #define HIGH_COUNTER_MSK GENMASK(29, 20)
46 #define HIGH_COUNTER_SHFT 20
47 #define LOW_COUNTER_MSK GENMASK(19, 10)
48 #define LOW_COUNTER_SHFT 10
49 #define CYCLE_COUNTER_MSK GENMASK(9, 0)
50
51 enum geni_i2c_err_code {
52 GP_IRQ0,
53 NACK,
54 GP_IRQ2,
55 BUS_PROTO,
56 ARB_LOST,
57 GP_IRQ5,
58 GENI_OVERRUN,
59 GENI_ILLEGAL_CMD,
60 GENI_ABORT_DONE,
61 GENI_TIMEOUT,
62 };
63
64 #define DM_I2C_CB_ERR ((BIT(NACK) | BIT(BUS_PROTO) | BIT(ARB_LOST)) \
65 << 5)
66
67 #define I2C_AUTO_SUSPEND_DELAY 250
68 #define KHZ(freq) (1000 * freq)
69 #define PACKING_BYTES_PW 4
70
71 #define ABORT_TIMEOUT HZ
72 #define XFER_TIMEOUT HZ
73 #define RST_TIMEOUT HZ
74
75 struct geni_i2c_dev {
76 struct geni_se se;
77 u32 tx_wm;
78 int irq;
79 int err;
80 struct i2c_adapter adap;
81 struct completion done;
82 struct i2c_msg *cur;
83 int cur_wr;
84 int cur_rd;
85 spinlock_t lock;
86 u32 clk_freq_out;
87 const struct geni_i2c_clk_fld *clk_fld;
88 int suspended;
89 };
90
91 struct geni_i2c_err_log {
92 int err;
93 const char *msg;
94 };
95
96 static const struct geni_i2c_err_log gi2c_log[] = {
97 [GP_IRQ0] = {-EIO, "Unknown I2C err GP_IRQ0"},
98 [NACK] = {-ENXIO, "NACK: slv unresponsive, check its power/reset-ln"},
99 [GP_IRQ2] = {-EIO, "Unknown I2C err GP IRQ2"},
100 [BUS_PROTO] = {-EPROTO, "Bus proto err, noisy/unepxected start/stop"},
101 [ARB_LOST] = {-EAGAIN, "Bus arbitration lost, clock line undriveable"},
102 [GP_IRQ5] = {-EIO, "Unknown I2C err GP IRQ5"},
103 [GENI_OVERRUN] = {-EIO, "Cmd overrun, check GENI cmd-state machine"},
104 [GENI_ILLEGAL_CMD] = {-EIO, "Illegal cmd, check GENI cmd-state machine"},
105 [GENI_ABORT_DONE] = {-ETIMEDOUT, "Abort after timeout successful"},
106 [GENI_TIMEOUT] = {-ETIMEDOUT, "I2C TXN timed out"},
107 };
108
109 struct geni_i2c_clk_fld {
110 u32 clk_freq_out;
111 u8 clk_div;
112 u8 t_high_cnt;
113 u8 t_low_cnt;
114 u8 t_cycle_cnt;
115 };
116
117 /*
118 * Hardware uses the underlying formula to calculate time periods of
119 * SCL clock cycle. Firmware uses some additional cycles excluded from the
120 * below formula and it is confirmed that the time periods are within
121 * specification limits.
122 *
123 * time of high period of SCL: t_high = (t_high_cnt * clk_div) / source_clock
124 * time of low period of SCL: t_low = (t_low_cnt * clk_div) / source_clock
125 * time of full period of SCL: t_cycle = (t_cycle_cnt * clk_div) / source_clock
126 * clk_freq_out = t / t_cycle
127 * source_clock = 19.2 MHz
128 */
129 static const struct geni_i2c_clk_fld geni_i2c_clk_map[] = {
130 {KHZ(100), 7, 10, 11, 26},
131 {KHZ(400), 2, 5, 12, 24},
132 {KHZ(1000), 1, 3, 9, 18},
133 };
134
geni_i2c_clk_map_idx(struct geni_i2c_dev * gi2c)135 static int geni_i2c_clk_map_idx(struct geni_i2c_dev *gi2c)
136 {
137 int i;
138 const struct geni_i2c_clk_fld *itr = geni_i2c_clk_map;
139
140 for (i = 0; i < ARRAY_SIZE(geni_i2c_clk_map); i++, itr++) {
141 if (itr->clk_freq_out == gi2c->clk_freq_out) {
142 gi2c->clk_fld = itr;
143 return 0;
144 }
145 }
146 return -EINVAL;
147 }
148
qcom_geni_i2c_conf(struct geni_i2c_dev * gi2c)149 static void qcom_geni_i2c_conf(struct geni_i2c_dev *gi2c)
150 {
151 const struct geni_i2c_clk_fld *itr = gi2c->clk_fld;
152 u32 val;
153
154 writel_relaxed(0, gi2c->se.base + SE_GENI_CLK_SEL);
155
156 val = (itr->clk_div << CLK_DIV_SHFT) | SER_CLK_EN;
157 writel_relaxed(val, gi2c->se.base + GENI_SER_M_CLK_CFG);
158
159 val = itr->t_high_cnt << HIGH_COUNTER_SHFT;
160 val |= itr->t_low_cnt << LOW_COUNTER_SHFT;
161 val |= itr->t_cycle_cnt;
162 writel_relaxed(val, gi2c->se.base + SE_I2C_SCL_COUNTERS);
163 }
164
geni_i2c_err_misc(struct geni_i2c_dev * gi2c)165 static void geni_i2c_err_misc(struct geni_i2c_dev *gi2c)
166 {
167 u32 m_cmd = readl_relaxed(gi2c->se.base + SE_GENI_M_CMD0);
168 u32 m_stat = readl_relaxed(gi2c->se.base + SE_GENI_M_IRQ_STATUS);
169 u32 geni_s = readl_relaxed(gi2c->se.base + SE_GENI_STATUS);
170 u32 geni_ios = readl_relaxed(gi2c->se.base + SE_GENI_IOS);
171 u32 dma = readl_relaxed(gi2c->se.base + SE_GENI_DMA_MODE_EN);
172 u32 rx_st, tx_st;
173
174 if (dma) {
175 rx_st = readl_relaxed(gi2c->se.base + SE_DMA_RX_IRQ_STAT);
176 tx_st = readl_relaxed(gi2c->se.base + SE_DMA_TX_IRQ_STAT);
177 } else {
178 rx_st = readl_relaxed(gi2c->se.base + SE_GENI_RX_FIFO_STATUS);
179 tx_st = readl_relaxed(gi2c->se.base + SE_GENI_TX_FIFO_STATUS);
180 }
181 dev_dbg(gi2c->se.dev, "DMA:%d tx_stat:0x%x, rx_stat:0x%x, irq-stat:0x%x\n",
182 dma, tx_st, rx_st, m_stat);
183 dev_dbg(gi2c->se.dev, "m_cmd:0x%x, geni_status:0x%x, geni_ios:0x%x\n",
184 m_cmd, geni_s, geni_ios);
185 }
186
geni_i2c_err(struct geni_i2c_dev * gi2c,int err)187 static void geni_i2c_err(struct geni_i2c_dev *gi2c, int err)
188 {
189 if (!gi2c->err)
190 gi2c->err = gi2c_log[err].err;
191 if (gi2c->cur)
192 dev_dbg(gi2c->se.dev, "len:%d, slv-addr:0x%x, RD/WR:%d\n",
193 gi2c->cur->len, gi2c->cur->addr, gi2c->cur->flags);
194
195 if (err != NACK && err != GENI_ABORT_DONE) {
196 dev_err(gi2c->se.dev, "%s\n", gi2c_log[err].msg);
197 geni_i2c_err_misc(gi2c);
198 }
199 }
200
geni_i2c_irq(int irq,void * dev)201 static irqreturn_t geni_i2c_irq(int irq, void *dev)
202 {
203 struct geni_i2c_dev *gi2c = dev;
204 int j;
205 u32 m_stat;
206 u32 rx_st;
207 u32 dm_tx_st;
208 u32 dm_rx_st;
209 u32 dma;
210 struct i2c_msg *cur;
211 unsigned long flags;
212
213 spin_lock_irqsave(&gi2c->lock, flags);
214 m_stat = readl_relaxed(gi2c->se.base + SE_GENI_M_IRQ_STATUS);
215 rx_st = readl_relaxed(gi2c->se.base + SE_GENI_RX_FIFO_STATUS);
216 dm_tx_st = readl_relaxed(gi2c->se.base + SE_DMA_TX_IRQ_STAT);
217 dm_rx_st = readl_relaxed(gi2c->se.base + SE_DMA_RX_IRQ_STAT);
218 dma = readl_relaxed(gi2c->se.base + SE_GENI_DMA_MODE_EN);
219 cur = gi2c->cur;
220
221 if (!cur ||
222 m_stat & (M_CMD_FAILURE_EN | M_CMD_ABORT_EN) ||
223 dm_rx_st & (DM_I2C_CB_ERR)) {
224 if (m_stat & M_GP_IRQ_1_EN)
225 geni_i2c_err(gi2c, NACK);
226 if (m_stat & M_GP_IRQ_3_EN)
227 geni_i2c_err(gi2c, BUS_PROTO);
228 if (m_stat & M_GP_IRQ_4_EN)
229 geni_i2c_err(gi2c, ARB_LOST);
230 if (m_stat & M_CMD_OVERRUN_EN)
231 geni_i2c_err(gi2c, GENI_OVERRUN);
232 if (m_stat & M_ILLEGAL_CMD_EN)
233 geni_i2c_err(gi2c, GENI_ILLEGAL_CMD);
234 if (m_stat & M_CMD_ABORT_EN)
235 geni_i2c_err(gi2c, GENI_ABORT_DONE);
236 if (m_stat & M_GP_IRQ_0_EN)
237 geni_i2c_err(gi2c, GP_IRQ0);
238
239 /* Disable the TX Watermark interrupt to stop TX */
240 if (!dma)
241 writel_relaxed(0, gi2c->se.base +
242 SE_GENI_TX_WATERMARK_REG);
243 goto irqret;
244 }
245
246 if (dma) {
247 dev_dbg(gi2c->se.dev, "i2c dma tx:0x%x, dma rx:0x%x\n",
248 dm_tx_st, dm_rx_st);
249 goto irqret;
250 }
251
252 if (cur->flags & I2C_M_RD &&
253 m_stat & (M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN)) {
254 u32 rxcnt = rx_st & RX_FIFO_WC_MSK;
255
256 for (j = 0; j < rxcnt; j++) {
257 u32 val;
258 int p = 0;
259
260 val = readl_relaxed(gi2c->se.base + SE_GENI_RX_FIFOn);
261 while (gi2c->cur_rd < cur->len && p < sizeof(val)) {
262 cur->buf[gi2c->cur_rd++] = val & 0xff;
263 val >>= 8;
264 p++;
265 }
266 if (gi2c->cur_rd == cur->len)
267 break;
268 }
269 } else if (!(cur->flags & I2C_M_RD) &&
270 m_stat & M_TX_FIFO_WATERMARK_EN) {
271 for (j = 0; j < gi2c->tx_wm; j++) {
272 u32 temp;
273 u32 val = 0;
274 int p = 0;
275
276 while (gi2c->cur_wr < cur->len && p < sizeof(val)) {
277 temp = cur->buf[gi2c->cur_wr++];
278 val |= temp << (p * 8);
279 p++;
280 }
281 writel_relaxed(val, gi2c->se.base + SE_GENI_TX_FIFOn);
282 /* TX Complete, Disable the TX Watermark interrupt */
283 if (gi2c->cur_wr == cur->len) {
284 writel_relaxed(0, gi2c->se.base +
285 SE_GENI_TX_WATERMARK_REG);
286 break;
287 }
288 }
289 }
290 irqret:
291 if (m_stat)
292 writel_relaxed(m_stat, gi2c->se.base + SE_GENI_M_IRQ_CLEAR);
293
294 if (dma) {
295 if (dm_tx_st)
296 writel_relaxed(dm_tx_st, gi2c->se.base +
297 SE_DMA_TX_IRQ_CLR);
298 if (dm_rx_st)
299 writel_relaxed(dm_rx_st, gi2c->se.base +
300 SE_DMA_RX_IRQ_CLR);
301 }
302 /* if this is err with done-bit not set, handle that through timeout. */
303 if (m_stat & M_CMD_DONE_EN || m_stat & M_CMD_ABORT_EN)
304 complete(&gi2c->done);
305 else if (dm_tx_st & TX_DMA_DONE || dm_tx_st & TX_RESET_DONE)
306 complete(&gi2c->done);
307 else if (dm_rx_st & RX_DMA_DONE || dm_rx_st & RX_RESET_DONE)
308 complete(&gi2c->done);
309
310 spin_unlock_irqrestore(&gi2c->lock, flags);
311 return IRQ_HANDLED;
312 }
313
geni_i2c_abort_xfer(struct geni_i2c_dev * gi2c)314 static void geni_i2c_abort_xfer(struct geni_i2c_dev *gi2c)
315 {
316 u32 val;
317 unsigned long time_left = ABORT_TIMEOUT;
318 unsigned long flags;
319
320 spin_lock_irqsave(&gi2c->lock, flags);
321 geni_i2c_err(gi2c, GENI_TIMEOUT);
322 gi2c->cur = NULL;
323 geni_se_abort_m_cmd(&gi2c->se);
324 spin_unlock_irqrestore(&gi2c->lock, flags);
325 do {
326 time_left = wait_for_completion_timeout(&gi2c->done, time_left);
327 val = readl_relaxed(gi2c->se.base + SE_GENI_M_IRQ_STATUS);
328 } while (!(val & M_CMD_ABORT_EN) && time_left);
329
330 if (!(val & M_CMD_ABORT_EN))
331 dev_err(gi2c->se.dev, "Timeout abort_m_cmd\n");
332 }
333
geni_i2c_rx_fsm_rst(struct geni_i2c_dev * gi2c)334 static void geni_i2c_rx_fsm_rst(struct geni_i2c_dev *gi2c)
335 {
336 u32 val;
337 unsigned long time_left = RST_TIMEOUT;
338
339 writel_relaxed(1, gi2c->se.base + SE_DMA_RX_FSM_RST);
340 do {
341 time_left = wait_for_completion_timeout(&gi2c->done, time_left);
342 val = readl_relaxed(gi2c->se.base + SE_DMA_RX_IRQ_STAT);
343 } while (!(val & RX_RESET_DONE) && time_left);
344
345 if (!(val & RX_RESET_DONE))
346 dev_err(gi2c->se.dev, "Timeout resetting RX_FSM\n");
347 }
348
geni_i2c_tx_fsm_rst(struct geni_i2c_dev * gi2c)349 static void geni_i2c_tx_fsm_rst(struct geni_i2c_dev *gi2c)
350 {
351 u32 val;
352 unsigned long time_left = RST_TIMEOUT;
353
354 writel_relaxed(1, gi2c->se.base + SE_DMA_TX_FSM_RST);
355 do {
356 time_left = wait_for_completion_timeout(&gi2c->done, time_left);
357 val = readl_relaxed(gi2c->se.base + SE_DMA_TX_IRQ_STAT);
358 } while (!(val & TX_RESET_DONE) && time_left);
359
360 if (!(val & TX_RESET_DONE))
361 dev_err(gi2c->se.dev, "Timeout resetting TX_FSM\n");
362 }
363
geni_i2c_rx_one_msg(struct geni_i2c_dev * gi2c,struct i2c_msg * msg,u32 m_param)364 static int geni_i2c_rx_one_msg(struct geni_i2c_dev *gi2c, struct i2c_msg *msg,
365 u32 m_param)
366 {
367 dma_addr_t rx_dma;
368 enum geni_se_xfer_mode mode;
369 unsigned long time_left = XFER_TIMEOUT;
370 void *dma_buf;
371
372 gi2c->cur = msg;
373 mode = GENI_SE_FIFO;
374 dma_buf = i2c_get_dma_safe_msg_buf(msg, 32);
375 if (dma_buf)
376 mode = GENI_SE_DMA;
377
378 geni_se_select_mode(&gi2c->se, mode);
379 writel_relaxed(msg->len, gi2c->se.base + SE_I2C_RX_TRANS_LEN);
380 geni_se_setup_m_cmd(&gi2c->se, I2C_READ, m_param);
381 if (mode == GENI_SE_DMA) {
382 int ret;
383
384 ret = geni_se_rx_dma_prep(&gi2c->se, dma_buf, msg->len,
385 &rx_dma);
386 if (ret) {
387 mode = GENI_SE_FIFO;
388 geni_se_select_mode(&gi2c->se, mode);
389 i2c_put_dma_safe_msg_buf(dma_buf, msg, false);
390 }
391 }
392
393 time_left = wait_for_completion_timeout(&gi2c->done, XFER_TIMEOUT);
394 if (!time_left)
395 geni_i2c_abort_xfer(gi2c);
396
397 gi2c->cur_rd = 0;
398 if (mode == GENI_SE_DMA) {
399 if (gi2c->err)
400 geni_i2c_rx_fsm_rst(gi2c);
401 geni_se_rx_dma_unprep(&gi2c->se, rx_dma, msg->len);
402 i2c_put_dma_safe_msg_buf(dma_buf, msg, !gi2c->err);
403 }
404 return gi2c->err;
405 }
406
geni_i2c_tx_one_msg(struct geni_i2c_dev * gi2c,struct i2c_msg * msg,u32 m_param)407 static int geni_i2c_tx_one_msg(struct geni_i2c_dev *gi2c, struct i2c_msg *msg,
408 u32 m_param)
409 {
410 dma_addr_t tx_dma;
411 enum geni_se_xfer_mode mode;
412 unsigned long time_left;
413 void *dma_buf;
414
415 gi2c->cur = msg;
416 mode = GENI_SE_FIFO;
417 dma_buf = i2c_get_dma_safe_msg_buf(msg, 32);
418 if (dma_buf)
419 mode = GENI_SE_DMA;
420
421 geni_se_select_mode(&gi2c->se, mode);
422 writel_relaxed(msg->len, gi2c->se.base + SE_I2C_TX_TRANS_LEN);
423 geni_se_setup_m_cmd(&gi2c->se, I2C_WRITE, m_param);
424 if (mode == GENI_SE_DMA) {
425 int ret;
426
427 ret = geni_se_tx_dma_prep(&gi2c->se, dma_buf, msg->len,
428 &tx_dma);
429 if (ret) {
430 mode = GENI_SE_FIFO;
431 geni_se_select_mode(&gi2c->se, mode);
432 i2c_put_dma_safe_msg_buf(dma_buf, msg, false);
433 }
434 }
435
436 if (mode == GENI_SE_FIFO) /* Get FIFO IRQ */
437 writel_relaxed(1, gi2c->se.base + SE_GENI_TX_WATERMARK_REG);
438
439 time_left = wait_for_completion_timeout(&gi2c->done, XFER_TIMEOUT);
440 if (!time_left)
441 geni_i2c_abort_xfer(gi2c);
442
443 gi2c->cur_wr = 0;
444 if (mode == GENI_SE_DMA) {
445 if (gi2c->err)
446 geni_i2c_tx_fsm_rst(gi2c);
447 geni_se_tx_dma_unprep(&gi2c->se, tx_dma, msg->len);
448 i2c_put_dma_safe_msg_buf(dma_buf, msg, !gi2c->err);
449 }
450 return gi2c->err;
451 }
452
geni_i2c_xfer(struct i2c_adapter * adap,struct i2c_msg msgs[],int num)453 static int geni_i2c_xfer(struct i2c_adapter *adap,
454 struct i2c_msg msgs[],
455 int num)
456 {
457 struct geni_i2c_dev *gi2c = i2c_get_adapdata(adap);
458 int i, ret;
459
460 gi2c->err = 0;
461 reinit_completion(&gi2c->done);
462 ret = pm_runtime_get_sync(gi2c->se.dev);
463 if (ret < 0) {
464 dev_err(gi2c->se.dev, "error turning SE resources:%d\n", ret);
465 pm_runtime_put_noidle(gi2c->se.dev);
466 /* Set device in suspended since resume failed */
467 pm_runtime_set_suspended(gi2c->se.dev);
468 return ret;
469 }
470
471 qcom_geni_i2c_conf(gi2c);
472 for (i = 0; i < num; i++) {
473 u32 m_param = i < (num - 1) ? STOP_STRETCH : 0;
474
475 m_param |= ((msgs[i].addr << SLV_ADDR_SHFT) & SLV_ADDR_MSK);
476
477 if (msgs[i].flags & I2C_M_RD)
478 ret = geni_i2c_rx_one_msg(gi2c, &msgs[i], m_param);
479 else
480 ret = geni_i2c_tx_one_msg(gi2c, &msgs[i], m_param);
481
482 if (ret)
483 break;
484 }
485 if (ret == 0)
486 ret = num;
487
488 pm_runtime_mark_last_busy(gi2c->se.dev);
489 pm_runtime_put_autosuspend(gi2c->se.dev);
490 gi2c->cur = NULL;
491 gi2c->err = 0;
492 return ret;
493 }
494
geni_i2c_func(struct i2c_adapter * adap)495 static u32 geni_i2c_func(struct i2c_adapter *adap)
496 {
497 return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
498 }
499
500 static const struct i2c_algorithm geni_i2c_algo = {
501 .master_xfer = geni_i2c_xfer,
502 .functionality = geni_i2c_func,
503 };
504
geni_i2c_probe(struct platform_device * pdev)505 static int geni_i2c_probe(struct platform_device *pdev)
506 {
507 struct geni_i2c_dev *gi2c;
508 struct resource *res;
509 u32 proto, tx_depth;
510 int ret;
511
512 gi2c = devm_kzalloc(&pdev->dev, sizeof(*gi2c), GFP_KERNEL);
513 if (!gi2c)
514 return -ENOMEM;
515
516 gi2c->se.dev = &pdev->dev;
517 gi2c->se.wrapper = dev_get_drvdata(pdev->dev.parent);
518 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
519 gi2c->se.base = devm_ioremap_resource(&pdev->dev, res);
520 if (IS_ERR(gi2c->se.base))
521 return PTR_ERR(gi2c->se.base);
522
523 gi2c->se.clk = devm_clk_get(&pdev->dev, "se");
524 if (IS_ERR(gi2c->se.clk)) {
525 ret = PTR_ERR(gi2c->se.clk);
526 dev_err(&pdev->dev, "Err getting SE Core clk %d\n", ret);
527 return ret;
528 }
529
530 ret = device_property_read_u32(&pdev->dev, "clock-frequency",
531 &gi2c->clk_freq_out);
532 if (ret) {
533 dev_info(&pdev->dev,
534 "Bus frequency not specified, default to 100kHz.\n");
535 gi2c->clk_freq_out = KHZ(100);
536 }
537
538 gi2c->irq = platform_get_irq(pdev, 0);
539 if (gi2c->irq < 0) {
540 dev_err(&pdev->dev, "IRQ error for i2c-geni\n");
541 return gi2c->irq;
542 }
543
544 ret = geni_i2c_clk_map_idx(gi2c);
545 if (ret) {
546 dev_err(&pdev->dev, "Invalid clk frequency %d Hz: %d\n",
547 gi2c->clk_freq_out, ret);
548 return ret;
549 }
550
551 gi2c->adap.algo = &geni_i2c_algo;
552 init_completion(&gi2c->done);
553 spin_lock_init(&gi2c->lock);
554 platform_set_drvdata(pdev, gi2c);
555 ret = devm_request_irq(&pdev->dev, gi2c->irq, geni_i2c_irq,
556 IRQF_TRIGGER_HIGH, "i2c_geni", gi2c);
557 if (ret) {
558 dev_err(&pdev->dev, "Request_irq failed:%d: err:%d\n",
559 gi2c->irq, ret);
560 return ret;
561 }
562 /* Disable the interrupt so that the system can enter low-power mode */
563 disable_irq(gi2c->irq);
564 i2c_set_adapdata(&gi2c->adap, gi2c);
565 gi2c->adap.dev.parent = &pdev->dev;
566 gi2c->adap.dev.of_node = pdev->dev.of_node;
567 strlcpy(gi2c->adap.name, "Geni-I2C", sizeof(gi2c->adap.name));
568
569 ret = geni_se_resources_on(&gi2c->se);
570 if (ret) {
571 dev_err(&pdev->dev, "Error turning on resources %d\n", ret);
572 return ret;
573 }
574 proto = geni_se_read_proto(&gi2c->se);
575 tx_depth = geni_se_get_tx_fifo_depth(&gi2c->se);
576 if (proto != GENI_SE_I2C) {
577 dev_err(&pdev->dev, "Invalid proto %d\n", proto);
578 geni_se_resources_off(&gi2c->se);
579 return -ENXIO;
580 }
581 gi2c->tx_wm = tx_depth - 1;
582 geni_se_init(&gi2c->se, gi2c->tx_wm, tx_depth);
583 geni_se_config_packing(&gi2c->se, BITS_PER_BYTE, PACKING_BYTES_PW,
584 true, true, true);
585 ret = geni_se_resources_off(&gi2c->se);
586 if (ret) {
587 dev_err(&pdev->dev, "Error turning off resources %d\n", ret);
588 return ret;
589 }
590
591 dev_dbg(&pdev->dev, "i2c fifo/se-dma mode. fifo depth:%d\n", tx_depth);
592
593 ret = i2c_add_adapter(&gi2c->adap);
594 if (ret) {
595 dev_err(&pdev->dev, "Error adding i2c adapter %d\n", ret);
596 return ret;
597 }
598
599 gi2c->suspended = 1;
600 pm_runtime_set_suspended(gi2c->se.dev);
601 pm_runtime_set_autosuspend_delay(gi2c->se.dev, I2C_AUTO_SUSPEND_DELAY);
602 pm_runtime_use_autosuspend(gi2c->se.dev);
603 pm_runtime_enable(gi2c->se.dev);
604
605 return 0;
606 }
607
geni_i2c_remove(struct platform_device * pdev)608 static int geni_i2c_remove(struct platform_device *pdev)
609 {
610 struct geni_i2c_dev *gi2c = platform_get_drvdata(pdev);
611
612 pm_runtime_disable(gi2c->se.dev);
613 i2c_del_adapter(&gi2c->adap);
614 return 0;
615 }
616
geni_i2c_runtime_suspend(struct device * dev)617 static int __maybe_unused geni_i2c_runtime_suspend(struct device *dev)
618 {
619 int ret;
620 struct geni_i2c_dev *gi2c = dev_get_drvdata(dev);
621
622 disable_irq(gi2c->irq);
623 ret = geni_se_resources_off(&gi2c->se);
624 if (ret) {
625 enable_irq(gi2c->irq);
626 return ret;
627
628 } else {
629 gi2c->suspended = 1;
630 }
631
632 return 0;
633 }
634
geni_i2c_runtime_resume(struct device * dev)635 static int __maybe_unused geni_i2c_runtime_resume(struct device *dev)
636 {
637 int ret;
638 struct geni_i2c_dev *gi2c = dev_get_drvdata(dev);
639
640 ret = geni_se_resources_on(&gi2c->se);
641 if (ret)
642 return ret;
643
644 enable_irq(gi2c->irq);
645 gi2c->suspended = 0;
646 return 0;
647 }
648
geni_i2c_suspend_noirq(struct device * dev)649 static int __maybe_unused geni_i2c_suspend_noirq(struct device *dev)
650 {
651 struct geni_i2c_dev *gi2c = dev_get_drvdata(dev);
652
653 if (!gi2c->suspended) {
654 geni_i2c_runtime_suspend(dev);
655 pm_runtime_disable(dev);
656 pm_runtime_set_suspended(dev);
657 pm_runtime_enable(dev);
658 }
659 return 0;
660 }
661
662 static const struct dev_pm_ops geni_i2c_pm_ops = {
663 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(geni_i2c_suspend_noirq, NULL)
664 SET_RUNTIME_PM_OPS(geni_i2c_runtime_suspend, geni_i2c_runtime_resume,
665 NULL)
666 };
667
668 static const struct of_device_id geni_i2c_dt_match[] = {
669 { .compatible = "qcom,geni-i2c" },
670 {}
671 };
672 MODULE_DEVICE_TABLE(of, geni_i2c_dt_match);
673
674 static struct platform_driver geni_i2c_driver = {
675 .probe = geni_i2c_probe,
676 .remove = geni_i2c_remove,
677 .driver = {
678 .name = "geni_i2c",
679 .pm = &geni_i2c_pm_ops,
680 .of_match_table = geni_i2c_dt_match,
681 },
682 };
683
684 module_platform_driver(geni_i2c_driver);
685
686 MODULE_DESCRIPTION("I2C Controller Driver for GENI based QUP cores");
687 MODULE_LICENSE("GPL v2");
688
