1 // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0
2 /*
3 * Mellanox i2c driver
4 *
5 * Copyright (C) 2016-2020 Mellanox Technologies
6 */
7
8 #include <linux/delay.h>
9 #include <linux/i2c.h>
10 #include <linux/init.h>
11 #include <linux/io.h>
12 #include <linux/kernel.h>
13 #include <linux/module.h>
14 #include <linux/platform_data/mlxreg.h>
15 #include <linux/platform_device.h>
16 #include <linux/regmap.h>
17
18 /* General defines */
19 #define MLXPLAT_CPLD_LPC_I2C_BASE_ADDR 0x2000
20 #define MLXCPLD_I2C_DEVICE_NAME "i2c_mlxcpld"
21 #define MLXCPLD_I2C_VALID_FLAG (I2C_M_RECV_LEN | I2C_M_RD)
22 #define MLXCPLD_I2C_BUS_NUM 1
23 #define MLXCPLD_I2C_DATA_REG_SZ 36
24 #define MLXCPLD_I2C_DATA_SZ_BIT BIT(5)
25 #define MLXCPLD_I2C_DATA_SZ_MASK GENMASK(6, 5)
26 #define MLXCPLD_I2C_SMBUS_BLK_BIT BIT(7)
27 #define MLXCPLD_I2C_MAX_ADDR_LEN 4
28 #define MLXCPLD_I2C_RETR_NUM 2
29 #define MLXCPLD_I2C_XFER_TO 500000 /* usec */
30 #define MLXCPLD_I2C_POLL_TIME 200 /* usec */
31
32 /* LPC I2C registers */
33 #define MLXCPLD_LPCI2C_CPBLTY_REG 0x0
34 #define MLXCPLD_LPCI2C_CTRL_REG 0x1
35 #define MLXCPLD_LPCI2C_HALF_CYC_REG 0x4
36 #define MLXCPLD_LPCI2C_I2C_HOLD_REG 0x5
37 #define MLXCPLD_LPCI2C_CMD_REG 0x6
38 #define MLXCPLD_LPCI2C_NUM_DAT_REG 0x7
39 #define MLXCPLD_LPCI2C_NUM_ADDR_REG 0x8
40 #define MLXCPLD_LPCI2C_STATUS_REG 0x9
41 #define MLXCPLD_LPCI2C_DATA_REG 0xa
42
43 /* LPC I2C masks and parameters */
44 #define MLXCPLD_LPCI2C_RST_SEL_MASK 0x1
45 #define MLXCPLD_LPCI2C_TRANS_END 0x1
46 #define MLXCPLD_LPCI2C_STATUS_NACK 0x10
47 #define MLXCPLD_LPCI2C_NO_IND 0
48 #define MLXCPLD_LPCI2C_ACK_IND 1
49 #define MLXCPLD_LPCI2C_NACK_IND 2
50
51 #define MLXCPLD_I2C_FREQ_1000KHZ_SET 0x04
52 #define MLXCPLD_I2C_FREQ_400KHZ_SET 0x0e
53 #define MLXCPLD_I2C_FREQ_100KHZ_SET 0x42
54
55 enum mlxcpld_i2c_frequency {
56 MLXCPLD_I2C_FREQ_1000KHZ = 1,
57 MLXCPLD_I2C_FREQ_400KHZ = 2,
58 MLXCPLD_I2C_FREQ_100KHZ = 3,
59 };
60
61 struct mlxcpld_i2c_curr_xfer {
62 u8 cmd;
63 u8 addr_width;
64 u8 data_len;
65 u8 msg_num;
66 struct i2c_msg *msg;
67 };
68
69 struct mlxcpld_i2c_priv {
70 struct i2c_adapter adap;
71 u32 base_addr;
72 struct mutex lock;
73 struct mlxcpld_i2c_curr_xfer xfer;
74 struct device *dev;
75 bool smbus_block;
76 int polling_time;
77 };
78
mlxcpld_i2c_lpc_write_buf(u8 * data,u8 len,u32 addr)79 static void mlxcpld_i2c_lpc_write_buf(u8 *data, u8 len, u32 addr)
80 {
81 int i;
82
83 for (i = 0; i < len - len % 4; i += 4)
84 outl(*(u32 *)(data + i), addr + i);
85 for (; i < len; ++i)
86 outb(*(data + i), addr + i);
87 }
88
mlxcpld_i2c_lpc_read_buf(u8 * data,u8 len,u32 addr)89 static void mlxcpld_i2c_lpc_read_buf(u8 *data, u8 len, u32 addr)
90 {
91 int i;
92
93 for (i = 0; i < len - len % 4; i += 4)
94 *(u32 *)(data + i) = inl(addr + i);
95 for (; i < len; ++i)
96 *(data + i) = inb(addr + i);
97 }
98
mlxcpld_i2c_read_comm(struct mlxcpld_i2c_priv * priv,u8 offs,u8 * data,u8 datalen)99 static void mlxcpld_i2c_read_comm(struct mlxcpld_i2c_priv *priv, u8 offs,
100 u8 *data, u8 datalen)
101 {
102 u32 addr = priv->base_addr + offs;
103
104 switch (datalen) {
105 case 1:
106 *(data) = inb(addr);
107 break;
108 case 2:
109 *((u16 *)data) = inw(addr);
110 break;
111 case 3:
112 *((u16 *)data) = inw(addr);
113 *(data + 2) = inb(addr + 2);
114 break;
115 case 4:
116 *((u32 *)data) = inl(addr);
117 break;
118 default:
119 mlxcpld_i2c_lpc_read_buf(data, datalen, addr);
120 break;
121 }
122 }
123
mlxcpld_i2c_write_comm(struct mlxcpld_i2c_priv * priv,u8 offs,u8 * data,u8 datalen)124 static void mlxcpld_i2c_write_comm(struct mlxcpld_i2c_priv *priv, u8 offs,
125 u8 *data, u8 datalen)
126 {
127 u32 addr = priv->base_addr + offs;
128
129 switch (datalen) {
130 case 1:
131 outb(*(data), addr);
132 break;
133 case 2:
134 outw(*((u16 *)data), addr);
135 break;
136 case 3:
137 outw(*((u16 *)data), addr);
138 outb(*(data + 2), addr + 2);
139 break;
140 case 4:
141 outl(*((u32 *)data), addr);
142 break;
143 default:
144 mlxcpld_i2c_lpc_write_buf(data, datalen, addr);
145 break;
146 }
147 }
148
149 /*
150 * Check validity of received i2c messages parameters.
151 * Returns 0 if OK, other - in case of invalid parameters.
152 */
mlxcpld_i2c_check_msg_params(struct mlxcpld_i2c_priv * priv,struct i2c_msg * msgs,int num)153 static int mlxcpld_i2c_check_msg_params(struct mlxcpld_i2c_priv *priv,
154 struct i2c_msg *msgs, int num)
155 {
156 int i;
157
158 if (!num) {
159 dev_err(priv->dev, "Incorrect 0 num of messages\n");
160 return -EINVAL;
161 }
162
163 if (unlikely(msgs[0].addr > 0x7f)) {
164 dev_err(priv->dev, "Invalid address 0x%03x\n",
165 msgs[0].addr);
166 return -EINVAL;
167 }
168
169 for (i = 0; i < num; ++i) {
170 if (unlikely(!msgs[i].buf)) {
171 dev_err(priv->dev, "Invalid buf in msg[%d]\n",
172 i);
173 return -EINVAL;
174 }
175 if (unlikely(msgs[0].addr != msgs[i].addr)) {
176 dev_err(priv->dev, "Invalid addr in msg[%d]\n",
177 i);
178 return -EINVAL;
179 }
180 }
181
182 return 0;
183 }
184
185 /*
186 * Check if transfer is completed and status of operation.
187 * Returns 0 - transfer completed (both ACK or NACK),
188 * negative - transfer isn't finished.
189 */
mlxcpld_i2c_check_status(struct mlxcpld_i2c_priv * priv,int * status)190 static int mlxcpld_i2c_check_status(struct mlxcpld_i2c_priv *priv, int *status)
191 {
192 u8 val;
193
194 mlxcpld_i2c_read_comm(priv, MLXCPLD_LPCI2C_STATUS_REG, &val, 1);
195
196 if (val & MLXCPLD_LPCI2C_TRANS_END) {
197 if (val & MLXCPLD_LPCI2C_STATUS_NACK)
198 /*
199 * The slave is unable to accept the data. No such
200 * slave, command not understood, or unable to accept
201 * any more data.
202 */
203 *status = MLXCPLD_LPCI2C_NACK_IND;
204 else
205 *status = MLXCPLD_LPCI2C_ACK_IND;
206 return 0;
207 }
208 *status = MLXCPLD_LPCI2C_NO_IND;
209
210 return -EIO;
211 }
212
mlxcpld_i2c_set_transf_data(struct mlxcpld_i2c_priv * priv,struct i2c_msg * msgs,int num,u8 comm_len)213 static void mlxcpld_i2c_set_transf_data(struct mlxcpld_i2c_priv *priv,
214 struct i2c_msg *msgs, int num,
215 u8 comm_len)
216 {
217 priv->xfer.msg = msgs;
218 priv->xfer.msg_num = num;
219
220 /*
221 * All upper layers currently are never use transfer with more than
222 * 2 messages. Actually, it's also not so relevant in Mellanox systems
223 * because of HW limitation. Max size of transfer is not more than 32
224 * or 68 bytes in the current x86 LPCI2C bridge.
225 */
226 priv->xfer.cmd = msgs[num - 1].flags & I2C_M_RD;
227
228 if (priv->xfer.cmd == I2C_M_RD && comm_len != msgs[0].len) {
229 priv->xfer.addr_width = msgs[0].len;
230 priv->xfer.data_len = comm_len - priv->xfer.addr_width;
231 } else {
232 priv->xfer.addr_width = 0;
233 priv->xfer.data_len = comm_len;
234 }
235 }
236
237 /* Reset CPLD LPCI2C block */
mlxcpld_i2c_reset(struct mlxcpld_i2c_priv * priv)238 static void mlxcpld_i2c_reset(struct mlxcpld_i2c_priv *priv)
239 {
240 u8 val;
241
242 mutex_lock(&priv->lock);
243
244 mlxcpld_i2c_read_comm(priv, MLXCPLD_LPCI2C_CTRL_REG, &val, 1);
245 val &= ~MLXCPLD_LPCI2C_RST_SEL_MASK;
246 mlxcpld_i2c_write_comm(priv, MLXCPLD_LPCI2C_CTRL_REG, &val, 1);
247
248 mutex_unlock(&priv->lock);
249 }
250
251 /* Make sure the CPLD is ready to start transmitting. */
mlxcpld_i2c_check_busy(struct mlxcpld_i2c_priv * priv)252 static int mlxcpld_i2c_check_busy(struct mlxcpld_i2c_priv *priv)
253 {
254 u8 val;
255
256 mlxcpld_i2c_read_comm(priv, MLXCPLD_LPCI2C_STATUS_REG, &val, 1);
257
258 if (val & MLXCPLD_LPCI2C_TRANS_END)
259 return 0;
260
261 return -EIO;
262 }
263
mlxcpld_i2c_wait_for_free(struct mlxcpld_i2c_priv * priv)264 static int mlxcpld_i2c_wait_for_free(struct mlxcpld_i2c_priv *priv)
265 {
266 int timeout = 0;
267
268 do {
269 if (!mlxcpld_i2c_check_busy(priv))
270 break;
271 usleep_range(priv->polling_time / 2, priv->polling_time);
272 timeout += priv->polling_time;
273 } while (timeout <= MLXCPLD_I2C_XFER_TO);
274
275 if (timeout > MLXCPLD_I2C_XFER_TO)
276 return -ETIMEDOUT;
277
278 return 0;
279 }
280
281 /*
282 * Wait for master transfer to complete.
283 * It puts current process to sleep until we get interrupt or timeout expires.
284 * Returns the number of transferred or read bytes or error (<0).
285 */
mlxcpld_i2c_wait_for_tc(struct mlxcpld_i2c_priv * priv)286 static int mlxcpld_i2c_wait_for_tc(struct mlxcpld_i2c_priv *priv)
287 {
288 int status, i, timeout = 0;
289 u8 datalen, val;
290
291 do {
292 usleep_range(priv->polling_time / 2, priv->polling_time);
293 if (!mlxcpld_i2c_check_status(priv, &status))
294 break;
295 timeout += priv->polling_time;
296 } while (status == 0 && timeout < MLXCPLD_I2C_XFER_TO);
297
298 switch (status) {
299 case MLXCPLD_LPCI2C_NO_IND:
300 return -ETIMEDOUT;
301
302 case MLXCPLD_LPCI2C_ACK_IND:
303 if (priv->xfer.cmd != I2C_M_RD)
304 return (priv->xfer.addr_width + priv->xfer.data_len);
305
306 if (priv->xfer.msg_num == 1)
307 i = 0;
308 else
309 i = 1;
310
311 if (!priv->xfer.msg[i].buf)
312 return -EINVAL;
313
314 /*
315 * Actual read data len will be always the same as
316 * requested len. 0xff (line pull-up) will be returned
317 * if slave has no data to return. Thus don't read
318 * MLXCPLD_LPCI2C_NUM_DAT_REG reg from CPLD. Only in case of
319 * SMBus block read transaction data len can be different,
320 * check this case.
321 */
322 mlxcpld_i2c_read_comm(priv, MLXCPLD_LPCI2C_NUM_ADDR_REG, &val,
323 1);
324 if (priv->smbus_block && (val & MLXCPLD_I2C_SMBUS_BLK_BIT)) {
325 mlxcpld_i2c_read_comm(priv, MLXCPLD_LPCI2C_NUM_DAT_REG,
326 &datalen, 1);
327 if (unlikely(datalen > I2C_SMBUS_BLOCK_MAX)) {
328 dev_err(priv->dev, "Incorrect smbus block read message len\n");
329 return -EPROTO;
330 }
331 } else {
332 datalen = priv->xfer.data_len;
333 }
334
335 mlxcpld_i2c_read_comm(priv, MLXCPLD_LPCI2C_DATA_REG,
336 priv->xfer.msg[i].buf, datalen);
337
338 return datalen;
339
340 case MLXCPLD_LPCI2C_NACK_IND:
341 return -ENXIO;
342
343 default:
344 return -EINVAL;
345 }
346 }
347
mlxcpld_i2c_xfer_msg(struct mlxcpld_i2c_priv * priv)348 static void mlxcpld_i2c_xfer_msg(struct mlxcpld_i2c_priv *priv)
349 {
350 int i, len = 0;
351 u8 cmd, val;
352
353 mlxcpld_i2c_write_comm(priv, MLXCPLD_LPCI2C_NUM_DAT_REG,
354 &priv->xfer.data_len, 1);
355
356 val = priv->xfer.addr_width;
357 /* Notify HW about SMBus block read transaction */
358 if (priv->smbus_block && priv->xfer.msg_num >= 2 &&
359 priv->xfer.msg[1].len == 1 &&
360 (priv->xfer.msg[1].flags & I2C_M_RECV_LEN) &&
361 (priv->xfer.msg[1].flags & I2C_M_RD))
362 val |= MLXCPLD_I2C_SMBUS_BLK_BIT;
363
364 mlxcpld_i2c_write_comm(priv, MLXCPLD_LPCI2C_NUM_ADDR_REG, &val, 1);
365
366 for (i = 0; i < priv->xfer.msg_num; i++) {
367 if ((priv->xfer.msg[i].flags & I2C_M_RD) != I2C_M_RD) {
368 /* Don't write to CPLD buffer in read transaction */
369 mlxcpld_i2c_write_comm(priv, MLXCPLD_LPCI2C_DATA_REG +
370 len, priv->xfer.msg[i].buf,
371 priv->xfer.msg[i].len);
372 len += priv->xfer.msg[i].len;
373 }
374 }
375
376 /*
377 * Set target slave address with command for master transfer.
378 * It should be latest executed function before CPLD transaction.
379 */
380 cmd = (priv->xfer.msg[0].addr << 1) | priv->xfer.cmd;
381 mlxcpld_i2c_write_comm(priv, MLXCPLD_LPCI2C_CMD_REG, &cmd, 1);
382 }
383
384 /*
385 * Generic lpc-i2c transfer.
386 * Returns the number of processed messages or error (<0).
387 */
mlxcpld_i2c_xfer(struct i2c_adapter * adap,struct i2c_msg * msgs,int num)388 static int mlxcpld_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
389 int num)
390 {
391 struct mlxcpld_i2c_priv *priv = i2c_get_adapdata(adap);
392 u8 comm_len = 0;
393 int i, err;
394
395 err = mlxcpld_i2c_check_msg_params(priv, msgs, num);
396 if (err) {
397 dev_err(priv->dev, "Incorrect message\n");
398 return err;
399 }
400
401 for (i = 0; i < num; ++i)
402 comm_len += msgs[i].len;
403
404 /* Check bus state */
405 if (mlxcpld_i2c_wait_for_free(priv)) {
406 dev_err(priv->dev, "LPCI2C bridge is busy\n");
407
408 /*
409 * Usually it means something serious has happened.
410 * We can not have unfinished previous transfer
411 * so it doesn't make any sense to try to stop it.
412 * Probably we were not able to recover from the
413 * previous error.
414 * The only reasonable thing - is soft reset.
415 */
416 mlxcpld_i2c_reset(priv);
417 if (mlxcpld_i2c_check_busy(priv)) {
418 dev_err(priv->dev, "LPCI2C bridge is busy after reset\n");
419 return -EIO;
420 }
421 }
422
423 mlxcpld_i2c_set_transf_data(priv, msgs, num, comm_len);
424
425 mutex_lock(&priv->lock);
426
427 /* Do real transfer. Can't fail */
428 mlxcpld_i2c_xfer_msg(priv);
429
430 /* Wait for transaction complete */
431 err = mlxcpld_i2c_wait_for_tc(priv);
432
433 mutex_unlock(&priv->lock);
434
435 return err < 0 ? err : num;
436 }
437
mlxcpld_i2c_func(struct i2c_adapter * adap)438 static u32 mlxcpld_i2c_func(struct i2c_adapter *adap)
439 {
440 struct mlxcpld_i2c_priv *priv = i2c_get_adapdata(adap);
441
442 if (priv->smbus_block)
443 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
444 I2C_FUNC_SMBUS_I2C_BLOCK | I2C_FUNC_SMBUS_BLOCK_DATA;
445 else
446 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
447 I2C_FUNC_SMBUS_I2C_BLOCK;
448 }
449
450 static const struct i2c_algorithm mlxcpld_i2c_algo = {
451 .master_xfer = mlxcpld_i2c_xfer,
452 .functionality = mlxcpld_i2c_func
453 };
454
455 static const struct i2c_adapter_quirks mlxcpld_i2c_quirks = {
456 .flags = I2C_AQ_COMB_WRITE_THEN_READ,
457 .max_read_len = MLXCPLD_I2C_DATA_REG_SZ - MLXCPLD_I2C_MAX_ADDR_LEN,
458 .max_write_len = MLXCPLD_I2C_DATA_REG_SZ,
459 .max_comb_1st_msg_len = 4,
460 };
461
462 static const struct i2c_adapter_quirks mlxcpld_i2c_quirks_ext = {
463 .flags = I2C_AQ_COMB_WRITE_THEN_READ,
464 .max_read_len = MLXCPLD_I2C_DATA_REG_SZ * 2 - MLXCPLD_I2C_MAX_ADDR_LEN,
465 .max_write_len = MLXCPLD_I2C_DATA_REG_SZ * 2,
466 .max_comb_1st_msg_len = 4,
467 };
468
469 static struct i2c_adapter mlxcpld_i2c_adapter = {
470 .owner = THIS_MODULE,
471 .name = "i2c-mlxcpld",
472 .class = I2C_CLASS_HWMON | I2C_CLASS_SPD,
473 .algo = &mlxcpld_i2c_algo,
474 .quirks = &mlxcpld_i2c_quirks,
475 .retries = MLXCPLD_I2C_RETR_NUM,
476 .nr = MLXCPLD_I2C_BUS_NUM,
477 };
478
479 static int
mlxcpld_i2c_set_frequency(struct mlxcpld_i2c_priv * priv,struct mlxreg_core_hotplug_platform_data * pdata)480 mlxcpld_i2c_set_frequency(struct mlxcpld_i2c_priv *priv,
481 struct mlxreg_core_hotplug_platform_data *pdata)
482 {
483 struct mlxreg_core_item *item = pdata->items;
484 struct mlxreg_core_data *data;
485 u32 regval;
486 u8 freq;
487 int err;
488
489 if (!item)
490 return 0;
491
492 /* Read frequency setting. */
493 data = item->data;
494 err = regmap_read(pdata->regmap, data->reg, ®val);
495 if (err)
496 return err;
497
498 /* Set frequency only if it is not 100KHz, which is default. */
499 switch ((regval & data->mask) >> data->bit) {
500 case MLXCPLD_I2C_FREQ_1000KHZ:
501 freq = MLXCPLD_I2C_FREQ_1000KHZ_SET;
502 priv->polling_time /= 4;
503 break;
504 case MLXCPLD_I2C_FREQ_400KHZ:
505 freq = MLXCPLD_I2C_FREQ_400KHZ_SET;
506 priv->polling_time /= 4;
507 break;
508 default:
509 return 0;
510 }
511
512 mlxcpld_i2c_write_comm(priv, MLXCPLD_LPCI2C_HALF_CYC_REG, &freq, 1);
513
514 return 0;
515 }
516
mlxcpld_i2c_probe(struct platform_device * pdev)517 static int mlxcpld_i2c_probe(struct platform_device *pdev)
518 {
519 struct mlxreg_core_hotplug_platform_data *pdata;
520 struct mlxcpld_i2c_priv *priv;
521 int err;
522 u8 val;
523
524 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
525 if (!priv)
526 return -ENOMEM;
527
528 mutex_init(&priv->lock);
529 platform_set_drvdata(pdev, priv);
530
531 priv->dev = &pdev->dev;
532 priv->base_addr = MLXPLAT_CPLD_LPC_I2C_BASE_ADDR;
533 priv->polling_time = MLXCPLD_I2C_POLL_TIME;
534
535 /* Set I2C bus frequency if platform data provides this info. */
536 pdata = dev_get_platdata(&pdev->dev);
537 if (pdata) {
538 err = mlxcpld_i2c_set_frequency(priv, pdata);
539 if (err)
540 goto mlxcpld_i2_probe_failed;
541 }
542
543 /* Register with i2c layer */
544 mlxcpld_i2c_adapter.timeout = usecs_to_jiffies(MLXCPLD_I2C_XFER_TO);
545 /* Read capability register */
546 mlxcpld_i2c_read_comm(priv, MLXCPLD_LPCI2C_CPBLTY_REG, &val, 1);
547 /* Check support for extended transaction length */
548 if ((val & MLXCPLD_I2C_DATA_SZ_MASK) == MLXCPLD_I2C_DATA_SZ_BIT)
549 mlxcpld_i2c_adapter.quirks = &mlxcpld_i2c_quirks_ext;
550 /* Check support for smbus block transaction */
551 if (val & MLXCPLD_I2C_SMBUS_BLK_BIT)
552 priv->smbus_block = true;
553 if (pdev->id >= -1)
554 mlxcpld_i2c_adapter.nr = pdev->id;
555 priv->adap = mlxcpld_i2c_adapter;
556 priv->adap.dev.parent = &pdev->dev;
557 i2c_set_adapdata(&priv->adap, priv);
558
559 err = i2c_add_numbered_adapter(&priv->adap);
560 if (err)
561 goto mlxcpld_i2_probe_failed;
562
563 /* Notify caller when adapter is added. */
564 if (pdata && pdata->completion_notify)
565 pdata->completion_notify(pdata->handle, mlxcpld_i2c_adapter.nr);
566
567 return 0;
568
569 mlxcpld_i2_probe_failed:
570 mutex_destroy(&priv->lock);
571 return err;
572 }
573
mlxcpld_i2c_remove(struct platform_device * pdev)574 static int mlxcpld_i2c_remove(struct platform_device *pdev)
575 {
576 struct mlxcpld_i2c_priv *priv = platform_get_drvdata(pdev);
577
578 i2c_del_adapter(&priv->adap);
579 mutex_destroy(&priv->lock);
580
581 return 0;
582 }
583
584 static struct platform_driver mlxcpld_i2c_driver = {
585 .probe = mlxcpld_i2c_probe,
586 .remove = mlxcpld_i2c_remove,
587 .driver = {
588 .name = MLXCPLD_I2C_DEVICE_NAME,
589 },
590 };
591
592 module_platform_driver(mlxcpld_i2c_driver);
593
594 MODULE_AUTHOR("Michael Shych <michaels@mellanox.com>");
595 MODULE_DESCRIPTION("Mellanox I2C-CPLD controller driver");
596 MODULE_LICENSE("Dual BSD/GPL");
597 MODULE_ALIAS("platform:i2c-mlxcpld");
598
