1 /*
2 * Copyright (c) 2016 Mellanox Technologies. All rights reserved.
3 * Copyright (c) 2016 Michael Shych <michaels@mellanox.com>
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 *
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. Neither the names of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * Alternatively, this software may be distributed under the terms of the
18 * GNU General Public License ("GPL") version 2 as published by the Free
19 * Software Foundation.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 */
33
34 #include <linux/delay.h>
35 #include <linux/i2c.h>
36 #include <linux/init.h>
37 #include <linux/io.h>
38 #include <linux/kernel.h>
39 #include <linux/module.h>
40 #include <linux/platform_device.h>
41
42 /* General defines */
43 #define MLXPLAT_CPLD_LPC_I2C_BASE_ADDR 0x2000
44 #define MLXCPLD_I2C_DEVICE_NAME "i2c_mlxcpld"
45 #define MLXCPLD_I2C_VALID_FLAG (I2C_M_RECV_LEN | I2C_M_RD)
46 #define MLXCPLD_I2C_BUS_NUM 1
47 #define MLXCPLD_I2C_DATA_REG_SZ 36
48 #define MLXCPLD_I2C_DATA_SZ_BIT BIT(5)
49 #define MLXCPLD_I2C_DATA_SZ_MASK GENMASK(6, 5)
50 #define MLXCPLD_I2C_SMBUS_BLK_BIT BIT(7)
51 #define MLXCPLD_I2C_MAX_ADDR_LEN 4
52 #define MLXCPLD_I2C_RETR_NUM 2
53 #define MLXCPLD_I2C_XFER_TO 500000 /* usec */
54 #define MLXCPLD_I2C_POLL_TIME 2000 /* usec */
55
56 /* LPC I2C registers */
57 #define MLXCPLD_LPCI2C_CPBLTY_REG 0x0
58 #define MLXCPLD_LPCI2C_CTRL_REG 0x1
59 #define MLXCPLD_LPCI2C_HALF_CYC_REG 0x4
60 #define MLXCPLD_LPCI2C_I2C_HOLD_REG 0x5
61 #define MLXCPLD_LPCI2C_CMD_REG 0x6
62 #define MLXCPLD_LPCI2C_NUM_DAT_REG 0x7
63 #define MLXCPLD_LPCI2C_NUM_ADDR_REG 0x8
64 #define MLXCPLD_LPCI2C_STATUS_REG 0x9
65 #define MLXCPLD_LPCI2C_DATA_REG 0xa
66
67 /* LPC I2C masks and parametres */
68 #define MLXCPLD_LPCI2C_RST_SEL_MASK 0x1
69 #define MLXCPLD_LPCI2C_TRANS_END 0x1
70 #define MLXCPLD_LPCI2C_STATUS_NACK 0x10
71 #define MLXCPLD_LPCI2C_NO_IND 0
72 #define MLXCPLD_LPCI2C_ACK_IND 1
73 #define MLXCPLD_LPCI2C_NACK_IND 2
74
75 struct mlxcpld_i2c_curr_xfer {
76 u8 cmd;
77 u8 addr_width;
78 u8 data_len;
79 u8 msg_num;
80 struct i2c_msg *msg;
81 };
82
83 struct mlxcpld_i2c_priv {
84 struct i2c_adapter adap;
85 u32 base_addr;
86 struct mutex lock;
87 struct mlxcpld_i2c_curr_xfer xfer;
88 struct device *dev;
89 bool smbus_block;
90 };
91
mlxcpld_i2c_lpc_write_buf(u8 * data,u8 len,u32 addr)92 static void mlxcpld_i2c_lpc_write_buf(u8 *data, u8 len, u32 addr)
93 {
94 int i;
95
96 for (i = 0; i < len - len % 4; i += 4)
97 outl(*(u32 *)(data + i), addr + i);
98 for (; i < len; ++i)
99 outb(*(data + i), addr + i);
100 }
101
mlxcpld_i2c_lpc_read_buf(u8 * data,u8 len,u32 addr)102 static void mlxcpld_i2c_lpc_read_buf(u8 *data, u8 len, u32 addr)
103 {
104 int i;
105
106 for (i = 0; i < len - len % 4; i += 4)
107 *(u32 *)(data + i) = inl(addr + i);
108 for (; i < len; ++i)
109 *(data + i) = inb(addr + i);
110 }
111
mlxcpld_i2c_read_comm(struct mlxcpld_i2c_priv * priv,u8 offs,u8 * data,u8 datalen)112 static void mlxcpld_i2c_read_comm(struct mlxcpld_i2c_priv *priv, u8 offs,
113 u8 *data, u8 datalen)
114 {
115 u32 addr = priv->base_addr + offs;
116
117 switch (datalen) {
118 case 1:
119 *(data) = inb(addr);
120 break;
121 case 2:
122 *((u16 *)data) = inw(addr);
123 break;
124 case 3:
125 *((u16 *)data) = inw(addr);
126 *(data + 2) = inb(addr + 2);
127 break;
128 case 4:
129 *((u32 *)data) = inl(addr);
130 break;
131 default:
132 mlxcpld_i2c_lpc_read_buf(data, datalen, addr);
133 break;
134 }
135 }
136
mlxcpld_i2c_write_comm(struct mlxcpld_i2c_priv * priv,u8 offs,u8 * data,u8 datalen)137 static void mlxcpld_i2c_write_comm(struct mlxcpld_i2c_priv *priv, u8 offs,
138 u8 *data, u8 datalen)
139 {
140 u32 addr = priv->base_addr + offs;
141
142 switch (datalen) {
143 case 1:
144 outb(*(data), addr);
145 break;
146 case 2:
147 outw(*((u16 *)data), addr);
148 break;
149 case 3:
150 outw(*((u16 *)data), addr);
151 outb(*(data + 2), addr + 2);
152 break;
153 case 4:
154 outl(*((u32 *)data), addr);
155 break;
156 default:
157 mlxcpld_i2c_lpc_write_buf(data, datalen, addr);
158 break;
159 }
160 }
161
162 /*
163 * Check validity of received i2c messages parameters.
164 * Returns 0 if OK, other - in case of invalid parameters.
165 */
mlxcpld_i2c_check_msg_params(struct mlxcpld_i2c_priv * priv,struct i2c_msg * msgs,int num)166 static int mlxcpld_i2c_check_msg_params(struct mlxcpld_i2c_priv *priv,
167 struct i2c_msg *msgs, int num)
168 {
169 int i;
170
171 if (!num) {
172 dev_err(priv->dev, "Incorrect 0 num of messages\n");
173 return -EINVAL;
174 }
175
176 if (unlikely(msgs[0].addr > 0x7f)) {
177 dev_err(priv->dev, "Invalid address 0x%03x\n",
178 msgs[0].addr);
179 return -EINVAL;
180 }
181
182 for (i = 0; i < num; ++i) {
183 if (unlikely(!msgs[i].buf)) {
184 dev_err(priv->dev, "Invalid buf in msg[%d]\n",
185 i);
186 return -EINVAL;
187 }
188 if (unlikely(msgs[0].addr != msgs[i].addr)) {
189 dev_err(priv->dev, "Invalid addr in msg[%d]\n",
190 i);
191 return -EINVAL;
192 }
193 }
194
195 return 0;
196 }
197
198 /*
199 * Check if transfer is completed and status of operation.
200 * Returns 0 - transfer completed (both ACK or NACK),
201 * negative - transfer isn't finished.
202 */
mlxcpld_i2c_check_status(struct mlxcpld_i2c_priv * priv,int * status)203 static int mlxcpld_i2c_check_status(struct mlxcpld_i2c_priv *priv, int *status)
204 {
205 u8 val;
206
207 mlxcpld_i2c_read_comm(priv, MLXCPLD_LPCI2C_STATUS_REG, &val, 1);
208
209 if (val & MLXCPLD_LPCI2C_TRANS_END) {
210 if (val & MLXCPLD_LPCI2C_STATUS_NACK)
211 /*
212 * The slave is unable to accept the data. No such
213 * slave, command not understood, or unable to accept
214 * any more data.
215 */
216 *status = MLXCPLD_LPCI2C_NACK_IND;
217 else
218 *status = MLXCPLD_LPCI2C_ACK_IND;
219 return 0;
220 }
221 *status = MLXCPLD_LPCI2C_NO_IND;
222
223 return -EIO;
224 }
225
mlxcpld_i2c_set_transf_data(struct mlxcpld_i2c_priv * priv,struct i2c_msg * msgs,int num,u8 comm_len)226 static void mlxcpld_i2c_set_transf_data(struct mlxcpld_i2c_priv *priv,
227 struct i2c_msg *msgs, int num,
228 u8 comm_len)
229 {
230 priv->xfer.msg = msgs;
231 priv->xfer.msg_num = num;
232
233 /*
234 * All upper layers currently are never use transfer with more than
235 * 2 messages. Actually, it's also not so relevant in Mellanox systems
236 * because of HW limitation. Max size of transfer is not more than 32
237 * or 68 bytes in the current x86 LPCI2C bridge.
238 */
239 priv->xfer.cmd = msgs[num - 1].flags & I2C_M_RD;
240
241 if (priv->xfer.cmd == I2C_M_RD && comm_len != msgs[0].len) {
242 priv->xfer.addr_width = msgs[0].len;
243 priv->xfer.data_len = comm_len - priv->xfer.addr_width;
244 } else {
245 priv->xfer.addr_width = 0;
246 priv->xfer.data_len = comm_len;
247 }
248 }
249
250 /* Reset CPLD LPCI2C block */
mlxcpld_i2c_reset(struct mlxcpld_i2c_priv * priv)251 static void mlxcpld_i2c_reset(struct mlxcpld_i2c_priv *priv)
252 {
253 u8 val;
254
255 mutex_lock(&priv->lock);
256
257 mlxcpld_i2c_read_comm(priv, MLXCPLD_LPCI2C_CTRL_REG, &val, 1);
258 val &= ~MLXCPLD_LPCI2C_RST_SEL_MASK;
259 mlxcpld_i2c_write_comm(priv, MLXCPLD_LPCI2C_CTRL_REG, &val, 1);
260
261 mutex_unlock(&priv->lock);
262 }
263
264 /* Make sure the CPLD is ready to start transmitting. */
mlxcpld_i2c_check_busy(struct mlxcpld_i2c_priv * priv)265 static int mlxcpld_i2c_check_busy(struct mlxcpld_i2c_priv *priv)
266 {
267 u8 val;
268
269 mlxcpld_i2c_read_comm(priv, MLXCPLD_LPCI2C_STATUS_REG, &val, 1);
270
271 if (val & MLXCPLD_LPCI2C_TRANS_END)
272 return 0;
273
274 return -EIO;
275 }
276
mlxcpld_i2c_wait_for_free(struct mlxcpld_i2c_priv * priv)277 static int mlxcpld_i2c_wait_for_free(struct mlxcpld_i2c_priv *priv)
278 {
279 int timeout = 0;
280
281 do {
282 if (!mlxcpld_i2c_check_busy(priv))
283 break;
284 usleep_range(MLXCPLD_I2C_POLL_TIME / 2, MLXCPLD_I2C_POLL_TIME);
285 timeout += MLXCPLD_I2C_POLL_TIME;
286 } while (timeout <= MLXCPLD_I2C_XFER_TO);
287
288 if (timeout > MLXCPLD_I2C_XFER_TO)
289 return -ETIMEDOUT;
290
291 return 0;
292 }
293
294 /*
295 * Wait for master transfer to complete.
296 * It puts current process to sleep until we get interrupt or timeout expires.
297 * Returns the number of transferred or read bytes or error (<0).
298 */
mlxcpld_i2c_wait_for_tc(struct mlxcpld_i2c_priv * priv)299 static int mlxcpld_i2c_wait_for_tc(struct mlxcpld_i2c_priv *priv)
300 {
301 int status, i, timeout = 0;
302 u8 datalen, val;
303
304 do {
305 usleep_range(MLXCPLD_I2C_POLL_TIME / 2, MLXCPLD_I2C_POLL_TIME);
306 if (!mlxcpld_i2c_check_status(priv, &status))
307 break;
308 timeout += MLXCPLD_I2C_POLL_TIME;
309 } while (status == 0 && timeout < MLXCPLD_I2C_XFER_TO);
310
311 switch (status) {
312 case MLXCPLD_LPCI2C_NO_IND:
313 return -ETIMEDOUT;
314
315 case MLXCPLD_LPCI2C_ACK_IND:
316 if (priv->xfer.cmd != I2C_M_RD)
317 return (priv->xfer.addr_width + priv->xfer.data_len);
318
319 if (priv->xfer.msg_num == 1)
320 i = 0;
321 else
322 i = 1;
323
324 if (!priv->xfer.msg[i].buf)
325 return -EINVAL;
326
327 /*
328 * Actual read data len will be always the same as
329 * requested len. 0xff (line pull-up) will be returned
330 * if slave has no data to return. Thus don't read
331 * MLXCPLD_LPCI2C_NUM_DAT_REG reg from CPLD. Only in case of
332 * SMBus block read transaction data len can be different,
333 * check this case.
334 */
335 mlxcpld_i2c_read_comm(priv, MLXCPLD_LPCI2C_NUM_ADDR_REG, &val,
336 1);
337 if (priv->smbus_block && (val & MLXCPLD_I2C_SMBUS_BLK_BIT)) {
338 mlxcpld_i2c_read_comm(priv, MLXCPLD_LPCI2C_NUM_DAT_REG,
339 &datalen, 1);
340 if (unlikely(datalen > (I2C_SMBUS_BLOCK_MAX + 1))) {
341 dev_err(priv->dev, "Incorrect smbus block read message len\n");
342 return -E2BIG;
343 }
344 } else {
345 datalen = priv->xfer.data_len;
346 }
347
348 mlxcpld_i2c_read_comm(priv, MLXCPLD_LPCI2C_DATA_REG,
349 priv->xfer.msg[i].buf, datalen);
350
351 return datalen;
352
353 case MLXCPLD_LPCI2C_NACK_IND:
354 return -ENXIO;
355
356 default:
357 return -EINVAL;
358 }
359 }
360
mlxcpld_i2c_xfer_msg(struct mlxcpld_i2c_priv * priv)361 static void mlxcpld_i2c_xfer_msg(struct mlxcpld_i2c_priv *priv)
362 {
363 int i, len = 0;
364 u8 cmd, val;
365
366 mlxcpld_i2c_write_comm(priv, MLXCPLD_LPCI2C_NUM_DAT_REG,
367 &priv->xfer.data_len, 1);
368
369 val = priv->xfer.addr_width;
370 /* Notify HW about SMBus block read transaction */
371 if (priv->smbus_block && priv->xfer.msg_num >= 2 &&
372 priv->xfer.msg[1].len == 1 &&
373 (priv->xfer.msg[1].flags & I2C_M_RECV_LEN) &&
374 (priv->xfer.msg[1].flags & I2C_M_RD))
375 val |= MLXCPLD_I2C_SMBUS_BLK_BIT;
376
377 mlxcpld_i2c_write_comm(priv, MLXCPLD_LPCI2C_NUM_ADDR_REG, &val, 1);
378
379 for (i = 0; i < priv->xfer.msg_num; i++) {
380 if ((priv->xfer.msg[i].flags & I2C_M_RD) != I2C_M_RD) {
381 /* Don't write to CPLD buffer in read transaction */
382 mlxcpld_i2c_write_comm(priv, MLXCPLD_LPCI2C_DATA_REG +
383 len, priv->xfer.msg[i].buf,
384 priv->xfer.msg[i].len);
385 len += priv->xfer.msg[i].len;
386 }
387 }
388
389 /*
390 * Set target slave address with command for master transfer.
391 * It should be latest executed function before CPLD transaction.
392 */
393 cmd = (priv->xfer.msg[0].addr << 1) | priv->xfer.cmd;
394 mlxcpld_i2c_write_comm(priv, MLXCPLD_LPCI2C_CMD_REG, &cmd, 1);
395 }
396
397 /*
398 * Generic lpc-i2c transfer.
399 * Returns the number of processed messages or error (<0).
400 */
mlxcpld_i2c_xfer(struct i2c_adapter * adap,struct i2c_msg * msgs,int num)401 static int mlxcpld_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
402 int num)
403 {
404 struct mlxcpld_i2c_priv *priv = i2c_get_adapdata(adap);
405 u8 comm_len = 0;
406 int i, err;
407
408 err = mlxcpld_i2c_check_msg_params(priv, msgs, num);
409 if (err) {
410 dev_err(priv->dev, "Incorrect message\n");
411 return err;
412 }
413
414 for (i = 0; i < num; ++i)
415 comm_len += msgs[i].len;
416
417 /* Check bus state */
418 if (mlxcpld_i2c_wait_for_free(priv)) {
419 dev_err(priv->dev, "LPCI2C bridge is busy\n");
420
421 /*
422 * Usually it means something serious has happened.
423 * We can not have unfinished previous transfer
424 * so it doesn't make any sense to try to stop it.
425 * Probably we were not able to recover from the
426 * previous error.
427 * The only reasonable thing - is soft reset.
428 */
429 mlxcpld_i2c_reset(priv);
430 if (mlxcpld_i2c_check_busy(priv)) {
431 dev_err(priv->dev, "LPCI2C bridge is busy after reset\n");
432 return -EIO;
433 }
434 }
435
436 mlxcpld_i2c_set_transf_data(priv, msgs, num, comm_len);
437
438 mutex_lock(&priv->lock);
439
440 /* Do real transfer. Can't fail */
441 mlxcpld_i2c_xfer_msg(priv);
442
443 /* Wait for transaction complete */
444 err = mlxcpld_i2c_wait_for_tc(priv);
445
446 mutex_unlock(&priv->lock);
447
448 return err < 0 ? err : num;
449 }
450
mlxcpld_i2c_func(struct i2c_adapter * adap)451 static u32 mlxcpld_i2c_func(struct i2c_adapter *adap)
452 {
453 struct mlxcpld_i2c_priv *priv = i2c_get_adapdata(adap);
454
455 if (priv->smbus_block)
456 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
457 I2C_FUNC_SMBUS_I2C_BLOCK | I2C_FUNC_SMBUS_BLOCK_DATA;
458 else
459 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
460 I2C_FUNC_SMBUS_I2C_BLOCK;
461 }
462
463 static const struct i2c_algorithm mlxcpld_i2c_algo = {
464 .master_xfer = mlxcpld_i2c_xfer,
465 .functionality = mlxcpld_i2c_func
466 };
467
468 static const struct i2c_adapter_quirks mlxcpld_i2c_quirks = {
469 .flags = I2C_AQ_COMB_WRITE_THEN_READ,
470 .max_read_len = MLXCPLD_I2C_DATA_REG_SZ - MLXCPLD_I2C_MAX_ADDR_LEN,
471 .max_write_len = MLXCPLD_I2C_DATA_REG_SZ,
472 .max_comb_1st_msg_len = 4,
473 };
474
475 static const struct i2c_adapter_quirks mlxcpld_i2c_quirks_ext = {
476 .flags = I2C_AQ_COMB_WRITE_THEN_READ,
477 .max_read_len = MLXCPLD_I2C_DATA_REG_SZ * 2 - MLXCPLD_I2C_MAX_ADDR_LEN,
478 .max_write_len = MLXCPLD_I2C_DATA_REG_SZ * 2,
479 .max_comb_1st_msg_len = 4,
480 };
481
482 static struct i2c_adapter mlxcpld_i2c_adapter = {
483 .owner = THIS_MODULE,
484 .name = "i2c-mlxcpld",
485 .class = I2C_CLASS_HWMON | I2C_CLASS_SPD,
486 .algo = &mlxcpld_i2c_algo,
487 .quirks = &mlxcpld_i2c_quirks,
488 .retries = MLXCPLD_I2C_RETR_NUM,
489 .nr = MLXCPLD_I2C_BUS_NUM,
490 };
491
mlxcpld_i2c_probe(struct platform_device * pdev)492 static int mlxcpld_i2c_probe(struct platform_device *pdev)
493 {
494 struct mlxcpld_i2c_priv *priv;
495 int err;
496 u8 val;
497
498 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
499 if (!priv)
500 return -ENOMEM;
501
502 mutex_init(&priv->lock);
503 platform_set_drvdata(pdev, priv);
504
505 priv->dev = &pdev->dev;
506
507 /* Register with i2c layer */
508 mlxcpld_i2c_adapter.timeout = usecs_to_jiffies(MLXCPLD_I2C_XFER_TO);
509 /* Read capability register */
510 mlxcpld_i2c_read_comm(priv, MLXCPLD_LPCI2C_CPBLTY_REG, &val, 1);
511 /* Check support for extended transaction length */
512 if ((val & MLXCPLD_I2C_DATA_SZ_MASK) == MLXCPLD_I2C_DATA_SZ_BIT)
513 mlxcpld_i2c_adapter.quirks = &mlxcpld_i2c_quirks_ext;
514 /* Check support for smbus block transaction */
515 if (val & MLXCPLD_I2C_SMBUS_BLK_BIT)
516 priv->smbus_block = true;
517 if (pdev->id >= -1)
518 mlxcpld_i2c_adapter.nr = pdev->id;
519 priv->adap = mlxcpld_i2c_adapter;
520 priv->adap.dev.parent = &pdev->dev;
521 priv->base_addr = MLXPLAT_CPLD_LPC_I2C_BASE_ADDR;
522 i2c_set_adapdata(&priv->adap, priv);
523
524 err = i2c_add_numbered_adapter(&priv->adap);
525 if (err)
526 mutex_destroy(&priv->lock);
527
528 return err;
529 }
530
mlxcpld_i2c_remove(struct platform_device * pdev)531 static int mlxcpld_i2c_remove(struct platform_device *pdev)
532 {
533 struct mlxcpld_i2c_priv *priv = platform_get_drvdata(pdev);
534
535 i2c_del_adapter(&priv->adap);
536 mutex_destroy(&priv->lock);
537
538 return 0;
539 }
540
541 static struct platform_driver mlxcpld_i2c_driver = {
542 .probe = mlxcpld_i2c_probe,
543 .remove = mlxcpld_i2c_remove,
544 .driver = {
545 .name = MLXCPLD_I2C_DEVICE_NAME,
546 },
547 };
548
549 module_platform_driver(mlxcpld_i2c_driver);
550
551 MODULE_AUTHOR("Michael Shych <michaels@mellanox.com>");
552 MODULE_DESCRIPTION("Mellanox I2C-CPLD controller driver");
553 MODULE_LICENSE("Dual BSD/GPL");
554 MODULE_ALIAS("platform:i2c-mlxcpld");
555
