1 /*
2 * This file is provided under a dual BSD/GPLv2 license. When using or
3 * redistributing this file, you may do so under either license.
4 *
5 * Copyright(c) 2012 Intel Corporation. All rights reserved.
6 *
7 * GPL LICENSE SUMMARY
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of version 2 of the GNU General Public License as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 * The full GNU General Public License is included in this distribution
18 * in the file called LICENSE.GPL.
19 *
20 * BSD LICENSE
21 *
22 * Redistribution and use in source and binary forms, with or without
23 * modification, are permitted provided that the following conditions
24 * are met:
25 *
26 * * Redistributions of source code must retain the above copyright
27 * notice, this list of conditions and the following disclaimer.
28 * * Redistributions in binary form must reproduce the above copyright
29 * notice, this list of conditions and the following disclaimer in
30 * the documentation and/or other materials provided with the
31 * distribution.
32 * * Neither the name of Intel Corporation nor the names of its
33 * contributors may be used to endorse or promote products derived
34 * from this software without specific prior written permission.
35 *
36 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
37 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
38 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
39 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
40 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
41 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
42 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
43 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
44 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
45 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
46 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
47 */
48
49 /*
50 * Supports the SMBus Message Transport (SMT) in the Intel Atom Processor
51 * S12xx Product Family.
52 *
53 * Features supported by this driver:
54 * Hardware PEC yes
55 * Block buffer yes
56 * Block process call transaction no
57 * Slave mode no
58 */
59
60 #include <linux/module.h>
61 #include <linux/pci.h>
62 #include <linux/kernel.h>
63 #include <linux/stddef.h>
64 #include <linux/completion.h>
65 #include <linux/dma-mapping.h>
66 #include <linux/i2c.h>
67 #include <linux/acpi.h>
68 #include <linux/interrupt.h>
69
70 #include <linux/io-64-nonatomic-lo-hi.h>
71
72 /* PCI Address Constants */
73 #define SMBBAR 0
74
75 /* PCI DIDs for the Intel SMBus Message Transport (SMT) Devices */
76 #define PCI_DEVICE_ID_INTEL_S1200_SMT0 0x0c59
77 #define PCI_DEVICE_ID_INTEL_S1200_SMT1 0x0c5a
78 #define PCI_DEVICE_ID_INTEL_CDF_SMT 0x18ac
79 #define PCI_DEVICE_ID_INTEL_DNV_SMT 0x19ac
80 #define PCI_DEVICE_ID_INTEL_AVOTON_SMT 0x1f15
81
82 #define ISMT_DESC_ENTRIES 2 /* number of descriptor entries */
83 #define ISMT_MAX_RETRIES 3 /* number of SMBus retries to attempt */
84
85 /* Hardware Descriptor Constants - Control Field */
86 #define ISMT_DESC_CWRL 0x01 /* Command/Write Length */
87 #define ISMT_DESC_BLK 0X04 /* Perform Block Transaction */
88 #define ISMT_DESC_FAIR 0x08 /* Set fairness flag upon successful arbit. */
89 #define ISMT_DESC_PEC 0x10 /* Packet Error Code */
90 #define ISMT_DESC_I2C 0x20 /* I2C Enable */
91 #define ISMT_DESC_INT 0x40 /* Interrupt */
92 #define ISMT_DESC_SOE 0x80 /* Stop On Error */
93
94 /* Hardware Descriptor Constants - Status Field */
95 #define ISMT_DESC_SCS 0x01 /* Success */
96 #define ISMT_DESC_DLTO 0x04 /* Data Low Time Out */
97 #define ISMT_DESC_NAK 0x08 /* NAK Received */
98 #define ISMT_DESC_CRC 0x10 /* CRC Error */
99 #define ISMT_DESC_CLTO 0x20 /* Clock Low Time Out */
100 #define ISMT_DESC_COL 0x40 /* Collisions */
101 #define ISMT_DESC_LPR 0x80 /* Large Packet Received */
102
103 /* Macros */
104 #define ISMT_DESC_ADDR_RW(addr, rw) (((addr) << 1) | (rw))
105
106 /* iSMT General Register address offsets (SMBBAR + <addr>) */
107 #define ISMT_GR_GCTRL 0x000 /* General Control */
108 #define ISMT_GR_SMTICL 0x008 /* SMT Interrupt Cause Location */
109 #define ISMT_GR_ERRINTMSK 0x010 /* Error Interrupt Mask */
110 #define ISMT_GR_ERRAERMSK 0x014 /* Error AER Mask */
111 #define ISMT_GR_ERRSTS 0x018 /* Error Status */
112 #define ISMT_GR_ERRINFO 0x01c /* Error Information */
113
114 /* iSMT Master Registers */
115 #define ISMT_MSTR_MDBA 0x100 /* Master Descriptor Base Address */
116 #define ISMT_MSTR_MCTRL 0x108 /* Master Control */
117 #define ISMT_MSTR_MSTS 0x10c /* Master Status */
118 #define ISMT_MSTR_MDS 0x110 /* Master Descriptor Size */
119 #define ISMT_MSTR_RPOLICY 0x114 /* Retry Policy */
120
121 /* iSMT Miscellaneous Registers */
122 #define ISMT_SPGT 0x300 /* SMBus PHY Global Timing */
123
124 /* General Control Register (GCTRL) bit definitions */
125 #define ISMT_GCTRL_TRST 0x04 /* Target Reset */
126 #define ISMT_GCTRL_KILL 0x08 /* Kill */
127 #define ISMT_GCTRL_SRST 0x40 /* Soft Reset */
128
129 /* Master Control Register (MCTRL) bit definitions */
130 #define ISMT_MCTRL_SS 0x01 /* Start/Stop */
131 #define ISMT_MCTRL_MEIE 0x10 /* Master Error Interrupt Enable */
132 #define ISMT_MCTRL_FMHP 0x00ff0000 /* Firmware Master Head Ptr (FMHP) */
133
134 /* Master Status Register (MSTS) bit definitions */
135 #define ISMT_MSTS_HMTP 0xff0000 /* HW Master Tail Pointer (HMTP) */
136 #define ISMT_MSTS_MIS 0x20 /* Master Interrupt Status (MIS) */
137 #define ISMT_MSTS_MEIS 0x10 /* Master Error Int Status (MEIS) */
138 #define ISMT_MSTS_IP 0x01 /* In Progress */
139
140 /* Master Descriptor Size (MDS) bit definitions */
141 #define ISMT_MDS_MASK 0xff /* Master Descriptor Size mask (MDS) */
142
143 /* SMBus PHY Global Timing Register (SPGT) bit definitions */
144 #define ISMT_SPGT_SPD_MASK 0xc0000000 /* SMBus Speed mask */
145 #define ISMT_SPGT_SPD_80K 0x00 /* 80 kHz */
146 #define ISMT_SPGT_SPD_100K (0x1 << 30) /* 100 kHz */
147 #define ISMT_SPGT_SPD_400K (0x2 << 30) /* 400 kHz */
148 #define ISMT_SPGT_SPD_1M (0x3 << 30) /* 1 MHz */
149
150
151 /* MSI Control Register (MSICTL) bit definitions */
152 #define ISMT_MSICTL_MSIE 0x01 /* MSI Enable */
153
154 /* iSMT Hardware Descriptor */
155 struct ismt_desc {
156 u8 tgtaddr_rw; /* target address & r/w bit */
157 u8 wr_len_cmd; /* write length in bytes or a command */
158 u8 rd_len; /* read length */
159 u8 control; /* control bits */
160 u8 status; /* status bits */
161 u8 retry; /* collision retry and retry count */
162 u8 rxbytes; /* received bytes */
163 u8 txbytes; /* transmitted bytes */
164 u32 dptr_low; /* lower 32 bit of the data pointer */
165 u32 dptr_high; /* upper 32 bit of the data pointer */
166 } __packed;
167
168 struct ismt_priv {
169 struct i2c_adapter adapter;
170 void __iomem *smba; /* PCI BAR */
171 struct pci_dev *pci_dev;
172 struct ismt_desc *hw; /* descriptor virt base addr */
173 dma_addr_t io_rng_dma; /* descriptor HW base addr */
174 u8 head; /* ring buffer head pointer */
175 struct completion cmp; /* interrupt completion */
176 u8 buffer[I2C_SMBUS_BLOCK_MAX + 16]; /* temp R/W data buffer */
177 };
178
179 /**
180 * ismt_ids - PCI device IDs supported by this driver
181 */
182 static const struct pci_device_id ismt_ids[] = {
183 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_S1200_SMT0) },
184 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_S1200_SMT1) },
185 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CDF_SMT) },
186 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DNV_SMT) },
187 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_AVOTON_SMT) },
188 { 0, }
189 };
190
191 MODULE_DEVICE_TABLE(pci, ismt_ids);
192
193 /* Bus speed control bits for slow debuggers - refer to the docs for usage */
194 static unsigned int bus_speed;
195 module_param(bus_speed, uint, S_IRUGO);
196 MODULE_PARM_DESC(bus_speed, "Bus Speed in kHz (0 = BIOS default)");
197
198 /**
199 * __ismt_desc_dump() - dump the contents of a specific descriptor
200 */
__ismt_desc_dump(struct device * dev,const struct ismt_desc * desc)201 static void __ismt_desc_dump(struct device *dev, const struct ismt_desc *desc)
202 {
203
204 dev_dbg(dev, "Descriptor struct: %p\n", desc);
205 dev_dbg(dev, "\ttgtaddr_rw=0x%02X\n", desc->tgtaddr_rw);
206 dev_dbg(dev, "\twr_len_cmd=0x%02X\n", desc->wr_len_cmd);
207 dev_dbg(dev, "\trd_len= 0x%02X\n", desc->rd_len);
208 dev_dbg(dev, "\tcontrol= 0x%02X\n", desc->control);
209 dev_dbg(dev, "\tstatus= 0x%02X\n", desc->status);
210 dev_dbg(dev, "\tretry= 0x%02X\n", desc->retry);
211 dev_dbg(dev, "\trxbytes= 0x%02X\n", desc->rxbytes);
212 dev_dbg(dev, "\ttxbytes= 0x%02X\n", desc->txbytes);
213 dev_dbg(dev, "\tdptr_low= 0x%08X\n", desc->dptr_low);
214 dev_dbg(dev, "\tdptr_high= 0x%08X\n", desc->dptr_high);
215 }
216 /**
217 * ismt_desc_dump() - dump the contents of a descriptor for debug purposes
218 * @priv: iSMT private data
219 */
ismt_desc_dump(struct ismt_priv * priv)220 static void ismt_desc_dump(struct ismt_priv *priv)
221 {
222 struct device *dev = &priv->pci_dev->dev;
223 struct ismt_desc *desc = &priv->hw[priv->head];
224
225 dev_dbg(dev, "Dump of the descriptor struct: 0x%X\n", priv->head);
226 __ismt_desc_dump(dev, desc);
227 }
228
229 /**
230 * ismt_gen_reg_dump() - dump the iSMT General Registers
231 * @priv: iSMT private data
232 */
ismt_gen_reg_dump(struct ismt_priv * priv)233 static void ismt_gen_reg_dump(struct ismt_priv *priv)
234 {
235 struct device *dev = &priv->pci_dev->dev;
236
237 dev_dbg(dev, "Dump of the iSMT General Registers\n");
238 dev_dbg(dev, " GCTRL.... : (0x%p)=0x%X\n",
239 priv->smba + ISMT_GR_GCTRL,
240 readl(priv->smba + ISMT_GR_GCTRL));
241 dev_dbg(dev, " SMTICL... : (0x%p)=0x%016llX\n",
242 priv->smba + ISMT_GR_SMTICL,
243 (long long unsigned int)readq(priv->smba + ISMT_GR_SMTICL));
244 dev_dbg(dev, " ERRINTMSK : (0x%p)=0x%X\n",
245 priv->smba + ISMT_GR_ERRINTMSK,
246 readl(priv->smba + ISMT_GR_ERRINTMSK));
247 dev_dbg(dev, " ERRAERMSK : (0x%p)=0x%X\n",
248 priv->smba + ISMT_GR_ERRAERMSK,
249 readl(priv->smba + ISMT_GR_ERRAERMSK));
250 dev_dbg(dev, " ERRSTS... : (0x%p)=0x%X\n",
251 priv->smba + ISMT_GR_ERRSTS,
252 readl(priv->smba + ISMT_GR_ERRSTS));
253 dev_dbg(dev, " ERRINFO.. : (0x%p)=0x%X\n",
254 priv->smba + ISMT_GR_ERRINFO,
255 readl(priv->smba + ISMT_GR_ERRINFO));
256 }
257
258 /**
259 * ismt_mstr_reg_dump() - dump the iSMT Master Registers
260 * @priv: iSMT private data
261 */
ismt_mstr_reg_dump(struct ismt_priv * priv)262 static void ismt_mstr_reg_dump(struct ismt_priv *priv)
263 {
264 struct device *dev = &priv->pci_dev->dev;
265
266 dev_dbg(dev, "Dump of the iSMT Master Registers\n");
267 dev_dbg(dev, " MDBA..... : (0x%p)=0x%016llX\n",
268 priv->smba + ISMT_MSTR_MDBA,
269 (long long unsigned int)readq(priv->smba + ISMT_MSTR_MDBA));
270 dev_dbg(dev, " MCTRL.... : (0x%p)=0x%X\n",
271 priv->smba + ISMT_MSTR_MCTRL,
272 readl(priv->smba + ISMT_MSTR_MCTRL));
273 dev_dbg(dev, " MSTS..... : (0x%p)=0x%X\n",
274 priv->smba + ISMT_MSTR_MSTS,
275 readl(priv->smba + ISMT_MSTR_MSTS));
276 dev_dbg(dev, " MDS...... : (0x%p)=0x%X\n",
277 priv->smba + ISMT_MSTR_MDS,
278 readl(priv->smba + ISMT_MSTR_MDS));
279 dev_dbg(dev, " RPOLICY.. : (0x%p)=0x%X\n",
280 priv->smba + ISMT_MSTR_RPOLICY,
281 readl(priv->smba + ISMT_MSTR_RPOLICY));
282 dev_dbg(dev, " SPGT..... : (0x%p)=0x%X\n",
283 priv->smba + ISMT_SPGT,
284 readl(priv->smba + ISMT_SPGT));
285 }
286
287 /**
288 * ismt_submit_desc() - add a descriptor to the ring
289 * @priv: iSMT private data
290 */
ismt_submit_desc(struct ismt_priv * priv)291 static void ismt_submit_desc(struct ismt_priv *priv)
292 {
293 uint fmhp;
294 uint val;
295
296 ismt_desc_dump(priv);
297 ismt_gen_reg_dump(priv);
298 ismt_mstr_reg_dump(priv);
299
300 /* Set the FMHP (Firmware Master Head Pointer)*/
301 fmhp = ((priv->head + 1) % ISMT_DESC_ENTRIES) << 16;
302 val = readl(priv->smba + ISMT_MSTR_MCTRL);
303 writel((val & ~ISMT_MCTRL_FMHP) | fmhp,
304 priv->smba + ISMT_MSTR_MCTRL);
305
306 /* Set the start bit */
307 val = readl(priv->smba + ISMT_MSTR_MCTRL);
308 writel(val | ISMT_MCTRL_SS,
309 priv->smba + ISMT_MSTR_MCTRL);
310 }
311
312 /**
313 * ismt_process_desc() - handle the completion of the descriptor
314 * @desc: the iSMT hardware descriptor
315 * @data: data buffer from the upper layer
316 * @priv: ismt_priv struct holding our dma buffer
317 * @size: SMBus transaction type
318 * @read_write: flag to indicate if this is a read or write
319 */
ismt_process_desc(const struct ismt_desc * desc,union i2c_smbus_data * data,struct ismt_priv * priv,int size,char read_write)320 static int ismt_process_desc(const struct ismt_desc *desc,
321 union i2c_smbus_data *data,
322 struct ismt_priv *priv, int size,
323 char read_write)
324 {
325 u8 *dma_buffer = PTR_ALIGN(&priv->buffer[0], 16);
326
327 dev_dbg(&priv->pci_dev->dev, "Processing completed descriptor\n");
328 __ismt_desc_dump(&priv->pci_dev->dev, desc);
329 ismt_gen_reg_dump(priv);
330 ismt_mstr_reg_dump(priv);
331
332 if (desc->status & ISMT_DESC_SCS) {
333 if (read_write == I2C_SMBUS_WRITE &&
334 size != I2C_SMBUS_PROC_CALL)
335 return 0;
336
337 switch (size) {
338 case I2C_SMBUS_BYTE:
339 case I2C_SMBUS_BYTE_DATA:
340 data->byte = dma_buffer[0];
341 break;
342 case I2C_SMBUS_WORD_DATA:
343 case I2C_SMBUS_PROC_CALL:
344 data->word = dma_buffer[0] | (dma_buffer[1] << 8);
345 break;
346 case I2C_SMBUS_BLOCK_DATA:
347 if (desc->rxbytes != dma_buffer[0] + 1)
348 return -EMSGSIZE;
349
350 memcpy(data->block, dma_buffer, desc->rxbytes);
351 break;
352 case I2C_SMBUS_I2C_BLOCK_DATA:
353 memcpy(&data->block[1], dma_buffer, desc->rxbytes);
354 data->block[0] = desc->rxbytes;
355 break;
356 }
357 return 0;
358 }
359
360 if (likely(desc->status & ISMT_DESC_NAK))
361 return -ENXIO;
362
363 if (desc->status & ISMT_DESC_CRC)
364 return -EBADMSG;
365
366 if (desc->status & ISMT_DESC_COL)
367 return -EAGAIN;
368
369 if (desc->status & ISMT_DESC_LPR)
370 return -EPROTO;
371
372 if (desc->status & (ISMT_DESC_DLTO | ISMT_DESC_CLTO))
373 return -ETIMEDOUT;
374
375 return -EIO;
376 }
377
378 /**
379 * ismt_access() - process an SMBus command
380 * @adap: the i2c host adapter
381 * @addr: address of the i2c/SMBus target
382 * @flags: command options
383 * @read_write: read from or write to device
384 * @command: the i2c/SMBus command to issue
385 * @size: SMBus transaction type
386 * @data: read/write data buffer
387 */
ismt_access(struct i2c_adapter * adap,u16 addr,unsigned short flags,char read_write,u8 command,int size,union i2c_smbus_data * data)388 static int ismt_access(struct i2c_adapter *adap, u16 addr,
389 unsigned short flags, char read_write, u8 command,
390 int size, union i2c_smbus_data *data)
391 {
392 int ret;
393 unsigned long time_left;
394 dma_addr_t dma_addr = 0; /* address of the data buffer */
395 u8 dma_size = 0;
396 enum dma_data_direction dma_direction = 0;
397 struct ismt_desc *desc;
398 struct ismt_priv *priv = i2c_get_adapdata(adap);
399 struct device *dev = &priv->pci_dev->dev;
400 u8 *dma_buffer = PTR_ALIGN(&priv->buffer[0], 16);
401
402 desc = &priv->hw[priv->head];
403
404 /* Initialize the DMA buffer */
405 memset(priv->buffer, 0, sizeof(priv->buffer));
406
407 /* Initialize the descriptor */
408 memset(desc, 0, sizeof(struct ismt_desc));
409 desc->tgtaddr_rw = ISMT_DESC_ADDR_RW(addr, read_write);
410
411 /* Initialize common control bits */
412 if (likely(pci_dev_msi_enabled(priv->pci_dev)))
413 desc->control = ISMT_DESC_INT | ISMT_DESC_FAIR;
414 else
415 desc->control = ISMT_DESC_FAIR;
416
417 if ((flags & I2C_CLIENT_PEC) && (size != I2C_SMBUS_QUICK)
418 && (size != I2C_SMBUS_I2C_BLOCK_DATA))
419 desc->control |= ISMT_DESC_PEC;
420
421 switch (size) {
422 case I2C_SMBUS_QUICK:
423 dev_dbg(dev, "I2C_SMBUS_QUICK\n");
424 break;
425
426 case I2C_SMBUS_BYTE:
427 if (read_write == I2C_SMBUS_WRITE) {
428 /*
429 * Send Byte
430 * The command field contains the write data
431 */
432 dev_dbg(dev, "I2C_SMBUS_BYTE: WRITE\n");
433 desc->control |= ISMT_DESC_CWRL;
434 desc->wr_len_cmd = command;
435 } else {
436 /* Receive Byte */
437 dev_dbg(dev, "I2C_SMBUS_BYTE: READ\n");
438 dma_size = 1;
439 dma_direction = DMA_FROM_DEVICE;
440 desc->rd_len = 1;
441 }
442 break;
443
444 case I2C_SMBUS_BYTE_DATA:
445 if (read_write == I2C_SMBUS_WRITE) {
446 /*
447 * Write Byte
448 * Command plus 1 data byte
449 */
450 dev_dbg(dev, "I2C_SMBUS_BYTE_DATA: WRITE\n");
451 desc->wr_len_cmd = 2;
452 dma_size = 2;
453 dma_direction = DMA_TO_DEVICE;
454 dma_buffer[0] = command;
455 dma_buffer[1] = data->byte;
456 } else {
457 /* Read Byte */
458 dev_dbg(dev, "I2C_SMBUS_BYTE_DATA: READ\n");
459 desc->control |= ISMT_DESC_CWRL;
460 desc->wr_len_cmd = command;
461 desc->rd_len = 1;
462 dma_size = 1;
463 dma_direction = DMA_FROM_DEVICE;
464 }
465 break;
466
467 case I2C_SMBUS_WORD_DATA:
468 if (read_write == I2C_SMBUS_WRITE) {
469 /* Write Word */
470 dev_dbg(dev, "I2C_SMBUS_WORD_DATA: WRITE\n");
471 desc->wr_len_cmd = 3;
472 dma_size = 3;
473 dma_direction = DMA_TO_DEVICE;
474 dma_buffer[0] = command;
475 dma_buffer[1] = data->word & 0xff;
476 dma_buffer[2] = data->word >> 8;
477 } else {
478 /* Read Word */
479 dev_dbg(dev, "I2C_SMBUS_WORD_DATA: READ\n");
480 desc->wr_len_cmd = command;
481 desc->control |= ISMT_DESC_CWRL;
482 desc->rd_len = 2;
483 dma_size = 2;
484 dma_direction = DMA_FROM_DEVICE;
485 }
486 break;
487
488 case I2C_SMBUS_PROC_CALL:
489 dev_dbg(dev, "I2C_SMBUS_PROC_CALL\n");
490 desc->wr_len_cmd = 3;
491 desc->rd_len = 2;
492 dma_size = 3;
493 dma_direction = DMA_BIDIRECTIONAL;
494 dma_buffer[0] = command;
495 dma_buffer[1] = data->word & 0xff;
496 dma_buffer[2] = data->word >> 8;
497 break;
498
499 case I2C_SMBUS_BLOCK_DATA:
500 if (read_write == I2C_SMBUS_WRITE) {
501 /* Block Write */
502 dev_dbg(dev, "I2C_SMBUS_BLOCK_DATA: WRITE\n");
503 dma_size = data->block[0] + 1;
504 dma_direction = DMA_TO_DEVICE;
505 desc->wr_len_cmd = dma_size;
506 desc->control |= ISMT_DESC_BLK;
507 dma_buffer[0] = command;
508 memcpy(&dma_buffer[1], &data->block[1], dma_size - 1);
509 } else {
510 /* Block Read */
511 dev_dbg(dev, "I2C_SMBUS_BLOCK_DATA: READ\n");
512 dma_size = I2C_SMBUS_BLOCK_MAX;
513 dma_direction = DMA_FROM_DEVICE;
514 desc->rd_len = dma_size;
515 desc->wr_len_cmd = command;
516 desc->control |= (ISMT_DESC_BLK | ISMT_DESC_CWRL);
517 }
518 break;
519
520 case I2C_SMBUS_I2C_BLOCK_DATA:
521 /* Make sure the length is valid */
522 if (data->block[0] < 1)
523 data->block[0] = 1;
524
525 if (data->block[0] > I2C_SMBUS_BLOCK_MAX)
526 data->block[0] = I2C_SMBUS_BLOCK_MAX;
527
528 if (read_write == I2C_SMBUS_WRITE) {
529 /* i2c Block Write */
530 dev_dbg(dev, "I2C_SMBUS_I2C_BLOCK_DATA: WRITE\n");
531 dma_size = data->block[0] + 1;
532 dma_direction = DMA_TO_DEVICE;
533 desc->wr_len_cmd = dma_size;
534 desc->control |= ISMT_DESC_I2C;
535 dma_buffer[0] = command;
536 memcpy(&dma_buffer[1], &data->block[1], dma_size - 1);
537 } else {
538 /* i2c Block Read */
539 dev_dbg(dev, "I2C_SMBUS_I2C_BLOCK_DATA: READ\n");
540 dma_size = data->block[0];
541 dma_direction = DMA_FROM_DEVICE;
542 desc->rd_len = dma_size;
543 desc->wr_len_cmd = command;
544 desc->control |= (ISMT_DESC_I2C | ISMT_DESC_CWRL);
545 /*
546 * Per the "Table 15-15. I2C Commands",
547 * in the External Design Specification (EDS),
548 * (Document Number: 508084, Revision: 2.0),
549 * the _rw bit must be 0
550 */
551 desc->tgtaddr_rw = ISMT_DESC_ADDR_RW(addr, 0);
552 }
553 break;
554
555 default:
556 dev_err(dev, "Unsupported transaction %d\n",
557 size);
558 return -EOPNOTSUPP;
559 }
560
561 /* map the data buffer */
562 if (dma_size != 0) {
563 dev_dbg(dev, " dev=%p\n", dev);
564 dev_dbg(dev, " data=%p\n", data);
565 dev_dbg(dev, " dma_buffer=%p\n", dma_buffer);
566 dev_dbg(dev, " dma_size=%d\n", dma_size);
567 dev_dbg(dev, " dma_direction=%d\n", dma_direction);
568
569 dma_addr = dma_map_single(dev,
570 dma_buffer,
571 dma_size,
572 dma_direction);
573
574 if (dma_mapping_error(dev, dma_addr)) {
575 dev_err(dev, "Error in mapping dma buffer %p\n",
576 dma_buffer);
577 return -EIO;
578 }
579
580 dev_dbg(dev, " dma_addr = %pad\n", &dma_addr);
581
582 desc->dptr_low = lower_32_bits(dma_addr);
583 desc->dptr_high = upper_32_bits(dma_addr);
584 }
585
586 reinit_completion(&priv->cmp);
587
588 /* Add the descriptor */
589 ismt_submit_desc(priv);
590
591 /* Now we wait for interrupt completion, 1s */
592 time_left = wait_for_completion_timeout(&priv->cmp, HZ*1);
593
594 /* unmap the data buffer */
595 if (dma_size != 0)
596 dma_unmap_single(dev, dma_addr, dma_size, dma_direction);
597
598 if (unlikely(!time_left)) {
599 dev_err(dev, "completion wait timed out\n");
600 ret = -ETIMEDOUT;
601 goto out;
602 }
603
604 /* do any post processing of the descriptor here */
605 ret = ismt_process_desc(desc, data, priv, size, read_write);
606
607 out:
608 /* Update the ring pointer */
609 priv->head++;
610 priv->head %= ISMT_DESC_ENTRIES;
611
612 return ret;
613 }
614
615 /**
616 * ismt_func() - report which i2c commands are supported by this adapter
617 * @adap: the i2c host adapter
618 */
ismt_func(struct i2c_adapter * adap)619 static u32 ismt_func(struct i2c_adapter *adap)
620 {
621 return I2C_FUNC_SMBUS_QUICK |
622 I2C_FUNC_SMBUS_BYTE |
623 I2C_FUNC_SMBUS_BYTE_DATA |
624 I2C_FUNC_SMBUS_WORD_DATA |
625 I2C_FUNC_SMBUS_PROC_CALL |
626 I2C_FUNC_SMBUS_BLOCK_DATA |
627 I2C_FUNC_SMBUS_I2C_BLOCK |
628 I2C_FUNC_SMBUS_PEC;
629 }
630
631 /**
632 * smbus_algorithm - the adapter algorithm and supported functionality
633 * @smbus_xfer: the adapter algorithm
634 * @functionality: functionality supported by the adapter
635 */
636 static const struct i2c_algorithm smbus_algorithm = {
637 .smbus_xfer = ismt_access,
638 .functionality = ismt_func,
639 };
640
641 /**
642 * ismt_handle_isr() - interrupt handler bottom half
643 * @priv: iSMT private data
644 */
ismt_handle_isr(struct ismt_priv * priv)645 static irqreturn_t ismt_handle_isr(struct ismt_priv *priv)
646 {
647 complete(&priv->cmp);
648
649 return IRQ_HANDLED;
650 }
651
652
653 /**
654 * ismt_do_interrupt() - IRQ interrupt handler
655 * @vec: interrupt vector
656 * @data: iSMT private data
657 */
ismt_do_interrupt(int vec,void * data)658 static irqreturn_t ismt_do_interrupt(int vec, void *data)
659 {
660 u32 val;
661 struct ismt_priv *priv = data;
662
663 /*
664 * check to see it's our interrupt, return IRQ_NONE if not ours
665 * since we are sharing interrupt
666 */
667 val = readl(priv->smba + ISMT_MSTR_MSTS);
668
669 if (!(val & (ISMT_MSTS_MIS | ISMT_MSTS_MEIS)))
670 return IRQ_NONE;
671 else
672 writel(val | ISMT_MSTS_MIS | ISMT_MSTS_MEIS,
673 priv->smba + ISMT_MSTR_MSTS);
674
675 return ismt_handle_isr(priv);
676 }
677
678 /**
679 * ismt_do_msi_interrupt() - MSI interrupt handler
680 * @vec: interrupt vector
681 * @data: iSMT private data
682 */
ismt_do_msi_interrupt(int vec,void * data)683 static irqreturn_t ismt_do_msi_interrupt(int vec, void *data)
684 {
685 return ismt_handle_isr(data);
686 }
687
688 /**
689 * ismt_hw_init() - initialize the iSMT hardware
690 * @priv: iSMT private data
691 */
ismt_hw_init(struct ismt_priv * priv)692 static void ismt_hw_init(struct ismt_priv *priv)
693 {
694 u32 val;
695 struct device *dev = &priv->pci_dev->dev;
696
697 /* initialize the Master Descriptor Base Address (MDBA) */
698 writeq(priv->io_rng_dma, priv->smba + ISMT_MSTR_MDBA);
699
700 /* initialize the Master Control Register (MCTRL) */
701 writel(ISMT_MCTRL_MEIE, priv->smba + ISMT_MSTR_MCTRL);
702
703 /* initialize the Master Status Register (MSTS) */
704 writel(0, priv->smba + ISMT_MSTR_MSTS);
705
706 /* initialize the Master Descriptor Size (MDS) */
707 val = readl(priv->smba + ISMT_MSTR_MDS);
708 writel((val & ~ISMT_MDS_MASK) | (ISMT_DESC_ENTRIES - 1),
709 priv->smba + ISMT_MSTR_MDS);
710
711 /*
712 * Set the SMBus speed (could use this for slow HW debuggers)
713 */
714
715 val = readl(priv->smba + ISMT_SPGT);
716
717 switch (bus_speed) {
718 case 0:
719 break;
720
721 case 80:
722 dev_dbg(dev, "Setting SMBus clock to 80 kHz\n");
723 writel(((val & ~ISMT_SPGT_SPD_MASK) | ISMT_SPGT_SPD_80K),
724 priv->smba + ISMT_SPGT);
725 break;
726
727 case 100:
728 dev_dbg(dev, "Setting SMBus clock to 100 kHz\n");
729 writel(((val & ~ISMT_SPGT_SPD_MASK) | ISMT_SPGT_SPD_100K),
730 priv->smba + ISMT_SPGT);
731 break;
732
733 case 400:
734 dev_dbg(dev, "Setting SMBus clock to 400 kHz\n");
735 writel(((val & ~ISMT_SPGT_SPD_MASK) | ISMT_SPGT_SPD_400K),
736 priv->smba + ISMT_SPGT);
737 break;
738
739 case 1000:
740 dev_dbg(dev, "Setting SMBus clock to 1000 kHz\n");
741 writel(((val & ~ISMT_SPGT_SPD_MASK) | ISMT_SPGT_SPD_1M),
742 priv->smba + ISMT_SPGT);
743 break;
744
745 default:
746 dev_warn(dev, "Invalid SMBus clock speed, only 0, 80, 100, 400, and 1000 are valid\n");
747 break;
748 }
749
750 val = readl(priv->smba + ISMT_SPGT);
751
752 switch (val & ISMT_SPGT_SPD_MASK) {
753 case ISMT_SPGT_SPD_80K:
754 bus_speed = 80;
755 break;
756 case ISMT_SPGT_SPD_100K:
757 bus_speed = 100;
758 break;
759 case ISMT_SPGT_SPD_400K:
760 bus_speed = 400;
761 break;
762 case ISMT_SPGT_SPD_1M:
763 bus_speed = 1000;
764 break;
765 }
766 dev_dbg(dev, "SMBus clock is running at %d kHz\n", bus_speed);
767 }
768
769 /**
770 * ismt_dev_init() - initialize the iSMT data structures
771 * @priv: iSMT private data
772 */
ismt_dev_init(struct ismt_priv * priv)773 static int ismt_dev_init(struct ismt_priv *priv)
774 {
775 /* allocate memory for the descriptor */
776 priv->hw = dmam_alloc_coherent(&priv->pci_dev->dev,
777 (ISMT_DESC_ENTRIES
778 * sizeof(struct ismt_desc)),
779 &priv->io_rng_dma,
780 GFP_KERNEL);
781 if (!priv->hw)
782 return -ENOMEM;
783
784 priv->head = 0;
785 init_completion(&priv->cmp);
786
787 return 0;
788 }
789
790 /**
791 * ismt_int_init() - initialize interrupts
792 * @priv: iSMT private data
793 */
ismt_int_init(struct ismt_priv * priv)794 static int ismt_int_init(struct ismt_priv *priv)
795 {
796 int err;
797
798 /* Try using MSI interrupts */
799 err = pci_enable_msi(priv->pci_dev);
800 if (err)
801 goto intx;
802
803 err = devm_request_irq(&priv->pci_dev->dev,
804 priv->pci_dev->irq,
805 ismt_do_msi_interrupt,
806 0,
807 "ismt-msi",
808 priv);
809 if (err) {
810 pci_disable_msi(priv->pci_dev);
811 goto intx;
812 }
813
814 return 0;
815
816 /* Try using legacy interrupts */
817 intx:
818 dev_warn(&priv->pci_dev->dev,
819 "Unable to use MSI interrupts, falling back to legacy\n");
820
821 err = devm_request_irq(&priv->pci_dev->dev,
822 priv->pci_dev->irq,
823 ismt_do_interrupt,
824 IRQF_SHARED,
825 "ismt-intx",
826 priv);
827 if (err) {
828 dev_err(&priv->pci_dev->dev, "no usable interrupts\n");
829 return err;
830 }
831
832 return 0;
833 }
834
835 static struct pci_driver ismt_driver;
836
837 /**
838 * ismt_probe() - probe for iSMT devices
839 * @pdev: PCI-Express device
840 * @id: PCI-Express device ID
841 */
842 static int
ismt_probe(struct pci_dev * pdev,const struct pci_device_id * id)843 ismt_probe(struct pci_dev *pdev, const struct pci_device_id *id)
844 {
845 int err;
846 struct ismt_priv *priv;
847 unsigned long start, len;
848
849 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
850 if (!priv)
851 return -ENOMEM;
852
853 pci_set_drvdata(pdev, priv);
854
855 i2c_set_adapdata(&priv->adapter, priv);
856 priv->adapter.owner = THIS_MODULE;
857 priv->adapter.class = I2C_CLASS_HWMON;
858 priv->adapter.algo = &smbus_algorithm;
859 priv->adapter.dev.parent = &pdev->dev;
860 ACPI_COMPANION_SET(&priv->adapter.dev, ACPI_COMPANION(&pdev->dev));
861 priv->adapter.retries = ISMT_MAX_RETRIES;
862
863 priv->pci_dev = pdev;
864
865 err = pcim_enable_device(pdev);
866 if (err) {
867 dev_err(&pdev->dev, "Failed to enable SMBus PCI device (%d)\n",
868 err);
869 return err;
870 }
871
872 /* enable bus mastering */
873 pci_set_master(pdev);
874
875 /* Determine the address of the SMBus area */
876 start = pci_resource_start(pdev, SMBBAR);
877 len = pci_resource_len(pdev, SMBBAR);
878 if (!start || !len) {
879 dev_err(&pdev->dev,
880 "SMBus base address uninitialized, upgrade BIOS\n");
881 return -ENODEV;
882 }
883
884 snprintf(priv->adapter.name, sizeof(priv->adapter.name),
885 "SMBus iSMT adapter at %lx", start);
886
887 dev_dbg(&priv->pci_dev->dev, " start=0x%lX\n", start);
888 dev_dbg(&priv->pci_dev->dev, " len=0x%lX\n", len);
889
890 err = acpi_check_resource_conflict(&pdev->resource[SMBBAR]);
891 if (err) {
892 dev_err(&pdev->dev, "ACPI resource conflict!\n");
893 return err;
894 }
895
896 err = pci_request_region(pdev, SMBBAR, ismt_driver.name);
897 if (err) {
898 dev_err(&pdev->dev,
899 "Failed to request SMBus region 0x%lx-0x%lx\n",
900 start, start + len);
901 return err;
902 }
903
904 priv->smba = pcim_iomap(pdev, SMBBAR, len);
905 if (!priv->smba) {
906 dev_err(&pdev->dev, "Unable to ioremap SMBus BAR\n");
907 return -ENODEV;
908 }
909
910 if ((pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) != 0) ||
911 (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)) != 0)) {
912 if ((pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) != 0) ||
913 (pci_set_consistent_dma_mask(pdev,
914 DMA_BIT_MASK(32)) != 0)) {
915 dev_err(&pdev->dev, "pci_set_dma_mask fail %p\n",
916 pdev);
917 return -ENODEV;
918 }
919 }
920
921 err = ismt_dev_init(priv);
922 if (err)
923 return err;
924
925 ismt_hw_init(priv);
926
927 err = ismt_int_init(priv);
928 if (err)
929 return err;
930
931 err = i2c_add_adapter(&priv->adapter);
932 if (err)
933 return -ENODEV;
934 return 0;
935 }
936
937 /**
938 * ismt_remove() - release driver resources
939 * @pdev: PCI-Express device
940 */
ismt_remove(struct pci_dev * pdev)941 static void ismt_remove(struct pci_dev *pdev)
942 {
943 struct ismt_priv *priv = pci_get_drvdata(pdev);
944
945 i2c_del_adapter(&priv->adapter);
946 }
947
948 static struct pci_driver ismt_driver = {
949 .name = "ismt_smbus",
950 .id_table = ismt_ids,
951 .probe = ismt_probe,
952 .remove = ismt_remove,
953 };
954
955 module_pci_driver(ismt_driver);
956
957 MODULE_LICENSE("Dual BSD/GPL");
958 MODULE_AUTHOR("Bill E. Brown <bill.e.brown@intel.com>");
959 MODULE_DESCRIPTION("Intel SMBus Message Transport (iSMT) driver");
960
