1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * I2C driver for the Renesas EMEV2 SoC
4 *
5 * Copyright (C) 2015 Wolfram Sang <wsa@sang-engineering.com>
6 * Copyright 2013 Codethink Ltd.
7 * Copyright 2010-2015 Renesas Electronics Corporation
8 */
9
10 #include <linux/clk.h>
11 #include <linux/completion.h>
12 #include <linux/device.h>
13 #include <linux/i2c.h>
14 #include <linux/init.h>
15 #include <linux/interrupt.h>
16 #include <linux/io.h>
17 #include <linux/kernel.h>
18 #include <linux/module.h>
19 #include <linux/of_device.h>
20 #include <linux/platform_device.h>
21 #include <linux/sched.h>
22
23 /* I2C Registers */
24 #define I2C_OFS_IICACT0 0x00 /* start */
25 #define I2C_OFS_IIC0 0x04 /* shift */
26 #define I2C_OFS_IICC0 0x08 /* control */
27 #define I2C_OFS_SVA0 0x0c /* slave address */
28 #define I2C_OFS_IICCL0 0x10 /* clock select */
29 #define I2C_OFS_IICX0 0x14 /* extension */
30 #define I2C_OFS_IICS0 0x18 /* status */
31 #define I2C_OFS_IICSE0 0x1c /* status For emulation */
32 #define I2C_OFS_IICF0 0x20 /* IIC flag */
33
34 /* I2C IICACT0 Masks */
35 #define I2C_BIT_IICE0 0x0001
36
37 /* I2C IICC0 Masks */
38 #define I2C_BIT_LREL0 0x0040
39 #define I2C_BIT_WREL0 0x0020
40 #define I2C_BIT_SPIE0 0x0010
41 #define I2C_BIT_WTIM0 0x0008
42 #define I2C_BIT_ACKE0 0x0004
43 #define I2C_BIT_STT0 0x0002
44 #define I2C_BIT_SPT0 0x0001
45
46 /* I2C IICCL0 Masks */
47 #define I2C_BIT_SMC0 0x0008
48 #define I2C_BIT_DFC0 0x0004
49
50 /* I2C IICSE0 Masks */
51 #define I2C_BIT_MSTS0 0x0080
52 #define I2C_BIT_ALD0 0x0040
53 #define I2C_BIT_EXC0 0x0020
54 #define I2C_BIT_COI0 0x0010
55 #define I2C_BIT_TRC0 0x0008
56 #define I2C_BIT_ACKD0 0x0004
57 #define I2C_BIT_STD0 0x0002
58 #define I2C_BIT_SPD0 0x0001
59
60 /* I2C IICF0 Masks */
61 #define I2C_BIT_STCF 0x0080
62 #define I2C_BIT_IICBSY 0x0040
63 #define I2C_BIT_STCEN 0x0002
64 #define I2C_BIT_IICRSV 0x0001
65
66 struct em_i2c_device {
67 void __iomem *base;
68 struct i2c_adapter adap;
69 struct completion msg_done;
70 struct clk *sclk;
71 struct i2c_client *slave;
72 };
73
em_clear_set_bit(struct em_i2c_device * priv,u8 clear,u8 set,u8 reg)74 static inline void em_clear_set_bit(struct em_i2c_device *priv, u8 clear, u8 set, u8 reg)
75 {
76 writeb((readb(priv->base + reg) & ~clear) | set, priv->base + reg);
77 }
78
em_i2c_wait_for_event(struct em_i2c_device * priv)79 static int em_i2c_wait_for_event(struct em_i2c_device *priv)
80 {
81 unsigned long time_left;
82 int status;
83
84 reinit_completion(&priv->msg_done);
85
86 time_left = wait_for_completion_timeout(&priv->msg_done, priv->adap.timeout);
87
88 if (!time_left)
89 return -ETIMEDOUT;
90
91 status = readb(priv->base + I2C_OFS_IICSE0);
92 return status & I2C_BIT_ALD0 ? -EAGAIN : status;
93 }
94
em_i2c_stop(struct em_i2c_device * priv)95 static void em_i2c_stop(struct em_i2c_device *priv)
96 {
97 /* Send Stop condition */
98 em_clear_set_bit(priv, 0, I2C_BIT_SPT0 | I2C_BIT_SPIE0, I2C_OFS_IICC0);
99
100 /* Wait for stop condition */
101 em_i2c_wait_for_event(priv);
102 }
103
em_i2c_reset(struct i2c_adapter * adap)104 static void em_i2c_reset(struct i2c_adapter *adap)
105 {
106 struct em_i2c_device *priv = i2c_get_adapdata(adap);
107 int retr;
108
109 /* If I2C active */
110 if (readb(priv->base + I2C_OFS_IICACT0) & I2C_BIT_IICE0) {
111 /* Disable I2C operation */
112 writeb(0, priv->base + I2C_OFS_IICACT0);
113
114 retr = 1000;
115 while (readb(priv->base + I2C_OFS_IICACT0) == 1 && retr)
116 retr--;
117 WARN_ON(retr == 0);
118 }
119
120 /* Transfer mode set */
121 writeb(I2C_BIT_DFC0, priv->base + I2C_OFS_IICCL0);
122
123 /* Can Issue start without detecting a stop, Reservation disabled. */
124 writeb(I2C_BIT_STCEN | I2C_BIT_IICRSV, priv->base + I2C_OFS_IICF0);
125
126 /* I2C enable, 9 bit interrupt mode */
127 writeb(I2C_BIT_WTIM0, priv->base + I2C_OFS_IICC0);
128
129 /* Enable I2C operation */
130 writeb(I2C_BIT_IICE0, priv->base + I2C_OFS_IICACT0);
131
132 retr = 1000;
133 while (readb(priv->base + I2C_OFS_IICACT0) == 0 && retr)
134 retr--;
135 WARN_ON(retr == 0);
136 }
137
__em_i2c_xfer(struct i2c_adapter * adap,struct i2c_msg * msg,int stop)138 static int __em_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msg,
139 int stop)
140 {
141 struct em_i2c_device *priv = i2c_get_adapdata(adap);
142 int count, status, read = !!(msg->flags & I2C_M_RD);
143
144 /* Send start condition */
145 em_clear_set_bit(priv, 0, I2C_BIT_ACKE0 | I2C_BIT_WTIM0, I2C_OFS_IICC0);
146 em_clear_set_bit(priv, 0, I2C_BIT_STT0, I2C_OFS_IICC0);
147
148 /* Send slave address and R/W type */
149 writeb(i2c_8bit_addr_from_msg(msg), priv->base + I2C_OFS_IIC0);
150
151 /* Wait for transaction */
152 status = em_i2c_wait_for_event(priv);
153 if (status < 0)
154 goto out_reset;
155
156 /* Received NACK (result of setting slave address and R/W) */
157 if (!(status & I2C_BIT_ACKD0)) {
158 em_i2c_stop(priv);
159 goto out;
160 }
161
162 /* Extra setup for read transactions */
163 if (read) {
164 /* 8 bit interrupt mode */
165 em_clear_set_bit(priv, I2C_BIT_WTIM0, I2C_BIT_ACKE0, I2C_OFS_IICC0);
166 em_clear_set_bit(priv, I2C_BIT_WTIM0, I2C_BIT_WREL0, I2C_OFS_IICC0);
167
168 /* Wait for transaction */
169 status = em_i2c_wait_for_event(priv);
170 if (status < 0)
171 goto out_reset;
172 }
173
174 /* Send / receive data */
175 for (count = 0; count < msg->len; count++) {
176 if (read) { /* Read transaction */
177 msg->buf[count] = readb(priv->base + I2C_OFS_IIC0);
178 em_clear_set_bit(priv, 0, I2C_BIT_WREL0, I2C_OFS_IICC0);
179
180 } else { /* Write transaction */
181 /* Received NACK */
182 if (!(status & I2C_BIT_ACKD0)) {
183 em_i2c_stop(priv);
184 goto out;
185 }
186
187 /* Write data */
188 writeb(msg->buf[count], priv->base + I2C_OFS_IIC0);
189 }
190
191 /* Wait for R/W transaction */
192 status = em_i2c_wait_for_event(priv);
193 if (status < 0)
194 goto out_reset;
195 }
196
197 if (stop)
198 em_i2c_stop(priv);
199
200 return count;
201
202 out_reset:
203 em_i2c_reset(adap);
204 out:
205 return status < 0 ? status : -ENXIO;
206 }
207
em_i2c_xfer(struct i2c_adapter * adap,struct i2c_msg * msgs,int num)208 static int em_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
209 int num)
210 {
211 struct em_i2c_device *priv = i2c_get_adapdata(adap);
212 int ret, i;
213
214 if (readb(priv->base + I2C_OFS_IICF0) & I2C_BIT_IICBSY)
215 return -EAGAIN;
216
217 for (i = 0; i < num; i++) {
218 ret = __em_i2c_xfer(adap, &msgs[i], (i == (num - 1)));
219 if (ret < 0)
220 return ret;
221 }
222
223 /* I2C transfer completed */
224 return num;
225 }
226
em_i2c_slave_irq(struct em_i2c_device * priv)227 static bool em_i2c_slave_irq(struct em_i2c_device *priv)
228 {
229 u8 status, value;
230 enum i2c_slave_event event;
231 int ret;
232
233 if (!priv->slave)
234 return false;
235
236 status = readb(priv->base + I2C_OFS_IICSE0);
237
238 /* Extension code, do not participate */
239 if (status & I2C_BIT_EXC0) {
240 em_clear_set_bit(priv, 0, I2C_BIT_LREL0, I2C_OFS_IICC0);
241 return true;
242 }
243
244 /* Stop detected, we don't know if it's for slave or master */
245 if (status & I2C_BIT_SPD0) {
246 /* Notify slave device */
247 i2c_slave_event(priv->slave, I2C_SLAVE_STOP, &value);
248 /* Pretend we did not handle the interrupt */
249 return false;
250 }
251
252 /* Only handle interrupts addressed to us */
253 if (!(status & I2C_BIT_COI0))
254 return false;
255
256 /* Enable stop interrupts */
257 em_clear_set_bit(priv, 0, I2C_BIT_SPIE0, I2C_OFS_IICC0);
258
259 /* Transmission or Reception */
260 if (status & I2C_BIT_TRC0) {
261 if (status & I2C_BIT_ACKD0) {
262 /* 9 bit interrupt mode */
263 em_clear_set_bit(priv, 0, I2C_BIT_WTIM0, I2C_OFS_IICC0);
264
265 /* Send data */
266 event = status & I2C_BIT_STD0 ?
267 I2C_SLAVE_READ_REQUESTED :
268 I2C_SLAVE_READ_PROCESSED;
269 i2c_slave_event(priv->slave, event, &value);
270 writeb(value, priv->base + I2C_OFS_IIC0);
271 } else {
272 /* NACK, stop transmitting */
273 em_clear_set_bit(priv, 0, I2C_BIT_LREL0, I2C_OFS_IICC0);
274 }
275 } else {
276 /* 8 bit interrupt mode */
277 em_clear_set_bit(priv, I2C_BIT_WTIM0, I2C_BIT_ACKE0,
278 I2C_OFS_IICC0);
279 em_clear_set_bit(priv, I2C_BIT_WTIM0, I2C_BIT_WREL0,
280 I2C_OFS_IICC0);
281
282 if (status & I2C_BIT_STD0) {
283 i2c_slave_event(priv->slave, I2C_SLAVE_WRITE_REQUESTED,
284 &value);
285 } else {
286 /* Recv data */
287 value = readb(priv->base + I2C_OFS_IIC0);
288 ret = i2c_slave_event(priv->slave,
289 I2C_SLAVE_WRITE_RECEIVED, &value);
290 if (ret < 0)
291 em_clear_set_bit(priv, I2C_BIT_ACKE0, 0,
292 I2C_OFS_IICC0);
293 }
294 }
295
296 return true;
297 }
298
em_i2c_irq_handler(int this_irq,void * dev_id)299 static irqreturn_t em_i2c_irq_handler(int this_irq, void *dev_id)
300 {
301 struct em_i2c_device *priv = dev_id;
302
303 if (em_i2c_slave_irq(priv))
304 return IRQ_HANDLED;
305
306 complete(&priv->msg_done);
307
308 return IRQ_HANDLED;
309 }
310
em_i2c_func(struct i2c_adapter * adap)311 static u32 em_i2c_func(struct i2c_adapter *adap)
312 {
313 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_SLAVE;
314 }
315
em_i2c_reg_slave(struct i2c_client * slave)316 static int em_i2c_reg_slave(struct i2c_client *slave)
317 {
318 struct em_i2c_device *priv = i2c_get_adapdata(slave->adapter);
319
320 if (priv->slave)
321 return -EBUSY;
322
323 if (slave->flags & I2C_CLIENT_TEN)
324 return -EAFNOSUPPORT;
325
326 priv->slave = slave;
327
328 /* Set slave address */
329 writeb(slave->addr << 1, priv->base + I2C_OFS_SVA0);
330
331 return 0;
332 }
333
em_i2c_unreg_slave(struct i2c_client * slave)334 static int em_i2c_unreg_slave(struct i2c_client *slave)
335 {
336 struct em_i2c_device *priv = i2c_get_adapdata(slave->adapter);
337
338 WARN_ON(!priv->slave);
339
340 writeb(0, priv->base + I2C_OFS_SVA0);
341
342 priv->slave = NULL;
343
344 return 0;
345 }
346
347 static const struct i2c_algorithm em_i2c_algo = {
348 .master_xfer = em_i2c_xfer,
349 .functionality = em_i2c_func,
350 .reg_slave = em_i2c_reg_slave,
351 .unreg_slave = em_i2c_unreg_slave,
352 };
353
em_i2c_probe(struct platform_device * pdev)354 static int em_i2c_probe(struct platform_device *pdev)
355 {
356 struct em_i2c_device *priv;
357 struct resource *r;
358 int irq, ret;
359
360 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
361 if (!priv)
362 return -ENOMEM;
363
364 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
365 priv->base = devm_ioremap_resource(&pdev->dev, r);
366 if (IS_ERR(priv->base))
367 return PTR_ERR(priv->base);
368
369 strlcpy(priv->adap.name, "EMEV2 I2C", sizeof(priv->adap.name));
370
371 priv->sclk = devm_clk_get(&pdev->dev, "sclk");
372 if (IS_ERR(priv->sclk))
373 return PTR_ERR(priv->sclk);
374
375 ret = clk_prepare_enable(priv->sclk);
376 if (ret)
377 return ret;
378
379 priv->adap.timeout = msecs_to_jiffies(100);
380 priv->adap.retries = 5;
381 priv->adap.dev.parent = &pdev->dev;
382 priv->adap.algo = &em_i2c_algo;
383 priv->adap.owner = THIS_MODULE;
384 priv->adap.dev.of_node = pdev->dev.of_node;
385
386 init_completion(&priv->msg_done);
387
388 platform_set_drvdata(pdev, priv);
389 i2c_set_adapdata(&priv->adap, priv);
390
391 em_i2c_reset(&priv->adap);
392
393 irq = platform_get_irq(pdev, 0);
394 ret = devm_request_irq(&pdev->dev, irq, em_i2c_irq_handler, 0,
395 "em_i2c", priv);
396 if (ret)
397 goto err_clk;
398
399 ret = i2c_add_adapter(&priv->adap);
400
401 if (ret)
402 goto err_clk;
403
404 dev_info(&pdev->dev, "Added i2c controller %d, irq %d\n", priv->adap.nr, irq);
405
406 return 0;
407
408 err_clk:
409 clk_disable_unprepare(priv->sclk);
410 return ret;
411 }
412
em_i2c_remove(struct platform_device * dev)413 static int em_i2c_remove(struct platform_device *dev)
414 {
415 struct em_i2c_device *priv = platform_get_drvdata(dev);
416
417 i2c_del_adapter(&priv->adap);
418 clk_disable_unprepare(priv->sclk);
419
420 return 0;
421 }
422
423 static const struct of_device_id em_i2c_ids[] = {
424 { .compatible = "renesas,iic-emev2", },
425 { }
426 };
427
428 static struct platform_driver em_i2c_driver = {
429 .probe = em_i2c_probe,
430 .remove = em_i2c_remove,
431 .driver = {
432 .name = "em-i2c",
433 .of_match_table = em_i2c_ids,
434 }
435 };
436 module_platform_driver(em_i2c_driver);
437
438 MODULE_DESCRIPTION("EMEV2 I2C bus driver");
439 MODULE_AUTHOR("Ian Molton and Wolfram Sang <wsa@sang-engineering.com>");
440 MODULE_LICENSE("GPL v2");
441 MODULE_DEVICE_TABLE(of, em_i2c_ids);
442
