1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Freescale CPM1/CPM2 I2C interface.
4 * Copyright (c) 1999 Dan Malek (dmalek@jlc.net).
5 *
6 * moved into proper i2c interface;
7 * Brad Parker (brad@heeltoe.com)
8 *
9 * Parts from dbox2_i2c.c (cvs.tuxbox.org)
10 * (C) 2000-2001 Felix Domke (tmbinc@gmx.net), Gillem (htoa@gmx.net)
11 *
12 * (C) 2007 Montavista Software, Inc.
13 * Vitaly Bordug <vitb@kernel.crashing.org>
14 *
15 * Converted to of_platform_device. Renamed to i2c-cpm.c.
16 * (C) 2007,2008 Jochen Friedrich <jochen@scram.de>
17 */
18
19 #include <linux/kernel.h>
20 #include <linux/module.h>
21 #include <linux/delay.h>
22 #include <linux/slab.h>
23 #include <linux/interrupt.h>
24 #include <linux/errno.h>
25 #include <linux/stddef.h>
26 #include <linux/i2c.h>
27 #include <linux/io.h>
28 #include <linux/dma-mapping.h>
29 #include <linux/of.h>
30 #include <linux/of_address.h>
31 #include <linux/of_irq.h>
32 #include <linux/platform_device.h>
33 #include <sysdev/fsl_soc.h>
34 #include <asm/cpm.h>
35
36 /* Try to define this if you have an older CPU (earlier than rev D4) */
37 /* However, better use a GPIO based bitbang driver in this case :/ */
38 #undef I2C_CHIP_ERRATA
39
40 #define CPM_MAX_READ 513
41 #define CPM_MAXBD 4
42
43 #define I2C_EB (0x10) /* Big endian mode */
44 #define I2C_EB_CPM2 (0x30) /* Big endian mode, memory snoop */
45
46 #define DPRAM_BASE ((u8 __iomem __force *)cpm_muram_addr(0))
47
48 /* I2C parameter RAM. */
49 struct i2c_ram {
50 ushort rbase; /* Rx Buffer descriptor base address */
51 ushort tbase; /* Tx Buffer descriptor base address */
52 u_char rfcr; /* Rx function code */
53 u_char tfcr; /* Tx function code */
54 ushort mrblr; /* Max receive buffer length */
55 uint rstate; /* Internal */
56 uint rdp; /* Internal */
57 ushort rbptr; /* Rx Buffer descriptor pointer */
58 ushort rbc; /* Internal */
59 uint rxtmp; /* Internal */
60 uint tstate; /* Internal */
61 uint tdp; /* Internal */
62 ushort tbptr; /* Tx Buffer descriptor pointer */
63 ushort tbc; /* Internal */
64 uint txtmp; /* Internal */
65 char res1[4]; /* Reserved */
66 ushort rpbase; /* Relocation pointer */
67 char res2[2]; /* Reserved */
68 /* The following elements are only for CPM2 */
69 char res3[4]; /* Reserved */
70 uint sdmatmp; /* Internal */
71 };
72
73 #define I2COM_START 0x80
74 #define I2COM_MASTER 0x01
75 #define I2CER_TXE 0x10
76 #define I2CER_BUSY 0x04
77 #define I2CER_TXB 0x02
78 #define I2CER_RXB 0x01
79 #define I2MOD_EN 0x01
80
81 /* I2C Registers */
82 struct i2c_reg {
83 u8 i2mod;
84 u8 res1[3];
85 u8 i2add;
86 u8 res2[3];
87 u8 i2brg;
88 u8 res3[3];
89 u8 i2com;
90 u8 res4[3];
91 u8 i2cer;
92 u8 res5[3];
93 u8 i2cmr;
94 };
95
96 struct cpm_i2c {
97 char *base;
98 struct platform_device *ofdev;
99 struct i2c_adapter adap;
100 uint dp_addr;
101 int version; /* CPM1=1, CPM2=2 */
102 int irq;
103 int cp_command;
104 int freq;
105 struct i2c_reg __iomem *i2c_reg;
106 struct i2c_ram __iomem *i2c_ram;
107 u16 i2c_addr;
108 wait_queue_head_t i2c_wait;
109 cbd_t __iomem *tbase;
110 cbd_t __iomem *rbase;
111 u_char *txbuf[CPM_MAXBD];
112 u_char *rxbuf[CPM_MAXBD];
113 dma_addr_t txdma[CPM_MAXBD];
114 dma_addr_t rxdma[CPM_MAXBD];
115 };
116
cpm_i2c_interrupt(int irq,void * dev_id)117 static irqreturn_t cpm_i2c_interrupt(int irq, void *dev_id)
118 {
119 struct cpm_i2c *cpm;
120 struct i2c_reg __iomem *i2c_reg;
121 struct i2c_adapter *adap = dev_id;
122 int i;
123
124 cpm = i2c_get_adapdata(dev_id);
125 i2c_reg = cpm->i2c_reg;
126
127 /* Clear interrupt. */
128 i = in_8(&i2c_reg->i2cer);
129 out_8(&i2c_reg->i2cer, i);
130
131 dev_dbg(&adap->dev, "Interrupt: %x\n", i);
132
133 wake_up(&cpm->i2c_wait);
134
135 return i ? IRQ_HANDLED : IRQ_NONE;
136 }
137
cpm_reset_i2c_params(struct cpm_i2c * cpm)138 static void cpm_reset_i2c_params(struct cpm_i2c *cpm)
139 {
140 struct i2c_ram __iomem *i2c_ram = cpm->i2c_ram;
141
142 /* Set up the I2C parameters in the parameter ram. */
143 out_be16(&i2c_ram->tbase, (u8 __iomem *)cpm->tbase - DPRAM_BASE);
144 out_be16(&i2c_ram->rbase, (u8 __iomem *)cpm->rbase - DPRAM_BASE);
145
146 if (cpm->version == 1) {
147 out_8(&i2c_ram->tfcr, I2C_EB);
148 out_8(&i2c_ram->rfcr, I2C_EB);
149 } else {
150 out_8(&i2c_ram->tfcr, I2C_EB_CPM2);
151 out_8(&i2c_ram->rfcr, I2C_EB_CPM2);
152 }
153
154 out_be16(&i2c_ram->mrblr, CPM_MAX_READ);
155
156 out_be32(&i2c_ram->rstate, 0);
157 out_be32(&i2c_ram->rdp, 0);
158 out_be16(&i2c_ram->rbptr, 0);
159 out_be16(&i2c_ram->rbc, 0);
160 out_be32(&i2c_ram->rxtmp, 0);
161 out_be32(&i2c_ram->tstate, 0);
162 out_be32(&i2c_ram->tdp, 0);
163 out_be16(&i2c_ram->tbptr, 0);
164 out_be16(&i2c_ram->tbc, 0);
165 out_be32(&i2c_ram->txtmp, 0);
166 }
167
cpm_i2c_force_close(struct i2c_adapter * adap)168 static void cpm_i2c_force_close(struct i2c_adapter *adap)
169 {
170 struct cpm_i2c *cpm = i2c_get_adapdata(adap);
171 struct i2c_reg __iomem *i2c_reg = cpm->i2c_reg;
172
173 dev_dbg(&adap->dev, "cpm_i2c_force_close()\n");
174
175 cpm_command(cpm->cp_command, CPM_CR_CLOSE_RX_BD);
176
177 out_8(&i2c_reg->i2cmr, 0x00); /* Disable all interrupts */
178 out_8(&i2c_reg->i2cer, 0xff);
179 }
180
cpm_i2c_parse_message(struct i2c_adapter * adap,struct i2c_msg * pmsg,int num,int tx,int rx)181 static void cpm_i2c_parse_message(struct i2c_adapter *adap,
182 struct i2c_msg *pmsg, int num, int tx, int rx)
183 {
184 cbd_t __iomem *tbdf;
185 cbd_t __iomem *rbdf;
186 u_char addr;
187 u_char *tb;
188 u_char *rb;
189 struct cpm_i2c *cpm = i2c_get_adapdata(adap);
190
191 tbdf = cpm->tbase + tx;
192 rbdf = cpm->rbase + rx;
193
194 addr = i2c_8bit_addr_from_msg(pmsg);
195
196 tb = cpm->txbuf[tx];
197 rb = cpm->rxbuf[rx];
198
199 /* Align read buffer */
200 rb = (u_char *) (((ulong) rb + 1) & ~1);
201
202 tb[0] = addr; /* Device address byte w/rw flag */
203
204 out_be16(&tbdf->cbd_datlen, pmsg->len + 1);
205 out_be16(&tbdf->cbd_sc, 0);
206
207 if (!(pmsg->flags & I2C_M_NOSTART))
208 setbits16(&tbdf->cbd_sc, BD_I2C_START);
209
210 if (tx + 1 == num)
211 setbits16(&tbdf->cbd_sc, BD_SC_LAST | BD_SC_WRAP);
212
213 if (pmsg->flags & I2C_M_RD) {
214 /*
215 * To read, we need an empty buffer of the proper length.
216 * All that is used is the first byte for address, the remainder
217 * is just used for timing (and doesn't really have to exist).
218 */
219
220 dev_dbg(&adap->dev, "cpm_i2c_read(abyte=0x%x)\n", addr);
221
222 out_be16(&rbdf->cbd_datlen, 0);
223 out_be16(&rbdf->cbd_sc, BD_SC_EMPTY | BD_SC_INTRPT);
224
225 if (rx + 1 == CPM_MAXBD)
226 setbits16(&rbdf->cbd_sc, BD_SC_WRAP);
227
228 eieio();
229 setbits16(&tbdf->cbd_sc, BD_SC_READY);
230 } else {
231 dev_dbg(&adap->dev, "cpm_i2c_write(abyte=0x%x)\n", addr);
232
233 memcpy(tb+1, pmsg->buf, pmsg->len);
234
235 eieio();
236 setbits16(&tbdf->cbd_sc, BD_SC_READY | BD_SC_INTRPT);
237 }
238 }
239
cpm_i2c_check_message(struct i2c_adapter * adap,struct i2c_msg * pmsg,int tx,int rx)240 static int cpm_i2c_check_message(struct i2c_adapter *adap,
241 struct i2c_msg *pmsg, int tx, int rx)
242 {
243 cbd_t __iomem *tbdf;
244 cbd_t __iomem *rbdf;
245 u_char *tb;
246 u_char *rb;
247 struct cpm_i2c *cpm = i2c_get_adapdata(adap);
248
249 tbdf = cpm->tbase + tx;
250 rbdf = cpm->rbase + rx;
251
252 tb = cpm->txbuf[tx];
253 rb = cpm->rxbuf[rx];
254
255 /* Align read buffer */
256 rb = (u_char *) (((uint) rb + 1) & ~1);
257
258 eieio();
259 if (pmsg->flags & I2C_M_RD) {
260 dev_dbg(&adap->dev, "tx sc 0x%04x, rx sc 0x%04x\n",
261 in_be16(&tbdf->cbd_sc), in_be16(&rbdf->cbd_sc));
262
263 if (in_be16(&tbdf->cbd_sc) & BD_SC_NAK) {
264 dev_dbg(&adap->dev, "I2C read; No ack\n");
265 return -ENXIO;
266 }
267 if (in_be16(&rbdf->cbd_sc) & BD_SC_EMPTY) {
268 dev_err(&adap->dev,
269 "I2C read; complete but rbuf empty\n");
270 return -EREMOTEIO;
271 }
272 if (in_be16(&rbdf->cbd_sc) & BD_SC_OV) {
273 dev_err(&adap->dev, "I2C read; Overrun\n");
274 return -EREMOTEIO;
275 }
276 memcpy(pmsg->buf, rb, pmsg->len);
277 } else {
278 dev_dbg(&adap->dev, "tx sc %d 0x%04x\n", tx,
279 in_be16(&tbdf->cbd_sc));
280
281 if (in_be16(&tbdf->cbd_sc) & BD_SC_NAK) {
282 dev_dbg(&adap->dev, "I2C write; No ack\n");
283 return -ENXIO;
284 }
285 if (in_be16(&tbdf->cbd_sc) & BD_SC_UN) {
286 dev_err(&adap->dev, "I2C write; Underrun\n");
287 return -EIO;
288 }
289 if (in_be16(&tbdf->cbd_sc) & BD_SC_CL) {
290 dev_err(&adap->dev, "I2C write; Collision\n");
291 return -EIO;
292 }
293 }
294 return 0;
295 }
296
cpm_i2c_xfer(struct i2c_adapter * adap,struct i2c_msg * msgs,int num)297 static int cpm_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
298 {
299 struct cpm_i2c *cpm = i2c_get_adapdata(adap);
300 struct i2c_reg __iomem *i2c_reg = cpm->i2c_reg;
301 struct i2c_ram __iomem *i2c_ram = cpm->i2c_ram;
302 struct i2c_msg *pmsg;
303 int ret;
304 int tptr;
305 int rptr;
306 cbd_t __iomem *tbdf;
307 cbd_t __iomem *rbdf;
308
309 /* Reset to use first buffer */
310 out_be16(&i2c_ram->rbptr, in_be16(&i2c_ram->rbase));
311 out_be16(&i2c_ram->tbptr, in_be16(&i2c_ram->tbase));
312
313 tbdf = cpm->tbase;
314 rbdf = cpm->rbase;
315
316 tptr = 0;
317 rptr = 0;
318
319 /*
320 * If there was a collision in the last i2c transaction,
321 * Set I2COM_MASTER as it was cleared during collision.
322 */
323 if (in_be16(&tbdf->cbd_sc) & BD_SC_CL) {
324 out_8(&cpm->i2c_reg->i2com, I2COM_MASTER);
325 }
326
327 while (tptr < num) {
328 pmsg = &msgs[tptr];
329 dev_dbg(&adap->dev, "R: %d T: %d\n", rptr, tptr);
330
331 cpm_i2c_parse_message(adap, pmsg, num, tptr, rptr);
332 if (pmsg->flags & I2C_M_RD)
333 rptr++;
334 tptr++;
335 }
336 /* Start transfer now */
337 /* Enable RX/TX/Error interupts */
338 out_8(&i2c_reg->i2cmr, I2CER_TXE | I2CER_TXB | I2CER_RXB);
339 out_8(&i2c_reg->i2cer, 0xff); /* Clear interrupt status */
340 /* Chip bug, set enable here */
341 setbits8(&i2c_reg->i2mod, I2MOD_EN); /* Enable */
342 /* Begin transmission */
343 setbits8(&i2c_reg->i2com, I2COM_START);
344
345 tptr = 0;
346 rptr = 0;
347
348 while (tptr < num) {
349 /* Check for outstanding messages */
350 dev_dbg(&adap->dev, "test ready.\n");
351 pmsg = &msgs[tptr];
352 if (pmsg->flags & I2C_M_RD)
353 ret = wait_event_timeout(cpm->i2c_wait,
354 (in_be16(&tbdf[tptr].cbd_sc) & BD_SC_NAK) ||
355 !(in_be16(&rbdf[rptr].cbd_sc) & BD_SC_EMPTY),
356 1 * HZ);
357 else
358 ret = wait_event_timeout(cpm->i2c_wait,
359 !(in_be16(&tbdf[tptr].cbd_sc) & BD_SC_READY),
360 1 * HZ);
361 if (ret == 0) {
362 ret = -EREMOTEIO;
363 dev_err(&adap->dev, "I2C transfer: timeout\n");
364 goto out_err;
365 }
366 if (ret > 0) {
367 dev_dbg(&adap->dev, "ready.\n");
368 ret = cpm_i2c_check_message(adap, pmsg, tptr, rptr);
369 tptr++;
370 if (pmsg->flags & I2C_M_RD)
371 rptr++;
372 if (ret)
373 goto out_err;
374 }
375 }
376 #ifdef I2C_CHIP_ERRATA
377 /*
378 * Chip errata, clear enable. This is not needed on rev D4 CPUs.
379 * Disabling I2C too early may cause too short stop condition
380 */
381 udelay(4);
382 clrbits8(&i2c_reg->i2mod, I2MOD_EN);
383 #endif
384 return (num);
385
386 out_err:
387 cpm_i2c_force_close(adap);
388 #ifdef I2C_CHIP_ERRATA
389 /*
390 * Chip errata, clear enable. This is not needed on rev D4 CPUs.
391 */
392 clrbits8(&i2c_reg->i2mod, I2MOD_EN);
393 #endif
394 return ret;
395 }
396
cpm_i2c_func(struct i2c_adapter * adap)397 static u32 cpm_i2c_func(struct i2c_adapter *adap)
398 {
399 return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
400 }
401
402 /* -----exported algorithm data: ------------------------------------- */
403
404 static const struct i2c_algorithm cpm_i2c_algo = {
405 .master_xfer = cpm_i2c_xfer,
406 .functionality = cpm_i2c_func,
407 };
408
409 /* CPM_MAX_READ is also limiting writes according to the code! */
410 static const struct i2c_adapter_quirks cpm_i2c_quirks = {
411 .max_num_msgs = CPM_MAXBD,
412 .max_read_len = CPM_MAX_READ,
413 .max_write_len = CPM_MAX_READ,
414 };
415
416 static const struct i2c_adapter cpm_ops = {
417 .owner = THIS_MODULE,
418 .name = "i2c-cpm",
419 .algo = &cpm_i2c_algo,
420 .quirks = &cpm_i2c_quirks,
421 };
422
cpm_i2c_setup(struct cpm_i2c * cpm)423 static int cpm_i2c_setup(struct cpm_i2c *cpm)
424 {
425 struct platform_device *ofdev = cpm->ofdev;
426 const u32 *data;
427 int len, ret, i;
428 void __iomem *i2c_base;
429 cbd_t __iomem *tbdf;
430 cbd_t __iomem *rbdf;
431 unsigned char brg;
432
433 dev_dbg(&cpm->ofdev->dev, "cpm_i2c_setup()\n");
434
435 init_waitqueue_head(&cpm->i2c_wait);
436
437 cpm->irq = irq_of_parse_and_map(ofdev->dev.of_node, 0);
438 if (!cpm->irq)
439 return -EINVAL;
440
441 /* Install interrupt handler. */
442 ret = request_irq(cpm->irq, cpm_i2c_interrupt, 0, "cpm_i2c",
443 &cpm->adap);
444 if (ret)
445 return ret;
446
447 /* I2C parameter RAM */
448 i2c_base = of_iomap(ofdev->dev.of_node, 1);
449 if (i2c_base == NULL) {
450 ret = -EINVAL;
451 goto out_irq;
452 }
453
454 if (of_device_is_compatible(ofdev->dev.of_node, "fsl,cpm1-i2c")) {
455
456 /* Check for and use a microcode relocation patch. */
457 cpm->i2c_ram = i2c_base;
458 cpm->i2c_addr = in_be16(&cpm->i2c_ram->rpbase);
459
460 /*
461 * Maybe should use cpm_muram_alloc instead of hardcoding
462 * this in micropatch.c
463 */
464 if (cpm->i2c_addr) {
465 cpm->i2c_ram = cpm_muram_addr(cpm->i2c_addr);
466 iounmap(i2c_base);
467 }
468
469 cpm->version = 1;
470
471 } else if (of_device_is_compatible(ofdev->dev.of_node, "fsl,cpm2-i2c")) {
472 cpm->i2c_addr = cpm_muram_alloc(sizeof(struct i2c_ram), 64);
473 cpm->i2c_ram = cpm_muram_addr(cpm->i2c_addr);
474 out_be16(i2c_base, cpm->i2c_addr);
475 iounmap(i2c_base);
476
477 cpm->version = 2;
478
479 } else {
480 iounmap(i2c_base);
481 ret = -EINVAL;
482 goto out_irq;
483 }
484
485 /* I2C control/status registers */
486 cpm->i2c_reg = of_iomap(ofdev->dev.of_node, 0);
487 if (cpm->i2c_reg == NULL) {
488 ret = -EINVAL;
489 goto out_ram;
490 }
491
492 data = of_get_property(ofdev->dev.of_node, "fsl,cpm-command", &len);
493 if (!data || len != 4) {
494 ret = -EINVAL;
495 goto out_reg;
496 }
497 cpm->cp_command = *data;
498
499 data = of_get_property(ofdev->dev.of_node, "linux,i2c-class", &len);
500 if (data && len == 4)
501 cpm->adap.class = *data;
502
503 data = of_get_property(ofdev->dev.of_node, "clock-frequency", &len);
504 if (data && len == 4)
505 cpm->freq = *data;
506 else
507 cpm->freq = 60000; /* use 60kHz i2c clock by default */
508
509 /*
510 * Allocate space for CPM_MAXBD transmit and receive buffer
511 * descriptors in the DP ram.
512 */
513 cpm->dp_addr = cpm_muram_alloc(sizeof(cbd_t) * 2 * CPM_MAXBD, 8);
514 if (!cpm->dp_addr) {
515 ret = -ENOMEM;
516 goto out_reg;
517 }
518
519 cpm->tbase = cpm_muram_addr(cpm->dp_addr);
520 cpm->rbase = cpm_muram_addr(cpm->dp_addr + sizeof(cbd_t) * CPM_MAXBD);
521
522 /* Allocate TX and RX buffers */
523
524 tbdf = cpm->tbase;
525 rbdf = cpm->rbase;
526
527 for (i = 0; i < CPM_MAXBD; i++) {
528 cpm->rxbuf[i] = dma_alloc_coherent(&cpm->ofdev->dev,
529 CPM_MAX_READ + 1,
530 &cpm->rxdma[i], GFP_KERNEL);
531 if (!cpm->rxbuf[i]) {
532 ret = -ENOMEM;
533 goto out_muram;
534 }
535 out_be32(&rbdf[i].cbd_bufaddr, ((cpm->rxdma[i] + 1) & ~1));
536
537 cpm->txbuf[i] = dma_alloc_coherent(&cpm->ofdev->dev,
538 CPM_MAX_READ + 1,
539 &cpm->txdma[i], GFP_KERNEL);
540 if (!cpm->txbuf[i]) {
541 ret = -ENOMEM;
542 goto out_muram;
543 }
544 out_be32(&tbdf[i].cbd_bufaddr, cpm->txdma[i]);
545 }
546
547 /* Initialize Tx/Rx parameters. */
548
549 cpm_reset_i2c_params(cpm);
550
551 dev_dbg(&cpm->ofdev->dev, "i2c_ram 0x%p, i2c_addr 0x%04x, freq %d\n",
552 cpm->i2c_ram, cpm->i2c_addr, cpm->freq);
553 dev_dbg(&cpm->ofdev->dev, "tbase 0x%04x, rbase 0x%04x\n",
554 (u8 __iomem *)cpm->tbase - DPRAM_BASE,
555 (u8 __iomem *)cpm->rbase - DPRAM_BASE);
556
557 cpm_command(cpm->cp_command, CPM_CR_INIT_TRX);
558
559 /*
560 * Select an invalid address. Just make sure we don't use loopback mode
561 */
562 out_8(&cpm->i2c_reg->i2add, 0x7f << 1);
563
564 /*
565 * PDIV is set to 00 in i2mod, so brgclk/32 is used as input to the
566 * i2c baud rate generator. This is divided by 2 x (DIV + 3) to get
567 * the actual i2c bus frequency.
568 */
569 brg = get_brgfreq() / (32 * 2 * cpm->freq) - 3;
570 out_8(&cpm->i2c_reg->i2brg, brg);
571
572 out_8(&cpm->i2c_reg->i2mod, 0x00);
573 out_8(&cpm->i2c_reg->i2com, I2COM_MASTER); /* Master mode */
574
575 /* Disable interrupts. */
576 out_8(&cpm->i2c_reg->i2cmr, 0);
577 out_8(&cpm->i2c_reg->i2cer, 0xff);
578
579 return 0;
580
581 out_muram:
582 for (i = 0; i < CPM_MAXBD; i++) {
583 if (cpm->rxbuf[i])
584 dma_free_coherent(&cpm->ofdev->dev, CPM_MAX_READ + 1,
585 cpm->rxbuf[i], cpm->rxdma[i]);
586 if (cpm->txbuf[i])
587 dma_free_coherent(&cpm->ofdev->dev, CPM_MAX_READ + 1,
588 cpm->txbuf[i], cpm->txdma[i]);
589 }
590 cpm_muram_free(cpm->dp_addr);
591 out_reg:
592 iounmap(cpm->i2c_reg);
593 out_ram:
594 if ((cpm->version == 1) && (!cpm->i2c_addr))
595 iounmap(cpm->i2c_ram);
596 if (cpm->version == 2)
597 cpm_muram_free(cpm->i2c_addr);
598 out_irq:
599 free_irq(cpm->irq, &cpm->adap);
600 return ret;
601 }
602
cpm_i2c_shutdown(struct cpm_i2c * cpm)603 static void cpm_i2c_shutdown(struct cpm_i2c *cpm)
604 {
605 int i;
606
607 /* Shut down I2C. */
608 clrbits8(&cpm->i2c_reg->i2mod, I2MOD_EN);
609
610 /* Disable interrupts */
611 out_8(&cpm->i2c_reg->i2cmr, 0);
612 out_8(&cpm->i2c_reg->i2cer, 0xff);
613
614 free_irq(cpm->irq, &cpm->adap);
615
616 /* Free all memory */
617 for (i = 0; i < CPM_MAXBD; i++) {
618 dma_free_coherent(&cpm->ofdev->dev, CPM_MAX_READ + 1,
619 cpm->rxbuf[i], cpm->rxdma[i]);
620 dma_free_coherent(&cpm->ofdev->dev, CPM_MAX_READ + 1,
621 cpm->txbuf[i], cpm->txdma[i]);
622 }
623
624 cpm_muram_free(cpm->dp_addr);
625 iounmap(cpm->i2c_reg);
626
627 if ((cpm->version == 1) && (!cpm->i2c_addr))
628 iounmap(cpm->i2c_ram);
629 if (cpm->version == 2)
630 cpm_muram_free(cpm->i2c_addr);
631 }
632
cpm_i2c_probe(struct platform_device * ofdev)633 static int cpm_i2c_probe(struct platform_device *ofdev)
634 {
635 int result, len;
636 struct cpm_i2c *cpm;
637 const u32 *data;
638
639 cpm = kzalloc(sizeof(struct cpm_i2c), GFP_KERNEL);
640 if (!cpm)
641 return -ENOMEM;
642
643 cpm->ofdev = ofdev;
644
645 platform_set_drvdata(ofdev, cpm);
646
647 cpm->adap = cpm_ops;
648 i2c_set_adapdata(&cpm->adap, cpm);
649 cpm->adap.dev.parent = &ofdev->dev;
650 cpm->adap.dev.of_node = of_node_get(ofdev->dev.of_node);
651
652 result = cpm_i2c_setup(cpm);
653 if (result) {
654 dev_err(&ofdev->dev, "Unable to init hardware\n");
655 goto out_free;
656 }
657
658 /* register new adapter to i2c module... */
659
660 data = of_get_property(ofdev->dev.of_node, "linux,i2c-index", &len);
661 cpm->adap.nr = (data && len == 4) ? be32_to_cpup(data) : -1;
662 result = i2c_add_numbered_adapter(&cpm->adap);
663
664 if (result < 0)
665 goto out_shut;
666
667 dev_dbg(&ofdev->dev, "hw routines for %s registered.\n",
668 cpm->adap.name);
669
670 return 0;
671 out_shut:
672 cpm_i2c_shutdown(cpm);
673 out_free:
674 kfree(cpm);
675
676 return result;
677 }
678
cpm_i2c_remove(struct platform_device * ofdev)679 static void cpm_i2c_remove(struct platform_device *ofdev)
680 {
681 struct cpm_i2c *cpm = platform_get_drvdata(ofdev);
682
683 i2c_del_adapter(&cpm->adap);
684
685 cpm_i2c_shutdown(cpm);
686
687 kfree(cpm);
688 }
689
690 static const struct of_device_id cpm_i2c_match[] = {
691 {
692 .compatible = "fsl,cpm1-i2c",
693 },
694 {
695 .compatible = "fsl,cpm2-i2c",
696 },
697 {},
698 };
699
700 MODULE_DEVICE_TABLE(of, cpm_i2c_match);
701
702 static struct platform_driver cpm_i2c_driver = {
703 .probe = cpm_i2c_probe,
704 .remove_new = cpm_i2c_remove,
705 .driver = {
706 .name = "fsl-i2c-cpm",
707 .of_match_table = cpm_i2c_match,
708 },
709 };
710
711 module_platform_driver(cpm_i2c_driver);
712
713 MODULE_AUTHOR("Jochen Friedrich <jochen@scram.de>");
714 MODULE_DESCRIPTION("I2C-Bus adapter routines for CPM boards");
715 MODULE_LICENSE("GPL");
716
