1 /*
2 * i2c Support for Atmel's AT91 Two-Wire Interface (TWI)
3 *
4 * Copyright (C) 2011 Weinmann Medical GmbH
5 * Author: Nikolaus Voss <n.voss@weinmann.de>
6 *
7 * Evolved from original work by:
8 * Copyright (C) 2004 Rick Bronson
9 * Converted to 2.6 by Andrew Victor <andrew@sanpeople.com>
10 *
11 * Borrowed heavily from original work by:
12 * Copyright (C) 2000 Philip Edelbrock <phil@stimpy.netroedge.com>
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 */
19
20 #include <linux/clk.h>
21 #include <linux/completion.h>
22 #include <linux/dma-mapping.h>
23 #include <linux/dmaengine.h>
24 #include <linux/err.h>
25 #include <linux/i2c.h>
26 #include <linux/interrupt.h>
27 #include <linux/io.h>
28 #include <linux/module.h>
29 #include <linux/of.h>
30 #include <linux/of_device.h>
31 #include <linux/platform_device.h>
32 #include <linux/slab.h>
33 #include <linux/platform_data/dma-atmel.h>
34 #include <linux/pm_runtime.h>
35 #include <linux/pinctrl/consumer.h>
36
37 #define DEFAULT_TWI_CLK_HZ 100000 /* max 400 Kbits/s */
38 #define AT91_I2C_TIMEOUT msecs_to_jiffies(100) /* transfer timeout */
39 #define AT91_I2C_DMA_THRESHOLD 8 /* enable DMA if transfer size is bigger than this threshold */
40 #define AUTOSUSPEND_TIMEOUT 2000
41 #define AT91_I2C_MAX_ALT_CMD_DATA_SIZE 256
42
43 /* AT91 TWI register definitions */
44 #define AT91_TWI_CR 0x0000 /* Control Register */
45 #define AT91_TWI_START BIT(0) /* Send a Start Condition */
46 #define AT91_TWI_STOP BIT(1) /* Send a Stop Condition */
47 #define AT91_TWI_MSEN BIT(2) /* Master Transfer Enable */
48 #define AT91_TWI_MSDIS BIT(3) /* Master Transfer Disable */
49 #define AT91_TWI_SVEN BIT(4) /* Slave Transfer Enable */
50 #define AT91_TWI_SVDIS BIT(5) /* Slave Transfer Disable */
51 #define AT91_TWI_QUICK BIT(6) /* SMBus quick command */
52 #define AT91_TWI_SWRST BIT(7) /* Software Reset */
53 #define AT91_TWI_ACMEN BIT(16) /* Alternative Command Mode Enable */
54 #define AT91_TWI_ACMDIS BIT(17) /* Alternative Command Mode Disable */
55 #define AT91_TWI_THRCLR BIT(24) /* Transmit Holding Register Clear */
56 #define AT91_TWI_RHRCLR BIT(25) /* Receive Holding Register Clear */
57 #define AT91_TWI_LOCKCLR BIT(26) /* Lock Clear */
58 #define AT91_TWI_FIFOEN BIT(28) /* FIFO Enable */
59 #define AT91_TWI_FIFODIS BIT(29) /* FIFO Disable */
60
61 #define AT91_TWI_MMR 0x0004 /* Master Mode Register */
62 #define AT91_TWI_IADRSZ_1 0x0100 /* Internal Device Address Size */
63 #define AT91_TWI_MREAD BIT(12) /* Master Read Direction */
64
65 #define AT91_TWI_IADR 0x000c /* Internal Address Register */
66
67 #define AT91_TWI_CWGR 0x0010 /* Clock Waveform Generator Reg */
68 #define AT91_TWI_CWGR_HOLD_MAX 0x1f
69 #define AT91_TWI_CWGR_HOLD(x) (((x) & AT91_TWI_CWGR_HOLD_MAX) << 24)
70
71 #define AT91_TWI_SR 0x0020 /* Status Register */
72 #define AT91_TWI_TXCOMP BIT(0) /* Transmission Complete */
73 #define AT91_TWI_RXRDY BIT(1) /* Receive Holding Register Ready */
74 #define AT91_TWI_TXRDY BIT(2) /* Transmit Holding Register Ready */
75 #define AT91_TWI_OVRE BIT(6) /* Overrun Error */
76 #define AT91_TWI_UNRE BIT(7) /* Underrun Error */
77 #define AT91_TWI_NACK BIT(8) /* Not Acknowledged */
78 #define AT91_TWI_LOCK BIT(23) /* TWI Lock due to Frame Errors */
79
80 #define AT91_TWI_INT_MASK \
81 (AT91_TWI_TXCOMP | AT91_TWI_RXRDY | AT91_TWI_TXRDY | AT91_TWI_NACK)
82
83 #define AT91_TWI_IER 0x0024 /* Interrupt Enable Register */
84 #define AT91_TWI_IDR 0x0028 /* Interrupt Disable Register */
85 #define AT91_TWI_IMR 0x002c /* Interrupt Mask Register */
86 #define AT91_TWI_RHR 0x0030 /* Receive Holding Register */
87 #define AT91_TWI_THR 0x0034 /* Transmit Holding Register */
88
89 #define AT91_TWI_ACR 0x0040 /* Alternative Command Register */
90 #define AT91_TWI_ACR_DATAL(len) ((len) & 0xff)
91 #define AT91_TWI_ACR_DIR BIT(8)
92
93 #define AT91_TWI_FMR 0x0050 /* FIFO Mode Register */
94 #define AT91_TWI_FMR_TXRDYM(mode) (((mode) & 0x3) << 0)
95 #define AT91_TWI_FMR_TXRDYM_MASK (0x3 << 0)
96 #define AT91_TWI_FMR_RXRDYM(mode) (((mode) & 0x3) << 4)
97 #define AT91_TWI_FMR_RXRDYM_MASK (0x3 << 4)
98 #define AT91_TWI_ONE_DATA 0x0
99 #define AT91_TWI_TWO_DATA 0x1
100 #define AT91_TWI_FOUR_DATA 0x2
101
102 #define AT91_TWI_FLR 0x0054 /* FIFO Level Register */
103
104 #define AT91_TWI_FSR 0x0060 /* FIFO Status Register */
105 #define AT91_TWI_FIER 0x0064 /* FIFO Interrupt Enable Register */
106 #define AT91_TWI_FIDR 0x0068 /* FIFO Interrupt Disable Register */
107 #define AT91_TWI_FIMR 0x006c /* FIFO Interrupt Mask Register */
108
109 #define AT91_TWI_VER 0x00fc /* Version Register */
110
111 struct at91_twi_pdata {
112 unsigned clk_max_div;
113 unsigned clk_offset;
114 bool has_unre_flag;
115 bool has_alt_cmd;
116 bool has_hold_field;
117 struct at_dma_slave dma_slave;
118 };
119
120 struct at91_twi_dma {
121 struct dma_chan *chan_rx;
122 struct dma_chan *chan_tx;
123 struct scatterlist sg[2];
124 struct dma_async_tx_descriptor *data_desc;
125 enum dma_data_direction direction;
126 bool buf_mapped;
127 bool xfer_in_progress;
128 };
129
130 struct at91_twi_dev {
131 struct device *dev;
132 void __iomem *base;
133 struct completion cmd_complete;
134 struct clk *clk;
135 u8 *buf;
136 size_t buf_len;
137 struct i2c_msg *msg;
138 int irq;
139 unsigned imr;
140 unsigned transfer_status;
141 struct i2c_adapter adapter;
142 unsigned twi_cwgr_reg;
143 struct at91_twi_pdata *pdata;
144 bool use_dma;
145 bool use_alt_cmd;
146 bool recv_len_abort;
147 u32 fifo_size;
148 struct at91_twi_dma dma;
149 };
150
at91_twi_read(struct at91_twi_dev * dev,unsigned reg)151 static unsigned at91_twi_read(struct at91_twi_dev *dev, unsigned reg)
152 {
153 return readl_relaxed(dev->base + reg);
154 }
155
at91_twi_write(struct at91_twi_dev * dev,unsigned reg,unsigned val)156 static void at91_twi_write(struct at91_twi_dev *dev, unsigned reg, unsigned val)
157 {
158 writel_relaxed(val, dev->base + reg);
159 }
160
at91_disable_twi_interrupts(struct at91_twi_dev * dev)161 static void at91_disable_twi_interrupts(struct at91_twi_dev *dev)
162 {
163 at91_twi_write(dev, AT91_TWI_IDR, AT91_TWI_INT_MASK);
164 }
165
at91_twi_irq_save(struct at91_twi_dev * dev)166 static void at91_twi_irq_save(struct at91_twi_dev *dev)
167 {
168 dev->imr = at91_twi_read(dev, AT91_TWI_IMR) & AT91_TWI_INT_MASK;
169 at91_disable_twi_interrupts(dev);
170 }
171
at91_twi_irq_restore(struct at91_twi_dev * dev)172 static void at91_twi_irq_restore(struct at91_twi_dev *dev)
173 {
174 at91_twi_write(dev, AT91_TWI_IER, dev->imr);
175 }
176
at91_init_twi_bus(struct at91_twi_dev * dev)177 static void at91_init_twi_bus(struct at91_twi_dev *dev)
178 {
179 at91_disable_twi_interrupts(dev);
180 at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_SWRST);
181 /* FIFO should be enabled immediately after the software reset */
182 if (dev->fifo_size)
183 at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_FIFOEN);
184 at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_MSEN);
185 at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_SVDIS);
186 at91_twi_write(dev, AT91_TWI_CWGR, dev->twi_cwgr_reg);
187 }
188
189 /*
190 * Calculate symmetric clock as stated in datasheet:
191 * twi_clk = F_MAIN / (2 * (cdiv * (1 << ckdiv) + offset))
192 */
at91_calc_twi_clock(struct at91_twi_dev * dev,int twi_clk)193 static void at91_calc_twi_clock(struct at91_twi_dev *dev, int twi_clk)
194 {
195 int ckdiv, cdiv, div, hold = 0;
196 struct at91_twi_pdata *pdata = dev->pdata;
197 int offset = pdata->clk_offset;
198 int max_ckdiv = pdata->clk_max_div;
199 u32 twd_hold_time_ns = 0;
200
201 div = max(0, (int)DIV_ROUND_UP(clk_get_rate(dev->clk),
202 2 * twi_clk) - offset);
203 ckdiv = fls(div >> 8);
204 cdiv = div >> ckdiv;
205
206 if (ckdiv > max_ckdiv) {
207 dev_warn(dev->dev, "%d exceeds ckdiv max value which is %d.\n",
208 ckdiv, max_ckdiv);
209 ckdiv = max_ckdiv;
210 cdiv = 255;
211 }
212
213 if (pdata->has_hold_field) {
214 of_property_read_u32(dev->dev->of_node, "i2c-sda-hold-time-ns",
215 &twd_hold_time_ns);
216
217 /*
218 * hold time = HOLD + 3 x T_peripheral_clock
219 * Use clk rate in kHz to prevent overflows when computing
220 * hold.
221 */
222 hold = DIV_ROUND_UP(twd_hold_time_ns
223 * (clk_get_rate(dev->clk) / 1000), 1000000);
224 hold -= 3;
225 if (hold < 0)
226 hold = 0;
227 if (hold > AT91_TWI_CWGR_HOLD_MAX) {
228 dev_warn(dev->dev,
229 "HOLD field set to its maximum value (%d instead of %d)\n",
230 AT91_TWI_CWGR_HOLD_MAX, hold);
231 hold = AT91_TWI_CWGR_HOLD_MAX;
232 }
233 }
234
235 dev->twi_cwgr_reg = (ckdiv << 16) | (cdiv << 8) | cdiv
236 | AT91_TWI_CWGR_HOLD(hold);
237
238 dev_dbg(dev->dev, "cdiv %d ckdiv %d hold %d (%d ns)\n",
239 cdiv, ckdiv, hold, twd_hold_time_ns);
240 }
241
at91_twi_dma_cleanup(struct at91_twi_dev * dev)242 static void at91_twi_dma_cleanup(struct at91_twi_dev *dev)
243 {
244 struct at91_twi_dma *dma = &dev->dma;
245
246 at91_twi_irq_save(dev);
247
248 if (dma->xfer_in_progress) {
249 if (dma->direction == DMA_FROM_DEVICE)
250 dmaengine_terminate_all(dma->chan_rx);
251 else
252 dmaengine_terminate_all(dma->chan_tx);
253 dma->xfer_in_progress = false;
254 }
255 if (dma->buf_mapped) {
256 dma_unmap_single(dev->dev, sg_dma_address(&dma->sg[0]),
257 dev->buf_len, dma->direction);
258 dma->buf_mapped = false;
259 }
260
261 at91_twi_irq_restore(dev);
262 }
263
at91_twi_write_next_byte(struct at91_twi_dev * dev)264 static void at91_twi_write_next_byte(struct at91_twi_dev *dev)
265 {
266 if (!dev->buf_len)
267 return;
268
269 /* 8bit write works with and without FIFO */
270 writeb_relaxed(*dev->buf, dev->base + AT91_TWI_THR);
271
272 /* send stop when last byte has been written */
273 if (--dev->buf_len == 0)
274 if (!dev->use_alt_cmd)
275 at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_STOP);
276
277 dev_dbg(dev->dev, "wrote 0x%x, to go %zu\n", *dev->buf, dev->buf_len);
278
279 ++dev->buf;
280 }
281
at91_twi_write_data_dma_callback(void * data)282 static void at91_twi_write_data_dma_callback(void *data)
283 {
284 struct at91_twi_dev *dev = (struct at91_twi_dev *)data;
285
286 dma_unmap_single(dev->dev, sg_dma_address(&dev->dma.sg[0]),
287 dev->buf_len, DMA_TO_DEVICE);
288
289 /*
290 * When this callback is called, THR/TX FIFO is likely not to be empty
291 * yet. So we have to wait for TXCOMP or NACK bits to be set into the
292 * Status Register to be sure that the STOP bit has been sent and the
293 * transfer is completed. The NACK interrupt has already been enabled,
294 * we just have to enable TXCOMP one.
295 */
296 at91_twi_write(dev, AT91_TWI_IER, AT91_TWI_TXCOMP);
297 if (!dev->use_alt_cmd)
298 at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_STOP);
299 }
300
at91_twi_write_data_dma(struct at91_twi_dev * dev)301 static void at91_twi_write_data_dma(struct at91_twi_dev *dev)
302 {
303 dma_addr_t dma_addr;
304 struct dma_async_tx_descriptor *txdesc;
305 struct at91_twi_dma *dma = &dev->dma;
306 struct dma_chan *chan_tx = dma->chan_tx;
307 unsigned int sg_len = 1;
308
309 if (!dev->buf_len)
310 return;
311
312 dma->direction = DMA_TO_DEVICE;
313
314 at91_twi_irq_save(dev);
315 dma_addr = dma_map_single(dev->dev, dev->buf, dev->buf_len,
316 DMA_TO_DEVICE);
317 if (dma_mapping_error(dev->dev, dma_addr)) {
318 dev_err(dev->dev, "dma map failed\n");
319 return;
320 }
321 dma->buf_mapped = true;
322 at91_twi_irq_restore(dev);
323
324 if (dev->fifo_size) {
325 size_t part1_len, part2_len;
326 struct scatterlist *sg;
327 unsigned fifo_mr;
328
329 sg_len = 0;
330
331 part1_len = dev->buf_len & ~0x3;
332 if (part1_len) {
333 sg = &dma->sg[sg_len++];
334 sg_dma_len(sg) = part1_len;
335 sg_dma_address(sg) = dma_addr;
336 }
337
338 part2_len = dev->buf_len & 0x3;
339 if (part2_len) {
340 sg = &dma->sg[sg_len++];
341 sg_dma_len(sg) = part2_len;
342 sg_dma_address(sg) = dma_addr + part1_len;
343 }
344
345 /*
346 * DMA controller is triggered when at least 4 data can be
347 * written into the TX FIFO
348 */
349 fifo_mr = at91_twi_read(dev, AT91_TWI_FMR);
350 fifo_mr &= ~AT91_TWI_FMR_TXRDYM_MASK;
351 fifo_mr |= AT91_TWI_FMR_TXRDYM(AT91_TWI_FOUR_DATA);
352 at91_twi_write(dev, AT91_TWI_FMR, fifo_mr);
353 } else {
354 sg_dma_len(&dma->sg[0]) = dev->buf_len;
355 sg_dma_address(&dma->sg[0]) = dma_addr;
356 }
357
358 txdesc = dmaengine_prep_slave_sg(chan_tx, dma->sg, sg_len,
359 DMA_MEM_TO_DEV,
360 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
361 if (!txdesc) {
362 dev_err(dev->dev, "dma prep slave sg failed\n");
363 goto error;
364 }
365
366 txdesc->callback = at91_twi_write_data_dma_callback;
367 txdesc->callback_param = dev;
368
369 dma->xfer_in_progress = true;
370 dmaengine_submit(txdesc);
371 dma_async_issue_pending(chan_tx);
372
373 return;
374
375 error:
376 at91_twi_dma_cleanup(dev);
377 }
378
at91_twi_read_next_byte(struct at91_twi_dev * dev)379 static void at91_twi_read_next_byte(struct at91_twi_dev *dev)
380 {
381 /*
382 * If we are in this case, it means there is garbage data in RHR, so
383 * delete them.
384 */
385 if (!dev->buf_len) {
386 at91_twi_read(dev, AT91_TWI_RHR);
387 return;
388 }
389
390 /* 8bit read works with and without FIFO */
391 *dev->buf = readb_relaxed(dev->base + AT91_TWI_RHR);
392 --dev->buf_len;
393
394 /* return if aborting, we only needed to read RHR to clear RXRDY*/
395 if (dev->recv_len_abort)
396 return;
397
398 /* handle I2C_SMBUS_BLOCK_DATA */
399 if (unlikely(dev->msg->flags & I2C_M_RECV_LEN)) {
400 /* ensure length byte is a valid value */
401 if (*dev->buf <= I2C_SMBUS_BLOCK_MAX && *dev->buf > 0) {
402 dev->msg->flags &= ~I2C_M_RECV_LEN;
403 dev->buf_len += *dev->buf;
404 dev->msg->len = dev->buf_len + 1;
405 dev_dbg(dev->dev, "received block length %zu\n",
406 dev->buf_len);
407 } else {
408 /* abort and send the stop by reading one more byte */
409 dev->recv_len_abort = true;
410 dev->buf_len = 1;
411 }
412 }
413
414 /* send stop if second but last byte has been read */
415 if (!dev->use_alt_cmd && dev->buf_len == 1)
416 at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_STOP);
417
418 dev_dbg(dev->dev, "read 0x%x, to go %zu\n", *dev->buf, dev->buf_len);
419
420 ++dev->buf;
421 }
422
at91_twi_read_data_dma_callback(void * data)423 static void at91_twi_read_data_dma_callback(void *data)
424 {
425 struct at91_twi_dev *dev = (struct at91_twi_dev *)data;
426 unsigned ier = AT91_TWI_TXCOMP;
427
428 dma_unmap_single(dev->dev, sg_dma_address(&dev->dma.sg[0]),
429 dev->buf_len, DMA_FROM_DEVICE);
430
431 if (!dev->use_alt_cmd) {
432 /* The last two bytes have to be read without using dma */
433 dev->buf += dev->buf_len - 2;
434 dev->buf_len = 2;
435 ier |= AT91_TWI_RXRDY;
436 }
437 at91_twi_write(dev, AT91_TWI_IER, ier);
438 }
439
at91_twi_read_data_dma(struct at91_twi_dev * dev)440 static void at91_twi_read_data_dma(struct at91_twi_dev *dev)
441 {
442 dma_addr_t dma_addr;
443 struct dma_async_tx_descriptor *rxdesc;
444 struct at91_twi_dma *dma = &dev->dma;
445 struct dma_chan *chan_rx = dma->chan_rx;
446 size_t buf_len;
447
448 buf_len = (dev->use_alt_cmd) ? dev->buf_len : dev->buf_len - 2;
449 dma->direction = DMA_FROM_DEVICE;
450
451 /* Keep in mind that we won't use dma to read the last two bytes */
452 at91_twi_irq_save(dev);
453 dma_addr = dma_map_single(dev->dev, dev->buf, buf_len, DMA_FROM_DEVICE);
454 if (dma_mapping_error(dev->dev, dma_addr)) {
455 dev_err(dev->dev, "dma map failed\n");
456 return;
457 }
458 dma->buf_mapped = true;
459 at91_twi_irq_restore(dev);
460
461 if (dev->fifo_size && IS_ALIGNED(buf_len, 4)) {
462 unsigned fifo_mr;
463
464 /*
465 * DMA controller is triggered when at least 4 data can be
466 * read from the RX FIFO
467 */
468 fifo_mr = at91_twi_read(dev, AT91_TWI_FMR);
469 fifo_mr &= ~AT91_TWI_FMR_RXRDYM_MASK;
470 fifo_mr |= AT91_TWI_FMR_RXRDYM(AT91_TWI_FOUR_DATA);
471 at91_twi_write(dev, AT91_TWI_FMR, fifo_mr);
472 }
473
474 sg_dma_len(&dma->sg[0]) = buf_len;
475 sg_dma_address(&dma->sg[0]) = dma_addr;
476
477 rxdesc = dmaengine_prep_slave_sg(chan_rx, dma->sg, 1, DMA_DEV_TO_MEM,
478 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
479 if (!rxdesc) {
480 dev_err(dev->dev, "dma prep slave sg failed\n");
481 goto error;
482 }
483
484 rxdesc->callback = at91_twi_read_data_dma_callback;
485 rxdesc->callback_param = dev;
486
487 dma->xfer_in_progress = true;
488 dmaengine_submit(rxdesc);
489 dma_async_issue_pending(dma->chan_rx);
490
491 return;
492
493 error:
494 at91_twi_dma_cleanup(dev);
495 }
496
atmel_twi_interrupt(int irq,void * dev_id)497 static irqreturn_t atmel_twi_interrupt(int irq, void *dev_id)
498 {
499 struct at91_twi_dev *dev = dev_id;
500 const unsigned status = at91_twi_read(dev, AT91_TWI_SR);
501 const unsigned irqstatus = status & at91_twi_read(dev, AT91_TWI_IMR);
502
503 if (!irqstatus)
504 return IRQ_NONE;
505 /*
506 * In reception, the behavior of the twi device (before sama5d2) is
507 * weird. There is some magic about RXRDY flag! When a data has been
508 * almost received, the reception of a new one is anticipated if there
509 * is no stop command to send. That is the reason why ask for sending
510 * the stop command not on the last data but on the second last one.
511 *
512 * Unfortunately, we could still have the RXRDY flag set even if the
513 * transfer is done and we have read the last data. It might happen
514 * when the i2c slave device sends too quickly data after receiving the
515 * ack from the master. The data has been almost received before having
516 * the order to send stop. In this case, sending the stop command could
517 * cause a RXRDY interrupt with a TXCOMP one. It is better to manage
518 * the RXRDY interrupt first in order to not keep garbage data in the
519 * Receive Holding Register for the next transfer.
520 */
521 if (irqstatus & AT91_TWI_RXRDY) {
522 /*
523 * Read all available bytes at once by polling RXRDY usable w/
524 * and w/o FIFO. With FIFO enabled we could also read RXFL and
525 * avoid polling RXRDY.
526 */
527 do {
528 at91_twi_read_next_byte(dev);
529 } while (at91_twi_read(dev, AT91_TWI_SR) & AT91_TWI_RXRDY);
530 }
531
532 /*
533 * When a NACK condition is detected, the I2C controller sets the NACK,
534 * TXCOMP and TXRDY bits all together in the Status Register (SR).
535 *
536 * 1 - Handling NACK errors with CPU write transfer.
537 *
538 * In such case, we should not write the next byte into the Transmit
539 * Holding Register (THR) otherwise the I2C controller would start a new
540 * transfer and the I2C slave is likely to reply by another NACK.
541 *
542 * 2 - Handling NACK errors with DMA write transfer.
543 *
544 * By setting the TXRDY bit in the SR, the I2C controller also triggers
545 * the DMA controller to write the next data into the THR. Then the
546 * result depends on the hardware version of the I2C controller.
547 *
548 * 2a - Without support of the Alternative Command mode.
549 *
550 * This is the worst case: the DMA controller is triggered to write the
551 * next data into the THR, hence starting a new transfer: the I2C slave
552 * is likely to reply by another NACK.
553 * Concurrently, this interrupt handler is likely to be called to manage
554 * the first NACK before the I2C controller detects the second NACK and
555 * sets once again the NACK bit into the SR.
556 * When handling the first NACK, this interrupt handler disables the I2C
557 * controller interruptions, especially the NACK interrupt.
558 * Hence, the NACK bit is pending into the SR. This is why we should
559 * read the SR to clear all pending interrupts at the beginning of
560 * at91_do_twi_transfer() before actually starting a new transfer.
561 *
562 * 2b - With support of the Alternative Command mode.
563 *
564 * When a NACK condition is detected, the I2C controller also locks the
565 * THR (and sets the LOCK bit in the SR): even though the DMA controller
566 * is triggered by the TXRDY bit to write the next data into the THR,
567 * this data actually won't go on the I2C bus hence a second NACK is not
568 * generated.
569 */
570 if (irqstatus & (AT91_TWI_TXCOMP | AT91_TWI_NACK)) {
571 at91_disable_twi_interrupts(dev);
572 complete(&dev->cmd_complete);
573 } else if (irqstatus & AT91_TWI_TXRDY) {
574 at91_twi_write_next_byte(dev);
575 }
576
577 /* catch error flags */
578 dev->transfer_status |= status;
579
580 return IRQ_HANDLED;
581 }
582
at91_do_twi_transfer(struct at91_twi_dev * dev)583 static int at91_do_twi_transfer(struct at91_twi_dev *dev)
584 {
585 int ret;
586 unsigned long time_left;
587 bool has_unre_flag = dev->pdata->has_unre_flag;
588 bool has_alt_cmd = dev->pdata->has_alt_cmd;
589
590 /*
591 * WARNING: the TXCOMP bit in the Status Register is NOT a clear on
592 * read flag but shows the state of the transmission at the time the
593 * Status Register is read. According to the programmer datasheet,
594 * TXCOMP is set when both holding register and internal shifter are
595 * empty and STOP condition has been sent.
596 * Consequently, we should enable NACK interrupt rather than TXCOMP to
597 * detect transmission failure.
598 * Indeed let's take the case of an i2c write command using DMA.
599 * Whenever the slave doesn't acknowledge a byte, the LOCK, NACK and
600 * TXCOMP bits are set together into the Status Register.
601 * LOCK is a clear on write bit, which is set to prevent the DMA
602 * controller from sending new data on the i2c bus after a NACK
603 * condition has happened. Once locked, this i2c peripheral stops
604 * triggering the DMA controller for new data but it is more than
605 * likely that a new DMA transaction is already in progress, writing
606 * into the Transmit Holding Register. Since the peripheral is locked,
607 * these new data won't be sent to the i2c bus but they will remain
608 * into the Transmit Holding Register, so TXCOMP bit is cleared.
609 * Then when the interrupt handler is called, the Status Register is
610 * read: the TXCOMP bit is clear but NACK bit is still set. The driver
611 * manage the error properly, without waiting for timeout.
612 * This case can be reproduced easyly when writing into an at24 eeprom.
613 *
614 * Besides, the TXCOMP bit is already set before the i2c transaction
615 * has been started. For read transactions, this bit is cleared when
616 * writing the START bit into the Control Register. So the
617 * corresponding interrupt can safely be enabled just after.
618 * However for write transactions managed by the CPU, we first write
619 * into THR, so TXCOMP is cleared. Then we can safely enable TXCOMP
620 * interrupt. If TXCOMP interrupt were enabled before writing into THR,
621 * the interrupt handler would be called immediately and the i2c command
622 * would be reported as completed.
623 * Also when a write transaction is managed by the DMA controller,
624 * enabling the TXCOMP interrupt in this function may lead to a race
625 * condition since we don't know whether the TXCOMP interrupt is enabled
626 * before or after the DMA has started to write into THR. So the TXCOMP
627 * interrupt is enabled later by at91_twi_write_data_dma_callback().
628 * Immediately after in that DMA callback, if the alternative command
629 * mode is not used, we still need to send the STOP condition manually
630 * writing the corresponding bit into the Control Register.
631 */
632
633 dev_dbg(dev->dev, "transfer: %s %zu bytes.\n",
634 (dev->msg->flags & I2C_M_RD) ? "read" : "write", dev->buf_len);
635
636 reinit_completion(&dev->cmd_complete);
637 dev->transfer_status = 0;
638
639 /* Clear pending interrupts, such as NACK. */
640 at91_twi_read(dev, AT91_TWI_SR);
641
642 if (dev->fifo_size) {
643 unsigned fifo_mr = at91_twi_read(dev, AT91_TWI_FMR);
644
645 /* Reset FIFO mode register */
646 fifo_mr &= ~(AT91_TWI_FMR_TXRDYM_MASK |
647 AT91_TWI_FMR_RXRDYM_MASK);
648 fifo_mr |= AT91_TWI_FMR_TXRDYM(AT91_TWI_ONE_DATA);
649 fifo_mr |= AT91_TWI_FMR_RXRDYM(AT91_TWI_ONE_DATA);
650 at91_twi_write(dev, AT91_TWI_FMR, fifo_mr);
651
652 /* Flush FIFOs */
653 at91_twi_write(dev, AT91_TWI_CR,
654 AT91_TWI_THRCLR | AT91_TWI_RHRCLR);
655 }
656
657 if (!dev->buf_len) {
658 at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_QUICK);
659 at91_twi_write(dev, AT91_TWI_IER, AT91_TWI_TXCOMP);
660 } else if (dev->msg->flags & I2C_M_RD) {
661 unsigned start_flags = AT91_TWI_START;
662
663 /* if only one byte is to be read, immediately stop transfer */
664 if (!dev->use_alt_cmd && dev->buf_len <= 1 &&
665 !(dev->msg->flags & I2C_M_RECV_LEN))
666 start_flags |= AT91_TWI_STOP;
667 at91_twi_write(dev, AT91_TWI_CR, start_flags);
668 /*
669 * When using dma without alternative command mode, the last
670 * byte has to be read manually in order to not send the stop
671 * command too late and then to receive extra data.
672 * In practice, there are some issues if you use the dma to
673 * read n-1 bytes because of latency.
674 * Reading n-2 bytes with dma and the two last ones manually
675 * seems to be the best solution.
676 */
677 if (dev->use_dma && (dev->buf_len > AT91_I2C_DMA_THRESHOLD)) {
678 at91_twi_write(dev, AT91_TWI_IER, AT91_TWI_NACK);
679 at91_twi_read_data_dma(dev);
680 } else {
681 at91_twi_write(dev, AT91_TWI_IER,
682 AT91_TWI_TXCOMP |
683 AT91_TWI_NACK |
684 AT91_TWI_RXRDY);
685 }
686 } else {
687 if (dev->use_dma && (dev->buf_len > AT91_I2C_DMA_THRESHOLD)) {
688 at91_twi_write(dev, AT91_TWI_IER, AT91_TWI_NACK);
689 at91_twi_write_data_dma(dev);
690 } else {
691 at91_twi_write_next_byte(dev);
692 at91_twi_write(dev, AT91_TWI_IER,
693 AT91_TWI_TXCOMP |
694 AT91_TWI_NACK |
695 AT91_TWI_TXRDY);
696 }
697 }
698
699 time_left = wait_for_completion_timeout(&dev->cmd_complete,
700 dev->adapter.timeout);
701 if (time_left == 0) {
702 dev->transfer_status |= at91_twi_read(dev, AT91_TWI_SR);
703 dev_err(dev->dev, "controller timed out\n");
704 at91_init_twi_bus(dev);
705 ret = -ETIMEDOUT;
706 goto error;
707 }
708 if (dev->transfer_status & AT91_TWI_NACK) {
709 dev_dbg(dev->dev, "received nack\n");
710 ret = -EREMOTEIO;
711 goto error;
712 }
713 if (dev->transfer_status & AT91_TWI_OVRE) {
714 dev_err(dev->dev, "overrun while reading\n");
715 ret = -EIO;
716 goto error;
717 }
718 if (has_unre_flag && dev->transfer_status & AT91_TWI_UNRE) {
719 dev_err(dev->dev, "underrun while writing\n");
720 ret = -EIO;
721 goto error;
722 }
723 if ((has_alt_cmd || dev->fifo_size) &&
724 (dev->transfer_status & AT91_TWI_LOCK)) {
725 dev_err(dev->dev, "tx locked\n");
726 ret = -EIO;
727 goto error;
728 }
729 if (dev->recv_len_abort) {
730 dev_err(dev->dev, "invalid smbus block length recvd\n");
731 ret = -EPROTO;
732 goto error;
733 }
734
735 dev_dbg(dev->dev, "transfer complete\n");
736
737 return 0;
738
739 error:
740 /* first stop DMA transfer if still in progress */
741 at91_twi_dma_cleanup(dev);
742 /* then flush THR/FIFO and unlock TX if locked */
743 if ((has_alt_cmd || dev->fifo_size) &&
744 (dev->transfer_status & AT91_TWI_LOCK)) {
745 dev_dbg(dev->dev, "unlock tx\n");
746 at91_twi_write(dev, AT91_TWI_CR,
747 AT91_TWI_THRCLR | AT91_TWI_LOCKCLR);
748 }
749 return ret;
750 }
751
at91_twi_xfer(struct i2c_adapter * adap,struct i2c_msg * msg,int num)752 static int at91_twi_xfer(struct i2c_adapter *adap, struct i2c_msg *msg, int num)
753 {
754 struct at91_twi_dev *dev = i2c_get_adapdata(adap);
755 int ret;
756 unsigned int_addr_flag = 0;
757 struct i2c_msg *m_start = msg;
758 bool is_read;
759
760 dev_dbg(&adap->dev, "at91_xfer: processing %d messages:\n", num);
761
762 ret = pm_runtime_get_sync(dev->dev);
763 if (ret < 0)
764 goto out;
765
766 if (num == 2) {
767 int internal_address = 0;
768 int i;
769
770 /* 1st msg is put into the internal address, start with 2nd */
771 m_start = &msg[1];
772 for (i = 0; i < msg->len; ++i) {
773 const unsigned addr = msg->buf[msg->len - 1 - i];
774
775 internal_address |= addr << (8 * i);
776 int_addr_flag += AT91_TWI_IADRSZ_1;
777 }
778 at91_twi_write(dev, AT91_TWI_IADR, internal_address);
779 }
780
781 dev->use_alt_cmd = false;
782 is_read = (m_start->flags & I2C_M_RD);
783 if (dev->pdata->has_alt_cmd) {
784 if (m_start->len > 0 &&
785 m_start->len < AT91_I2C_MAX_ALT_CMD_DATA_SIZE) {
786 at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_ACMEN);
787 at91_twi_write(dev, AT91_TWI_ACR,
788 AT91_TWI_ACR_DATAL(m_start->len) |
789 ((is_read) ? AT91_TWI_ACR_DIR : 0));
790 dev->use_alt_cmd = true;
791 } else {
792 at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_ACMDIS);
793 }
794 }
795
796 at91_twi_write(dev, AT91_TWI_MMR,
797 (m_start->addr << 16) |
798 int_addr_flag |
799 ((!dev->use_alt_cmd && is_read) ? AT91_TWI_MREAD : 0));
800
801 dev->buf_len = m_start->len;
802 dev->buf = m_start->buf;
803 dev->msg = m_start;
804 dev->recv_len_abort = false;
805
806 ret = at91_do_twi_transfer(dev);
807
808 ret = (ret < 0) ? ret : num;
809 out:
810 pm_runtime_mark_last_busy(dev->dev);
811 pm_runtime_put_autosuspend(dev->dev);
812
813 return ret;
814 }
815
816 /*
817 * The hardware can handle at most two messages concatenated by a
818 * repeated start via it's internal address feature.
819 */
820 static const struct i2c_adapter_quirks at91_twi_quirks = {
821 .flags = I2C_AQ_COMB | I2C_AQ_COMB_WRITE_FIRST | I2C_AQ_COMB_SAME_ADDR,
822 .max_comb_1st_msg_len = 3,
823 };
824
at91_twi_func(struct i2c_adapter * adapter)825 static u32 at91_twi_func(struct i2c_adapter *adapter)
826 {
827 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL
828 | I2C_FUNC_SMBUS_READ_BLOCK_DATA;
829 }
830
831 static const struct i2c_algorithm at91_twi_algorithm = {
832 .master_xfer = at91_twi_xfer,
833 .functionality = at91_twi_func,
834 };
835
836 static struct at91_twi_pdata at91rm9200_config = {
837 .clk_max_div = 5,
838 .clk_offset = 3,
839 .has_unre_flag = true,
840 .has_alt_cmd = false,
841 .has_hold_field = false,
842 };
843
844 static struct at91_twi_pdata at91sam9261_config = {
845 .clk_max_div = 5,
846 .clk_offset = 4,
847 .has_unre_flag = false,
848 .has_alt_cmd = false,
849 .has_hold_field = false,
850 };
851
852 static struct at91_twi_pdata at91sam9260_config = {
853 .clk_max_div = 7,
854 .clk_offset = 4,
855 .has_unre_flag = false,
856 .has_alt_cmd = false,
857 .has_hold_field = false,
858 };
859
860 static struct at91_twi_pdata at91sam9g20_config = {
861 .clk_max_div = 7,
862 .clk_offset = 4,
863 .has_unre_flag = false,
864 .has_alt_cmd = false,
865 .has_hold_field = false,
866 };
867
868 static struct at91_twi_pdata at91sam9g10_config = {
869 .clk_max_div = 7,
870 .clk_offset = 4,
871 .has_unre_flag = false,
872 .has_alt_cmd = false,
873 .has_hold_field = false,
874 };
875
876 static const struct platform_device_id at91_twi_devtypes[] = {
877 {
878 .name = "i2c-at91rm9200",
879 .driver_data = (unsigned long) &at91rm9200_config,
880 }, {
881 .name = "i2c-at91sam9261",
882 .driver_data = (unsigned long) &at91sam9261_config,
883 }, {
884 .name = "i2c-at91sam9260",
885 .driver_data = (unsigned long) &at91sam9260_config,
886 }, {
887 .name = "i2c-at91sam9g20",
888 .driver_data = (unsigned long) &at91sam9g20_config,
889 }, {
890 .name = "i2c-at91sam9g10",
891 .driver_data = (unsigned long) &at91sam9g10_config,
892 }, {
893 /* sentinel */
894 }
895 };
896
897 #if defined(CONFIG_OF)
898 static struct at91_twi_pdata at91sam9x5_config = {
899 .clk_max_div = 7,
900 .clk_offset = 4,
901 .has_unre_flag = false,
902 .has_alt_cmd = false,
903 .has_hold_field = false,
904 };
905
906 static struct at91_twi_pdata sama5d4_config = {
907 .clk_max_div = 7,
908 .clk_offset = 4,
909 .has_unre_flag = false,
910 .has_alt_cmd = false,
911 .has_hold_field = true,
912 };
913
914 static struct at91_twi_pdata sama5d2_config = {
915 .clk_max_div = 7,
916 .clk_offset = 4,
917 .has_unre_flag = true,
918 .has_alt_cmd = true,
919 .has_hold_field = true,
920 };
921
922 static const struct of_device_id atmel_twi_dt_ids[] = {
923 {
924 .compatible = "atmel,at91rm9200-i2c",
925 .data = &at91rm9200_config,
926 } , {
927 .compatible = "atmel,at91sam9260-i2c",
928 .data = &at91sam9260_config,
929 } , {
930 .compatible = "atmel,at91sam9261-i2c",
931 .data = &at91sam9261_config,
932 } , {
933 .compatible = "atmel,at91sam9g20-i2c",
934 .data = &at91sam9g20_config,
935 } , {
936 .compatible = "atmel,at91sam9g10-i2c",
937 .data = &at91sam9g10_config,
938 }, {
939 .compatible = "atmel,at91sam9x5-i2c",
940 .data = &at91sam9x5_config,
941 }, {
942 .compatible = "atmel,sama5d4-i2c",
943 .data = &sama5d4_config,
944 }, {
945 .compatible = "atmel,sama5d2-i2c",
946 .data = &sama5d2_config,
947 }, {
948 /* sentinel */
949 }
950 };
951 MODULE_DEVICE_TABLE(of, atmel_twi_dt_ids);
952 #endif
953
at91_twi_configure_dma(struct at91_twi_dev * dev,u32 phy_addr)954 static int at91_twi_configure_dma(struct at91_twi_dev *dev, u32 phy_addr)
955 {
956 int ret = 0;
957 struct dma_slave_config slave_config;
958 struct at91_twi_dma *dma = &dev->dma;
959 enum dma_slave_buswidth addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
960
961 /*
962 * The actual width of the access will be chosen in
963 * dmaengine_prep_slave_sg():
964 * for each buffer in the scatter-gather list, if its size is aligned
965 * to addr_width then addr_width accesses will be performed to transfer
966 * the buffer. On the other hand, if the buffer size is not aligned to
967 * addr_width then the buffer is transferred using single byte accesses.
968 * Please refer to the Atmel eXtended DMA controller driver.
969 * When FIFOs are used, the TXRDYM threshold can always be set to
970 * trigger the XDMAC when at least 4 data can be written into the TX
971 * FIFO, even if single byte accesses are performed.
972 * However the RXRDYM threshold must be set to fit the access width,
973 * deduced from buffer length, so the XDMAC is triggered properly to
974 * read data from the RX FIFO.
975 */
976 if (dev->fifo_size)
977 addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
978
979 memset(&slave_config, 0, sizeof(slave_config));
980 slave_config.src_addr = (dma_addr_t)phy_addr + AT91_TWI_RHR;
981 slave_config.src_addr_width = addr_width;
982 slave_config.src_maxburst = 1;
983 slave_config.dst_addr = (dma_addr_t)phy_addr + AT91_TWI_THR;
984 slave_config.dst_addr_width = addr_width;
985 slave_config.dst_maxburst = 1;
986 slave_config.device_fc = false;
987
988 dma->chan_tx = dma_request_slave_channel_reason(dev->dev, "tx");
989 if (IS_ERR(dma->chan_tx)) {
990 ret = PTR_ERR(dma->chan_tx);
991 dma->chan_tx = NULL;
992 goto error;
993 }
994
995 dma->chan_rx = dma_request_slave_channel_reason(dev->dev, "rx");
996 if (IS_ERR(dma->chan_rx)) {
997 ret = PTR_ERR(dma->chan_rx);
998 dma->chan_rx = NULL;
999 goto error;
1000 }
1001
1002 slave_config.direction = DMA_MEM_TO_DEV;
1003 if (dmaengine_slave_config(dma->chan_tx, &slave_config)) {
1004 dev_err(dev->dev, "failed to configure tx channel\n");
1005 ret = -EINVAL;
1006 goto error;
1007 }
1008
1009 slave_config.direction = DMA_DEV_TO_MEM;
1010 if (dmaengine_slave_config(dma->chan_rx, &slave_config)) {
1011 dev_err(dev->dev, "failed to configure rx channel\n");
1012 ret = -EINVAL;
1013 goto error;
1014 }
1015
1016 sg_init_table(dma->sg, 2);
1017 dma->buf_mapped = false;
1018 dma->xfer_in_progress = false;
1019 dev->use_dma = true;
1020
1021 dev_info(dev->dev, "using %s (tx) and %s (rx) for DMA transfers\n",
1022 dma_chan_name(dma->chan_tx), dma_chan_name(dma->chan_rx));
1023
1024 return ret;
1025
1026 error:
1027 if (ret != -EPROBE_DEFER)
1028 dev_info(dev->dev, "can't get DMA channel, continue without DMA support\n");
1029 if (dma->chan_rx)
1030 dma_release_channel(dma->chan_rx);
1031 if (dma->chan_tx)
1032 dma_release_channel(dma->chan_tx);
1033 return ret;
1034 }
1035
at91_twi_get_driver_data(struct platform_device * pdev)1036 static struct at91_twi_pdata *at91_twi_get_driver_data(
1037 struct platform_device *pdev)
1038 {
1039 if (pdev->dev.of_node) {
1040 const struct of_device_id *match;
1041 match = of_match_node(atmel_twi_dt_ids, pdev->dev.of_node);
1042 if (!match)
1043 return NULL;
1044 return (struct at91_twi_pdata *)match->data;
1045 }
1046 return (struct at91_twi_pdata *) platform_get_device_id(pdev)->driver_data;
1047 }
1048
at91_twi_probe(struct platform_device * pdev)1049 static int at91_twi_probe(struct platform_device *pdev)
1050 {
1051 struct at91_twi_dev *dev;
1052 struct resource *mem;
1053 int rc;
1054 u32 phy_addr;
1055 u32 bus_clk_rate;
1056
1057 dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
1058 if (!dev)
1059 return -ENOMEM;
1060 init_completion(&dev->cmd_complete);
1061 dev->dev = &pdev->dev;
1062
1063 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1064 if (!mem)
1065 return -ENODEV;
1066 phy_addr = mem->start;
1067
1068 dev->pdata = at91_twi_get_driver_data(pdev);
1069 if (!dev->pdata)
1070 return -ENODEV;
1071
1072 dev->base = devm_ioremap_resource(&pdev->dev, mem);
1073 if (IS_ERR(dev->base))
1074 return PTR_ERR(dev->base);
1075
1076 dev->irq = platform_get_irq(pdev, 0);
1077 if (dev->irq < 0)
1078 return dev->irq;
1079
1080 rc = devm_request_irq(&pdev->dev, dev->irq, atmel_twi_interrupt, 0,
1081 dev_name(dev->dev), dev);
1082 if (rc) {
1083 dev_err(dev->dev, "Cannot get irq %d: %d\n", dev->irq, rc);
1084 return rc;
1085 }
1086
1087 platform_set_drvdata(pdev, dev);
1088
1089 dev->clk = devm_clk_get(dev->dev, NULL);
1090 if (IS_ERR(dev->clk)) {
1091 dev_err(dev->dev, "no clock defined\n");
1092 return -ENODEV;
1093 }
1094 rc = clk_prepare_enable(dev->clk);
1095 if (rc)
1096 return rc;
1097
1098 if (dev->dev->of_node) {
1099 rc = at91_twi_configure_dma(dev, phy_addr);
1100 if (rc == -EPROBE_DEFER) {
1101 clk_disable_unprepare(dev->clk);
1102 return rc;
1103 }
1104 }
1105
1106 if (!of_property_read_u32(pdev->dev.of_node, "atmel,fifo-size",
1107 &dev->fifo_size)) {
1108 dev_info(dev->dev, "Using FIFO (%u data)\n", dev->fifo_size);
1109 }
1110
1111 rc = of_property_read_u32(dev->dev->of_node, "clock-frequency",
1112 &bus_clk_rate);
1113 if (rc)
1114 bus_clk_rate = DEFAULT_TWI_CLK_HZ;
1115
1116 at91_calc_twi_clock(dev, bus_clk_rate);
1117 at91_init_twi_bus(dev);
1118
1119 snprintf(dev->adapter.name, sizeof(dev->adapter.name), "AT91");
1120 i2c_set_adapdata(&dev->adapter, dev);
1121 dev->adapter.owner = THIS_MODULE;
1122 dev->adapter.class = I2C_CLASS_DEPRECATED;
1123 dev->adapter.algo = &at91_twi_algorithm;
1124 dev->adapter.quirks = &at91_twi_quirks;
1125 dev->adapter.dev.parent = dev->dev;
1126 dev->adapter.nr = pdev->id;
1127 dev->adapter.timeout = AT91_I2C_TIMEOUT;
1128 dev->adapter.dev.of_node = pdev->dev.of_node;
1129
1130 pm_runtime_set_autosuspend_delay(dev->dev, AUTOSUSPEND_TIMEOUT);
1131 pm_runtime_use_autosuspend(dev->dev);
1132 pm_runtime_set_active(dev->dev);
1133 pm_runtime_enable(dev->dev);
1134
1135 rc = i2c_add_numbered_adapter(&dev->adapter);
1136 if (rc) {
1137 clk_disable_unprepare(dev->clk);
1138
1139 pm_runtime_disable(dev->dev);
1140 pm_runtime_set_suspended(dev->dev);
1141
1142 return rc;
1143 }
1144
1145 dev_info(dev->dev, "AT91 i2c bus driver (hw version: %#x).\n",
1146 at91_twi_read(dev, AT91_TWI_VER));
1147 return 0;
1148 }
1149
at91_twi_remove(struct platform_device * pdev)1150 static int at91_twi_remove(struct platform_device *pdev)
1151 {
1152 struct at91_twi_dev *dev = platform_get_drvdata(pdev);
1153
1154 i2c_del_adapter(&dev->adapter);
1155 clk_disable_unprepare(dev->clk);
1156
1157 pm_runtime_disable(dev->dev);
1158 pm_runtime_set_suspended(dev->dev);
1159
1160 return 0;
1161 }
1162
1163 #ifdef CONFIG_PM
1164
at91_twi_runtime_suspend(struct device * dev)1165 static int at91_twi_runtime_suspend(struct device *dev)
1166 {
1167 struct at91_twi_dev *twi_dev = dev_get_drvdata(dev);
1168
1169 clk_disable_unprepare(twi_dev->clk);
1170
1171 pinctrl_pm_select_sleep_state(dev);
1172
1173 return 0;
1174 }
1175
at91_twi_runtime_resume(struct device * dev)1176 static int at91_twi_runtime_resume(struct device *dev)
1177 {
1178 struct at91_twi_dev *twi_dev = dev_get_drvdata(dev);
1179
1180 pinctrl_pm_select_default_state(dev);
1181
1182 return clk_prepare_enable(twi_dev->clk);
1183 }
1184
at91_twi_suspend_noirq(struct device * dev)1185 static int at91_twi_suspend_noirq(struct device *dev)
1186 {
1187 if (!pm_runtime_status_suspended(dev))
1188 at91_twi_runtime_suspend(dev);
1189
1190 return 0;
1191 }
1192
at91_twi_resume_noirq(struct device * dev)1193 static int at91_twi_resume_noirq(struct device *dev)
1194 {
1195 struct at91_twi_dev *twi_dev = dev_get_drvdata(dev);
1196 int ret;
1197
1198 if (!pm_runtime_status_suspended(dev)) {
1199 ret = at91_twi_runtime_resume(dev);
1200 if (ret)
1201 return ret;
1202 }
1203
1204 pm_runtime_mark_last_busy(dev);
1205 pm_request_autosuspend(dev);
1206
1207 at91_init_twi_bus(twi_dev);
1208
1209 return 0;
1210 }
1211
1212 static const struct dev_pm_ops at91_twi_pm = {
1213 .suspend_noirq = at91_twi_suspend_noirq,
1214 .resume_noirq = at91_twi_resume_noirq,
1215 .runtime_suspend = at91_twi_runtime_suspend,
1216 .runtime_resume = at91_twi_runtime_resume,
1217 };
1218
1219 #define at91_twi_pm_ops (&at91_twi_pm)
1220 #else
1221 #define at91_twi_pm_ops NULL
1222 #endif
1223
1224 static struct platform_driver at91_twi_driver = {
1225 .probe = at91_twi_probe,
1226 .remove = at91_twi_remove,
1227 .id_table = at91_twi_devtypes,
1228 .driver = {
1229 .name = "at91_i2c",
1230 .of_match_table = of_match_ptr(atmel_twi_dt_ids),
1231 .pm = at91_twi_pm_ops,
1232 },
1233 };
1234
at91_twi_init(void)1235 static int __init at91_twi_init(void)
1236 {
1237 return platform_driver_register(&at91_twi_driver);
1238 }
1239
at91_twi_exit(void)1240 static void __exit at91_twi_exit(void)
1241 {
1242 platform_driver_unregister(&at91_twi_driver);
1243 }
1244
1245 subsys_initcall(at91_twi_init);
1246 module_exit(at91_twi_exit);
1247
1248 MODULE_AUTHOR("Nikolaus Voss <n.voss@weinmann.de>");
1249 MODULE_DESCRIPTION("I2C (TWI) driver for Atmel AT91");
1250 MODULE_LICENSE("GPL");
1251 MODULE_ALIAS("platform:at91_i2c");
1252
