1 /*
2 * Aspeed 24XX/25XX I2C Controller.
3 *
4 * Copyright (C) 2012-2017 ASPEED Technology Inc.
5 * Copyright 2017 IBM Corporation
6 * Copyright 2017 Google, Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13 #include <linux/clk.h>
14 #include <linux/completion.h>
15 #include <linux/err.h>
16 #include <linux/errno.h>
17 #include <linux/i2c.h>
18 #include <linux/init.h>
19 #include <linux/interrupt.h>
20 #include <linux/io.h>
21 #include <linux/irq.h>
22 #include <linux/irqchip/chained_irq.h>
23 #include <linux/irqdomain.h>
24 #include <linux/kernel.h>
25 #include <linux/module.h>
26 #include <linux/of_address.h>
27 #include <linux/of_irq.h>
28 #include <linux/of_platform.h>
29 #include <linux/platform_device.h>
30 #include <linux/reset.h>
31 #include <linux/slab.h>
32
33 /* I2C Register */
34 #define ASPEED_I2C_FUN_CTRL_REG 0x00
35 #define ASPEED_I2C_AC_TIMING_REG1 0x04
36 #define ASPEED_I2C_AC_TIMING_REG2 0x08
37 #define ASPEED_I2C_INTR_CTRL_REG 0x0c
38 #define ASPEED_I2C_INTR_STS_REG 0x10
39 #define ASPEED_I2C_CMD_REG 0x14
40 #define ASPEED_I2C_DEV_ADDR_REG 0x18
41 #define ASPEED_I2C_BYTE_BUF_REG 0x20
42
43 /* Global Register Definition */
44 /* 0x00 : I2C Interrupt Status Register */
45 /* 0x08 : I2C Interrupt Target Assignment */
46
47 /* Device Register Definition */
48 /* 0x00 : I2CD Function Control Register */
49 #define ASPEED_I2CD_MULTI_MASTER_DIS BIT(15)
50 #define ASPEED_I2CD_SDA_DRIVE_1T_EN BIT(8)
51 #define ASPEED_I2CD_M_SDA_DRIVE_1T_EN BIT(7)
52 #define ASPEED_I2CD_M_HIGH_SPEED_EN BIT(6)
53 #define ASPEED_I2CD_SLAVE_EN BIT(1)
54 #define ASPEED_I2CD_MASTER_EN BIT(0)
55
56 /* 0x04 : I2CD Clock and AC Timing Control Register #1 */
57 #define ASPEED_I2CD_TIME_TBUF_MASK GENMASK(31, 28)
58 #define ASPEED_I2CD_TIME_THDSTA_MASK GENMASK(27, 24)
59 #define ASPEED_I2CD_TIME_TACST_MASK GENMASK(23, 20)
60 #define ASPEED_I2CD_TIME_SCL_HIGH_SHIFT 16
61 #define ASPEED_I2CD_TIME_SCL_HIGH_MASK GENMASK(19, 16)
62 #define ASPEED_I2CD_TIME_SCL_LOW_SHIFT 12
63 #define ASPEED_I2CD_TIME_SCL_LOW_MASK GENMASK(15, 12)
64 #define ASPEED_I2CD_TIME_BASE_DIVISOR_MASK GENMASK(3, 0)
65 #define ASPEED_I2CD_TIME_SCL_REG_MAX GENMASK(3, 0)
66 /* 0x08 : I2CD Clock and AC Timing Control Register #2 */
67 #define ASPEED_NO_TIMEOUT_CTRL 0
68
69 /* 0x0c : I2CD Interrupt Control Register &
70 * 0x10 : I2CD Interrupt Status Register
71 *
72 * These share bit definitions, so use the same values for the enable &
73 * status bits.
74 */
75 #define ASPEED_I2CD_INTR_SDA_DL_TIMEOUT BIT(14)
76 #define ASPEED_I2CD_INTR_BUS_RECOVER_DONE BIT(13)
77 #define ASPEED_I2CD_INTR_SLAVE_MATCH BIT(7)
78 #define ASPEED_I2CD_INTR_SCL_TIMEOUT BIT(6)
79 #define ASPEED_I2CD_INTR_ABNORMAL BIT(5)
80 #define ASPEED_I2CD_INTR_NORMAL_STOP BIT(4)
81 #define ASPEED_I2CD_INTR_ARBIT_LOSS BIT(3)
82 #define ASPEED_I2CD_INTR_RX_DONE BIT(2)
83 #define ASPEED_I2CD_INTR_TX_NAK BIT(1)
84 #define ASPEED_I2CD_INTR_TX_ACK BIT(0)
85 #define ASPEED_I2CD_INTR_ALL \
86 (ASPEED_I2CD_INTR_SDA_DL_TIMEOUT | \
87 ASPEED_I2CD_INTR_BUS_RECOVER_DONE | \
88 ASPEED_I2CD_INTR_SCL_TIMEOUT | \
89 ASPEED_I2CD_INTR_ABNORMAL | \
90 ASPEED_I2CD_INTR_NORMAL_STOP | \
91 ASPEED_I2CD_INTR_ARBIT_LOSS | \
92 ASPEED_I2CD_INTR_RX_DONE | \
93 ASPEED_I2CD_INTR_TX_NAK | \
94 ASPEED_I2CD_INTR_TX_ACK)
95
96 /* 0x14 : I2CD Command/Status Register */
97 #define ASPEED_I2CD_SCL_LINE_STS BIT(18)
98 #define ASPEED_I2CD_SDA_LINE_STS BIT(17)
99 #define ASPEED_I2CD_BUS_BUSY_STS BIT(16)
100 #define ASPEED_I2CD_BUS_RECOVER_CMD BIT(11)
101
102 /* Command Bit */
103 #define ASPEED_I2CD_M_STOP_CMD BIT(5)
104 #define ASPEED_I2CD_M_S_RX_CMD_LAST BIT(4)
105 #define ASPEED_I2CD_M_RX_CMD BIT(3)
106 #define ASPEED_I2CD_S_TX_CMD BIT(2)
107 #define ASPEED_I2CD_M_TX_CMD BIT(1)
108 #define ASPEED_I2CD_M_START_CMD BIT(0)
109
110 /* 0x18 : I2CD Slave Device Address Register */
111 #define ASPEED_I2CD_DEV_ADDR_MASK GENMASK(6, 0)
112
113 enum aspeed_i2c_master_state {
114 ASPEED_I2C_MASTER_INACTIVE,
115 ASPEED_I2C_MASTER_START,
116 ASPEED_I2C_MASTER_TX_FIRST,
117 ASPEED_I2C_MASTER_TX,
118 ASPEED_I2C_MASTER_RX_FIRST,
119 ASPEED_I2C_MASTER_RX,
120 ASPEED_I2C_MASTER_STOP,
121 };
122
123 enum aspeed_i2c_slave_state {
124 ASPEED_I2C_SLAVE_STOP,
125 ASPEED_I2C_SLAVE_START,
126 ASPEED_I2C_SLAVE_READ_REQUESTED,
127 ASPEED_I2C_SLAVE_READ_PROCESSED,
128 ASPEED_I2C_SLAVE_WRITE_REQUESTED,
129 ASPEED_I2C_SLAVE_WRITE_RECEIVED,
130 };
131
132 struct aspeed_i2c_bus {
133 struct i2c_adapter adap;
134 struct device *dev;
135 void __iomem *base;
136 struct reset_control *rst;
137 /* Synchronizes I/O mem access to base. */
138 spinlock_t lock;
139 struct completion cmd_complete;
140 u32 (*get_clk_reg_val)(u32 divisor);
141 unsigned long parent_clk_frequency;
142 u32 bus_frequency;
143 /* Transaction state. */
144 enum aspeed_i2c_master_state master_state;
145 struct i2c_msg *msgs;
146 size_t buf_index;
147 size_t msgs_index;
148 size_t msgs_count;
149 bool send_stop;
150 int cmd_err;
151 /* Protected only by i2c_lock_bus */
152 int master_xfer_result;
153 #if IS_ENABLED(CONFIG_I2C_SLAVE)
154 struct i2c_client *slave;
155 enum aspeed_i2c_slave_state slave_state;
156 #endif /* CONFIG_I2C_SLAVE */
157 };
158
159 static int aspeed_i2c_reset(struct aspeed_i2c_bus *bus);
160
aspeed_i2c_recover_bus(struct aspeed_i2c_bus * bus)161 static int aspeed_i2c_recover_bus(struct aspeed_i2c_bus *bus)
162 {
163 unsigned long time_left, flags;
164 int ret = 0;
165 u32 command;
166
167 spin_lock_irqsave(&bus->lock, flags);
168 command = readl(bus->base + ASPEED_I2C_CMD_REG);
169
170 if (command & ASPEED_I2CD_SDA_LINE_STS) {
171 /* Bus is idle: no recovery needed. */
172 if (command & ASPEED_I2CD_SCL_LINE_STS)
173 goto out;
174 dev_dbg(bus->dev, "SCL hung (state %x), attempting recovery\n",
175 command);
176
177 reinit_completion(&bus->cmd_complete);
178 writel(ASPEED_I2CD_M_STOP_CMD, bus->base + ASPEED_I2C_CMD_REG);
179 spin_unlock_irqrestore(&bus->lock, flags);
180
181 time_left = wait_for_completion_timeout(
182 &bus->cmd_complete, bus->adap.timeout);
183
184 spin_lock_irqsave(&bus->lock, flags);
185 if (time_left == 0)
186 goto reset_out;
187 else if (bus->cmd_err)
188 goto reset_out;
189 /* Recovery failed. */
190 else if (!(readl(bus->base + ASPEED_I2C_CMD_REG) &
191 ASPEED_I2CD_SCL_LINE_STS))
192 goto reset_out;
193 /* Bus error. */
194 } else {
195 dev_dbg(bus->dev, "SDA hung (state %x), attempting recovery\n",
196 command);
197
198 reinit_completion(&bus->cmd_complete);
199 /* Writes 1 to 8 SCL clock cycles until SDA is released. */
200 writel(ASPEED_I2CD_BUS_RECOVER_CMD,
201 bus->base + ASPEED_I2C_CMD_REG);
202 spin_unlock_irqrestore(&bus->lock, flags);
203
204 time_left = wait_for_completion_timeout(
205 &bus->cmd_complete, bus->adap.timeout);
206
207 spin_lock_irqsave(&bus->lock, flags);
208 if (time_left == 0)
209 goto reset_out;
210 else if (bus->cmd_err)
211 goto reset_out;
212 /* Recovery failed. */
213 else if (!(readl(bus->base + ASPEED_I2C_CMD_REG) &
214 ASPEED_I2CD_SDA_LINE_STS))
215 goto reset_out;
216 }
217
218 out:
219 spin_unlock_irqrestore(&bus->lock, flags);
220
221 return ret;
222
223 reset_out:
224 spin_unlock_irqrestore(&bus->lock, flags);
225
226 return aspeed_i2c_reset(bus);
227 }
228
229 #if IS_ENABLED(CONFIG_I2C_SLAVE)
aspeed_i2c_slave_irq(struct aspeed_i2c_bus * bus)230 static bool aspeed_i2c_slave_irq(struct aspeed_i2c_bus *bus)
231 {
232 u32 command, irq_status, status_ack = 0;
233 struct i2c_client *slave = bus->slave;
234 bool irq_handled = true;
235 u8 value;
236
237 if (!slave) {
238 irq_handled = false;
239 goto out;
240 }
241
242 command = readl(bus->base + ASPEED_I2C_CMD_REG);
243 irq_status = readl(bus->base + ASPEED_I2C_INTR_STS_REG);
244
245 /* Slave was requested, restart state machine. */
246 if (irq_status & ASPEED_I2CD_INTR_SLAVE_MATCH) {
247 status_ack |= ASPEED_I2CD_INTR_SLAVE_MATCH;
248 bus->slave_state = ASPEED_I2C_SLAVE_START;
249 }
250
251 /* Slave is not currently active, irq was for someone else. */
252 if (bus->slave_state == ASPEED_I2C_SLAVE_STOP) {
253 irq_handled = false;
254 goto out;
255 }
256
257 dev_dbg(bus->dev, "slave irq status 0x%08x, cmd 0x%08x\n",
258 irq_status, command);
259
260 /* Slave was sent something. */
261 if (irq_status & ASPEED_I2CD_INTR_RX_DONE) {
262 value = readl(bus->base + ASPEED_I2C_BYTE_BUF_REG) >> 8;
263 /* Handle address frame. */
264 if (bus->slave_state == ASPEED_I2C_SLAVE_START) {
265 if (value & 0x1)
266 bus->slave_state =
267 ASPEED_I2C_SLAVE_READ_REQUESTED;
268 else
269 bus->slave_state =
270 ASPEED_I2C_SLAVE_WRITE_REQUESTED;
271 }
272 status_ack |= ASPEED_I2CD_INTR_RX_DONE;
273 }
274
275 /* Slave was asked to stop. */
276 if (irq_status & ASPEED_I2CD_INTR_NORMAL_STOP) {
277 status_ack |= ASPEED_I2CD_INTR_NORMAL_STOP;
278 bus->slave_state = ASPEED_I2C_SLAVE_STOP;
279 }
280 if (irq_status & ASPEED_I2CD_INTR_TX_NAK) {
281 status_ack |= ASPEED_I2CD_INTR_TX_NAK;
282 bus->slave_state = ASPEED_I2C_SLAVE_STOP;
283 }
284
285 switch (bus->slave_state) {
286 case ASPEED_I2C_SLAVE_READ_REQUESTED:
287 if (irq_status & ASPEED_I2CD_INTR_TX_ACK)
288 dev_err(bus->dev, "Unexpected ACK on read request.\n");
289 bus->slave_state = ASPEED_I2C_SLAVE_READ_PROCESSED;
290
291 i2c_slave_event(slave, I2C_SLAVE_READ_REQUESTED, &value);
292 writel(value, bus->base + ASPEED_I2C_BYTE_BUF_REG);
293 writel(ASPEED_I2CD_S_TX_CMD, bus->base + ASPEED_I2C_CMD_REG);
294 break;
295 case ASPEED_I2C_SLAVE_READ_PROCESSED:
296 status_ack |= ASPEED_I2CD_INTR_TX_ACK;
297 if (!(irq_status & ASPEED_I2CD_INTR_TX_ACK))
298 dev_err(bus->dev,
299 "Expected ACK after processed read.\n");
300 i2c_slave_event(slave, I2C_SLAVE_READ_PROCESSED, &value);
301 writel(value, bus->base + ASPEED_I2C_BYTE_BUF_REG);
302 writel(ASPEED_I2CD_S_TX_CMD, bus->base + ASPEED_I2C_CMD_REG);
303 break;
304 case ASPEED_I2C_SLAVE_WRITE_REQUESTED:
305 bus->slave_state = ASPEED_I2C_SLAVE_WRITE_RECEIVED;
306 i2c_slave_event(slave, I2C_SLAVE_WRITE_REQUESTED, &value);
307 break;
308 case ASPEED_I2C_SLAVE_WRITE_RECEIVED:
309 i2c_slave_event(slave, I2C_SLAVE_WRITE_RECEIVED, &value);
310 break;
311 case ASPEED_I2C_SLAVE_STOP:
312 i2c_slave_event(slave, I2C_SLAVE_STOP, &value);
313 break;
314 default:
315 dev_err(bus->dev, "unhandled slave_state: %d\n",
316 bus->slave_state);
317 break;
318 }
319
320 if (status_ack != irq_status)
321 dev_err(bus->dev,
322 "irq handled != irq. expected %x, but was %x\n",
323 irq_status, status_ack);
324 writel(status_ack, bus->base + ASPEED_I2C_INTR_STS_REG);
325
326 out:
327 return irq_handled;
328 }
329 #endif /* CONFIG_I2C_SLAVE */
330
331 /* precondition: bus.lock has been acquired. */
aspeed_i2c_do_start(struct aspeed_i2c_bus * bus)332 static void aspeed_i2c_do_start(struct aspeed_i2c_bus *bus)
333 {
334 u32 command = ASPEED_I2CD_M_START_CMD | ASPEED_I2CD_M_TX_CMD;
335 struct i2c_msg *msg = &bus->msgs[bus->msgs_index];
336 u8 slave_addr = i2c_8bit_addr_from_msg(msg);
337
338 bus->master_state = ASPEED_I2C_MASTER_START;
339 bus->buf_index = 0;
340
341 if (msg->flags & I2C_M_RD) {
342 command |= ASPEED_I2CD_M_RX_CMD;
343 /* Need to let the hardware know to NACK after RX. */
344 if (msg->len == 1 && !(msg->flags & I2C_M_RECV_LEN))
345 command |= ASPEED_I2CD_M_S_RX_CMD_LAST;
346 }
347
348 writel(slave_addr, bus->base + ASPEED_I2C_BYTE_BUF_REG);
349 writel(command, bus->base + ASPEED_I2C_CMD_REG);
350 }
351
352 /* precondition: bus.lock has been acquired. */
aspeed_i2c_do_stop(struct aspeed_i2c_bus * bus)353 static void aspeed_i2c_do_stop(struct aspeed_i2c_bus *bus)
354 {
355 bus->master_state = ASPEED_I2C_MASTER_STOP;
356 writel(ASPEED_I2CD_M_STOP_CMD, bus->base + ASPEED_I2C_CMD_REG);
357 }
358
359 /* precondition: bus.lock has been acquired. */
aspeed_i2c_next_msg_or_stop(struct aspeed_i2c_bus * bus)360 static void aspeed_i2c_next_msg_or_stop(struct aspeed_i2c_bus *bus)
361 {
362 if (bus->msgs_index + 1 < bus->msgs_count) {
363 bus->msgs_index++;
364 aspeed_i2c_do_start(bus);
365 } else {
366 aspeed_i2c_do_stop(bus);
367 }
368 }
369
aspeed_i2c_is_irq_error(u32 irq_status)370 static int aspeed_i2c_is_irq_error(u32 irq_status)
371 {
372 if (irq_status & ASPEED_I2CD_INTR_ARBIT_LOSS)
373 return -EAGAIN;
374 if (irq_status & (ASPEED_I2CD_INTR_SDA_DL_TIMEOUT |
375 ASPEED_I2CD_INTR_SCL_TIMEOUT))
376 return -EBUSY;
377 if (irq_status & (ASPEED_I2CD_INTR_ABNORMAL))
378 return -EPROTO;
379
380 return 0;
381 }
382
aspeed_i2c_master_irq(struct aspeed_i2c_bus * bus)383 static bool aspeed_i2c_master_irq(struct aspeed_i2c_bus *bus)
384 {
385 u32 irq_status, status_ack = 0, command = 0;
386 struct i2c_msg *msg;
387 u8 recv_byte;
388 int ret;
389
390 irq_status = readl(bus->base + ASPEED_I2C_INTR_STS_REG);
391 /* Ack all interrupt bits. */
392 writel(irq_status, bus->base + ASPEED_I2C_INTR_STS_REG);
393
394 if (irq_status & ASPEED_I2CD_INTR_BUS_RECOVER_DONE) {
395 bus->master_state = ASPEED_I2C_MASTER_INACTIVE;
396 status_ack |= ASPEED_I2CD_INTR_BUS_RECOVER_DONE;
397 goto out_complete;
398 }
399
400 /*
401 * We encountered an interrupt that reports an error: the hardware
402 * should clear the command queue effectively taking us back to the
403 * INACTIVE state.
404 */
405 ret = aspeed_i2c_is_irq_error(irq_status);
406 if (ret < 0) {
407 dev_dbg(bus->dev, "received error interrupt: 0x%08x\n",
408 irq_status);
409 bus->cmd_err = ret;
410 bus->master_state = ASPEED_I2C_MASTER_INACTIVE;
411 goto out_complete;
412 }
413
414 /* We are in an invalid state; reset bus to a known state. */
415 if (!bus->msgs) {
416 dev_err(bus->dev, "bus in unknown state\n");
417 bus->cmd_err = -EIO;
418 if (bus->master_state != ASPEED_I2C_MASTER_STOP)
419 aspeed_i2c_do_stop(bus);
420 goto out_no_complete;
421 }
422 msg = &bus->msgs[bus->msgs_index];
423
424 /*
425 * START is a special case because we still have to handle a subsequent
426 * TX or RX immediately after we handle it, so we handle it here and
427 * then update the state and handle the new state below.
428 */
429 if (bus->master_state == ASPEED_I2C_MASTER_START) {
430 if (unlikely(!(irq_status & ASPEED_I2CD_INTR_TX_ACK))) {
431 pr_devel("no slave present at %02x\n", msg->addr);
432 status_ack |= ASPEED_I2CD_INTR_TX_NAK;
433 bus->cmd_err = -ENXIO;
434 aspeed_i2c_do_stop(bus);
435 goto out_no_complete;
436 }
437 status_ack |= ASPEED_I2CD_INTR_TX_ACK;
438 if (msg->len == 0) { /* SMBUS_QUICK */
439 aspeed_i2c_do_stop(bus);
440 goto out_no_complete;
441 }
442 if (msg->flags & I2C_M_RD)
443 bus->master_state = ASPEED_I2C_MASTER_RX_FIRST;
444 else
445 bus->master_state = ASPEED_I2C_MASTER_TX_FIRST;
446 }
447
448 switch (bus->master_state) {
449 case ASPEED_I2C_MASTER_TX:
450 if (unlikely(irq_status & ASPEED_I2CD_INTR_TX_NAK)) {
451 dev_dbg(bus->dev, "slave NACKed TX\n");
452 status_ack |= ASPEED_I2CD_INTR_TX_NAK;
453 goto error_and_stop;
454 } else if (unlikely(!(irq_status & ASPEED_I2CD_INTR_TX_ACK))) {
455 dev_err(bus->dev, "slave failed to ACK TX\n");
456 goto error_and_stop;
457 }
458 status_ack |= ASPEED_I2CD_INTR_TX_ACK;
459 /* fallthrough intended */
460 case ASPEED_I2C_MASTER_TX_FIRST:
461 if (bus->buf_index < msg->len) {
462 bus->master_state = ASPEED_I2C_MASTER_TX;
463 writel(msg->buf[bus->buf_index++],
464 bus->base + ASPEED_I2C_BYTE_BUF_REG);
465 writel(ASPEED_I2CD_M_TX_CMD,
466 bus->base + ASPEED_I2C_CMD_REG);
467 } else {
468 aspeed_i2c_next_msg_or_stop(bus);
469 }
470 goto out_no_complete;
471 case ASPEED_I2C_MASTER_RX_FIRST:
472 /* RX may not have completed yet (only address cycle) */
473 if (!(irq_status & ASPEED_I2CD_INTR_RX_DONE))
474 goto out_no_complete;
475 /* fallthrough intended */
476 case ASPEED_I2C_MASTER_RX:
477 if (unlikely(!(irq_status & ASPEED_I2CD_INTR_RX_DONE))) {
478 dev_err(bus->dev, "master failed to RX\n");
479 goto error_and_stop;
480 }
481 status_ack |= ASPEED_I2CD_INTR_RX_DONE;
482
483 recv_byte = readl(bus->base + ASPEED_I2C_BYTE_BUF_REG) >> 8;
484 msg->buf[bus->buf_index++] = recv_byte;
485
486 if (msg->flags & I2C_M_RECV_LEN) {
487 if (unlikely(recv_byte > I2C_SMBUS_BLOCK_MAX)) {
488 bus->cmd_err = -EPROTO;
489 aspeed_i2c_do_stop(bus);
490 goto out_no_complete;
491 }
492 msg->len = recv_byte +
493 ((msg->flags & I2C_CLIENT_PEC) ? 2 : 1);
494 msg->flags &= ~I2C_M_RECV_LEN;
495 }
496
497 if (bus->buf_index < msg->len) {
498 bus->master_state = ASPEED_I2C_MASTER_RX;
499 command = ASPEED_I2CD_M_RX_CMD;
500 if (bus->buf_index + 1 == msg->len)
501 command |= ASPEED_I2CD_M_S_RX_CMD_LAST;
502 writel(command, bus->base + ASPEED_I2C_CMD_REG);
503 } else {
504 aspeed_i2c_next_msg_or_stop(bus);
505 }
506 goto out_no_complete;
507 case ASPEED_I2C_MASTER_STOP:
508 if (unlikely(!(irq_status & ASPEED_I2CD_INTR_NORMAL_STOP))) {
509 dev_err(bus->dev, "master failed to STOP\n");
510 bus->cmd_err = -EIO;
511 /* Do not STOP as we have already tried. */
512 } else {
513 status_ack |= ASPEED_I2CD_INTR_NORMAL_STOP;
514 }
515
516 bus->master_state = ASPEED_I2C_MASTER_INACTIVE;
517 goto out_complete;
518 case ASPEED_I2C_MASTER_INACTIVE:
519 dev_err(bus->dev,
520 "master received interrupt 0x%08x, but is inactive\n",
521 irq_status);
522 bus->cmd_err = -EIO;
523 /* Do not STOP as we should be inactive. */
524 goto out_complete;
525 default:
526 WARN(1, "unknown master state\n");
527 bus->master_state = ASPEED_I2C_MASTER_INACTIVE;
528 bus->cmd_err = -EINVAL;
529 goto out_complete;
530 }
531 error_and_stop:
532 bus->cmd_err = -EIO;
533 aspeed_i2c_do_stop(bus);
534 goto out_no_complete;
535 out_complete:
536 bus->msgs = NULL;
537 if (bus->cmd_err)
538 bus->master_xfer_result = bus->cmd_err;
539 else
540 bus->master_xfer_result = bus->msgs_index + 1;
541 complete(&bus->cmd_complete);
542 out_no_complete:
543 if (irq_status != status_ack)
544 dev_err(bus->dev,
545 "irq handled != irq. expected 0x%08x, but was 0x%08x\n",
546 irq_status, status_ack);
547 return !!irq_status;
548 }
549
aspeed_i2c_bus_irq(int irq,void * dev_id)550 static irqreturn_t aspeed_i2c_bus_irq(int irq, void *dev_id)
551 {
552 struct aspeed_i2c_bus *bus = dev_id;
553 bool ret;
554
555 spin_lock(&bus->lock);
556
557 #if IS_ENABLED(CONFIG_I2C_SLAVE)
558 if (aspeed_i2c_slave_irq(bus)) {
559 dev_dbg(bus->dev, "irq handled by slave.\n");
560 ret = true;
561 goto out;
562 }
563 #endif /* CONFIG_I2C_SLAVE */
564
565 ret = aspeed_i2c_master_irq(bus);
566
567 out:
568 spin_unlock(&bus->lock);
569 return ret ? IRQ_HANDLED : IRQ_NONE;
570 }
571
aspeed_i2c_master_xfer(struct i2c_adapter * adap,struct i2c_msg * msgs,int num)572 static int aspeed_i2c_master_xfer(struct i2c_adapter *adap,
573 struct i2c_msg *msgs, int num)
574 {
575 struct aspeed_i2c_bus *bus = i2c_get_adapdata(adap);
576 unsigned long time_left, flags;
577 int ret = 0;
578
579 spin_lock_irqsave(&bus->lock, flags);
580 bus->cmd_err = 0;
581
582 /* If bus is busy, attempt recovery. We assume a single master
583 * environment.
584 */
585 if (readl(bus->base + ASPEED_I2C_CMD_REG) & ASPEED_I2CD_BUS_BUSY_STS) {
586 spin_unlock_irqrestore(&bus->lock, flags);
587 ret = aspeed_i2c_recover_bus(bus);
588 if (ret)
589 return ret;
590 spin_lock_irqsave(&bus->lock, flags);
591 }
592
593 bus->cmd_err = 0;
594 bus->msgs = msgs;
595 bus->msgs_index = 0;
596 bus->msgs_count = num;
597
598 reinit_completion(&bus->cmd_complete);
599 aspeed_i2c_do_start(bus);
600 spin_unlock_irqrestore(&bus->lock, flags);
601
602 time_left = wait_for_completion_timeout(&bus->cmd_complete,
603 bus->adap.timeout);
604
605 if (time_left == 0)
606 return -ETIMEDOUT;
607 else
608 return bus->master_xfer_result;
609 }
610
aspeed_i2c_functionality(struct i2c_adapter * adap)611 static u32 aspeed_i2c_functionality(struct i2c_adapter *adap)
612 {
613 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_SMBUS_BLOCK_DATA;
614 }
615
616 #if IS_ENABLED(CONFIG_I2C_SLAVE)
617 /* precondition: bus.lock has been acquired. */
__aspeed_i2c_reg_slave(struct aspeed_i2c_bus * bus,u16 slave_addr)618 static void __aspeed_i2c_reg_slave(struct aspeed_i2c_bus *bus, u16 slave_addr)
619 {
620 u32 addr_reg_val, func_ctrl_reg_val;
621
622 /* Set slave addr. */
623 addr_reg_val = readl(bus->base + ASPEED_I2C_DEV_ADDR_REG);
624 addr_reg_val &= ~ASPEED_I2CD_DEV_ADDR_MASK;
625 addr_reg_val |= slave_addr & ASPEED_I2CD_DEV_ADDR_MASK;
626 writel(addr_reg_val, bus->base + ASPEED_I2C_DEV_ADDR_REG);
627
628 /* Turn on slave mode. */
629 func_ctrl_reg_val = readl(bus->base + ASPEED_I2C_FUN_CTRL_REG);
630 func_ctrl_reg_val |= ASPEED_I2CD_SLAVE_EN;
631 writel(func_ctrl_reg_val, bus->base + ASPEED_I2C_FUN_CTRL_REG);
632 }
633
aspeed_i2c_reg_slave(struct i2c_client * client)634 static int aspeed_i2c_reg_slave(struct i2c_client *client)
635 {
636 struct aspeed_i2c_bus *bus = i2c_get_adapdata(client->adapter);
637 unsigned long flags;
638
639 spin_lock_irqsave(&bus->lock, flags);
640 if (bus->slave) {
641 spin_unlock_irqrestore(&bus->lock, flags);
642 return -EINVAL;
643 }
644
645 __aspeed_i2c_reg_slave(bus, client->addr);
646
647 bus->slave = client;
648 bus->slave_state = ASPEED_I2C_SLAVE_STOP;
649 spin_unlock_irqrestore(&bus->lock, flags);
650
651 return 0;
652 }
653
aspeed_i2c_unreg_slave(struct i2c_client * client)654 static int aspeed_i2c_unreg_slave(struct i2c_client *client)
655 {
656 struct aspeed_i2c_bus *bus = i2c_get_adapdata(client->adapter);
657 u32 func_ctrl_reg_val;
658 unsigned long flags;
659
660 spin_lock_irqsave(&bus->lock, flags);
661 if (!bus->slave) {
662 spin_unlock_irqrestore(&bus->lock, flags);
663 return -EINVAL;
664 }
665
666 /* Turn off slave mode. */
667 func_ctrl_reg_val = readl(bus->base + ASPEED_I2C_FUN_CTRL_REG);
668 func_ctrl_reg_val &= ~ASPEED_I2CD_SLAVE_EN;
669 writel(func_ctrl_reg_val, bus->base + ASPEED_I2C_FUN_CTRL_REG);
670
671 bus->slave = NULL;
672 spin_unlock_irqrestore(&bus->lock, flags);
673
674 return 0;
675 }
676 #endif /* CONFIG_I2C_SLAVE */
677
678 static const struct i2c_algorithm aspeed_i2c_algo = {
679 .master_xfer = aspeed_i2c_master_xfer,
680 .functionality = aspeed_i2c_functionality,
681 #if IS_ENABLED(CONFIG_I2C_SLAVE)
682 .reg_slave = aspeed_i2c_reg_slave,
683 .unreg_slave = aspeed_i2c_unreg_slave,
684 #endif /* CONFIG_I2C_SLAVE */
685 };
686
aspeed_i2c_get_clk_reg_val(u32 clk_high_low_max,u32 divisor)687 static u32 aspeed_i2c_get_clk_reg_val(u32 clk_high_low_max, u32 divisor)
688 {
689 u32 base_clk, clk_high, clk_low, tmp;
690
691 /*
692 * The actual clock frequency of SCL is:
693 * SCL_freq = APB_freq / (base_freq * (SCL_high + SCL_low))
694 * = APB_freq / divisor
695 * where base_freq is a programmable clock divider; its value is
696 * base_freq = 1 << base_clk
697 * SCL_high is the number of base_freq clock cycles that SCL stays high
698 * and SCL_low is the number of base_freq clock cycles that SCL stays
699 * low for a period of SCL.
700 * The actual register has a minimum SCL_high and SCL_low minimum of 1;
701 * thus, they start counting at zero. So
702 * SCL_high = clk_high + 1
703 * SCL_low = clk_low + 1
704 * Thus,
705 * SCL_freq = APB_freq /
706 * ((1 << base_clk) * (clk_high + 1 + clk_low + 1))
707 * The documentation recommends clk_high >= clk_high_max / 2 and
708 * clk_low >= clk_low_max / 2 - 1 when possible; this last constraint
709 * gives us the following solution:
710 */
711 base_clk = divisor > clk_high_low_max ?
712 ilog2((divisor - 1) / clk_high_low_max) + 1 : 0;
713 tmp = (divisor + (1 << base_clk) - 1) >> base_clk;
714 clk_low = tmp / 2;
715 clk_high = tmp - clk_low;
716
717 if (clk_high)
718 clk_high--;
719
720 if (clk_low)
721 clk_low--;
722
723
724 return ((clk_high << ASPEED_I2CD_TIME_SCL_HIGH_SHIFT)
725 & ASPEED_I2CD_TIME_SCL_HIGH_MASK)
726 | ((clk_low << ASPEED_I2CD_TIME_SCL_LOW_SHIFT)
727 & ASPEED_I2CD_TIME_SCL_LOW_MASK)
728 | (base_clk & ASPEED_I2CD_TIME_BASE_DIVISOR_MASK);
729 }
730
aspeed_i2c_24xx_get_clk_reg_val(u32 divisor)731 static u32 aspeed_i2c_24xx_get_clk_reg_val(u32 divisor)
732 {
733 /*
734 * clk_high and clk_low are each 3 bits wide, so each can hold a max
735 * value of 8 giving a clk_high_low_max of 16.
736 */
737 return aspeed_i2c_get_clk_reg_val(16, divisor);
738 }
739
aspeed_i2c_25xx_get_clk_reg_val(u32 divisor)740 static u32 aspeed_i2c_25xx_get_clk_reg_val(u32 divisor)
741 {
742 /*
743 * clk_high and clk_low are each 4 bits wide, so each can hold a max
744 * value of 16 giving a clk_high_low_max of 32.
745 */
746 return aspeed_i2c_get_clk_reg_val(32, divisor);
747 }
748
749 /* precondition: bus.lock has been acquired. */
aspeed_i2c_init_clk(struct aspeed_i2c_bus * bus)750 static int aspeed_i2c_init_clk(struct aspeed_i2c_bus *bus)
751 {
752 u32 divisor, clk_reg_val;
753
754 divisor = DIV_ROUND_UP(bus->parent_clk_frequency, bus->bus_frequency);
755 clk_reg_val = readl(bus->base + ASPEED_I2C_AC_TIMING_REG1);
756 clk_reg_val &= (ASPEED_I2CD_TIME_TBUF_MASK |
757 ASPEED_I2CD_TIME_THDSTA_MASK |
758 ASPEED_I2CD_TIME_TACST_MASK);
759 clk_reg_val |= bus->get_clk_reg_val(divisor);
760 writel(clk_reg_val, bus->base + ASPEED_I2C_AC_TIMING_REG1);
761 writel(ASPEED_NO_TIMEOUT_CTRL, bus->base + ASPEED_I2C_AC_TIMING_REG2);
762
763 return 0;
764 }
765
766 /* precondition: bus.lock has been acquired. */
aspeed_i2c_init(struct aspeed_i2c_bus * bus,struct platform_device * pdev)767 static int aspeed_i2c_init(struct aspeed_i2c_bus *bus,
768 struct platform_device *pdev)
769 {
770 u32 fun_ctrl_reg = ASPEED_I2CD_MASTER_EN;
771 int ret;
772
773 /* Disable everything. */
774 writel(0, bus->base + ASPEED_I2C_FUN_CTRL_REG);
775
776 ret = aspeed_i2c_init_clk(bus);
777 if (ret < 0)
778 return ret;
779
780 if (!of_property_read_bool(pdev->dev.of_node, "multi-master"))
781 fun_ctrl_reg |= ASPEED_I2CD_MULTI_MASTER_DIS;
782
783 /* Enable Master Mode */
784 writel(readl(bus->base + ASPEED_I2C_FUN_CTRL_REG) | fun_ctrl_reg,
785 bus->base + ASPEED_I2C_FUN_CTRL_REG);
786
787 #if IS_ENABLED(CONFIG_I2C_SLAVE)
788 /* If slave has already been registered, re-enable it. */
789 if (bus->slave)
790 __aspeed_i2c_reg_slave(bus, bus->slave->addr);
791 #endif /* CONFIG_I2C_SLAVE */
792
793 /* Set interrupt generation of I2C controller */
794 writel(ASPEED_I2CD_INTR_ALL, bus->base + ASPEED_I2C_INTR_CTRL_REG);
795
796 return 0;
797 }
798
aspeed_i2c_reset(struct aspeed_i2c_bus * bus)799 static int aspeed_i2c_reset(struct aspeed_i2c_bus *bus)
800 {
801 struct platform_device *pdev = to_platform_device(bus->dev);
802 unsigned long flags;
803 int ret;
804
805 spin_lock_irqsave(&bus->lock, flags);
806
807 /* Disable and ack all interrupts. */
808 writel(0, bus->base + ASPEED_I2C_INTR_CTRL_REG);
809 writel(0xffffffff, bus->base + ASPEED_I2C_INTR_STS_REG);
810
811 ret = aspeed_i2c_init(bus, pdev);
812
813 spin_unlock_irqrestore(&bus->lock, flags);
814
815 return ret;
816 }
817
818 static const struct of_device_id aspeed_i2c_bus_of_table[] = {
819 {
820 .compatible = "aspeed,ast2400-i2c-bus",
821 .data = aspeed_i2c_24xx_get_clk_reg_val,
822 },
823 {
824 .compatible = "aspeed,ast2500-i2c-bus",
825 .data = aspeed_i2c_25xx_get_clk_reg_val,
826 },
827 { },
828 };
829 MODULE_DEVICE_TABLE(of, aspeed_i2c_bus_of_table);
830
aspeed_i2c_probe_bus(struct platform_device * pdev)831 static int aspeed_i2c_probe_bus(struct platform_device *pdev)
832 {
833 const struct of_device_id *match;
834 struct aspeed_i2c_bus *bus;
835 struct clk *parent_clk;
836 struct resource *res;
837 int irq, ret;
838
839 bus = devm_kzalloc(&pdev->dev, sizeof(*bus), GFP_KERNEL);
840 if (!bus)
841 return -ENOMEM;
842
843 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
844 bus->base = devm_ioremap_resource(&pdev->dev, res);
845 if (IS_ERR(bus->base))
846 return PTR_ERR(bus->base);
847
848 parent_clk = devm_clk_get(&pdev->dev, NULL);
849 if (IS_ERR(parent_clk))
850 return PTR_ERR(parent_clk);
851 bus->parent_clk_frequency = clk_get_rate(parent_clk);
852 /* We just need the clock rate, we don't actually use the clk object. */
853 devm_clk_put(&pdev->dev, parent_clk);
854
855 bus->rst = devm_reset_control_get_shared(&pdev->dev, NULL);
856 if (IS_ERR(bus->rst)) {
857 dev_err(&pdev->dev,
858 "missing or invalid reset controller device tree entry\n");
859 return PTR_ERR(bus->rst);
860 }
861 reset_control_deassert(bus->rst);
862
863 ret = of_property_read_u32(pdev->dev.of_node,
864 "bus-frequency", &bus->bus_frequency);
865 if (ret < 0) {
866 dev_err(&pdev->dev,
867 "Could not read bus-frequency property\n");
868 bus->bus_frequency = 100000;
869 }
870
871 match = of_match_node(aspeed_i2c_bus_of_table, pdev->dev.of_node);
872 if (!match)
873 bus->get_clk_reg_val = aspeed_i2c_24xx_get_clk_reg_val;
874 else
875 bus->get_clk_reg_val = (u32 (*)(u32))match->data;
876
877 /* Initialize the I2C adapter */
878 spin_lock_init(&bus->lock);
879 init_completion(&bus->cmd_complete);
880 bus->adap.owner = THIS_MODULE;
881 bus->adap.retries = 0;
882 bus->adap.timeout = 5 * HZ;
883 bus->adap.algo = &aspeed_i2c_algo;
884 bus->adap.dev.parent = &pdev->dev;
885 bus->adap.dev.of_node = pdev->dev.of_node;
886 strlcpy(bus->adap.name, pdev->name, sizeof(bus->adap.name));
887 i2c_set_adapdata(&bus->adap, bus);
888
889 bus->dev = &pdev->dev;
890
891 /* Clean up any left over interrupt state. */
892 writel(0, bus->base + ASPEED_I2C_INTR_CTRL_REG);
893 writel(0xffffffff, bus->base + ASPEED_I2C_INTR_STS_REG);
894 /*
895 * bus.lock does not need to be held because the interrupt handler has
896 * not been enabled yet.
897 */
898 ret = aspeed_i2c_init(bus, pdev);
899 if (ret < 0)
900 return ret;
901
902 irq = irq_of_parse_and_map(pdev->dev.of_node, 0);
903 ret = devm_request_irq(&pdev->dev, irq, aspeed_i2c_bus_irq,
904 0, dev_name(&pdev->dev), bus);
905 if (ret < 0)
906 return ret;
907
908 ret = i2c_add_adapter(&bus->adap);
909 if (ret < 0)
910 return ret;
911
912 platform_set_drvdata(pdev, bus);
913
914 dev_info(bus->dev, "i2c bus %d registered, irq %d\n",
915 bus->adap.nr, irq);
916
917 return 0;
918 }
919
aspeed_i2c_remove_bus(struct platform_device * pdev)920 static int aspeed_i2c_remove_bus(struct platform_device *pdev)
921 {
922 struct aspeed_i2c_bus *bus = platform_get_drvdata(pdev);
923 unsigned long flags;
924
925 spin_lock_irqsave(&bus->lock, flags);
926
927 /* Disable everything. */
928 writel(0, bus->base + ASPEED_I2C_FUN_CTRL_REG);
929 writel(0, bus->base + ASPEED_I2C_INTR_CTRL_REG);
930
931 spin_unlock_irqrestore(&bus->lock, flags);
932
933 reset_control_assert(bus->rst);
934
935 i2c_del_adapter(&bus->adap);
936
937 return 0;
938 }
939
940 static struct platform_driver aspeed_i2c_bus_driver = {
941 .probe = aspeed_i2c_probe_bus,
942 .remove = aspeed_i2c_remove_bus,
943 .driver = {
944 .name = "aspeed-i2c-bus",
945 .of_match_table = aspeed_i2c_bus_of_table,
946 },
947 };
948 module_platform_driver(aspeed_i2c_bus_driver);
949
950 MODULE_AUTHOR("Brendan Higgins <brendanhiggins@google.com>");
951 MODULE_DESCRIPTION("Aspeed I2C Bus Driver");
952 MODULE_LICENSE("GPL v2");
953
