1 /*
2 * k10temp.c - AMD Family 10h/11h/12h/14h/15h/16h processor hardware monitoring
3 *
4 * Copyright (c) 2009 Clemens Ladisch <clemens@ladisch.de>
5 *
6 *
7 * This driver is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This driver is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
14 * See the GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this driver; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include <linux/err.h>
21 #include <linux/hwmon.h>
22 #include <linux/hwmon-sysfs.h>
23 #include <linux/init.h>
24 #include <linux/module.h>
25 #include <linux/pci.h>
26 #include <asm/amd_nb.h>
27 #include <asm/processor.h>
28
29 MODULE_DESCRIPTION("AMD Family 10h+ CPU core temperature monitor");
30 MODULE_AUTHOR("Clemens Ladisch <clemens@ladisch.de>");
31 MODULE_LICENSE("GPL");
32
33 static bool force;
34 module_param(force, bool, 0444);
35 MODULE_PARM_DESC(force, "force loading on processors with erratum 319");
36
37 /* Provide lock for writing to NB_SMU_IND_ADDR */
38 static DEFINE_MUTEX(nb_smu_ind_mutex);
39
40 #ifndef PCI_DEVICE_ID_AMD_15H_M70H_NB_F3
41 #define PCI_DEVICE_ID_AMD_15H_M70H_NB_F3 0x15b3
42 #endif
43
44 #ifndef PCI_DEVICE_ID_AMD_17H_DF_F3
45 #define PCI_DEVICE_ID_AMD_17H_DF_F3 0x1463
46 #endif
47
48 #ifndef PCI_DEVICE_ID_AMD_17H_M10H_DF_F3
49 #define PCI_DEVICE_ID_AMD_17H_M10H_DF_F3 0x15eb
50 #endif
51
52 /* CPUID function 0x80000001, ebx */
53 #define CPUID_PKGTYPE_MASK 0xf0000000
54 #define CPUID_PKGTYPE_F 0x00000000
55 #define CPUID_PKGTYPE_AM2R2_AM3 0x10000000
56
57 /* DRAM controller (PCI function 2) */
58 #define REG_DCT0_CONFIG_HIGH 0x094
59 #define DDR3_MODE 0x00000100
60
61 /* miscellaneous (PCI function 3) */
62 #define REG_HARDWARE_THERMAL_CONTROL 0x64
63 #define HTC_ENABLE 0x00000001
64
65 #define REG_REPORTED_TEMPERATURE 0xa4
66
67 #define REG_NORTHBRIDGE_CAPABILITIES 0xe8
68 #define NB_CAP_HTC 0x00000400
69
70 /*
71 * For F15h M60h and M70h, REG_HARDWARE_THERMAL_CONTROL
72 * and REG_REPORTED_TEMPERATURE have been moved to
73 * D0F0xBC_xD820_0C64 [Hardware Temperature Control]
74 * D0F0xBC_xD820_0CA4 [Reported Temperature Control]
75 */
76 #define F15H_M60H_HARDWARE_TEMP_CTRL_OFFSET 0xd8200c64
77 #define F15H_M60H_REPORTED_TEMP_CTRL_OFFSET 0xd8200ca4
78
79 /* F17h M01h Access througn SMN */
80 #define F17H_M01H_REPORTED_TEMP_CTRL_OFFSET 0x00059800
81
82 struct k10temp_data {
83 struct pci_dev *pdev;
84 void (*read_htcreg)(struct pci_dev *pdev, u32 *regval);
85 void (*read_tempreg)(struct pci_dev *pdev, u32 *regval);
86 int temp_offset;
87 u32 temp_adjust_mask;
88 bool show_tdie;
89 };
90
91 struct tctl_offset {
92 u8 model;
93 char const *id;
94 int offset;
95 };
96
97 static const struct tctl_offset tctl_offset_table[] = {
98 { 0x17, "AMD Ryzen 5 1600X", 20000 },
99 { 0x17, "AMD Ryzen 7 1700X", 20000 },
100 { 0x17, "AMD Ryzen 7 1800X", 20000 },
101 { 0x17, "AMD Ryzen 7 2700X", 10000 },
102 { 0x17, "AMD Ryzen Threadripper 19", 27000 }, /* 19{00,20,50}X */
103 { 0x17, "AMD Ryzen Threadripper 29", 27000 }, /* 29{20,50,70,90}[W]X */
104 };
105
read_htcreg_pci(struct pci_dev * pdev,u32 * regval)106 static void read_htcreg_pci(struct pci_dev *pdev, u32 *regval)
107 {
108 pci_read_config_dword(pdev, REG_HARDWARE_THERMAL_CONTROL, regval);
109 }
110
read_tempreg_pci(struct pci_dev * pdev,u32 * regval)111 static void read_tempreg_pci(struct pci_dev *pdev, u32 *regval)
112 {
113 pci_read_config_dword(pdev, REG_REPORTED_TEMPERATURE, regval);
114 }
115
amd_nb_index_read(struct pci_dev * pdev,unsigned int devfn,unsigned int base,int offset,u32 * val)116 static void amd_nb_index_read(struct pci_dev *pdev, unsigned int devfn,
117 unsigned int base, int offset, u32 *val)
118 {
119 mutex_lock(&nb_smu_ind_mutex);
120 pci_bus_write_config_dword(pdev->bus, devfn,
121 base, offset);
122 pci_bus_read_config_dword(pdev->bus, devfn,
123 base + 4, val);
124 mutex_unlock(&nb_smu_ind_mutex);
125 }
126
read_htcreg_nb_f15(struct pci_dev * pdev,u32 * regval)127 static void read_htcreg_nb_f15(struct pci_dev *pdev, u32 *regval)
128 {
129 amd_nb_index_read(pdev, PCI_DEVFN(0, 0), 0xb8,
130 F15H_M60H_HARDWARE_TEMP_CTRL_OFFSET, regval);
131 }
132
read_tempreg_nb_f15(struct pci_dev * pdev,u32 * regval)133 static void read_tempreg_nb_f15(struct pci_dev *pdev, u32 *regval)
134 {
135 amd_nb_index_read(pdev, PCI_DEVFN(0, 0), 0xb8,
136 F15H_M60H_REPORTED_TEMP_CTRL_OFFSET, regval);
137 }
138
read_tempreg_nb_f17(struct pci_dev * pdev,u32 * regval)139 static void read_tempreg_nb_f17(struct pci_dev *pdev, u32 *regval)
140 {
141 amd_smn_read(amd_pci_dev_to_node_id(pdev),
142 F17H_M01H_REPORTED_TEMP_CTRL_OFFSET, regval);
143 }
144
get_raw_temp(struct k10temp_data * data)145 static unsigned int get_raw_temp(struct k10temp_data *data)
146 {
147 unsigned int temp;
148 u32 regval;
149
150 data->read_tempreg(data->pdev, ®val);
151 temp = (regval >> 21) * 125;
152 if (regval & data->temp_adjust_mask)
153 temp -= 49000;
154 return temp;
155 }
156
temp1_input_show(struct device * dev,struct device_attribute * attr,char * buf)157 static ssize_t temp1_input_show(struct device *dev,
158 struct device_attribute *attr, char *buf)
159 {
160 struct k10temp_data *data = dev_get_drvdata(dev);
161 unsigned int temp = get_raw_temp(data);
162
163 if (temp > data->temp_offset)
164 temp -= data->temp_offset;
165 else
166 temp = 0;
167
168 return sprintf(buf, "%u\n", temp);
169 }
170
temp2_input_show(struct device * dev,struct device_attribute * devattr,char * buf)171 static ssize_t temp2_input_show(struct device *dev,
172 struct device_attribute *devattr, char *buf)
173 {
174 struct k10temp_data *data = dev_get_drvdata(dev);
175 unsigned int temp = get_raw_temp(data);
176
177 return sprintf(buf, "%u\n", temp);
178 }
179
temp_label_show(struct device * dev,struct device_attribute * devattr,char * buf)180 static ssize_t temp_label_show(struct device *dev,
181 struct device_attribute *devattr, char *buf)
182 {
183 struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
184
185 return sprintf(buf, "%s\n", attr->index ? "Tctl" : "Tdie");
186 }
187
temp1_max_show(struct device * dev,struct device_attribute * attr,char * buf)188 static ssize_t temp1_max_show(struct device *dev,
189 struct device_attribute *attr, char *buf)
190 {
191 return sprintf(buf, "%d\n", 70 * 1000);
192 }
193
show_temp_crit(struct device * dev,struct device_attribute * devattr,char * buf)194 static ssize_t show_temp_crit(struct device *dev,
195 struct device_attribute *devattr, char *buf)
196 {
197 struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
198 struct k10temp_data *data = dev_get_drvdata(dev);
199 int show_hyst = attr->index;
200 u32 regval;
201 int value;
202
203 data->read_htcreg(data->pdev, ®val);
204 value = ((regval >> 16) & 0x7f) * 500 + 52000;
205 if (show_hyst)
206 value -= ((regval >> 24) & 0xf) * 500;
207 return sprintf(buf, "%d\n", value);
208 }
209
210 static DEVICE_ATTR_RO(temp1_input);
211 static DEVICE_ATTR_RO(temp1_max);
212 static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, show_temp_crit, NULL, 0);
213 static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, show_temp_crit, NULL, 1);
214
215 static SENSOR_DEVICE_ATTR(temp1_label, 0444, temp_label_show, NULL, 0);
216 static DEVICE_ATTR_RO(temp2_input);
217 static SENSOR_DEVICE_ATTR(temp2_label, 0444, temp_label_show, NULL, 1);
218
k10temp_is_visible(struct kobject * kobj,struct attribute * attr,int index)219 static umode_t k10temp_is_visible(struct kobject *kobj,
220 struct attribute *attr, int index)
221 {
222 struct device *dev = container_of(kobj, struct device, kobj);
223 struct k10temp_data *data = dev_get_drvdata(dev);
224 struct pci_dev *pdev = data->pdev;
225 u32 reg;
226
227 switch (index) {
228 case 0 ... 1: /* temp1_input, temp1_max */
229 default:
230 break;
231 case 2 ... 3: /* temp1_crit, temp1_crit_hyst */
232 if (!data->read_htcreg)
233 return 0;
234
235 pci_read_config_dword(pdev, REG_NORTHBRIDGE_CAPABILITIES,
236 ®);
237 if (!(reg & NB_CAP_HTC))
238 return 0;
239
240 data->read_htcreg(data->pdev, ®);
241 if (!(reg & HTC_ENABLE))
242 return 0;
243 break;
244 case 4 ... 6: /* temp1_label, temp2_input, temp2_label */
245 if (!data->show_tdie)
246 return 0;
247 break;
248 }
249 return attr->mode;
250 }
251
252 static struct attribute *k10temp_attrs[] = {
253 &dev_attr_temp1_input.attr,
254 &dev_attr_temp1_max.attr,
255 &sensor_dev_attr_temp1_crit.dev_attr.attr,
256 &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr,
257 &sensor_dev_attr_temp1_label.dev_attr.attr,
258 &dev_attr_temp2_input.attr,
259 &sensor_dev_attr_temp2_label.dev_attr.attr,
260 NULL
261 };
262
263 static const struct attribute_group k10temp_group = {
264 .attrs = k10temp_attrs,
265 .is_visible = k10temp_is_visible,
266 };
267 __ATTRIBUTE_GROUPS(k10temp);
268
has_erratum_319(struct pci_dev * pdev)269 static bool has_erratum_319(struct pci_dev *pdev)
270 {
271 u32 pkg_type, reg_dram_cfg;
272
273 if (boot_cpu_data.x86 != 0x10)
274 return false;
275
276 /*
277 * Erratum 319: The thermal sensor of Socket F/AM2+ processors
278 * may be unreliable.
279 */
280 pkg_type = cpuid_ebx(0x80000001) & CPUID_PKGTYPE_MASK;
281 if (pkg_type == CPUID_PKGTYPE_F)
282 return true;
283 if (pkg_type != CPUID_PKGTYPE_AM2R2_AM3)
284 return false;
285
286 /* DDR3 memory implies socket AM3, which is good */
287 pci_bus_read_config_dword(pdev->bus,
288 PCI_DEVFN(PCI_SLOT(pdev->devfn), 2),
289 REG_DCT0_CONFIG_HIGH, ®_dram_cfg);
290 if (reg_dram_cfg & DDR3_MODE)
291 return false;
292
293 /*
294 * Unfortunately it is possible to run a socket AM3 CPU with DDR2
295 * memory. We blacklist all the cores which do exist in socket AM2+
296 * format. It still isn't perfect, as RB-C2 cores exist in both AM2+
297 * and AM3 formats, but that's the best we can do.
298 */
299 return boot_cpu_data.x86_model < 4 ||
300 (boot_cpu_data.x86_model == 4 && boot_cpu_data.x86_stepping <= 2);
301 }
302
k10temp_probe(struct pci_dev * pdev,const struct pci_device_id * id)303 static int k10temp_probe(struct pci_dev *pdev,
304 const struct pci_device_id *id)
305 {
306 int unreliable = has_erratum_319(pdev);
307 struct device *dev = &pdev->dev;
308 struct k10temp_data *data;
309 struct device *hwmon_dev;
310 int i;
311
312 if (unreliable) {
313 if (!force) {
314 dev_err(dev,
315 "unreliable CPU thermal sensor; monitoring disabled\n");
316 return -ENODEV;
317 }
318 dev_warn(dev,
319 "unreliable CPU thermal sensor; check erratum 319\n");
320 }
321
322 data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
323 if (!data)
324 return -ENOMEM;
325
326 data->pdev = pdev;
327
328 if (boot_cpu_data.x86 == 0x15 && (boot_cpu_data.x86_model == 0x60 ||
329 boot_cpu_data.x86_model == 0x70)) {
330 data->read_htcreg = read_htcreg_nb_f15;
331 data->read_tempreg = read_tempreg_nb_f15;
332 } else if (boot_cpu_data.x86 == 0x17) {
333 data->temp_adjust_mask = 0x80000;
334 data->read_tempreg = read_tempreg_nb_f17;
335 data->show_tdie = true;
336 } else {
337 data->read_htcreg = read_htcreg_pci;
338 data->read_tempreg = read_tempreg_pci;
339 }
340
341 for (i = 0; i < ARRAY_SIZE(tctl_offset_table); i++) {
342 const struct tctl_offset *entry = &tctl_offset_table[i];
343
344 if (boot_cpu_data.x86 == entry->model &&
345 strstr(boot_cpu_data.x86_model_id, entry->id)) {
346 data->temp_offset = entry->offset;
347 break;
348 }
349 }
350
351 hwmon_dev = devm_hwmon_device_register_with_groups(dev, "k10temp", data,
352 k10temp_groups);
353 return PTR_ERR_OR_ZERO(hwmon_dev);
354 }
355
356 static const struct pci_device_id k10temp_id_table[] = {
357 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_10H_NB_MISC) },
358 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_11H_NB_MISC) },
359 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_CNB17H_F3) },
360 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_NB_F3) },
361 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M10H_F3) },
362 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M30H_NB_F3) },
363 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M60H_NB_F3) },
364 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M70H_NB_F3) },
365 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_NB_F3) },
366 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_M30H_NB_F3) },
367 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_DF_F3) },
368 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_M10H_DF_F3) },
369 {}
370 };
371 MODULE_DEVICE_TABLE(pci, k10temp_id_table);
372
373 static struct pci_driver k10temp_driver = {
374 .name = "k10temp",
375 .id_table = k10temp_id_table,
376 .probe = k10temp_probe,
377 };
378
379 module_pci_driver(k10temp_driver);
380
