1 /* 2 * Copyright © 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 */ 23 #ifndef _INTEL_GUC_FWIF_H 24 #define _INTEL_GUC_FWIF_H 25 26 #define GUC_CLIENT_PRIORITY_KMD_HIGH 0 27 #define GUC_CLIENT_PRIORITY_HIGH 1 28 #define GUC_CLIENT_PRIORITY_KMD_NORMAL 2 29 #define GUC_CLIENT_PRIORITY_NORMAL 3 30 #define GUC_CLIENT_PRIORITY_NUM 4 31 32 #define GUC_MAX_STAGE_DESCRIPTORS 1024 33 #define GUC_INVALID_STAGE_ID GUC_MAX_STAGE_DESCRIPTORS 34 35 #define GUC_RENDER_ENGINE 0 36 #define GUC_VIDEO_ENGINE 1 37 #define GUC_BLITTER_ENGINE 2 38 #define GUC_VIDEOENHANCE_ENGINE 3 39 #define GUC_VIDEO_ENGINE2 4 40 #define GUC_MAX_ENGINES_NUM (GUC_VIDEO_ENGINE2 + 1) 41 42 /* Work queue item header definitions */ 43 #define WQ_STATUS_ACTIVE 1 44 #define WQ_STATUS_SUSPENDED 2 45 #define WQ_STATUS_CMD_ERROR 3 46 #define WQ_STATUS_ENGINE_ID_NOT_USED 4 47 #define WQ_STATUS_SUSPENDED_FROM_RESET 5 48 #define WQ_TYPE_SHIFT 0 49 #define WQ_TYPE_BATCH_BUF (0x1 << WQ_TYPE_SHIFT) 50 #define WQ_TYPE_PSEUDO (0x2 << WQ_TYPE_SHIFT) 51 #define WQ_TYPE_INORDER (0x3 << WQ_TYPE_SHIFT) 52 #define WQ_TARGET_SHIFT 10 53 #define WQ_LEN_SHIFT 16 54 #define WQ_NO_WCFLUSH_WAIT (1 << 27) 55 #define WQ_PRESENT_WORKLOAD (1 << 28) 56 57 #define WQ_RING_TAIL_SHIFT 20 58 #define WQ_RING_TAIL_MAX 0x7FF /* 2^11 QWords */ 59 #define WQ_RING_TAIL_MASK (WQ_RING_TAIL_MAX << WQ_RING_TAIL_SHIFT) 60 61 #define GUC_DOORBELL_ENABLED 1 62 #define GUC_DOORBELL_DISABLED 0 63 64 #define GUC_STAGE_DESC_ATTR_ACTIVE BIT(0) 65 #define GUC_STAGE_DESC_ATTR_PENDING_DB BIT(1) 66 #define GUC_STAGE_DESC_ATTR_KERNEL BIT(2) 67 #define GUC_STAGE_DESC_ATTR_PREEMPT BIT(3) 68 #define GUC_STAGE_DESC_ATTR_RESET BIT(4) 69 #define GUC_STAGE_DESC_ATTR_WQLOCKED BIT(5) 70 #define GUC_STAGE_DESC_ATTR_PCH BIT(6) 71 #define GUC_STAGE_DESC_ATTR_TERMINATED BIT(7) 72 73 /* The guc control data is 10 DWORDs */ 74 #define GUC_CTL_CTXINFO 0 75 #define GUC_CTL_CTXNUM_IN16_SHIFT 0 76 #define GUC_CTL_BASE_ADDR_SHIFT 12 77 78 #define GUC_CTL_ARAT_HIGH 1 79 #define GUC_CTL_ARAT_LOW 2 80 81 #define GUC_CTL_DEVICE_INFO 3 82 83 #define GUC_CTL_LOG_PARAMS 4 84 #define GUC_LOG_VALID (1 << 0) 85 #define GUC_LOG_NOTIFY_ON_HALF_FULL (1 << 1) 86 #define GUC_LOG_ALLOC_IN_MEGABYTE (1 << 3) 87 #define GUC_LOG_CRASH_SHIFT 4 88 #define GUC_LOG_CRASH_MASK (0x1 << GUC_LOG_CRASH_SHIFT) 89 #define GUC_LOG_DPC_SHIFT 6 90 #define GUC_LOG_DPC_MASK (0x7 << GUC_LOG_DPC_SHIFT) 91 #define GUC_LOG_ISR_SHIFT 9 92 #define GUC_LOG_ISR_MASK (0x7 << GUC_LOG_ISR_SHIFT) 93 #define GUC_LOG_BUF_ADDR_SHIFT 12 94 95 #define GUC_CTL_PAGE_FAULT_CONTROL 5 96 97 #define GUC_CTL_WA 6 98 #define GUC_CTL_WA_UK_BY_DRIVER (1 << 3) 99 100 #define GUC_CTL_FEATURE 7 101 #define GUC_CTL_VCS2_ENABLED (1 << 0) 102 #define GUC_CTL_KERNEL_SUBMISSIONS (1 << 1) 103 #define GUC_CTL_FEATURE2 (1 << 2) 104 #define GUC_CTL_POWER_GATING (1 << 3) 105 #define GUC_CTL_DISABLE_SCHEDULER (1 << 4) 106 #define GUC_CTL_PREEMPTION_LOG (1 << 5) 107 #define GUC_CTL_ENABLE_SLPC (1 << 7) 108 #define GUC_CTL_RESET_ON_PREMPT_FAILURE (1 << 8) 109 110 #define GUC_CTL_DEBUG 8 111 #define GUC_LOG_VERBOSITY_SHIFT 0 112 #define GUC_LOG_VERBOSITY_LOW (0 << GUC_LOG_VERBOSITY_SHIFT) 113 #define GUC_LOG_VERBOSITY_MED (1 << GUC_LOG_VERBOSITY_SHIFT) 114 #define GUC_LOG_VERBOSITY_HIGH (2 << GUC_LOG_VERBOSITY_SHIFT) 115 #define GUC_LOG_VERBOSITY_ULTRA (3 << GUC_LOG_VERBOSITY_SHIFT) 116 /* Verbosity range-check limits, without the shift */ 117 #define GUC_LOG_VERBOSITY_MIN 0 118 #define GUC_LOG_VERBOSITY_MAX 3 119 #define GUC_LOG_VERBOSITY_MASK 0x0000000f 120 #define GUC_LOG_DESTINATION_MASK (3 << 4) 121 #define GUC_LOG_DISABLED (1 << 6) 122 #define GUC_PROFILE_ENABLED (1 << 7) 123 #define GUC_WQ_TRACK_ENABLED (1 << 8) 124 #define GUC_ADS_ENABLED (1 << 9) 125 #define GUC_LOG_DEFAULT_DISABLED (1 << 10) 126 #define GUC_ADS_ADDR_SHIFT 11 127 #define GUC_ADS_ADDR_MASK 0xfffff800 128 129 #define GUC_CTL_RSRVD 9 130 131 #define GUC_CTL_MAX_DWORDS (SOFT_SCRATCH_COUNT - 2) /* [1..14] */ 132 133 /** 134 * DOC: GuC Firmware Layout 135 * 136 * The GuC firmware layout looks like this: 137 * 138 * +-------------------------------+ 139 * | uc_css_header | 140 * | | 141 * | contains major/minor version | 142 * +-------------------------------+ 143 * | uCode | 144 * +-------------------------------+ 145 * | RSA signature | 146 * +-------------------------------+ 147 * | modulus key | 148 * +-------------------------------+ 149 * | exponent val | 150 * +-------------------------------+ 151 * 152 * The firmware may or may not have modulus key and exponent data. The header, 153 * uCode and RSA signature are must-have components that will be used by driver. 154 * Length of each components, which is all in dwords, can be found in header. 155 * In the case that modulus and exponent are not present in fw, a.k.a truncated 156 * image, the length value still appears in header. 157 * 158 * Driver will do some basic fw size validation based on the following rules: 159 * 160 * 1. Header, uCode and RSA are must-have components. 161 * 2. All firmware components, if they present, are in the sequence illustrated 162 * in the layout table above. 163 * 3. Length info of each component can be found in header, in dwords. 164 * 4. Modulus and exponent key are not required by driver. They may not appear 165 * in fw. So driver will load a truncated firmware in this case. 166 * 167 * HuC firmware layout is same as GuC firmware. 168 * 169 * HuC firmware css header is different. However, the only difference is where 170 * the version information is saved. The uc_css_header is unified to support 171 * both. Driver should get HuC version from uc_css_header.huc_sw_version, while 172 * uc_css_header.guc_sw_version for GuC. 173 */ 174 175 struct uc_css_header { 176 u32 module_type; 177 /* header_size includes all non-uCode bits, including css_header, rsa 178 * key, modulus key and exponent data. */ 179 u32 header_size_dw; 180 u32 header_version; 181 u32 module_id; 182 u32 module_vendor; 183 union { 184 struct { 185 u8 day; 186 u8 month; 187 u16 year; 188 }; 189 u32 date; 190 }; 191 u32 size_dw; /* uCode plus header_size_dw */ 192 u32 key_size_dw; 193 u32 modulus_size_dw; 194 u32 exponent_size_dw; 195 union { 196 struct { 197 u8 hour; 198 u8 min; 199 u16 sec; 200 }; 201 u32 time; 202 }; 203 204 char username[8]; 205 char buildnumber[12]; 206 union { 207 struct { 208 u32 branch_client_version; 209 u32 sw_version; 210 } guc; 211 struct { 212 u32 sw_version; 213 u32 reserved; 214 } huc; 215 }; 216 u32 prod_preprod_fw; 217 u32 reserved[12]; 218 u32 header_info; 219 } __packed; 220 221 struct guc_doorbell_info { 222 u32 db_status; 223 u32 cookie; 224 u32 reserved[14]; 225 } __packed; 226 227 union guc_doorbell_qw { 228 struct { 229 u32 db_status; 230 u32 cookie; 231 }; 232 u64 value_qw; 233 } __packed; 234 235 #define GUC_NUM_DOORBELLS 256 236 #define GUC_DOORBELL_INVALID (GUC_NUM_DOORBELLS) 237 238 #define GUC_DB_SIZE (PAGE_SIZE) 239 #define GUC_WQ_SIZE (PAGE_SIZE * 2) 240 241 /* Work item for submitting workloads into work queue of GuC. */ 242 struct guc_wq_item { 243 u32 header; 244 u32 context_desc; 245 u32 submit_element_info; 246 u32 fence_id; 247 } __packed; 248 249 struct guc_process_desc { 250 u32 stage_id; 251 u64 db_base_addr; 252 u32 head; 253 u32 tail; 254 u32 error_offset; 255 u64 wq_base_addr; 256 u32 wq_size_bytes; 257 u32 wq_status; 258 u32 engine_presence; 259 u32 priority; 260 u32 reserved[30]; 261 } __packed; 262 263 /* engine id and context id is packed into guc_execlist_context.context_id*/ 264 #define GUC_ELC_CTXID_OFFSET 0 265 #define GUC_ELC_ENGINE_OFFSET 29 266 267 /* The execlist context including software and HW information */ 268 struct guc_execlist_context { 269 u32 context_desc; 270 u32 context_id; 271 u32 ring_status; 272 u32 ring_lrca; 273 u32 ring_begin; 274 u32 ring_end; 275 u32 ring_next_free_location; 276 u32 ring_current_tail_pointer_value; 277 u8 engine_state_submit_value; 278 u8 engine_state_wait_value; 279 u16 pagefault_count; 280 u16 engine_submit_queue_count; 281 } __packed; 282 283 /* 284 * This structure describes a stage set arranged for a particular communication 285 * between uKernel (GuC) and Driver (KMD). Technically, this is known as a 286 * "GuC Context descriptor" in the specs, but we use the term "stage descriptor" 287 * to avoid confusion with all the other things already named "context" in the 288 * driver. A static pool of these descriptors are stored inside a GEM object 289 * (stage_desc_pool) which is held for the entire lifetime of our interaction 290 * with the GuC, being allocated before the GuC is loaded with its firmware. 291 */ 292 struct guc_stage_desc { 293 u32 sched_common_area; 294 u32 stage_id; 295 u32 pas_id; 296 u8 engines_used; 297 u64 db_trigger_cpu; 298 u32 db_trigger_uk; 299 u64 db_trigger_phy; 300 u16 db_id; 301 302 struct guc_execlist_context lrc[GUC_MAX_ENGINES_NUM]; 303 304 u8 attribute; 305 306 u32 priority; 307 308 u32 wq_sampled_tail_offset; 309 u32 wq_total_submit_enqueues; 310 311 u32 process_desc; 312 u32 wq_addr; 313 u32 wq_size; 314 315 u32 engine_presence; 316 317 u8 engine_suspended; 318 319 u8 reserved0[3]; 320 u64 reserved1[1]; 321 322 u64 desc_private; 323 } __packed; 324 325 /** 326 * DOC: CTB based communication 327 * 328 * The CTB (command transport buffer) communication between Host and GuC 329 * is based on u32 data stream written to the shared buffer. One buffer can 330 * be used to transmit data only in one direction (one-directional channel). 331 * 332 * Current status of the each buffer is stored in the buffer descriptor. 333 * Buffer descriptor holds tail and head fields that represents active data 334 * stream. The tail field is updated by the data producer (sender), and head 335 * field is updated by the data consumer (receiver):: 336 * 337 * +------------+ 338 * | DESCRIPTOR | +=================+============+========+ 339 * +============+ | | MESSAGE(s) | | 340 * | address |--------->+=================+============+========+ 341 * +------------+ 342 * | head | ^-----head--------^ 343 * +------------+ 344 * | tail | ^---------tail-----------------^ 345 * +------------+ 346 * | size | ^---------------size--------------------^ 347 * +------------+ 348 * 349 * Each message in data stream starts with the single u32 treated as a header, 350 * followed by optional set of u32 data that makes message specific payload:: 351 * 352 * +------------+---------+---------+---------+ 353 * | MESSAGE | 354 * +------------+---------+---------+---------+ 355 * | msg[0] | [1] | ... | [n-1] | 356 * +------------+---------+---------+---------+ 357 * | MESSAGE | MESSAGE PAYLOAD | 358 * + HEADER +---------+---------+---------+ 359 * | | 0 | ... | n | 360 * +======+=====+=========+=========+=========+ 361 * | 31:16| code| | | | 362 * +------+-----+ | | | 363 * | 15:5|flags| | | | 364 * +------+-----+ | | | 365 * | 4:0| len| | | | 366 * +------+-----+---------+---------+---------+ 367 * 368 * ^-------------len-------------^ 369 * 370 * The message header consists of: 371 * 372 * - **len**, indicates length of the message payload (in u32) 373 * - **code**, indicates message code 374 * - **flags**, holds various bits to control message handling 375 */ 376 377 /* 378 * Describes single command transport buffer. 379 * Used by both guc-master and clients. 380 */ 381 struct guc_ct_buffer_desc { 382 u32 addr; /* gfx address */ 383 u64 host_private; /* host private data */ 384 u32 size; /* size in bytes */ 385 u32 head; /* offset updated by GuC*/ 386 u32 tail; /* offset updated by owner */ 387 u32 is_in_error; /* error indicator */ 388 u32 fence; /* fence updated by GuC */ 389 u32 status; /* status updated by GuC */ 390 u32 owner; /* id of the channel owner */ 391 u32 owner_sub_id; /* owner-defined field for extra tracking */ 392 u32 reserved[5]; 393 } __packed; 394 395 /* Type of command transport buffer */ 396 #define INTEL_GUC_CT_BUFFER_TYPE_SEND 0x0u 397 #define INTEL_GUC_CT_BUFFER_TYPE_RECV 0x1u 398 399 /* 400 * Definition of the command transport message header (DW0) 401 * 402 * bit[4..0] message len (in dwords) 403 * bit[7..5] reserved 404 * bit[8] write fence to desc 405 * bit[9] write status to H2G buff 406 * bit[10] send status (via G2H) 407 * bit[15..11] reserved 408 * bit[31..16] action code 409 */ 410 #define GUC_CT_MSG_LEN_SHIFT 0 411 #define GUC_CT_MSG_LEN_MASK 0x1F 412 #define GUC_CT_MSG_WRITE_FENCE_TO_DESC (1 << 8) 413 #define GUC_CT_MSG_WRITE_STATUS_TO_BUFF (1 << 9) 414 #define GUC_CT_MSG_SEND_STATUS (1 << 10) 415 #define GUC_CT_MSG_ACTION_SHIFT 16 416 #define GUC_CT_MSG_ACTION_MASK 0xFFFF 417 418 #define GUC_FORCEWAKE_RENDER (1 << 0) 419 #define GUC_FORCEWAKE_MEDIA (1 << 1) 420 421 #define GUC_POWER_UNSPECIFIED 0 422 #define GUC_POWER_D0 1 423 #define GUC_POWER_D1 2 424 #define GUC_POWER_D2 3 425 #define GUC_POWER_D3 4 426 427 /* Scheduling policy settings */ 428 429 /* Reset engine upon preempt failure */ 430 #define POLICY_RESET_ENGINE (1<<0) 431 /* Preempt to idle on quantum expiry */ 432 #define POLICY_PREEMPT_TO_IDLE (1<<1) 433 434 #define POLICY_MAX_NUM_WI 15 435 #define POLICY_DEFAULT_DPC_PROMOTE_TIME_US 500000 436 #define POLICY_DEFAULT_EXECUTION_QUANTUM_US 1000000 437 #define POLICY_DEFAULT_PREEMPTION_TIME_US 500000 438 #define POLICY_DEFAULT_FAULT_TIME_US 250000 439 440 struct guc_policy { 441 /* Time for one workload to execute. (in micro seconds) */ 442 u32 execution_quantum; 443 u32 reserved1; 444 445 /* Time to wait for a preemption request to completed before issuing a 446 * reset. (in micro seconds). */ 447 u32 preemption_time; 448 449 /* How much time to allow to run after the first fault is observed. 450 * Then preempt afterwards. (in micro seconds) */ 451 u32 fault_time; 452 453 u32 policy_flags; 454 u32 reserved[2]; 455 } __packed; 456 457 struct guc_policies { 458 struct guc_policy policy[GUC_CLIENT_PRIORITY_NUM][GUC_MAX_ENGINES_NUM]; 459 460 /* In micro seconds. How much time to allow before DPC processing is 461 * called back via interrupt (to prevent DPC queue drain starving). 462 * Typically 1000s of micro seconds (example only, not granularity). */ 463 u32 dpc_promote_time; 464 465 /* Must be set to take these new values. */ 466 u32 is_valid; 467 468 /* Max number of WIs to process per call. A large value may keep CS 469 * idle. */ 470 u32 max_num_work_items; 471 472 u32 reserved[19]; 473 } __packed; 474 475 /* GuC MMIO reg state struct */ 476 477 #define GUC_REGSET_FLAGS_NONE 0x0 478 #define GUC_REGSET_POWERCYCLE 0x1 479 #define GUC_REGSET_MASKED 0x2 480 #define GUC_REGSET_ENGINERESET 0x4 481 #define GUC_REGSET_SAVE_DEFAULT_VALUE 0x8 482 #define GUC_REGSET_SAVE_CURRENT_VALUE 0x10 483 484 #define GUC_REGSET_MAX_REGISTERS 25 485 #define GUC_MMIO_WHITE_LIST_START 0x24d0 486 #define GUC_MMIO_WHITE_LIST_MAX 12 487 #define GUC_S3_SAVE_SPACE_PAGES 10 488 489 struct guc_mmio_regset { 490 struct __packed { 491 u32 offset; 492 u32 value; 493 u32 flags; 494 } registers[GUC_REGSET_MAX_REGISTERS]; 495 496 u32 values_valid; 497 u32 number_of_registers; 498 } __packed; 499 500 /* MMIO registers that are set as non privileged */ 501 struct mmio_white_list { 502 u32 mmio_start; 503 u32 offsets[GUC_MMIO_WHITE_LIST_MAX]; 504 u32 count; 505 } __packed; 506 507 struct guc_mmio_reg_state { 508 struct guc_mmio_regset global_reg; 509 struct guc_mmio_regset engine_reg[GUC_MAX_ENGINES_NUM]; 510 struct mmio_white_list white_list[GUC_MAX_ENGINES_NUM]; 511 } __packed; 512 513 /* GuC Additional Data Struct */ 514 515 struct guc_ads { 516 u32 reg_state_addr; 517 u32 reg_state_buffer; 518 u32 golden_context_lrca; 519 u32 scheduler_policies; 520 u32 reserved0[3]; 521 u32 eng_state_size[GUC_MAX_ENGINES_NUM]; 522 u32 reserved2[4]; 523 } __packed; 524 525 /* GuC logging structures */ 526 527 enum guc_log_buffer_type { 528 GUC_ISR_LOG_BUFFER, 529 GUC_DPC_LOG_BUFFER, 530 GUC_CRASH_DUMP_LOG_BUFFER, 531 GUC_MAX_LOG_BUFFER 532 }; 533 534 /** 535 * Below state structure is used for coordination of retrieval of GuC firmware 536 * logs. Separate state is maintained for each log buffer type. 537 * read_ptr points to the location where i915 read last in log buffer and 538 * is read only for GuC firmware. write_ptr is incremented by GuC with number 539 * of bytes written for each log entry and is read only for i915. 540 * When any type of log buffer becomes half full, GuC sends a flush interrupt. 541 * GuC firmware expects that while it is writing to 2nd half of the buffer, 542 * first half would get consumed by Host and then get a flush completed 543 * acknowledgment from Host, so that it does not end up doing any overwrite 544 * causing loss of logs. So when buffer gets half filled & i915 has requested 545 * for interrupt, GuC will set flush_to_file field, set the sampled_write_ptr 546 * to the value of write_ptr and raise the interrupt. 547 * On receiving the interrupt i915 should read the buffer, clear flush_to_file 548 * field and also update read_ptr with the value of sample_write_ptr, before 549 * sending an acknowledgment to GuC. marker & version fields are for internal 550 * usage of GuC and opaque to i915. buffer_full_cnt field is incremented every 551 * time GuC detects the log buffer overflow. 552 */ 553 struct guc_log_buffer_state { 554 u32 marker[2]; 555 u32 read_ptr; 556 u32 write_ptr; 557 u32 size; 558 u32 sampled_write_ptr; 559 union { 560 struct { 561 u32 flush_to_file:1; 562 u32 buffer_full_cnt:4; 563 u32 reserved:27; 564 }; 565 u32 flags; 566 }; 567 u32 version; 568 } __packed; 569 570 struct guc_ctx_report { 571 u32 report_return_status; 572 u32 reserved1[64]; 573 u32 affected_count; 574 u32 reserved2[2]; 575 } __packed; 576 577 /* GuC Shared Context Data Struct */ 578 struct guc_shared_ctx_data { 579 u32 addr_of_last_preempted_data_low; 580 u32 addr_of_last_preempted_data_high; 581 u32 addr_of_last_preempted_data_high_tmp; 582 u32 padding; 583 u32 is_mapped_to_proxy; 584 u32 proxy_ctx_id; 585 u32 engine_reset_ctx_id; 586 u32 media_reset_count; 587 u32 reserved1[8]; 588 u32 uk_last_ctx_switch_reason; 589 u32 was_reset; 590 u32 lrca_gpu_addr; 591 u64 execlist_ctx; 592 u32 reserved2[66]; 593 struct guc_ctx_report preempt_ctx_report[GUC_MAX_ENGINES_NUM]; 594 } __packed; 595 596 /** 597 * DOC: MMIO based communication 598 * 599 * The MMIO based communication between Host and GuC uses software scratch 600 * registers, where first register holds data treated as message header, 601 * and other registers are used to hold message payload. 602 * 603 * For Gen9+, GuC uses software scratch registers 0xC180-0xC1B8 604 * 605 * +-----------+---------+---------+---------+ 606 * | MMIO[0] | MMIO[1] | ... | MMIO[n] | 607 * +-----------+---------+---------+---------+ 608 * | header | optional payload | 609 * +======+====+=========+=========+=========+ 610 * | 31:28|type| | | | 611 * +------+----+ | | | 612 * | 27:16|data| | | | 613 * +------+----+ | | | 614 * | 15:0|code| | | | 615 * +------+----+---------+---------+---------+ 616 * 617 * The message header consists of: 618 * 619 * - **type**, indicates message type 620 * - **code**, indicates message code, is specific for **type** 621 * - **data**, indicates message data, optional, depends on **code** 622 * 623 * The following message **types** are supported: 624 * 625 * - **REQUEST**, indicates Host-to-GuC request, requested GuC action code 626 * must be priovided in **code** field. Optional action specific parameters 627 * can be provided in remaining payload registers or **data** field. 628 * 629 * - **RESPONSE**, indicates GuC-to-Host response from earlier GuC request, 630 * action response status will be provided in **code** field. Optional 631 * response data can be returned in remaining payload registers or **data** 632 * field. 633 */ 634 635 #define INTEL_GUC_MSG_TYPE_SHIFT 28 636 #define INTEL_GUC_MSG_TYPE_MASK (0xF << INTEL_GUC_MSG_TYPE_SHIFT) 637 #define INTEL_GUC_MSG_DATA_SHIFT 16 638 #define INTEL_GUC_MSG_DATA_MASK (0xFFF << INTEL_GUC_MSG_DATA_SHIFT) 639 #define INTEL_GUC_MSG_CODE_SHIFT 0 640 #define INTEL_GUC_MSG_CODE_MASK (0xFFFF << INTEL_GUC_MSG_CODE_SHIFT) 641 642 #define __INTEL_GUC_MSG_GET(T, m) \ 643 (((m) & INTEL_GUC_MSG_ ## T ## _MASK) >> INTEL_GUC_MSG_ ## T ## _SHIFT) 644 #define INTEL_GUC_MSG_TO_TYPE(m) __INTEL_GUC_MSG_GET(TYPE, m) 645 #define INTEL_GUC_MSG_TO_DATA(m) __INTEL_GUC_MSG_GET(DATA, m) 646 #define INTEL_GUC_MSG_TO_CODE(m) __INTEL_GUC_MSG_GET(CODE, m) 647 648 enum intel_guc_msg_type { 649 INTEL_GUC_MSG_TYPE_REQUEST = 0x0, 650 INTEL_GUC_MSG_TYPE_RESPONSE = 0xF, 651 }; 652 653 #define __INTEL_GUC_MSG_TYPE_IS(T, m) \ 654 (INTEL_GUC_MSG_TO_TYPE(m) == INTEL_GUC_MSG_TYPE_ ## T) 655 #define INTEL_GUC_MSG_IS_REQUEST(m) __INTEL_GUC_MSG_TYPE_IS(REQUEST, m) 656 #define INTEL_GUC_MSG_IS_RESPONSE(m) __INTEL_GUC_MSG_TYPE_IS(RESPONSE, m) 657 658 enum intel_guc_action { 659 INTEL_GUC_ACTION_DEFAULT = 0x0, 660 INTEL_GUC_ACTION_REQUEST_PREEMPTION = 0x2, 661 INTEL_GUC_ACTION_REQUEST_ENGINE_RESET = 0x3, 662 INTEL_GUC_ACTION_SAMPLE_FORCEWAKE = 0x6, 663 INTEL_GUC_ACTION_ALLOCATE_DOORBELL = 0x10, 664 INTEL_GUC_ACTION_DEALLOCATE_DOORBELL = 0x20, 665 INTEL_GUC_ACTION_LOG_BUFFER_FILE_FLUSH_COMPLETE = 0x30, 666 INTEL_GUC_ACTION_FORCE_LOG_BUFFER_FLUSH = 0x302, 667 INTEL_GUC_ACTION_ENTER_S_STATE = 0x501, 668 INTEL_GUC_ACTION_EXIT_S_STATE = 0x502, 669 INTEL_GUC_ACTION_SLPC_REQUEST = 0x3003, 670 INTEL_GUC_ACTION_AUTHENTICATE_HUC = 0x4000, 671 INTEL_GUC_ACTION_REGISTER_COMMAND_TRANSPORT_BUFFER = 0x4505, 672 INTEL_GUC_ACTION_DEREGISTER_COMMAND_TRANSPORT_BUFFER = 0x4506, 673 INTEL_GUC_ACTION_UK_LOG_ENABLE_LOGGING = 0x0E000, 674 INTEL_GUC_ACTION_LIMIT 675 }; 676 677 enum intel_guc_preempt_options { 678 INTEL_GUC_PREEMPT_OPTION_DROP_WORK_Q = 0x4, 679 INTEL_GUC_PREEMPT_OPTION_DROP_SUBMIT_Q = 0x8, 680 }; 681 682 enum intel_guc_report_status { 683 INTEL_GUC_REPORT_STATUS_UNKNOWN = 0x0, 684 INTEL_GUC_REPORT_STATUS_ACKED = 0x1, 685 INTEL_GUC_REPORT_STATUS_ERROR = 0x2, 686 INTEL_GUC_REPORT_STATUS_COMPLETE = 0x4, 687 }; 688 689 #define GUC_LOG_CONTROL_LOGGING_ENABLED (1 << 0) 690 #define GUC_LOG_CONTROL_VERBOSITY_SHIFT 4 691 #define GUC_LOG_CONTROL_VERBOSITY_MASK (0xF << GUC_LOG_CONTROL_VERBOSITY_SHIFT) 692 #define GUC_LOG_CONTROL_DEFAULT_LOGGING (1 << 8) 693 694 enum intel_guc_response_status { 695 INTEL_GUC_RESPONSE_STATUS_SUCCESS = 0x0, 696 INTEL_GUC_RESPONSE_STATUS_GENERIC_FAIL = 0xF000, 697 }; 698 699 #define INTEL_GUC_MSG_IS_RESPONSE_SUCCESS(m) \ 700 (typecheck(u32, (m)) && \ 701 ((m) & (INTEL_GUC_MSG_TYPE_MASK | INTEL_GUC_MSG_CODE_MASK)) == \ 702 ((INTEL_GUC_MSG_TYPE_RESPONSE << INTEL_GUC_MSG_TYPE_SHIFT) | \ 703 (INTEL_GUC_RESPONSE_STATUS_SUCCESS << INTEL_GUC_MSG_CODE_SHIFT))) 704 705 /* This action will be programmed in C1BC - SOFT_SCRATCH_15_REG */ 706 enum intel_guc_recv_message { 707 INTEL_GUC_RECV_MSG_CRASH_DUMP_POSTED = BIT(1), 708 INTEL_GUC_RECV_MSG_FLUSH_LOG_BUFFER = BIT(3) 709 }; 710 711 #endif 712
