1 /* 2 * Copyright © 2012-2016 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 */ 24 25 #ifndef _INTEL_DPLL_MGR_H_ 26 #define _INTEL_DPLL_MGR_H_ 27 28 /*FIXME: Move this to a more appropriate place. */ 29 #define abs_diff(a, b) ({ \ 30 typeof(a) __a = (a); \ 31 typeof(b) __b = (b); \ 32 (void) (&__a == &__b); \ 33 __a > __b ? (__a - __b) : (__b - __a); }) 34 35 struct drm_i915_private; 36 struct intel_crtc; 37 struct intel_crtc_state; 38 struct intel_encoder; 39 40 struct intel_shared_dpll; 41 struct intel_dpll_mgr; 42 43 /** 44 * enum intel_dpll_id - possible DPLL ids 45 * 46 * Enumeration of possible IDs for a DPLL. Real shared dpll ids must be >= 0. 47 */ 48 enum intel_dpll_id { 49 /** 50 * @DPLL_ID_PRIVATE: non-shared dpll in use 51 */ 52 DPLL_ID_PRIVATE = -1, 53 54 /** 55 * @DPLL_ID_PCH_PLL_A: DPLL A in ILK, SNB and IVB 56 */ 57 DPLL_ID_PCH_PLL_A = 0, 58 /** 59 * @DPLL_ID_PCH_PLL_B: DPLL B in ILK, SNB and IVB 60 */ 61 DPLL_ID_PCH_PLL_B = 1, 62 63 64 /** 65 * @DPLL_ID_WRPLL1: HSW and BDW WRPLL1 66 */ 67 DPLL_ID_WRPLL1 = 0, 68 /** 69 * @DPLL_ID_WRPLL2: HSW and BDW WRPLL2 70 */ 71 DPLL_ID_WRPLL2 = 1, 72 /** 73 * @DPLL_ID_SPLL: HSW and BDW SPLL 74 */ 75 DPLL_ID_SPLL = 2, 76 /** 77 * @DPLL_ID_LCPLL_810: HSW and BDW 0.81 GHz LCPLL 78 */ 79 DPLL_ID_LCPLL_810 = 3, 80 /** 81 * @DPLL_ID_LCPLL_1350: HSW and BDW 1.35 GHz LCPLL 82 */ 83 DPLL_ID_LCPLL_1350 = 4, 84 /** 85 * @DPLL_ID_LCPLL_2700: HSW and BDW 2.7 GHz LCPLL 86 */ 87 DPLL_ID_LCPLL_2700 = 5, 88 89 90 /** 91 * @DPLL_ID_SKL_DPLL0: SKL and later DPLL0 92 */ 93 DPLL_ID_SKL_DPLL0 = 0, 94 /** 95 * @DPLL_ID_SKL_DPLL1: SKL and later DPLL1 96 */ 97 DPLL_ID_SKL_DPLL1 = 1, 98 /** 99 * @DPLL_ID_SKL_DPLL2: SKL and later DPLL2 100 */ 101 DPLL_ID_SKL_DPLL2 = 2, 102 /** 103 * @DPLL_ID_SKL_DPLL3: SKL and later DPLL3 104 */ 105 DPLL_ID_SKL_DPLL3 = 3, 106 107 108 /** 109 * @DPLL_ID_ICL_DPLL0: ICL combo PHY DPLL0 110 */ 111 DPLL_ID_ICL_DPLL0 = 0, 112 /** 113 * @DPLL_ID_ICL_DPLL1: ICL combo PHY DPLL1 114 */ 115 DPLL_ID_ICL_DPLL1 = 1, 116 /** 117 * @DPLL_ID_ICL_TBTPLL: ICL TBT PLL 118 */ 119 DPLL_ID_ICL_TBTPLL = 2, 120 /** 121 * @DPLL_ID_ICL_MGPLL1: ICL MG PLL 1 port 1 (C) 122 */ 123 DPLL_ID_ICL_MGPLL1 = 3, 124 /** 125 * @DPLL_ID_ICL_MGPLL2: ICL MG PLL 1 port 2 (D) 126 */ 127 DPLL_ID_ICL_MGPLL2 = 4, 128 /** 129 * @DPLL_ID_ICL_MGPLL3: ICL MG PLL 1 port 3 (E) 130 */ 131 DPLL_ID_ICL_MGPLL3 = 5, 132 /** 133 * @DPLL_ID_ICL_MGPLL4: ICL MG PLL 1 port 4 (F) 134 */ 135 DPLL_ID_ICL_MGPLL4 = 6, 136 }; 137 #define I915_NUM_PLLS 7 138 139 struct intel_dpll_hw_state { 140 /* i9xx, pch plls */ 141 uint32_t dpll; 142 uint32_t dpll_md; 143 uint32_t fp0; 144 uint32_t fp1; 145 146 /* hsw, bdw */ 147 uint32_t wrpll; 148 uint32_t spll; 149 150 /* skl */ 151 /* 152 * DPLL_CTRL1 has 6 bits for each each this DPLL. We store those in 153 * lower part of ctrl1 and they get shifted into position when writing 154 * the register. This allows us to easily compare the state to share 155 * the DPLL. 156 */ 157 uint32_t ctrl1; 158 /* HDMI only, 0 when used for DP */ 159 uint32_t cfgcr1, cfgcr2; 160 161 /* cnl */ 162 uint32_t cfgcr0; 163 /* CNL also uses cfgcr1 */ 164 165 /* bxt */ 166 uint32_t ebb0, ebb4, pll0, pll1, pll2, pll3, pll6, pll8, pll9, pll10, 167 pcsdw12; 168 169 /* 170 * ICL uses the following, already defined: 171 * uint32_t cfgcr0, cfgcr1; 172 */ 173 uint32_t mg_refclkin_ctl; 174 uint32_t mg_clktop2_coreclkctl1; 175 uint32_t mg_clktop2_hsclkctl; 176 uint32_t mg_pll_div0; 177 uint32_t mg_pll_div1; 178 uint32_t mg_pll_lf; 179 uint32_t mg_pll_frac_lock; 180 uint32_t mg_pll_ssc; 181 uint32_t mg_pll_bias; 182 uint32_t mg_pll_tdc_coldst_bias; 183 uint32_t mg_pll_bias_mask; 184 uint32_t mg_pll_tdc_coldst_bias_mask; 185 }; 186 187 /** 188 * struct intel_shared_dpll_state - hold the DPLL atomic state 189 * 190 * This structure holds an atomic state for the DPLL, that can represent 191 * either its current state (in struct &intel_shared_dpll) or a desired 192 * future state which would be applied by an atomic mode set (stored in 193 * a struct &intel_atomic_state). 194 * 195 * See also intel_get_shared_dpll() and intel_release_shared_dpll(). 196 */ 197 struct intel_shared_dpll_state { 198 /** 199 * @crtc_mask: mask of CRTC using this DPLL, active or not 200 */ 201 unsigned crtc_mask; 202 203 /** 204 * @hw_state: hardware configuration for the DPLL stored in 205 * struct &intel_dpll_hw_state. 206 */ 207 struct intel_dpll_hw_state hw_state; 208 }; 209 210 /** 211 * struct intel_shared_dpll_funcs - platform specific hooks for managing DPLLs 212 */ 213 struct intel_shared_dpll_funcs { 214 /** 215 * @prepare: 216 * 217 * Optional hook to perform operations prior to enabling the PLL. 218 * Called from intel_prepare_shared_dpll() function unless the PLL 219 * is already enabled. 220 */ 221 void (*prepare)(struct drm_i915_private *dev_priv, 222 struct intel_shared_dpll *pll); 223 224 /** 225 * @enable: 226 * 227 * Hook for enabling the pll, called from intel_enable_shared_dpll() 228 * if the pll is not already enabled. 229 */ 230 void (*enable)(struct drm_i915_private *dev_priv, 231 struct intel_shared_dpll *pll); 232 233 /** 234 * @disable: 235 * 236 * Hook for disabling the pll, called from intel_disable_shared_dpll() 237 * only when it is safe to disable the pll, i.e., there are no more 238 * tracked users for it. 239 */ 240 void (*disable)(struct drm_i915_private *dev_priv, 241 struct intel_shared_dpll *pll); 242 243 /** 244 * @get_hw_state: 245 * 246 * Hook for reading the values currently programmed to the DPLL 247 * registers. This is used for initial hw state readout and state 248 * verification after a mode set. 249 */ 250 bool (*get_hw_state)(struct drm_i915_private *dev_priv, 251 struct intel_shared_dpll *pll, 252 struct intel_dpll_hw_state *hw_state); 253 }; 254 255 /** 256 * struct dpll_info - display PLL platform specific info 257 */ 258 struct dpll_info { 259 /** 260 * @name: DPLL name; used for logging 261 */ 262 const char *name; 263 264 /** 265 * @funcs: platform specific hooks 266 */ 267 const struct intel_shared_dpll_funcs *funcs; 268 269 /** 270 * @id: unique indentifier for this DPLL; should match the index in the 271 * dev_priv->shared_dplls array 272 */ 273 enum intel_dpll_id id; 274 275 #define INTEL_DPLL_ALWAYS_ON (1 << 0) 276 /** 277 * @flags: 278 * 279 * INTEL_DPLL_ALWAYS_ON 280 * Inform the state checker that the DPLL is kept enabled even if 281 * not in use by any CRTC. 282 */ 283 uint32_t flags; 284 }; 285 286 /** 287 * struct intel_shared_dpll - display PLL with tracked state and users 288 */ 289 struct intel_shared_dpll { 290 /** 291 * @state: 292 * 293 * Store the state for the pll, including the its hw state 294 * and CRTCs using it. 295 */ 296 struct intel_shared_dpll_state state; 297 298 /** 299 * @active_mask: mask of active CRTCs (i.e. DPMS on) using this DPLL 300 */ 301 unsigned active_mask; 302 303 /** 304 * @on: is the PLL actually active? Disabled during modeset 305 */ 306 bool on; 307 308 /** 309 * @info: platform specific info 310 */ 311 const struct dpll_info *info; 312 }; 313 314 #define SKL_DPLL0 0 315 #define SKL_DPLL1 1 316 #define SKL_DPLL2 2 317 #define SKL_DPLL3 3 318 319 /* shared dpll functions */ 320 struct intel_shared_dpll * 321 intel_get_shared_dpll_by_id(struct drm_i915_private *dev_priv, 322 enum intel_dpll_id id); 323 enum intel_dpll_id 324 intel_get_shared_dpll_id(struct drm_i915_private *dev_priv, 325 struct intel_shared_dpll *pll); 326 void assert_shared_dpll(struct drm_i915_private *dev_priv, 327 struct intel_shared_dpll *pll, 328 bool state); 329 #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true) 330 #define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false) 331 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc, 332 struct intel_crtc_state *state, 333 struct intel_encoder *encoder); 334 void intel_release_shared_dpll(struct intel_shared_dpll *dpll, 335 struct intel_crtc *crtc, 336 struct drm_atomic_state *state); 337 void intel_prepare_shared_dpll(struct intel_crtc *crtc); 338 void intel_enable_shared_dpll(struct intel_crtc *crtc); 339 void intel_disable_shared_dpll(struct intel_crtc *crtc); 340 void intel_shared_dpll_swap_state(struct drm_atomic_state *state); 341 void intel_shared_dpll_init(struct drm_device *dev); 342 343 void intel_dpll_dump_hw_state(struct drm_i915_private *dev_priv, 344 struct intel_dpll_hw_state *hw_state); 345 int icl_calc_dp_combo_pll_link(struct drm_i915_private *dev_priv, 346 uint32_t pll_id); 347 348 #endif /* _INTEL_DPLL_MGR_H_ */ 349
