1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2016 MediaTek Inc.
4 */
5
6 #include <linux/delay.h>
7 #include <linux/err.h>
8 #include <linux/gpio/consumer.h>
9 #include <linux/i2c.h>
10 #include <linux/module.h>
11 #include <linux/of_graph.h>
12 #include <linux/pm_runtime.h>
13 #include <linux/regmap.h>
14 #include <linux/regulator/consumer.h>
15
16 #include <drm/display/drm_dp_aux_bus.h>
17 #include <drm/display/drm_dp_helper.h>
18 #include <drm/drm_atomic_state_helper.h>
19 #include <drm/drm_bridge.h>
20 #include <drm/drm_edid.h>
21 #include <drm/drm_mipi_dsi.h>
22 #include <drm/drm_of.h>
23 #include <drm/drm_panel.h>
24 #include <drm/drm_print.h>
25
26 #define PAGE0_AUXCH_CFG3 0x76
27 #define AUXCH_CFG3_RESET 0xff
28 #define PAGE0_SWAUX_ADDR_7_0 0x7d
29 #define PAGE0_SWAUX_ADDR_15_8 0x7e
30 #define PAGE0_SWAUX_ADDR_23_16 0x7f
31 #define SWAUX_ADDR_MASK GENMASK(19, 0)
32 #define PAGE0_SWAUX_LENGTH 0x80
33 #define SWAUX_LENGTH_MASK GENMASK(3, 0)
34 #define SWAUX_NO_PAYLOAD BIT(7)
35 #define PAGE0_SWAUX_WDATA 0x81
36 #define PAGE0_SWAUX_RDATA 0x82
37 #define PAGE0_SWAUX_CTRL 0x83
38 #define SWAUX_SEND BIT(0)
39 #define PAGE0_SWAUX_STATUS 0x84
40 #define SWAUX_M_MASK GENMASK(4, 0)
41 #define SWAUX_STATUS_MASK GENMASK(7, 5)
42 #define SWAUX_STATUS_NACK (0x1 << 5)
43 #define SWAUX_STATUS_DEFER (0x2 << 5)
44 #define SWAUX_STATUS_ACKM (0x3 << 5)
45 #define SWAUX_STATUS_INVALID (0x4 << 5)
46 #define SWAUX_STATUS_I2C_NACK (0x5 << 5)
47 #define SWAUX_STATUS_I2C_DEFER (0x6 << 5)
48 #define SWAUX_STATUS_TIMEOUT (0x7 << 5)
49
50 #define PAGE2_GPIO_H 0xa7
51 #define PS_GPIO9 BIT(1)
52 #define PAGE2_I2C_BYPASS 0xea
53 #define I2C_BYPASS_EN 0xd0
54 #define PAGE2_MCS_EN 0xf3
55 #define MCS_EN BIT(0)
56
57 #define PAGE3_SET_ADD 0xfe
58 #define VDO_CTL_ADD 0x13
59 #define VDO_DIS 0x18
60 #define VDO_EN 0x1c
61
62 #define NUM_MIPI_LANES 4
63
64 #define COMMON_PS8640_REGMAP_CONFIG \
65 .reg_bits = 8, \
66 .val_bits = 8, \
67 .cache_type = REGCACHE_NONE
68
69 /*
70 * PS8640 uses multiple addresses:
71 * page[0]: for DP control
72 * page[1]: for VIDEO Bridge
73 * page[2]: for control top
74 * page[3]: for DSI Link Control1
75 * page[4]: for MIPI Phy
76 * page[5]: for VPLL
77 * page[6]: for DSI Link Control2
78 * page[7]: for SPI ROM mapping
79 */
80 enum page_addr_offset {
81 PAGE0_DP_CNTL = 0,
82 PAGE1_VDO_BDG,
83 PAGE2_TOP_CNTL,
84 PAGE3_DSI_CNTL1,
85 PAGE4_MIPI_PHY,
86 PAGE5_VPLL,
87 PAGE6_DSI_CNTL2,
88 PAGE7_SPI_CNTL,
89 MAX_DEVS
90 };
91
92 enum ps8640_vdo_control {
93 DISABLE = VDO_DIS,
94 ENABLE = VDO_EN,
95 };
96
97 struct ps8640 {
98 struct drm_bridge bridge;
99 struct drm_bridge *panel_bridge;
100 struct drm_dp_aux aux;
101 struct mipi_dsi_device *dsi;
102 struct i2c_client *page[MAX_DEVS];
103 struct regmap *regmap[MAX_DEVS];
104 struct regulator_bulk_data supplies[2];
105 struct gpio_desc *gpio_reset;
106 struct gpio_desc *gpio_powerdown;
107 struct device_link *link;
108 bool pre_enabled;
109 bool need_post_hpd_delay;
110 };
111
112 static const struct regmap_config ps8640_regmap_config[] = {
113 [PAGE0_DP_CNTL] = {
114 COMMON_PS8640_REGMAP_CONFIG,
115 .max_register = 0xbf,
116 },
117 [PAGE1_VDO_BDG] = {
118 COMMON_PS8640_REGMAP_CONFIG,
119 .max_register = 0xff,
120 },
121 [PAGE2_TOP_CNTL] = {
122 COMMON_PS8640_REGMAP_CONFIG,
123 .max_register = 0xff,
124 },
125 [PAGE3_DSI_CNTL1] = {
126 COMMON_PS8640_REGMAP_CONFIG,
127 .max_register = 0xff,
128 },
129 [PAGE4_MIPI_PHY] = {
130 COMMON_PS8640_REGMAP_CONFIG,
131 .max_register = 0xff,
132 },
133 [PAGE5_VPLL] = {
134 COMMON_PS8640_REGMAP_CONFIG,
135 .max_register = 0x7f,
136 },
137 [PAGE6_DSI_CNTL2] = {
138 COMMON_PS8640_REGMAP_CONFIG,
139 .max_register = 0xff,
140 },
141 [PAGE7_SPI_CNTL] = {
142 COMMON_PS8640_REGMAP_CONFIG,
143 .max_register = 0xff,
144 },
145 };
146
bridge_to_ps8640(struct drm_bridge * e)147 static inline struct ps8640 *bridge_to_ps8640(struct drm_bridge *e)
148 {
149 return container_of(e, struct ps8640, bridge);
150 }
151
aux_to_ps8640(struct drm_dp_aux * aux)152 static inline struct ps8640 *aux_to_ps8640(struct drm_dp_aux *aux)
153 {
154 return container_of(aux, struct ps8640, aux);
155 }
156
_ps8640_wait_hpd_asserted(struct ps8640 * ps_bridge,unsigned long wait_us)157 static int _ps8640_wait_hpd_asserted(struct ps8640 *ps_bridge, unsigned long wait_us)
158 {
159 struct regmap *map = ps_bridge->regmap[PAGE2_TOP_CNTL];
160 int status;
161 int ret;
162
163 /*
164 * Apparently something about the firmware in the chip signals that
165 * HPD goes high by reporting GPIO9 as high (even though HPD isn't
166 * actually connected to GPIO9).
167 */
168 ret = regmap_read_poll_timeout(map, PAGE2_GPIO_H, status,
169 status & PS_GPIO9, 20000, wait_us);
170
171 /*
172 * The first time we see HPD go high after a reset we delay an extra
173 * 50 ms. The best guess is that the MCU is doing "stuff" during this
174 * time (maybe talking to the panel) and we don't want to interrupt it.
175 *
176 * No locking is done around "need_post_hpd_delay". If we're here we
177 * know we're holding a PM Runtime reference and the only other place
178 * that touches this is PM Runtime resume.
179 */
180 if (!ret && ps_bridge->need_post_hpd_delay) {
181 ps_bridge->need_post_hpd_delay = false;
182 msleep(50);
183 }
184
185 return ret;
186 }
187
ps8640_wait_hpd_asserted(struct drm_dp_aux * aux,unsigned long wait_us)188 static int ps8640_wait_hpd_asserted(struct drm_dp_aux *aux, unsigned long wait_us)
189 {
190 struct ps8640 *ps_bridge = aux_to_ps8640(aux);
191 struct device *dev = &ps_bridge->page[PAGE0_DP_CNTL]->dev;
192 int ret;
193
194 /*
195 * Note that this function is called by code that has already powered
196 * the panel. We have to power ourselves up but we don't need to worry
197 * about powering the panel.
198 */
199 pm_runtime_get_sync(dev);
200 ret = _ps8640_wait_hpd_asserted(ps_bridge, wait_us);
201 pm_runtime_mark_last_busy(dev);
202 pm_runtime_put_autosuspend(dev);
203
204 return ret;
205 }
206
ps8640_aux_transfer_msg(struct drm_dp_aux * aux,struct drm_dp_aux_msg * msg)207 static ssize_t ps8640_aux_transfer_msg(struct drm_dp_aux *aux,
208 struct drm_dp_aux_msg *msg)
209 {
210 struct ps8640 *ps_bridge = aux_to_ps8640(aux);
211 struct regmap *map = ps_bridge->regmap[PAGE0_DP_CNTL];
212 struct device *dev = &ps_bridge->page[PAGE0_DP_CNTL]->dev;
213 unsigned int len = msg->size;
214 unsigned int data;
215 unsigned int base;
216 int ret;
217 u8 request = msg->request &
218 ~(DP_AUX_I2C_MOT | DP_AUX_I2C_WRITE_STATUS_UPDATE);
219 u8 *buf = msg->buffer;
220 u8 addr_len[PAGE0_SWAUX_LENGTH + 1 - PAGE0_SWAUX_ADDR_7_0];
221 u8 i;
222 bool is_native_aux = false;
223
224 if (len > DP_AUX_MAX_PAYLOAD_BYTES)
225 return -EINVAL;
226
227 if (msg->address & ~SWAUX_ADDR_MASK)
228 return -EINVAL;
229
230 switch (request) {
231 case DP_AUX_NATIVE_WRITE:
232 case DP_AUX_NATIVE_READ:
233 is_native_aux = true;
234 fallthrough;
235 case DP_AUX_I2C_WRITE:
236 case DP_AUX_I2C_READ:
237 break;
238 default:
239 return -EINVAL;
240 }
241
242 ret = regmap_write(map, PAGE0_AUXCH_CFG3, AUXCH_CFG3_RESET);
243 if (ret) {
244 DRM_DEV_ERROR(dev, "failed to write PAGE0_AUXCH_CFG3: %d\n",
245 ret);
246 return ret;
247 }
248
249 /* Assume it's good */
250 msg->reply = 0;
251
252 base = PAGE0_SWAUX_ADDR_7_0;
253 addr_len[PAGE0_SWAUX_ADDR_7_0 - base] = msg->address;
254 addr_len[PAGE0_SWAUX_ADDR_15_8 - base] = msg->address >> 8;
255 addr_len[PAGE0_SWAUX_ADDR_23_16 - base] = (msg->address >> 16) |
256 (msg->request << 4);
257 addr_len[PAGE0_SWAUX_LENGTH - base] = (len == 0) ? SWAUX_NO_PAYLOAD :
258 ((len - 1) & SWAUX_LENGTH_MASK);
259
260 regmap_bulk_write(map, PAGE0_SWAUX_ADDR_7_0, addr_len,
261 ARRAY_SIZE(addr_len));
262
263 if (len && (request == DP_AUX_NATIVE_WRITE ||
264 request == DP_AUX_I2C_WRITE)) {
265 /* Write to the internal FIFO buffer */
266 for (i = 0; i < len; i++) {
267 ret = regmap_write(map, PAGE0_SWAUX_WDATA, buf[i]);
268 if (ret) {
269 DRM_DEV_ERROR(dev,
270 "failed to write WDATA: %d\n",
271 ret);
272 return ret;
273 }
274 }
275 }
276
277 regmap_write(map, PAGE0_SWAUX_CTRL, SWAUX_SEND);
278
279 /* Zero delay loop because i2c transactions are slow already */
280 regmap_read_poll_timeout(map, PAGE0_SWAUX_CTRL, data,
281 !(data & SWAUX_SEND), 0, 50 * 1000);
282
283 regmap_read(map, PAGE0_SWAUX_STATUS, &data);
284 if (ret) {
285 DRM_DEV_ERROR(dev, "failed to read PAGE0_SWAUX_STATUS: %d\n",
286 ret);
287 return ret;
288 }
289
290 switch (data & SWAUX_STATUS_MASK) {
291 case SWAUX_STATUS_NACK:
292 case SWAUX_STATUS_I2C_NACK:
293 /*
294 * The programming guide is not clear about whether a I2C NACK
295 * would trigger SWAUX_STATUS_NACK or SWAUX_STATUS_I2C_NACK. So
296 * we handle both cases together.
297 */
298 if (is_native_aux)
299 msg->reply |= DP_AUX_NATIVE_REPLY_NACK;
300 else
301 msg->reply |= DP_AUX_I2C_REPLY_NACK;
302
303 fallthrough;
304 case SWAUX_STATUS_ACKM:
305 len = data & SWAUX_M_MASK;
306 break;
307 case SWAUX_STATUS_DEFER:
308 case SWAUX_STATUS_I2C_DEFER:
309 if (is_native_aux)
310 msg->reply |= DP_AUX_NATIVE_REPLY_DEFER;
311 else
312 msg->reply |= DP_AUX_I2C_REPLY_DEFER;
313 len = data & SWAUX_M_MASK;
314 break;
315 case SWAUX_STATUS_INVALID:
316 return -EOPNOTSUPP;
317 case SWAUX_STATUS_TIMEOUT:
318 return -ETIMEDOUT;
319 }
320
321 if (len && (request == DP_AUX_NATIVE_READ ||
322 request == DP_AUX_I2C_READ)) {
323 /* Read from the internal FIFO buffer */
324 for (i = 0; i < len; i++) {
325 ret = regmap_read(map, PAGE0_SWAUX_RDATA, &data);
326 if (ret) {
327 DRM_DEV_ERROR(dev,
328 "failed to read RDATA: %d\n",
329 ret);
330 return ret;
331 }
332
333 buf[i] = data;
334 }
335 }
336
337 return len;
338 }
339
ps8640_aux_transfer(struct drm_dp_aux * aux,struct drm_dp_aux_msg * msg)340 static ssize_t ps8640_aux_transfer(struct drm_dp_aux *aux,
341 struct drm_dp_aux_msg *msg)
342 {
343 struct ps8640 *ps_bridge = aux_to_ps8640(aux);
344 struct device *dev = &ps_bridge->page[PAGE0_DP_CNTL]->dev;
345 int ret;
346
347 pm_runtime_get_sync(dev);
348 ret = ps8640_aux_transfer_msg(aux, msg);
349 pm_runtime_mark_last_busy(dev);
350 pm_runtime_put_autosuspend(dev);
351
352 return ret;
353 }
354
ps8640_bridge_vdo_control(struct ps8640 * ps_bridge,const enum ps8640_vdo_control ctrl)355 static void ps8640_bridge_vdo_control(struct ps8640 *ps_bridge,
356 const enum ps8640_vdo_control ctrl)
357 {
358 struct regmap *map = ps_bridge->regmap[PAGE3_DSI_CNTL1];
359 struct device *dev = &ps_bridge->page[PAGE3_DSI_CNTL1]->dev;
360 u8 vdo_ctrl_buf[] = { VDO_CTL_ADD, ctrl };
361 int ret;
362
363 ret = regmap_bulk_write(map, PAGE3_SET_ADD,
364 vdo_ctrl_buf, sizeof(vdo_ctrl_buf));
365
366 if (ret < 0)
367 dev_err(dev, "failed to %sable VDO: %d\n",
368 ctrl == ENABLE ? "en" : "dis", ret);
369 }
370
ps8640_resume(struct device * dev)371 static int __maybe_unused ps8640_resume(struct device *dev)
372 {
373 struct ps8640 *ps_bridge = dev_get_drvdata(dev);
374 int ret;
375
376 ret = regulator_bulk_enable(ARRAY_SIZE(ps_bridge->supplies),
377 ps_bridge->supplies);
378 if (ret < 0) {
379 dev_err(dev, "cannot enable regulators %d\n", ret);
380 return ret;
381 }
382
383 gpiod_set_value(ps_bridge->gpio_powerdown, 0);
384 gpiod_set_value(ps_bridge->gpio_reset, 1);
385 usleep_range(2000, 2500);
386 gpiod_set_value(ps_bridge->gpio_reset, 0);
387 /* Double reset for T4 and T5 */
388 msleep(50);
389 gpiod_set_value(ps_bridge->gpio_reset, 1);
390 msleep(50);
391 gpiod_set_value(ps_bridge->gpio_reset, 0);
392
393 /* We just reset things, so we need a delay after the first HPD */
394 ps_bridge->need_post_hpd_delay = true;
395
396 /*
397 * Mystery 200 ms delay for the "MCU to be ready". It's unclear if
398 * this is truly necessary since the MCU will already signal that
399 * things are "good to go" by signaling HPD on "gpio 9". See
400 * _ps8640_wait_hpd_asserted(). For now we'll keep this mystery delay
401 * just in case.
402 */
403 msleep(200);
404
405 return 0;
406 }
407
ps8640_suspend(struct device * dev)408 static int __maybe_unused ps8640_suspend(struct device *dev)
409 {
410 struct ps8640 *ps_bridge = dev_get_drvdata(dev);
411 int ret;
412
413 gpiod_set_value(ps_bridge->gpio_reset, 1);
414 gpiod_set_value(ps_bridge->gpio_powerdown, 1);
415 ret = regulator_bulk_disable(ARRAY_SIZE(ps_bridge->supplies),
416 ps_bridge->supplies);
417 if (ret < 0)
418 dev_err(dev, "cannot disable regulators %d\n", ret);
419
420 return ret;
421 }
422
423 static const struct dev_pm_ops ps8640_pm_ops = {
424 SET_RUNTIME_PM_OPS(ps8640_suspend, ps8640_resume, NULL)
425 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
426 pm_runtime_force_resume)
427 };
428
ps8640_atomic_pre_enable(struct drm_bridge * bridge,struct drm_bridge_state * old_bridge_state)429 static void ps8640_atomic_pre_enable(struct drm_bridge *bridge,
430 struct drm_bridge_state *old_bridge_state)
431 {
432 struct ps8640 *ps_bridge = bridge_to_ps8640(bridge);
433 struct regmap *map = ps_bridge->regmap[PAGE2_TOP_CNTL];
434 struct device *dev = &ps_bridge->page[PAGE0_DP_CNTL]->dev;
435 int ret;
436
437 pm_runtime_get_sync(dev);
438 ret = _ps8640_wait_hpd_asserted(ps_bridge, 200 * 1000);
439 if (ret < 0)
440 dev_warn(dev, "HPD didn't go high: %d\n", ret);
441
442 /*
443 * The Manufacturer Command Set (MCS) is a device dependent interface
444 * intended for factory programming of the display module default
445 * parameters. Once the display module is configured, the MCS shall be
446 * disabled by the manufacturer. Once disabled, all MCS commands are
447 * ignored by the display interface.
448 */
449
450 ret = regmap_update_bits(map, PAGE2_MCS_EN, MCS_EN, 0);
451 if (ret < 0)
452 dev_warn(dev, "failed write PAGE2_MCS_EN: %d\n", ret);
453
454 /* Switch access edp panel's edid through i2c */
455 ret = regmap_write(map, PAGE2_I2C_BYPASS, I2C_BYPASS_EN);
456 if (ret < 0)
457 dev_warn(dev, "failed write PAGE2_MCS_EN: %d\n", ret);
458
459 ps8640_bridge_vdo_control(ps_bridge, ENABLE);
460
461 ps_bridge->pre_enabled = true;
462 }
463
ps8640_atomic_post_disable(struct drm_bridge * bridge,struct drm_bridge_state * old_bridge_state)464 static void ps8640_atomic_post_disable(struct drm_bridge *bridge,
465 struct drm_bridge_state *old_bridge_state)
466 {
467 struct ps8640 *ps_bridge = bridge_to_ps8640(bridge);
468
469 ps_bridge->pre_enabled = false;
470
471 ps8640_bridge_vdo_control(ps_bridge, DISABLE);
472 pm_runtime_put_sync_suspend(&ps_bridge->page[PAGE0_DP_CNTL]->dev);
473 }
474
ps8640_bridge_attach(struct drm_bridge * bridge,enum drm_bridge_attach_flags flags)475 static int ps8640_bridge_attach(struct drm_bridge *bridge,
476 enum drm_bridge_attach_flags flags)
477 {
478 struct ps8640 *ps_bridge = bridge_to_ps8640(bridge);
479 struct device *dev = &ps_bridge->page[0]->dev;
480 int ret;
481
482 if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR))
483 return -EINVAL;
484
485 ps_bridge->aux.drm_dev = bridge->dev;
486 ret = drm_dp_aux_register(&ps_bridge->aux);
487 if (ret) {
488 dev_err(dev, "failed to register DP AUX channel: %d\n", ret);
489 return ret;
490 }
491
492 ps_bridge->link = device_link_add(bridge->dev->dev, dev, DL_FLAG_STATELESS);
493 if (!ps_bridge->link) {
494 dev_err(dev, "failed to create device link");
495 ret = -EINVAL;
496 goto err_devlink;
497 }
498
499 /* Attach the panel-bridge to the dsi bridge */
500 ret = drm_bridge_attach(bridge->encoder, ps_bridge->panel_bridge,
501 &ps_bridge->bridge, flags);
502 if (ret)
503 goto err_bridge_attach;
504
505 return 0;
506
507 err_bridge_attach:
508 device_link_del(ps_bridge->link);
509 err_devlink:
510 drm_dp_aux_unregister(&ps_bridge->aux);
511
512 return ret;
513 }
514
ps8640_bridge_detach(struct drm_bridge * bridge)515 static void ps8640_bridge_detach(struct drm_bridge *bridge)
516 {
517 struct ps8640 *ps_bridge = bridge_to_ps8640(bridge);
518
519 drm_dp_aux_unregister(&ps_bridge->aux);
520 if (ps_bridge->link)
521 device_link_del(ps_bridge->link);
522 }
523
ps8640_runtime_disable(void * data)524 static void ps8640_runtime_disable(void *data)
525 {
526 pm_runtime_dont_use_autosuspend(data);
527 pm_runtime_disable(data);
528 }
529
530 static const struct drm_bridge_funcs ps8640_bridge_funcs = {
531 .attach = ps8640_bridge_attach,
532 .detach = ps8640_bridge_detach,
533 .atomic_post_disable = ps8640_atomic_post_disable,
534 .atomic_pre_enable = ps8640_atomic_pre_enable,
535 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
536 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
537 .atomic_reset = drm_atomic_helper_bridge_reset,
538 };
539
ps8640_bridge_get_dsi_resources(struct device * dev,struct ps8640 * ps_bridge)540 static int ps8640_bridge_get_dsi_resources(struct device *dev, struct ps8640 *ps_bridge)
541 {
542 struct device_node *in_ep, *dsi_node;
543 struct mipi_dsi_device *dsi;
544 struct mipi_dsi_host *host;
545 const struct mipi_dsi_device_info info = { .type = "ps8640",
546 .channel = 0,
547 .node = NULL,
548 };
549
550 /* port@0 is ps8640 dsi input port */
551 in_ep = of_graph_get_endpoint_by_regs(dev->of_node, 0, -1);
552 if (!in_ep)
553 return -ENODEV;
554
555 dsi_node = of_graph_get_remote_port_parent(in_ep);
556 of_node_put(in_ep);
557 if (!dsi_node)
558 return -ENODEV;
559
560 host = of_find_mipi_dsi_host_by_node(dsi_node);
561 of_node_put(dsi_node);
562 if (!host)
563 return -EPROBE_DEFER;
564
565 dsi = devm_mipi_dsi_device_register_full(dev, host, &info);
566 if (IS_ERR(dsi)) {
567 dev_err(dev, "failed to create dsi device\n");
568 return PTR_ERR(dsi);
569 }
570
571 ps_bridge->dsi = dsi;
572
573 dsi->host = host;
574 dsi->mode_flags = MIPI_DSI_MODE_VIDEO |
575 MIPI_DSI_MODE_VIDEO_SYNC_PULSE;
576 dsi->format = MIPI_DSI_FMT_RGB888;
577 dsi->lanes = NUM_MIPI_LANES;
578
579 return 0;
580 }
581
ps8640_bridge_link_panel(struct drm_dp_aux * aux)582 static int ps8640_bridge_link_panel(struct drm_dp_aux *aux)
583 {
584 struct ps8640 *ps_bridge = aux_to_ps8640(aux);
585 struct device *dev = aux->dev;
586 struct device_node *np = dev->of_node;
587 int ret;
588
589 /*
590 * NOTE about returning -EPROBE_DEFER from this function: if we
591 * return an error (most relevant to -EPROBE_DEFER) it will only
592 * be passed out to ps8640_probe() if it called this directly (AKA the
593 * panel isn't under the "aux-bus" node). That should be fine because
594 * if the panel is under "aux-bus" it's guaranteed to have probed by
595 * the time this function has been called.
596 */
597
598 /* port@1 is ps8640 output port */
599 ps_bridge->panel_bridge = devm_drm_of_get_bridge(dev, np, 1, 0);
600 if (IS_ERR(ps_bridge->panel_bridge))
601 return PTR_ERR(ps_bridge->panel_bridge);
602
603 ret = devm_drm_bridge_add(dev, &ps_bridge->bridge);
604 if (ret)
605 return ret;
606
607 return devm_mipi_dsi_attach(dev, ps_bridge->dsi);
608 }
609
ps8640_probe(struct i2c_client * client)610 static int ps8640_probe(struct i2c_client *client)
611 {
612 struct device *dev = &client->dev;
613 struct ps8640 *ps_bridge;
614 int ret;
615 u32 i;
616
617 ps_bridge = devm_kzalloc(dev, sizeof(*ps_bridge), GFP_KERNEL);
618 if (!ps_bridge)
619 return -ENOMEM;
620
621 ps_bridge->supplies[0].supply = "vdd12";
622 ps_bridge->supplies[1].supply = "vdd33";
623 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(ps_bridge->supplies),
624 ps_bridge->supplies);
625 if (ret)
626 return ret;
627
628 ps_bridge->gpio_powerdown = devm_gpiod_get(&client->dev, "powerdown",
629 GPIOD_OUT_HIGH);
630 if (IS_ERR(ps_bridge->gpio_powerdown))
631 return PTR_ERR(ps_bridge->gpio_powerdown);
632
633 /*
634 * Assert the reset to avoid the bridge being initialized prematurely
635 */
636 ps_bridge->gpio_reset = devm_gpiod_get(&client->dev, "reset",
637 GPIOD_OUT_HIGH);
638 if (IS_ERR(ps_bridge->gpio_reset))
639 return PTR_ERR(ps_bridge->gpio_reset);
640
641 ps_bridge->bridge.funcs = &ps8640_bridge_funcs;
642 ps_bridge->bridge.of_node = dev->of_node;
643 ps_bridge->bridge.type = DRM_MODE_CONNECTOR_eDP;
644
645 /*
646 * Get MIPI DSI resources early. These can return -EPROBE_DEFER so
647 * we want to get them out of the way sooner.
648 */
649 ret = ps8640_bridge_get_dsi_resources(&client->dev, ps_bridge);
650 if (ret)
651 return ret;
652
653 ps_bridge->page[PAGE0_DP_CNTL] = client;
654
655 ps_bridge->regmap[PAGE0_DP_CNTL] = devm_regmap_init_i2c(client, ps8640_regmap_config);
656 if (IS_ERR(ps_bridge->regmap[PAGE0_DP_CNTL]))
657 return PTR_ERR(ps_bridge->regmap[PAGE0_DP_CNTL]);
658
659 for (i = 1; i < ARRAY_SIZE(ps_bridge->page); i++) {
660 ps_bridge->page[i] = devm_i2c_new_dummy_device(&client->dev,
661 client->adapter,
662 client->addr + i);
663 if (IS_ERR(ps_bridge->page[i]))
664 return PTR_ERR(ps_bridge->page[i]);
665
666 ps_bridge->regmap[i] = devm_regmap_init_i2c(ps_bridge->page[i],
667 ps8640_regmap_config + i);
668 if (IS_ERR(ps_bridge->regmap[i]))
669 return PTR_ERR(ps_bridge->regmap[i]);
670 }
671
672 i2c_set_clientdata(client, ps_bridge);
673
674 ps_bridge->aux.name = "parade-ps8640-aux";
675 ps_bridge->aux.dev = dev;
676 ps_bridge->aux.transfer = ps8640_aux_transfer;
677 ps_bridge->aux.wait_hpd_asserted = ps8640_wait_hpd_asserted;
678 drm_dp_aux_init(&ps_bridge->aux);
679
680 pm_runtime_enable(dev);
681 /*
682 * Powering on ps8640 takes ~300ms. To avoid wasting time on power
683 * cycling ps8640 too often, set autosuspend_delay to 2000ms to ensure
684 * the bridge wouldn't suspend in between each _aux_transfer_msg() call
685 * during EDID read (~20ms in my experiment) and in between the last
686 * _aux_transfer_msg() call during EDID read and the _pre_enable() call
687 * (~100ms in my experiment).
688 */
689 pm_runtime_set_autosuspend_delay(dev, 2000);
690 pm_runtime_use_autosuspend(dev);
691 pm_suspend_ignore_children(dev, true);
692 ret = devm_add_action_or_reset(dev, ps8640_runtime_disable, dev);
693 if (ret)
694 return ret;
695
696 ret = devm_of_dp_aux_populate_bus(&ps_bridge->aux, ps8640_bridge_link_panel);
697
698 /*
699 * If devm_of_dp_aux_populate_bus() returns -ENODEV then it's up to
700 * usa to call ps8640_bridge_link_panel() directly. NOTE: in this case
701 * the function is allowed to -EPROBE_DEFER.
702 */
703 if (ret == -ENODEV)
704 return ps8640_bridge_link_panel(&ps_bridge->aux);
705
706 return ret;
707 }
708
709 static const struct of_device_id ps8640_match[] = {
710 { .compatible = "parade,ps8640" },
711 { }
712 };
713 MODULE_DEVICE_TABLE(of, ps8640_match);
714
715 static struct i2c_driver ps8640_driver = {
716 .probe = ps8640_probe,
717 .driver = {
718 .name = "ps8640",
719 .of_match_table = ps8640_match,
720 .pm = &ps8640_pm_ops,
721 },
722 };
723 module_i2c_driver(ps8640_driver);
724
725 MODULE_AUTHOR("Jitao Shi <jitao.shi@mediatek.com>");
726 MODULE_AUTHOR("CK Hu <ck.hu@mediatek.com>");
727 MODULE_AUTHOR("Enric Balletbo i Serra <enric.balletbo@collabora.com>");
728 MODULE_DESCRIPTION("PARADE ps8640 DSI-eDP converter driver");
729 MODULE_LICENSE("GPL v2");
730
