1 /*
2 * GPIO driver for Marvell SoCs
3 *
4 * Copyright (C) 2012 Marvell
5 *
6 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
7 * Andrew Lunn <andrew@lunn.ch>
8 * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
9 *
10 * This file is licensed under the terms of the GNU General Public
11 * License version 2. This program is licensed "as is" without any
12 * warranty of any kind, whether express or implied.
13 *
14 * This driver is a fairly straightforward GPIO driver for the
15 * complete family of Marvell EBU SoC platforms (Orion, Dove,
16 * Kirkwood, Discovery, Armada 370/XP). The only complexity of this
17 * driver is the different register layout that exists between the
18 * non-SMP platforms (Orion, Dove, Kirkwood, Armada 370) and the SMP
19 * platforms (MV78200 from the Discovery family and the Armada
20 * XP). Therefore, this driver handles three variants of the GPIO
21 * block:
22 * - the basic variant, called "orion-gpio", with the simplest
23 * register set. Used on Orion, Dove, Kirkwoord, Armada 370 and
24 * non-SMP Discovery systems
25 * - the mv78200 variant for MV78200 Discovery systems. This variant
26 * turns the edge mask and level mask registers into CPU0 edge
27 * mask/level mask registers, and adds CPU1 edge mask/level mask
28 * registers.
29 * - the armadaxp variant for Armada XP systems. This variant keeps
30 * the normal cause/edge mask/level mask registers when the global
31 * interrupts are used, but adds per-CPU cause/edge mask/level mask
32 * registers n a separate memory area for the per-CPU GPIO
33 * interrupts.
34 */
35
36 #include <linux/bitops.h>
37 #include <linux/clk.h>
38 #include <linux/err.h>
39 #include <linux/gpio/driver.h>
40 #include <linux/gpio/consumer.h>
41 #include <linux/init.h>
42 #include <linux/io.h>
43 #include <linux/irq.h>
44 #include <linux/irqchip/chained_irq.h>
45 #include <linux/irqdomain.h>
46 #include <linux/mfd/syscon.h>
47 #include <linux/of_device.h>
48 #include <linux/of_irq.h>
49 #include <linux/pinctrl/consumer.h>
50 #include <linux/platform_device.h>
51 #include <linux/pwm.h>
52 #include <linux/regmap.h>
53 #include <linux/slab.h>
54
55 /*
56 * GPIO unit register offsets.
57 */
58 #define GPIO_OUT_OFF 0x0000
59 #define GPIO_IO_CONF_OFF 0x0004
60 #define GPIO_BLINK_EN_OFF 0x0008
61 #define GPIO_IN_POL_OFF 0x000c
62 #define GPIO_DATA_IN_OFF 0x0010
63 #define GPIO_EDGE_CAUSE_OFF 0x0014
64 #define GPIO_EDGE_MASK_OFF 0x0018
65 #define GPIO_LEVEL_MASK_OFF 0x001c
66 #define GPIO_BLINK_CNT_SELECT_OFF 0x0020
67
68 /*
69 * PWM register offsets.
70 */
71 #define PWM_BLINK_ON_DURATION_OFF 0x0
72 #define PWM_BLINK_OFF_DURATION_OFF 0x4
73
74
75 /* The MV78200 has per-CPU registers for edge mask and level mask */
76 #define GPIO_EDGE_MASK_MV78200_OFF(cpu) ((cpu) ? 0x30 : 0x18)
77 #define GPIO_LEVEL_MASK_MV78200_OFF(cpu) ((cpu) ? 0x34 : 0x1C)
78
79 /*
80 * The Armada XP has per-CPU registers for interrupt cause, interrupt
81 * mask and interrupt level mask. Those are relative to the
82 * percpu_membase.
83 */
84 #define GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu) ((cpu) * 0x4)
85 #define GPIO_EDGE_MASK_ARMADAXP_OFF(cpu) (0x10 + (cpu) * 0x4)
86 #define GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu) (0x20 + (cpu) * 0x4)
87
88 #define MVEBU_GPIO_SOC_VARIANT_ORION 0x1
89 #define MVEBU_GPIO_SOC_VARIANT_MV78200 0x2
90 #define MVEBU_GPIO_SOC_VARIANT_ARMADAXP 0x3
91 #define MVEBU_GPIO_SOC_VARIANT_A8K 0x4
92
93 #define MVEBU_MAX_GPIO_PER_BANK 32
94
95 struct mvebu_pwm {
96 void __iomem *membase;
97 unsigned long clk_rate;
98 struct gpio_desc *gpiod;
99 struct pwm_chip chip;
100 spinlock_t lock;
101 struct mvebu_gpio_chip *mvchip;
102
103 /* Used to preserve GPIO/PWM registers across suspend/resume */
104 u32 blink_select;
105 u32 blink_on_duration;
106 u32 blink_off_duration;
107 };
108
109 struct mvebu_gpio_chip {
110 struct gpio_chip chip;
111 struct regmap *regs;
112 u32 offset;
113 struct regmap *percpu_regs;
114 int irqbase;
115 struct irq_domain *domain;
116 int soc_variant;
117
118 /* Used for PWM support */
119 struct clk *clk;
120 struct mvebu_pwm *mvpwm;
121
122 /* Used to preserve GPIO registers across suspend/resume */
123 u32 out_reg;
124 u32 io_conf_reg;
125 u32 blink_en_reg;
126 u32 in_pol_reg;
127 u32 edge_mask_regs[4];
128 u32 level_mask_regs[4];
129 };
130
131 /*
132 * Functions returning addresses of individual registers for a given
133 * GPIO controller.
134 */
135
mvebu_gpioreg_edge_cause(struct mvebu_gpio_chip * mvchip,struct regmap ** map,unsigned int * offset)136 static void mvebu_gpioreg_edge_cause(struct mvebu_gpio_chip *mvchip,
137 struct regmap **map, unsigned int *offset)
138 {
139 int cpu;
140
141 switch (mvchip->soc_variant) {
142 case MVEBU_GPIO_SOC_VARIANT_ORION:
143 case MVEBU_GPIO_SOC_VARIANT_MV78200:
144 case MVEBU_GPIO_SOC_VARIANT_A8K:
145 *map = mvchip->regs;
146 *offset = GPIO_EDGE_CAUSE_OFF + mvchip->offset;
147 break;
148 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
149 cpu = smp_processor_id();
150 *map = mvchip->percpu_regs;
151 *offset = GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu);
152 break;
153 default:
154 BUG();
155 }
156 }
157
158 static u32
mvebu_gpio_read_edge_cause(struct mvebu_gpio_chip * mvchip)159 mvebu_gpio_read_edge_cause(struct mvebu_gpio_chip *mvchip)
160 {
161 struct regmap *map;
162 unsigned int offset;
163 u32 val;
164
165 mvebu_gpioreg_edge_cause(mvchip, &map, &offset);
166 regmap_read(map, offset, &val);
167
168 return val;
169 }
170
171 static void
mvebu_gpio_write_edge_cause(struct mvebu_gpio_chip * mvchip,u32 val)172 mvebu_gpio_write_edge_cause(struct mvebu_gpio_chip *mvchip, u32 val)
173 {
174 struct regmap *map;
175 unsigned int offset;
176
177 mvebu_gpioreg_edge_cause(mvchip, &map, &offset);
178 regmap_write(map, offset, val);
179 }
180
181 static inline void
mvebu_gpioreg_edge_mask(struct mvebu_gpio_chip * mvchip,struct regmap ** map,unsigned int * offset)182 mvebu_gpioreg_edge_mask(struct mvebu_gpio_chip *mvchip,
183 struct regmap **map, unsigned int *offset)
184 {
185 int cpu;
186
187 switch (mvchip->soc_variant) {
188 case MVEBU_GPIO_SOC_VARIANT_ORION:
189 case MVEBU_GPIO_SOC_VARIANT_A8K:
190 *map = mvchip->regs;
191 *offset = GPIO_EDGE_MASK_OFF + mvchip->offset;
192 break;
193 case MVEBU_GPIO_SOC_VARIANT_MV78200:
194 cpu = smp_processor_id();
195 *map = mvchip->regs;
196 *offset = GPIO_EDGE_MASK_MV78200_OFF(cpu);
197 break;
198 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
199 cpu = smp_processor_id();
200 *map = mvchip->percpu_regs;
201 *offset = GPIO_EDGE_MASK_ARMADAXP_OFF(cpu);
202 break;
203 default:
204 BUG();
205 }
206 }
207
208 static u32
mvebu_gpio_read_edge_mask(struct mvebu_gpio_chip * mvchip)209 mvebu_gpio_read_edge_mask(struct mvebu_gpio_chip *mvchip)
210 {
211 struct regmap *map;
212 unsigned int offset;
213 u32 val;
214
215 mvebu_gpioreg_edge_mask(mvchip, &map, &offset);
216 regmap_read(map, offset, &val);
217
218 return val;
219 }
220
221 static void
mvebu_gpio_write_edge_mask(struct mvebu_gpio_chip * mvchip,u32 val)222 mvebu_gpio_write_edge_mask(struct mvebu_gpio_chip *mvchip, u32 val)
223 {
224 struct regmap *map;
225 unsigned int offset;
226
227 mvebu_gpioreg_edge_mask(mvchip, &map, &offset);
228 regmap_write(map, offset, val);
229 }
230
231 static void
mvebu_gpioreg_level_mask(struct mvebu_gpio_chip * mvchip,struct regmap ** map,unsigned int * offset)232 mvebu_gpioreg_level_mask(struct mvebu_gpio_chip *mvchip,
233 struct regmap **map, unsigned int *offset)
234 {
235 int cpu;
236
237 switch (mvchip->soc_variant) {
238 case MVEBU_GPIO_SOC_VARIANT_ORION:
239 case MVEBU_GPIO_SOC_VARIANT_A8K:
240 *map = mvchip->regs;
241 *offset = GPIO_LEVEL_MASK_OFF + mvchip->offset;
242 break;
243 case MVEBU_GPIO_SOC_VARIANT_MV78200:
244 cpu = smp_processor_id();
245 *map = mvchip->regs;
246 *offset = GPIO_LEVEL_MASK_MV78200_OFF(cpu);
247 break;
248 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
249 cpu = smp_processor_id();
250 *map = mvchip->percpu_regs;
251 *offset = GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu);
252 break;
253 default:
254 BUG();
255 }
256 }
257
258 static u32
mvebu_gpio_read_level_mask(struct mvebu_gpio_chip * mvchip)259 mvebu_gpio_read_level_mask(struct mvebu_gpio_chip *mvchip)
260 {
261 struct regmap *map;
262 unsigned int offset;
263 u32 val;
264
265 mvebu_gpioreg_level_mask(mvchip, &map, &offset);
266 regmap_read(map, offset, &val);
267
268 return val;
269 }
270
271 static void
mvebu_gpio_write_level_mask(struct mvebu_gpio_chip * mvchip,u32 val)272 mvebu_gpio_write_level_mask(struct mvebu_gpio_chip *mvchip, u32 val)
273 {
274 struct regmap *map;
275 unsigned int offset;
276
277 mvebu_gpioreg_level_mask(mvchip, &map, &offset);
278 regmap_write(map, offset, val);
279 }
280
281 /*
282 * Functions returning addresses of individual registers for a given
283 * PWM controller.
284 */
mvebu_pwmreg_blink_on_duration(struct mvebu_pwm * mvpwm)285 static void __iomem *mvebu_pwmreg_blink_on_duration(struct mvebu_pwm *mvpwm)
286 {
287 return mvpwm->membase + PWM_BLINK_ON_DURATION_OFF;
288 }
289
mvebu_pwmreg_blink_off_duration(struct mvebu_pwm * mvpwm)290 static void __iomem *mvebu_pwmreg_blink_off_duration(struct mvebu_pwm *mvpwm)
291 {
292 return mvpwm->membase + PWM_BLINK_OFF_DURATION_OFF;
293 }
294
295 /*
296 * Functions implementing the gpio_chip methods
297 */
mvebu_gpio_set(struct gpio_chip * chip,unsigned int pin,int value)298 static void mvebu_gpio_set(struct gpio_chip *chip, unsigned int pin, int value)
299 {
300 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
301
302 regmap_update_bits(mvchip->regs, GPIO_OUT_OFF + mvchip->offset,
303 BIT(pin), value ? BIT(pin) : 0);
304 }
305
mvebu_gpio_get(struct gpio_chip * chip,unsigned int pin)306 static int mvebu_gpio_get(struct gpio_chip *chip, unsigned int pin)
307 {
308 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
309 u32 u;
310
311 regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, &u);
312
313 if (u & BIT(pin)) {
314 u32 data_in, in_pol;
315
316 regmap_read(mvchip->regs, GPIO_DATA_IN_OFF + mvchip->offset,
317 &data_in);
318 regmap_read(mvchip->regs, GPIO_IN_POL_OFF + mvchip->offset,
319 &in_pol);
320 u = data_in ^ in_pol;
321 } else {
322 regmap_read(mvchip->regs, GPIO_OUT_OFF + mvchip->offset, &u);
323 }
324
325 return (u >> pin) & 1;
326 }
327
mvebu_gpio_blink(struct gpio_chip * chip,unsigned int pin,int value)328 static void mvebu_gpio_blink(struct gpio_chip *chip, unsigned int pin,
329 int value)
330 {
331 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
332
333 regmap_update_bits(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset,
334 BIT(pin), value ? BIT(pin) : 0);
335 }
336
mvebu_gpio_direction_input(struct gpio_chip * chip,unsigned int pin)337 static int mvebu_gpio_direction_input(struct gpio_chip *chip, unsigned int pin)
338 {
339 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
340 int ret;
341
342 /*
343 * Check with the pinctrl driver whether this pin is usable as
344 * an input GPIO
345 */
346 ret = pinctrl_gpio_direction_input(chip->base + pin);
347 if (ret)
348 return ret;
349
350 regmap_update_bits(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset,
351 BIT(pin), BIT(pin));
352
353 return 0;
354 }
355
mvebu_gpio_direction_output(struct gpio_chip * chip,unsigned int pin,int value)356 static int mvebu_gpio_direction_output(struct gpio_chip *chip, unsigned int pin,
357 int value)
358 {
359 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
360 int ret;
361
362 /*
363 * Check with the pinctrl driver whether this pin is usable as
364 * an output GPIO
365 */
366 ret = pinctrl_gpio_direction_output(chip->base + pin);
367 if (ret)
368 return ret;
369
370 mvebu_gpio_blink(chip, pin, 0);
371 mvebu_gpio_set(chip, pin, value);
372
373 regmap_update_bits(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset,
374 BIT(pin), 0);
375
376 return 0;
377 }
378
mvebu_gpio_to_irq(struct gpio_chip * chip,unsigned int pin)379 static int mvebu_gpio_to_irq(struct gpio_chip *chip, unsigned int pin)
380 {
381 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
382
383 return irq_create_mapping(mvchip->domain, pin);
384 }
385
386 /*
387 * Functions implementing the irq_chip methods
388 */
mvebu_gpio_irq_ack(struct irq_data * d)389 static void mvebu_gpio_irq_ack(struct irq_data *d)
390 {
391 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
392 struct mvebu_gpio_chip *mvchip = gc->private;
393 u32 mask = d->mask;
394
395 irq_gc_lock(gc);
396 mvebu_gpio_write_edge_cause(mvchip, ~mask);
397 irq_gc_unlock(gc);
398 }
399
mvebu_gpio_edge_irq_mask(struct irq_data * d)400 static void mvebu_gpio_edge_irq_mask(struct irq_data *d)
401 {
402 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
403 struct mvebu_gpio_chip *mvchip = gc->private;
404 struct irq_chip_type *ct = irq_data_get_chip_type(d);
405 u32 mask = d->mask;
406
407 irq_gc_lock(gc);
408 ct->mask_cache_priv &= ~mask;
409 mvebu_gpio_write_edge_mask(mvchip, ct->mask_cache_priv);
410 irq_gc_unlock(gc);
411 }
412
mvebu_gpio_edge_irq_unmask(struct irq_data * d)413 static void mvebu_gpio_edge_irq_unmask(struct irq_data *d)
414 {
415 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
416 struct mvebu_gpio_chip *mvchip = gc->private;
417 struct irq_chip_type *ct = irq_data_get_chip_type(d);
418 u32 mask = d->mask;
419
420 irq_gc_lock(gc);
421 ct->mask_cache_priv |= mask;
422 mvebu_gpio_write_edge_mask(mvchip, ct->mask_cache_priv);
423 irq_gc_unlock(gc);
424 }
425
mvebu_gpio_level_irq_mask(struct irq_data * d)426 static void mvebu_gpio_level_irq_mask(struct irq_data *d)
427 {
428 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
429 struct mvebu_gpio_chip *mvchip = gc->private;
430 struct irq_chip_type *ct = irq_data_get_chip_type(d);
431 u32 mask = d->mask;
432
433 irq_gc_lock(gc);
434 ct->mask_cache_priv &= ~mask;
435 mvebu_gpio_write_level_mask(mvchip, ct->mask_cache_priv);
436 irq_gc_unlock(gc);
437 }
438
mvebu_gpio_level_irq_unmask(struct irq_data * d)439 static void mvebu_gpio_level_irq_unmask(struct irq_data *d)
440 {
441 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
442 struct mvebu_gpio_chip *mvchip = gc->private;
443 struct irq_chip_type *ct = irq_data_get_chip_type(d);
444 u32 mask = d->mask;
445
446 irq_gc_lock(gc);
447 ct->mask_cache_priv |= mask;
448 mvebu_gpio_write_level_mask(mvchip, ct->mask_cache_priv);
449 irq_gc_unlock(gc);
450 }
451
452 /*****************************************************************************
453 * MVEBU GPIO IRQ
454 *
455 * GPIO_IN_POL register controls whether GPIO_DATA_IN will hold the same
456 * value of the line or the opposite value.
457 *
458 * Level IRQ handlers: DATA_IN is used directly as cause register.
459 * Interrupt are masked by LEVEL_MASK registers.
460 * Edge IRQ handlers: Change in DATA_IN are latched in EDGE_CAUSE.
461 * Interrupt are masked by EDGE_MASK registers.
462 * Both-edge handlers: Similar to regular Edge handlers, but also swaps
463 * the polarity to catch the next line transaction.
464 * This is a race condition that might not perfectly
465 * work on some use cases.
466 *
467 * Every eight GPIO lines are grouped (OR'ed) before going up to main
468 * cause register.
469 *
470 * EDGE cause mask
471 * data-in /--------| |-----| |----\
472 * -----| |----- ---- to main cause reg
473 * X \----------------| |----/
474 * polarity LEVEL mask
475 *
476 ****************************************************************************/
477
mvebu_gpio_irq_set_type(struct irq_data * d,unsigned int type)478 static int mvebu_gpio_irq_set_type(struct irq_data *d, unsigned int type)
479 {
480 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
481 struct irq_chip_type *ct = irq_data_get_chip_type(d);
482 struct mvebu_gpio_chip *mvchip = gc->private;
483 int pin;
484 u32 u;
485
486 pin = d->hwirq;
487
488 regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, &u);
489 if ((u & BIT(pin)) == 0)
490 return -EINVAL;
491
492 type &= IRQ_TYPE_SENSE_MASK;
493 if (type == IRQ_TYPE_NONE)
494 return -EINVAL;
495
496 /* Check if we need to change chip and handler */
497 if (!(ct->type & type))
498 if (irq_setup_alt_chip(d, type))
499 return -EINVAL;
500
501 /*
502 * Configure interrupt polarity.
503 */
504 switch (type) {
505 case IRQ_TYPE_EDGE_RISING:
506 case IRQ_TYPE_LEVEL_HIGH:
507 regmap_update_bits(mvchip->regs,
508 GPIO_IN_POL_OFF + mvchip->offset,
509 BIT(pin), 0);
510 break;
511 case IRQ_TYPE_EDGE_FALLING:
512 case IRQ_TYPE_LEVEL_LOW:
513 regmap_update_bits(mvchip->regs,
514 GPIO_IN_POL_OFF + mvchip->offset,
515 BIT(pin), BIT(pin));
516 break;
517 case IRQ_TYPE_EDGE_BOTH: {
518 u32 data_in, in_pol, val;
519
520 regmap_read(mvchip->regs,
521 GPIO_IN_POL_OFF + mvchip->offset, &in_pol);
522 regmap_read(mvchip->regs,
523 GPIO_DATA_IN_OFF + mvchip->offset, &data_in);
524
525 /*
526 * set initial polarity based on current input level
527 */
528 if ((data_in ^ in_pol) & BIT(pin))
529 val = BIT(pin); /* falling */
530 else
531 val = 0; /* raising */
532
533 regmap_update_bits(mvchip->regs,
534 GPIO_IN_POL_OFF + mvchip->offset,
535 BIT(pin), val);
536 break;
537 }
538 }
539 return 0;
540 }
541
mvebu_gpio_irq_handler(struct irq_desc * desc)542 static void mvebu_gpio_irq_handler(struct irq_desc *desc)
543 {
544 struct mvebu_gpio_chip *mvchip = irq_desc_get_handler_data(desc);
545 struct irq_chip *chip = irq_desc_get_chip(desc);
546 u32 cause, type, data_in, level_mask, edge_cause, edge_mask;
547 int i;
548
549 if (mvchip == NULL)
550 return;
551
552 chained_irq_enter(chip, desc);
553
554 regmap_read(mvchip->regs, GPIO_DATA_IN_OFF + mvchip->offset, &data_in);
555 level_mask = mvebu_gpio_read_level_mask(mvchip);
556 edge_cause = mvebu_gpio_read_edge_cause(mvchip);
557 edge_mask = mvebu_gpio_read_edge_mask(mvchip);
558
559 cause = (data_in & level_mask) | (edge_cause & edge_mask);
560
561 for (i = 0; i < mvchip->chip.ngpio; i++) {
562 int irq;
563
564 irq = irq_find_mapping(mvchip->domain, i);
565
566 if (!(cause & BIT(i)))
567 continue;
568
569 type = irq_get_trigger_type(irq);
570 if ((type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
571 /* Swap polarity (race with GPIO line) */
572 u32 polarity;
573
574 regmap_read(mvchip->regs,
575 GPIO_IN_POL_OFF + mvchip->offset,
576 &polarity);
577 polarity ^= BIT(i);
578 regmap_write(mvchip->regs,
579 GPIO_IN_POL_OFF + mvchip->offset,
580 polarity);
581 }
582
583 generic_handle_irq(irq);
584 }
585
586 chained_irq_exit(chip, desc);
587 }
588
589 /*
590 * Functions implementing the pwm_chip methods
591 */
to_mvebu_pwm(struct pwm_chip * chip)592 static struct mvebu_pwm *to_mvebu_pwm(struct pwm_chip *chip)
593 {
594 return container_of(chip, struct mvebu_pwm, chip);
595 }
596
mvebu_pwm_request(struct pwm_chip * chip,struct pwm_device * pwm)597 static int mvebu_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
598 {
599 struct mvebu_pwm *mvpwm = to_mvebu_pwm(chip);
600 struct mvebu_gpio_chip *mvchip = mvpwm->mvchip;
601 struct gpio_desc *desc;
602 unsigned long flags;
603 int ret = 0;
604
605 spin_lock_irqsave(&mvpwm->lock, flags);
606
607 if (mvpwm->gpiod) {
608 ret = -EBUSY;
609 } else {
610 desc = gpiochip_request_own_desc(&mvchip->chip,
611 pwm->hwpwm, "mvebu-pwm");
612 if (IS_ERR(desc)) {
613 ret = PTR_ERR(desc);
614 goto out;
615 }
616
617 ret = gpiod_direction_output(desc, 0);
618 if (ret) {
619 gpiochip_free_own_desc(desc);
620 goto out;
621 }
622
623 mvpwm->gpiod = desc;
624 }
625 out:
626 spin_unlock_irqrestore(&mvpwm->lock, flags);
627 return ret;
628 }
629
mvebu_pwm_free(struct pwm_chip * chip,struct pwm_device * pwm)630 static void mvebu_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
631 {
632 struct mvebu_pwm *mvpwm = to_mvebu_pwm(chip);
633 unsigned long flags;
634
635 spin_lock_irqsave(&mvpwm->lock, flags);
636 gpiochip_free_own_desc(mvpwm->gpiod);
637 mvpwm->gpiod = NULL;
638 spin_unlock_irqrestore(&mvpwm->lock, flags);
639 }
640
mvebu_pwm_get_state(struct pwm_chip * chip,struct pwm_device * pwm,struct pwm_state * state)641 static void mvebu_pwm_get_state(struct pwm_chip *chip,
642 struct pwm_device *pwm,
643 struct pwm_state *state) {
644
645 struct mvebu_pwm *mvpwm = to_mvebu_pwm(chip);
646 struct mvebu_gpio_chip *mvchip = mvpwm->mvchip;
647 unsigned long long val;
648 unsigned long flags;
649 u32 u;
650
651 spin_lock_irqsave(&mvpwm->lock, flags);
652
653 val = (unsigned long long)
654 readl_relaxed(mvebu_pwmreg_blink_on_duration(mvpwm));
655 val *= NSEC_PER_SEC;
656 do_div(val, mvpwm->clk_rate);
657 if (val > UINT_MAX)
658 state->duty_cycle = UINT_MAX;
659 else if (val)
660 state->duty_cycle = val;
661 else
662 state->duty_cycle = 1;
663
664 val = (unsigned long long)
665 readl_relaxed(mvebu_pwmreg_blink_off_duration(mvpwm));
666 val *= NSEC_PER_SEC;
667 do_div(val, mvpwm->clk_rate);
668 if (val < state->duty_cycle) {
669 state->period = 1;
670 } else {
671 val -= state->duty_cycle;
672 if (val > UINT_MAX)
673 state->period = UINT_MAX;
674 else if (val)
675 state->period = val;
676 else
677 state->period = 1;
678 }
679
680 regmap_read(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset, &u);
681 if (u)
682 state->enabled = true;
683 else
684 state->enabled = false;
685
686 spin_unlock_irqrestore(&mvpwm->lock, flags);
687 }
688
mvebu_pwm_apply(struct pwm_chip * chip,struct pwm_device * pwm,struct pwm_state * state)689 static int mvebu_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
690 struct pwm_state *state)
691 {
692 struct mvebu_pwm *mvpwm = to_mvebu_pwm(chip);
693 struct mvebu_gpio_chip *mvchip = mvpwm->mvchip;
694 unsigned long long val;
695 unsigned long flags;
696 unsigned int on, off;
697
698 val = (unsigned long long) mvpwm->clk_rate * state->duty_cycle;
699 do_div(val, NSEC_PER_SEC);
700 if (val > UINT_MAX)
701 return -EINVAL;
702 if (val)
703 on = val;
704 else
705 on = 1;
706
707 val = (unsigned long long) mvpwm->clk_rate *
708 (state->period - state->duty_cycle);
709 do_div(val, NSEC_PER_SEC);
710 if (val > UINT_MAX)
711 return -EINVAL;
712 if (val)
713 off = val;
714 else
715 off = 1;
716
717 spin_lock_irqsave(&mvpwm->lock, flags);
718
719 writel_relaxed(on, mvebu_pwmreg_blink_on_duration(mvpwm));
720 writel_relaxed(off, mvebu_pwmreg_blink_off_duration(mvpwm));
721 if (state->enabled)
722 mvebu_gpio_blink(&mvchip->chip, pwm->hwpwm, 1);
723 else
724 mvebu_gpio_blink(&mvchip->chip, pwm->hwpwm, 0);
725
726 spin_unlock_irqrestore(&mvpwm->lock, flags);
727
728 return 0;
729 }
730
731 static const struct pwm_ops mvebu_pwm_ops = {
732 .request = mvebu_pwm_request,
733 .free = mvebu_pwm_free,
734 .get_state = mvebu_pwm_get_state,
735 .apply = mvebu_pwm_apply,
736 .owner = THIS_MODULE,
737 };
738
mvebu_pwm_suspend(struct mvebu_gpio_chip * mvchip)739 static void __maybe_unused mvebu_pwm_suspend(struct mvebu_gpio_chip *mvchip)
740 {
741 struct mvebu_pwm *mvpwm = mvchip->mvpwm;
742
743 regmap_read(mvchip->regs, GPIO_BLINK_CNT_SELECT_OFF + mvchip->offset,
744 &mvpwm->blink_select);
745 mvpwm->blink_on_duration =
746 readl_relaxed(mvebu_pwmreg_blink_on_duration(mvpwm));
747 mvpwm->blink_off_duration =
748 readl_relaxed(mvebu_pwmreg_blink_off_duration(mvpwm));
749 }
750
mvebu_pwm_resume(struct mvebu_gpio_chip * mvchip)751 static void __maybe_unused mvebu_pwm_resume(struct mvebu_gpio_chip *mvchip)
752 {
753 struct mvebu_pwm *mvpwm = mvchip->mvpwm;
754
755 regmap_write(mvchip->regs, GPIO_BLINK_CNT_SELECT_OFF + mvchip->offset,
756 mvpwm->blink_select);
757 writel_relaxed(mvpwm->blink_on_duration,
758 mvebu_pwmreg_blink_on_duration(mvpwm));
759 writel_relaxed(mvpwm->blink_off_duration,
760 mvebu_pwmreg_blink_off_duration(mvpwm));
761 }
762
mvebu_pwm_probe(struct platform_device * pdev,struct mvebu_gpio_chip * mvchip,int id)763 static int mvebu_pwm_probe(struct platform_device *pdev,
764 struct mvebu_gpio_chip *mvchip,
765 int id)
766 {
767 struct device *dev = &pdev->dev;
768 struct mvebu_pwm *mvpwm;
769 struct resource *res;
770 u32 set;
771
772 if (!of_device_is_compatible(mvchip->chip.of_node,
773 "marvell,armada-370-gpio"))
774 return 0;
775
776 if (IS_ERR(mvchip->clk))
777 return PTR_ERR(mvchip->clk);
778
779 /*
780 * There are only two sets of PWM configuration registers for
781 * all the GPIO lines on those SoCs which this driver reserves
782 * for the first two GPIO chips. So if the resource is missing
783 * we can't treat it as an error.
784 */
785 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pwm");
786 if (!res)
787 return 0;
788
789 /*
790 * Use set A for lines of GPIO chip with id 0, B for GPIO chip
791 * with id 1. Don't allow further GPIO chips to be used for PWM.
792 */
793 if (id == 0)
794 set = 0;
795 else if (id == 1)
796 set = U32_MAX;
797 else
798 return -EINVAL;
799 regmap_write(mvchip->regs,
800 GPIO_BLINK_CNT_SELECT_OFF + mvchip->offset, set);
801
802 mvpwm = devm_kzalloc(dev, sizeof(struct mvebu_pwm), GFP_KERNEL);
803 if (!mvpwm)
804 return -ENOMEM;
805 mvchip->mvpwm = mvpwm;
806 mvpwm->mvchip = mvchip;
807
808 mvpwm->membase = devm_ioremap_resource(dev, res);
809 if (IS_ERR(mvpwm->membase))
810 return PTR_ERR(mvpwm->membase);
811
812 mvpwm->clk_rate = clk_get_rate(mvchip->clk);
813 if (!mvpwm->clk_rate) {
814 dev_err(dev, "failed to get clock rate\n");
815 return -EINVAL;
816 }
817
818 mvpwm->chip.dev = dev;
819 mvpwm->chip.ops = &mvebu_pwm_ops;
820 mvpwm->chip.npwm = mvchip->chip.ngpio;
821 /*
822 * There may already be some PWM allocated, so we can't force
823 * mvpwm->chip.base to a fixed point like mvchip->chip.base.
824 * So, we let pwmchip_add() do the numbering and take the next free
825 * region.
826 */
827 mvpwm->chip.base = -1;
828
829 spin_lock_init(&mvpwm->lock);
830
831 return pwmchip_add(&mvpwm->chip);
832 }
833
834 #ifdef CONFIG_DEBUG_FS
835 #include <linux/seq_file.h>
836
mvebu_gpio_dbg_show(struct seq_file * s,struct gpio_chip * chip)837 static void mvebu_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
838 {
839 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
840 u32 out, io_conf, blink, in_pol, data_in, cause, edg_msk, lvl_msk;
841 int i;
842
843 regmap_read(mvchip->regs, GPIO_OUT_OFF + mvchip->offset, &out);
844 regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, &io_conf);
845 regmap_read(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset, &blink);
846 regmap_read(mvchip->regs, GPIO_IN_POL_OFF + mvchip->offset, &in_pol);
847 regmap_read(mvchip->regs, GPIO_DATA_IN_OFF + mvchip->offset, &data_in);
848 cause = mvebu_gpio_read_edge_cause(mvchip);
849 edg_msk = mvebu_gpio_read_edge_mask(mvchip);
850 lvl_msk = mvebu_gpio_read_level_mask(mvchip);
851
852 for (i = 0; i < chip->ngpio; i++) {
853 const char *label;
854 u32 msk;
855 bool is_out;
856
857 label = gpiochip_is_requested(chip, i);
858 if (!label)
859 continue;
860
861 msk = BIT(i);
862 is_out = !(io_conf & msk);
863
864 seq_printf(s, " gpio-%-3d (%-20.20s)", chip->base + i, label);
865
866 if (is_out) {
867 seq_printf(s, " out %s %s\n",
868 out & msk ? "hi" : "lo",
869 blink & msk ? "(blink )" : "");
870 continue;
871 }
872
873 seq_printf(s, " in %s (act %s) - IRQ",
874 (data_in ^ in_pol) & msk ? "hi" : "lo",
875 in_pol & msk ? "lo" : "hi");
876 if (!((edg_msk | lvl_msk) & msk)) {
877 seq_puts(s, " disabled\n");
878 continue;
879 }
880 if (edg_msk & msk)
881 seq_puts(s, " edge ");
882 if (lvl_msk & msk)
883 seq_puts(s, " level");
884 seq_printf(s, " (%s)\n", cause & msk ? "pending" : "clear ");
885 }
886 }
887 #else
888 #define mvebu_gpio_dbg_show NULL
889 #endif
890
891 static const struct of_device_id mvebu_gpio_of_match[] = {
892 {
893 .compatible = "marvell,orion-gpio",
894 .data = (void *) MVEBU_GPIO_SOC_VARIANT_ORION,
895 },
896 {
897 .compatible = "marvell,mv78200-gpio",
898 .data = (void *) MVEBU_GPIO_SOC_VARIANT_MV78200,
899 },
900 {
901 .compatible = "marvell,armadaxp-gpio",
902 .data = (void *) MVEBU_GPIO_SOC_VARIANT_ARMADAXP,
903 },
904 {
905 .compatible = "marvell,armada-370-gpio",
906 .data = (void *) MVEBU_GPIO_SOC_VARIANT_ORION,
907 },
908 {
909 .compatible = "marvell,armada-8k-gpio",
910 .data = (void *) MVEBU_GPIO_SOC_VARIANT_A8K,
911 },
912 {
913 /* sentinel */
914 },
915 };
916
mvebu_gpio_suspend(struct platform_device * pdev,pm_message_t state)917 static int mvebu_gpio_suspend(struct platform_device *pdev, pm_message_t state)
918 {
919 struct mvebu_gpio_chip *mvchip = platform_get_drvdata(pdev);
920 int i;
921
922 regmap_read(mvchip->regs, GPIO_OUT_OFF + mvchip->offset,
923 &mvchip->out_reg);
924 regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset,
925 &mvchip->io_conf_reg);
926 regmap_read(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset,
927 &mvchip->blink_en_reg);
928 regmap_read(mvchip->regs, GPIO_IN_POL_OFF + mvchip->offset,
929 &mvchip->in_pol_reg);
930
931 switch (mvchip->soc_variant) {
932 case MVEBU_GPIO_SOC_VARIANT_ORION:
933 case MVEBU_GPIO_SOC_VARIANT_A8K:
934 regmap_read(mvchip->regs, GPIO_EDGE_MASK_OFF + mvchip->offset,
935 &mvchip->edge_mask_regs[0]);
936 regmap_read(mvchip->regs, GPIO_LEVEL_MASK_OFF + mvchip->offset,
937 &mvchip->level_mask_regs[0]);
938 break;
939 case MVEBU_GPIO_SOC_VARIANT_MV78200:
940 for (i = 0; i < 2; i++) {
941 regmap_read(mvchip->regs,
942 GPIO_EDGE_MASK_MV78200_OFF(i),
943 &mvchip->edge_mask_regs[i]);
944 regmap_read(mvchip->regs,
945 GPIO_LEVEL_MASK_MV78200_OFF(i),
946 &mvchip->level_mask_regs[i]);
947 }
948 break;
949 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
950 for (i = 0; i < 4; i++) {
951 regmap_read(mvchip->regs,
952 GPIO_EDGE_MASK_ARMADAXP_OFF(i),
953 &mvchip->edge_mask_regs[i]);
954 regmap_read(mvchip->regs,
955 GPIO_LEVEL_MASK_ARMADAXP_OFF(i),
956 &mvchip->level_mask_regs[i]);
957 }
958 break;
959 default:
960 BUG();
961 }
962
963 if (IS_ENABLED(CONFIG_PWM))
964 mvebu_pwm_suspend(mvchip);
965
966 return 0;
967 }
968
mvebu_gpio_resume(struct platform_device * pdev)969 static int mvebu_gpio_resume(struct platform_device *pdev)
970 {
971 struct mvebu_gpio_chip *mvchip = platform_get_drvdata(pdev);
972 int i;
973
974 regmap_write(mvchip->regs, GPIO_OUT_OFF + mvchip->offset,
975 mvchip->out_reg);
976 regmap_write(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset,
977 mvchip->io_conf_reg);
978 regmap_write(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset,
979 mvchip->blink_en_reg);
980 regmap_write(mvchip->regs, GPIO_IN_POL_OFF + mvchip->offset,
981 mvchip->in_pol_reg);
982
983 switch (mvchip->soc_variant) {
984 case MVEBU_GPIO_SOC_VARIANT_ORION:
985 case MVEBU_GPIO_SOC_VARIANT_A8K:
986 regmap_write(mvchip->regs, GPIO_EDGE_MASK_OFF + mvchip->offset,
987 mvchip->edge_mask_regs[0]);
988 regmap_write(mvchip->regs, GPIO_LEVEL_MASK_OFF + mvchip->offset,
989 mvchip->level_mask_regs[0]);
990 break;
991 case MVEBU_GPIO_SOC_VARIANT_MV78200:
992 for (i = 0; i < 2; i++) {
993 regmap_write(mvchip->regs,
994 GPIO_EDGE_MASK_MV78200_OFF(i),
995 mvchip->edge_mask_regs[i]);
996 regmap_write(mvchip->regs,
997 GPIO_LEVEL_MASK_MV78200_OFF(i),
998 mvchip->level_mask_regs[i]);
999 }
1000 break;
1001 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
1002 for (i = 0; i < 4; i++) {
1003 regmap_write(mvchip->regs,
1004 GPIO_EDGE_MASK_ARMADAXP_OFF(i),
1005 mvchip->edge_mask_regs[i]);
1006 regmap_write(mvchip->regs,
1007 GPIO_LEVEL_MASK_ARMADAXP_OFF(i),
1008 mvchip->level_mask_regs[i]);
1009 }
1010 break;
1011 default:
1012 BUG();
1013 }
1014
1015 if (IS_ENABLED(CONFIG_PWM))
1016 mvebu_pwm_resume(mvchip);
1017
1018 return 0;
1019 }
1020
1021 static const struct regmap_config mvebu_gpio_regmap_config = {
1022 .reg_bits = 32,
1023 .reg_stride = 4,
1024 .val_bits = 32,
1025 .fast_io = true,
1026 };
1027
mvebu_gpio_probe_raw(struct platform_device * pdev,struct mvebu_gpio_chip * mvchip)1028 static int mvebu_gpio_probe_raw(struct platform_device *pdev,
1029 struct mvebu_gpio_chip *mvchip)
1030 {
1031 struct resource *res;
1032 void __iomem *base;
1033
1034 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1035 base = devm_ioremap_resource(&pdev->dev, res);
1036 if (IS_ERR(base))
1037 return PTR_ERR(base);
1038
1039 mvchip->regs = devm_regmap_init_mmio(&pdev->dev, base,
1040 &mvebu_gpio_regmap_config);
1041 if (IS_ERR(mvchip->regs))
1042 return PTR_ERR(mvchip->regs);
1043
1044 /*
1045 * For the legacy SoCs, the regmap directly maps to the GPIO
1046 * registers, so no offset is needed.
1047 */
1048 mvchip->offset = 0;
1049
1050 /*
1051 * The Armada XP has a second range of registers for the
1052 * per-CPU registers
1053 */
1054 if (mvchip->soc_variant == MVEBU_GPIO_SOC_VARIANT_ARMADAXP) {
1055 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1056 base = devm_ioremap_resource(&pdev->dev, res);
1057 if (IS_ERR(base))
1058 return PTR_ERR(base);
1059
1060 mvchip->percpu_regs =
1061 devm_regmap_init_mmio(&pdev->dev, base,
1062 &mvebu_gpio_regmap_config);
1063 if (IS_ERR(mvchip->percpu_regs))
1064 return PTR_ERR(mvchip->percpu_regs);
1065 }
1066
1067 return 0;
1068 }
1069
mvebu_gpio_probe_syscon(struct platform_device * pdev,struct mvebu_gpio_chip * mvchip)1070 static int mvebu_gpio_probe_syscon(struct platform_device *pdev,
1071 struct mvebu_gpio_chip *mvchip)
1072 {
1073 mvchip->regs = syscon_node_to_regmap(pdev->dev.parent->of_node);
1074 if (IS_ERR(mvchip->regs))
1075 return PTR_ERR(mvchip->regs);
1076
1077 if (of_property_read_u32(pdev->dev.of_node, "offset", &mvchip->offset))
1078 return -EINVAL;
1079
1080 return 0;
1081 }
1082
mvebu_gpio_probe(struct platform_device * pdev)1083 static int mvebu_gpio_probe(struct platform_device *pdev)
1084 {
1085 struct mvebu_gpio_chip *mvchip;
1086 const struct of_device_id *match;
1087 struct device_node *np = pdev->dev.of_node;
1088 struct irq_chip_generic *gc;
1089 struct irq_chip_type *ct;
1090 unsigned int ngpios;
1091 bool have_irqs;
1092 int soc_variant;
1093 int i, cpu, id;
1094 int err;
1095
1096 match = of_match_device(mvebu_gpio_of_match, &pdev->dev);
1097 if (match)
1098 soc_variant = (unsigned long) match->data;
1099 else
1100 soc_variant = MVEBU_GPIO_SOC_VARIANT_ORION;
1101
1102 /* Some gpio controllers do not provide irq support */
1103 have_irqs = of_irq_count(np) != 0;
1104
1105 mvchip = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_gpio_chip),
1106 GFP_KERNEL);
1107 if (!mvchip)
1108 return -ENOMEM;
1109
1110 platform_set_drvdata(pdev, mvchip);
1111
1112 if (of_property_read_u32(pdev->dev.of_node, "ngpios", &ngpios)) {
1113 dev_err(&pdev->dev, "Missing ngpios OF property\n");
1114 return -ENODEV;
1115 }
1116
1117 id = of_alias_get_id(pdev->dev.of_node, "gpio");
1118 if (id < 0) {
1119 dev_err(&pdev->dev, "Couldn't get OF id\n");
1120 return id;
1121 }
1122
1123 mvchip->clk = devm_clk_get(&pdev->dev, NULL);
1124 /* Not all SoCs require a clock.*/
1125 if (!IS_ERR(mvchip->clk))
1126 clk_prepare_enable(mvchip->clk);
1127
1128 mvchip->soc_variant = soc_variant;
1129 mvchip->chip.label = dev_name(&pdev->dev);
1130 mvchip->chip.parent = &pdev->dev;
1131 mvchip->chip.request = gpiochip_generic_request;
1132 mvchip->chip.free = gpiochip_generic_free;
1133 mvchip->chip.direction_input = mvebu_gpio_direction_input;
1134 mvchip->chip.get = mvebu_gpio_get;
1135 mvchip->chip.direction_output = mvebu_gpio_direction_output;
1136 mvchip->chip.set = mvebu_gpio_set;
1137 if (have_irqs)
1138 mvchip->chip.to_irq = mvebu_gpio_to_irq;
1139 mvchip->chip.base = id * MVEBU_MAX_GPIO_PER_BANK;
1140 mvchip->chip.ngpio = ngpios;
1141 mvchip->chip.can_sleep = false;
1142 mvchip->chip.of_node = np;
1143 mvchip->chip.dbg_show = mvebu_gpio_dbg_show;
1144
1145 if (soc_variant == MVEBU_GPIO_SOC_VARIANT_A8K)
1146 err = mvebu_gpio_probe_syscon(pdev, mvchip);
1147 else
1148 err = mvebu_gpio_probe_raw(pdev, mvchip);
1149
1150 if (err)
1151 return err;
1152
1153 /*
1154 * Mask and clear GPIO interrupts.
1155 */
1156 switch (soc_variant) {
1157 case MVEBU_GPIO_SOC_VARIANT_ORION:
1158 case MVEBU_GPIO_SOC_VARIANT_A8K:
1159 regmap_write(mvchip->regs,
1160 GPIO_EDGE_CAUSE_OFF + mvchip->offset, 0);
1161 regmap_write(mvchip->regs,
1162 GPIO_EDGE_MASK_OFF + mvchip->offset, 0);
1163 regmap_write(mvchip->regs,
1164 GPIO_LEVEL_MASK_OFF + mvchip->offset, 0);
1165 break;
1166 case MVEBU_GPIO_SOC_VARIANT_MV78200:
1167 regmap_write(mvchip->regs, GPIO_EDGE_CAUSE_OFF, 0);
1168 for (cpu = 0; cpu < 2; cpu++) {
1169 regmap_write(mvchip->regs,
1170 GPIO_EDGE_MASK_MV78200_OFF(cpu), 0);
1171 regmap_write(mvchip->regs,
1172 GPIO_LEVEL_MASK_MV78200_OFF(cpu), 0);
1173 }
1174 break;
1175 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
1176 regmap_write(mvchip->regs, GPIO_EDGE_CAUSE_OFF, 0);
1177 regmap_write(mvchip->regs, GPIO_EDGE_MASK_OFF, 0);
1178 regmap_write(mvchip->regs, GPIO_LEVEL_MASK_OFF, 0);
1179 for (cpu = 0; cpu < 4; cpu++) {
1180 regmap_write(mvchip->percpu_regs,
1181 GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu), 0);
1182 regmap_write(mvchip->percpu_regs,
1183 GPIO_EDGE_MASK_ARMADAXP_OFF(cpu), 0);
1184 regmap_write(mvchip->percpu_regs,
1185 GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu), 0);
1186 }
1187 break;
1188 default:
1189 BUG();
1190 }
1191
1192 devm_gpiochip_add_data(&pdev->dev, &mvchip->chip, mvchip);
1193
1194 /* Some gpio controllers do not provide irq support */
1195 if (!have_irqs)
1196 return 0;
1197
1198 mvchip->domain =
1199 irq_domain_add_linear(np, ngpios, &irq_generic_chip_ops, NULL);
1200 if (!mvchip->domain) {
1201 dev_err(&pdev->dev, "couldn't allocate irq domain %s (DT).\n",
1202 mvchip->chip.label);
1203 return -ENODEV;
1204 }
1205
1206 err = irq_alloc_domain_generic_chips(
1207 mvchip->domain, ngpios, 2, np->name, handle_level_irq,
1208 IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_LEVEL, 0, 0);
1209 if (err) {
1210 dev_err(&pdev->dev, "couldn't allocate irq chips %s (DT).\n",
1211 mvchip->chip.label);
1212 goto err_domain;
1213 }
1214
1215 /*
1216 * NOTE: The common accessors cannot be used because of the percpu
1217 * access to the mask registers
1218 */
1219 gc = irq_get_domain_generic_chip(mvchip->domain, 0);
1220 gc->private = mvchip;
1221 ct = &gc->chip_types[0];
1222 ct->type = IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW;
1223 ct->chip.irq_mask = mvebu_gpio_level_irq_mask;
1224 ct->chip.irq_unmask = mvebu_gpio_level_irq_unmask;
1225 ct->chip.irq_set_type = mvebu_gpio_irq_set_type;
1226 ct->chip.name = mvchip->chip.label;
1227
1228 ct = &gc->chip_types[1];
1229 ct->type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
1230 ct->chip.irq_ack = mvebu_gpio_irq_ack;
1231 ct->chip.irq_mask = mvebu_gpio_edge_irq_mask;
1232 ct->chip.irq_unmask = mvebu_gpio_edge_irq_unmask;
1233 ct->chip.irq_set_type = mvebu_gpio_irq_set_type;
1234 ct->handler = handle_edge_irq;
1235 ct->chip.name = mvchip->chip.label;
1236
1237 /*
1238 * Setup the interrupt handlers. Each chip can have up to 4
1239 * interrupt handlers, with each handler dealing with 8 GPIO
1240 * pins.
1241 */
1242 for (i = 0; i < 4; i++) {
1243 int irq = platform_get_irq(pdev, i);
1244
1245 if (irq < 0)
1246 continue;
1247 irq_set_chained_handler_and_data(irq, mvebu_gpio_irq_handler,
1248 mvchip);
1249 }
1250
1251 /* Some MVEBU SoCs have simple PWM support for GPIO lines */
1252 if (IS_ENABLED(CONFIG_PWM))
1253 return mvebu_pwm_probe(pdev, mvchip, id);
1254
1255 return 0;
1256
1257 err_domain:
1258 irq_domain_remove(mvchip->domain);
1259
1260 return err;
1261 }
1262
1263 static struct platform_driver mvebu_gpio_driver = {
1264 .driver = {
1265 .name = "mvebu-gpio",
1266 .of_match_table = mvebu_gpio_of_match,
1267 },
1268 .probe = mvebu_gpio_probe,
1269 .suspend = mvebu_gpio_suspend,
1270 .resume = mvebu_gpio_resume,
1271 };
1272 builtin_platform_driver(mvebu_gpio_driver);
1273
