1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2010 OKI SEMICONDUCTOR Co., LTD.
4 */
5 #include <linux/module.h>
6 #include <linux/kernel.h>
7 #include <linux/slab.h>
8 #include <linux/pci.h>
9 #include <linux/gpio/driver.h>
10 #include <linux/interrupt.h>
11 #include <linux/irq.h>
12
13 #define IOH_EDGE_FALLING 0
14 #define IOH_EDGE_RISING BIT(0)
15 #define IOH_LEVEL_L BIT(1)
16 #define IOH_LEVEL_H (BIT(0) | BIT(1))
17 #define IOH_EDGE_BOTH BIT(2)
18 #define IOH_IM_MASK (BIT(0) | BIT(1) | BIT(2))
19
20 #define IOH_IRQ_BASE 0
21
22 struct ioh_reg_comn {
23 u32 ien;
24 u32 istatus;
25 u32 idisp;
26 u32 iclr;
27 u32 imask;
28 u32 imaskclr;
29 u32 po;
30 u32 pi;
31 u32 pm;
32 u32 im_0;
33 u32 im_1;
34 u32 reserved;
35 };
36
37 struct ioh_regs {
38 struct ioh_reg_comn regs[8];
39 u32 reserve1[16];
40 u32 ioh_sel_reg[4];
41 u32 reserve2[11];
42 u32 srst;
43 };
44
45 /**
46 * struct ioh_gpio_reg_data - The register store data.
47 * @ien_reg: To store contents of interrupt enable register.
48 * @imask_reg: To store contents of interrupt mask regist
49 * @po_reg: To store contents of PO register.
50 * @pm_reg: To store contents of PM register.
51 * @im0_reg: To store contents of interrupt mode regist0
52 * @im1_reg: To store contents of interrupt mode regist1
53 * @use_sel_reg: To store contents of GPIO_USE_SEL0~3
54 */
55 struct ioh_gpio_reg_data {
56 u32 ien_reg;
57 u32 imask_reg;
58 u32 po_reg;
59 u32 pm_reg;
60 u32 im0_reg;
61 u32 im1_reg;
62 u32 use_sel_reg;
63 };
64
65 /**
66 * struct ioh_gpio - GPIO private data structure.
67 * @base: PCI base address of Memory mapped I/O register.
68 * @reg: Memory mapped IOH GPIO register list.
69 * @dev: Pointer to device structure.
70 * @gpio: Data for GPIO infrastructure.
71 * @ioh_gpio_reg: Memory mapped Register data is saved here
72 * when suspend.
73 * @gpio_use_sel: Save GPIO_USE_SEL1~4 register for PM
74 * @ch: Indicate GPIO channel
75 * @irq_base: Save base of IRQ number for interrupt
76 * @spinlock: Used for register access protection
77 */
78 struct ioh_gpio {
79 void __iomem *base;
80 struct ioh_regs __iomem *reg;
81 struct device *dev;
82 struct gpio_chip gpio;
83 struct ioh_gpio_reg_data ioh_gpio_reg;
84 u32 gpio_use_sel;
85 int ch;
86 int irq_base;
87 spinlock_t spinlock;
88 };
89
90 static const int num_ports[] = {6, 12, 16, 16, 15, 16, 16, 12};
91
ioh_gpio_set(struct gpio_chip * gpio,unsigned nr,int val)92 static void ioh_gpio_set(struct gpio_chip *gpio, unsigned nr, int val)
93 {
94 u32 reg_val;
95 struct ioh_gpio *chip = gpiochip_get_data(gpio);
96 unsigned long flags;
97
98 spin_lock_irqsave(&chip->spinlock, flags);
99 reg_val = ioread32(&chip->reg->regs[chip->ch].po);
100 if (val)
101 reg_val |= BIT(nr);
102 else
103 reg_val &= ~BIT(nr);
104
105 iowrite32(reg_val, &chip->reg->regs[chip->ch].po);
106 spin_unlock_irqrestore(&chip->spinlock, flags);
107 }
108
ioh_gpio_get(struct gpio_chip * gpio,unsigned nr)109 static int ioh_gpio_get(struct gpio_chip *gpio, unsigned nr)
110 {
111 struct ioh_gpio *chip = gpiochip_get_data(gpio);
112
113 return !!(ioread32(&chip->reg->regs[chip->ch].pi) & BIT(nr));
114 }
115
ioh_gpio_direction_output(struct gpio_chip * gpio,unsigned nr,int val)116 static int ioh_gpio_direction_output(struct gpio_chip *gpio, unsigned nr,
117 int val)
118 {
119 struct ioh_gpio *chip = gpiochip_get_data(gpio);
120 u32 pm;
121 u32 reg_val;
122 unsigned long flags;
123
124 spin_lock_irqsave(&chip->spinlock, flags);
125 pm = ioread32(&chip->reg->regs[chip->ch].pm);
126 pm &= BIT(num_ports[chip->ch]) - 1;
127 pm |= BIT(nr);
128 iowrite32(pm, &chip->reg->regs[chip->ch].pm);
129
130 reg_val = ioread32(&chip->reg->regs[chip->ch].po);
131 if (val)
132 reg_val |= BIT(nr);
133 else
134 reg_val &= ~BIT(nr);
135 iowrite32(reg_val, &chip->reg->regs[chip->ch].po);
136
137 spin_unlock_irqrestore(&chip->spinlock, flags);
138
139 return 0;
140 }
141
ioh_gpio_direction_input(struct gpio_chip * gpio,unsigned nr)142 static int ioh_gpio_direction_input(struct gpio_chip *gpio, unsigned nr)
143 {
144 struct ioh_gpio *chip = gpiochip_get_data(gpio);
145 u32 pm;
146 unsigned long flags;
147
148 spin_lock_irqsave(&chip->spinlock, flags);
149 pm = ioread32(&chip->reg->regs[chip->ch].pm);
150 pm &= BIT(num_ports[chip->ch]) - 1;
151 pm &= ~BIT(nr);
152 iowrite32(pm, &chip->reg->regs[chip->ch].pm);
153 spin_unlock_irqrestore(&chip->spinlock, flags);
154
155 return 0;
156 }
157
158 /*
159 * Save register configuration and disable interrupts.
160 */
ioh_gpio_save_reg_conf(struct ioh_gpio * chip)161 static void __maybe_unused ioh_gpio_save_reg_conf(struct ioh_gpio *chip)
162 {
163 int i;
164
165 for (i = 0; i < 8; i ++, chip++) {
166 chip->ioh_gpio_reg.po_reg =
167 ioread32(&chip->reg->regs[chip->ch].po);
168 chip->ioh_gpio_reg.pm_reg =
169 ioread32(&chip->reg->regs[chip->ch].pm);
170 chip->ioh_gpio_reg.ien_reg =
171 ioread32(&chip->reg->regs[chip->ch].ien);
172 chip->ioh_gpio_reg.imask_reg =
173 ioread32(&chip->reg->regs[chip->ch].imask);
174 chip->ioh_gpio_reg.im0_reg =
175 ioread32(&chip->reg->regs[chip->ch].im_0);
176 chip->ioh_gpio_reg.im1_reg =
177 ioread32(&chip->reg->regs[chip->ch].im_1);
178 if (i < 4)
179 chip->ioh_gpio_reg.use_sel_reg =
180 ioread32(&chip->reg->ioh_sel_reg[i]);
181 }
182 }
183
184 /*
185 * This function restores the register configuration of the GPIO device.
186 */
ioh_gpio_restore_reg_conf(struct ioh_gpio * chip)187 static void __maybe_unused ioh_gpio_restore_reg_conf(struct ioh_gpio *chip)
188 {
189 int i;
190
191 for (i = 0; i < 8; i ++, chip++) {
192 iowrite32(chip->ioh_gpio_reg.po_reg,
193 &chip->reg->regs[chip->ch].po);
194 iowrite32(chip->ioh_gpio_reg.pm_reg,
195 &chip->reg->regs[chip->ch].pm);
196 iowrite32(chip->ioh_gpio_reg.ien_reg,
197 &chip->reg->regs[chip->ch].ien);
198 iowrite32(chip->ioh_gpio_reg.imask_reg,
199 &chip->reg->regs[chip->ch].imask);
200 iowrite32(chip->ioh_gpio_reg.im0_reg,
201 &chip->reg->regs[chip->ch].im_0);
202 iowrite32(chip->ioh_gpio_reg.im1_reg,
203 &chip->reg->regs[chip->ch].im_1);
204 if (i < 4)
205 iowrite32(chip->ioh_gpio_reg.use_sel_reg,
206 &chip->reg->ioh_sel_reg[i]);
207 }
208 }
209
ioh_gpio_to_irq(struct gpio_chip * gpio,unsigned offset)210 static int ioh_gpio_to_irq(struct gpio_chip *gpio, unsigned offset)
211 {
212 struct ioh_gpio *chip = gpiochip_get_data(gpio);
213 return chip->irq_base + offset;
214 }
215
ioh_gpio_setup(struct ioh_gpio * chip,int num_port)216 static void ioh_gpio_setup(struct ioh_gpio *chip, int num_port)
217 {
218 struct gpio_chip *gpio = &chip->gpio;
219
220 gpio->label = dev_name(chip->dev);
221 gpio->owner = THIS_MODULE;
222 gpio->direction_input = ioh_gpio_direction_input;
223 gpio->get = ioh_gpio_get;
224 gpio->direction_output = ioh_gpio_direction_output;
225 gpio->set = ioh_gpio_set;
226 gpio->dbg_show = NULL;
227 gpio->base = -1;
228 gpio->ngpio = num_port;
229 gpio->can_sleep = false;
230 gpio->to_irq = ioh_gpio_to_irq;
231 }
232
ioh_irq_type(struct irq_data * d,unsigned int type)233 static int ioh_irq_type(struct irq_data *d, unsigned int type)
234 {
235 u32 im;
236 void __iomem *im_reg;
237 u32 ien;
238 u32 im_pos;
239 int ch;
240 unsigned long flags;
241 u32 val;
242 int irq = d->irq;
243 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
244 struct ioh_gpio *chip = gc->private;
245
246 ch = irq - chip->irq_base;
247 if (irq <= chip->irq_base + 7) {
248 im_reg = &chip->reg->regs[chip->ch].im_0;
249 im_pos = ch;
250 } else {
251 im_reg = &chip->reg->regs[chip->ch].im_1;
252 im_pos = ch - 8;
253 }
254 dev_dbg(chip->dev, "%s:irq=%d type=%d ch=%d pos=%d type=%d\n",
255 __func__, irq, type, ch, im_pos, type);
256
257 spin_lock_irqsave(&chip->spinlock, flags);
258
259 switch (type) {
260 case IRQ_TYPE_EDGE_RISING:
261 val = IOH_EDGE_RISING;
262 break;
263 case IRQ_TYPE_EDGE_FALLING:
264 val = IOH_EDGE_FALLING;
265 break;
266 case IRQ_TYPE_EDGE_BOTH:
267 val = IOH_EDGE_BOTH;
268 break;
269 case IRQ_TYPE_LEVEL_HIGH:
270 val = IOH_LEVEL_H;
271 break;
272 case IRQ_TYPE_LEVEL_LOW:
273 val = IOH_LEVEL_L;
274 break;
275 case IRQ_TYPE_PROBE:
276 goto end;
277 default:
278 dev_warn(chip->dev, "%s: unknown type(%dd)",
279 __func__, type);
280 goto end;
281 }
282
283 /* Set interrupt mode */
284 im = ioread32(im_reg) & ~(IOH_IM_MASK << (im_pos * 4));
285 iowrite32(im | (val << (im_pos * 4)), im_reg);
286
287 /* iclr */
288 iowrite32(BIT(ch), &chip->reg->regs[chip->ch].iclr);
289
290 /* IMASKCLR */
291 iowrite32(BIT(ch), &chip->reg->regs[chip->ch].imaskclr);
292
293 /* Enable interrupt */
294 ien = ioread32(&chip->reg->regs[chip->ch].ien);
295 iowrite32(ien | BIT(ch), &chip->reg->regs[chip->ch].ien);
296 end:
297 spin_unlock_irqrestore(&chip->spinlock, flags);
298
299 return 0;
300 }
301
ioh_irq_unmask(struct irq_data * d)302 static void ioh_irq_unmask(struct irq_data *d)
303 {
304 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
305 struct ioh_gpio *chip = gc->private;
306
307 iowrite32(BIT(d->irq - chip->irq_base),
308 &chip->reg->regs[chip->ch].imaskclr);
309 }
310
ioh_irq_mask(struct irq_data * d)311 static void ioh_irq_mask(struct irq_data *d)
312 {
313 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
314 struct ioh_gpio *chip = gc->private;
315
316 iowrite32(BIT(d->irq - chip->irq_base),
317 &chip->reg->regs[chip->ch].imask);
318 }
319
ioh_irq_disable(struct irq_data * d)320 static void ioh_irq_disable(struct irq_data *d)
321 {
322 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
323 struct ioh_gpio *chip = gc->private;
324 unsigned long flags;
325 u32 ien;
326
327 spin_lock_irqsave(&chip->spinlock, flags);
328 ien = ioread32(&chip->reg->regs[chip->ch].ien);
329 ien &= ~BIT(d->irq - chip->irq_base);
330 iowrite32(ien, &chip->reg->regs[chip->ch].ien);
331 spin_unlock_irqrestore(&chip->spinlock, flags);
332 }
333
ioh_irq_enable(struct irq_data * d)334 static void ioh_irq_enable(struct irq_data *d)
335 {
336 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
337 struct ioh_gpio *chip = gc->private;
338 unsigned long flags;
339 u32 ien;
340
341 spin_lock_irqsave(&chip->spinlock, flags);
342 ien = ioread32(&chip->reg->regs[chip->ch].ien);
343 ien |= BIT(d->irq - chip->irq_base);
344 iowrite32(ien, &chip->reg->regs[chip->ch].ien);
345 spin_unlock_irqrestore(&chip->spinlock, flags);
346 }
347
ioh_gpio_handler(int irq,void * dev_id)348 static irqreturn_t ioh_gpio_handler(int irq, void *dev_id)
349 {
350 struct ioh_gpio *chip = dev_id;
351 u32 reg_val;
352 int i, j;
353 int ret = IRQ_NONE;
354
355 for (i = 0; i < 8; i++, chip++) {
356 reg_val = ioread32(&chip->reg->regs[i].istatus);
357 for (j = 0; j < num_ports[i]; j++) {
358 if (reg_val & BIT(j)) {
359 dev_dbg(chip->dev,
360 "%s:[%d]:irq=%d status=0x%x\n",
361 __func__, j, irq, reg_val);
362 iowrite32(BIT(j),
363 &chip->reg->regs[chip->ch].iclr);
364 generic_handle_irq(chip->irq_base + j);
365 ret = IRQ_HANDLED;
366 }
367 }
368 }
369 return ret;
370 }
371
ioh_gpio_alloc_generic_chip(struct ioh_gpio * chip,unsigned int irq_start,unsigned int num)372 static int ioh_gpio_alloc_generic_chip(struct ioh_gpio *chip,
373 unsigned int irq_start,
374 unsigned int num)
375 {
376 struct irq_chip_generic *gc;
377 struct irq_chip_type *ct;
378 int rv;
379
380 gc = devm_irq_alloc_generic_chip(chip->dev, "ioh_gpio", 1, irq_start,
381 chip->base, handle_simple_irq);
382 if (!gc)
383 return -ENOMEM;
384
385 gc->private = chip;
386 ct = gc->chip_types;
387
388 ct->chip.irq_mask = ioh_irq_mask;
389 ct->chip.irq_unmask = ioh_irq_unmask;
390 ct->chip.irq_set_type = ioh_irq_type;
391 ct->chip.irq_disable = ioh_irq_disable;
392 ct->chip.irq_enable = ioh_irq_enable;
393
394 rv = devm_irq_setup_generic_chip(chip->dev, gc, IRQ_MSK(num),
395 IRQ_GC_INIT_MASK_CACHE,
396 IRQ_NOREQUEST | IRQ_NOPROBE, 0);
397
398 return rv;
399 }
400
ioh_gpio_probe(struct pci_dev * pdev,const struct pci_device_id * id)401 static int ioh_gpio_probe(struct pci_dev *pdev,
402 const struct pci_device_id *id)
403 {
404 struct device *dev = &pdev->dev;
405 int ret;
406 int i, j;
407 struct ioh_gpio *chip;
408 void __iomem *base;
409 void *chip_save;
410 int irq_base;
411
412 ret = pcim_enable_device(pdev);
413 if (ret) {
414 dev_err(dev, "%s : pcim_enable_device failed", __func__);
415 return ret;
416 }
417
418 ret = pcim_iomap_regions(pdev, BIT(1), KBUILD_MODNAME);
419 if (ret) {
420 dev_err(dev, "pcim_iomap_regions failed-%d", ret);
421 return ret;
422 }
423
424 base = pcim_iomap_table(pdev)[1];
425 if (!base) {
426 dev_err(dev, "%s : pcim_iomap_table failed", __func__);
427 return -ENOMEM;
428 }
429
430 chip_save = devm_kcalloc(dev, 8, sizeof(*chip), GFP_KERNEL);
431 if (chip_save == NULL) {
432 return -ENOMEM;
433 }
434
435 chip = chip_save;
436 for (i = 0; i < 8; i++, chip++) {
437 chip->dev = dev;
438 chip->base = base;
439 chip->reg = chip->base;
440 chip->ch = i;
441 spin_lock_init(&chip->spinlock);
442 ioh_gpio_setup(chip, num_ports[i]);
443 ret = devm_gpiochip_add_data(dev, &chip->gpio, chip);
444 if (ret) {
445 dev_err(dev, "IOH gpio: Failed to register GPIO\n");
446 return ret;
447 }
448 }
449
450 chip = chip_save;
451 for (j = 0; j < 8; j++, chip++) {
452 irq_base = devm_irq_alloc_descs(dev, -1, IOH_IRQ_BASE,
453 num_ports[j], NUMA_NO_NODE);
454 if (irq_base < 0) {
455 dev_warn(dev,
456 "ml_ioh_gpio: Failed to get IRQ base num\n");
457 return irq_base;
458 }
459 chip->irq_base = irq_base;
460
461 ret = ioh_gpio_alloc_generic_chip(chip,
462 irq_base, num_ports[j]);
463 if (ret)
464 return ret;
465 }
466
467 chip = chip_save;
468 ret = devm_request_irq(dev, pdev->irq, ioh_gpio_handler,
469 IRQF_SHARED, KBUILD_MODNAME, chip);
470 if (ret != 0) {
471 dev_err(dev, "%s request_irq failed\n", __func__);
472 return ret;
473 }
474
475 pci_set_drvdata(pdev, chip);
476
477 return 0;
478 }
479
ioh_gpio_suspend(struct device * dev)480 static int __maybe_unused ioh_gpio_suspend(struct device *dev)
481 {
482 struct ioh_gpio *chip = dev_get_drvdata(dev);
483 unsigned long flags;
484
485 spin_lock_irqsave(&chip->spinlock, flags);
486 ioh_gpio_save_reg_conf(chip);
487 spin_unlock_irqrestore(&chip->spinlock, flags);
488
489 return 0;
490 }
491
ioh_gpio_resume(struct device * dev)492 static int __maybe_unused ioh_gpio_resume(struct device *dev)
493 {
494 struct ioh_gpio *chip = dev_get_drvdata(dev);
495 unsigned long flags;
496
497 spin_lock_irqsave(&chip->spinlock, flags);
498 iowrite32(0x01, &chip->reg->srst);
499 iowrite32(0x00, &chip->reg->srst);
500 ioh_gpio_restore_reg_conf(chip);
501 spin_unlock_irqrestore(&chip->spinlock, flags);
502
503 return 0;
504 }
505
506 static SIMPLE_DEV_PM_OPS(ioh_gpio_pm_ops, ioh_gpio_suspend, ioh_gpio_resume);
507
508 static const struct pci_device_id ioh_gpio_pcidev_id[] = {
509 { PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x802E) },
510 { 0, }
511 };
512 MODULE_DEVICE_TABLE(pci, ioh_gpio_pcidev_id);
513
514 static struct pci_driver ioh_gpio_driver = {
515 .name = "ml_ioh_gpio",
516 .id_table = ioh_gpio_pcidev_id,
517 .probe = ioh_gpio_probe,
518 .driver = {
519 .pm = &ioh_gpio_pm_ops,
520 },
521 };
522
523 module_pci_driver(ioh_gpio_driver);
524
525 MODULE_DESCRIPTION("OKI SEMICONDUCTOR ML-IOH series GPIO Driver");
526 MODULE_LICENSE("GPL");
527
