1 /*
2  * Intel Merrifield SoC GPIO driver
3  *
4  * Copyright (c) 2016 Intel Corporation.
5  * Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
6  *
7  * This program is free software; you can redistribute it and/or modify
8  * it under the terms of the GNU General Public License version 2 as
9  * published by the Free Software Foundation.
10  */
11 
12 #include <linux/acpi.h>
13 #include <linux/bitops.h>
14 #include <linux/gpio/driver.h>
15 #include <linux/init.h>
16 #include <linux/interrupt.h>
17 #include <linux/io.h>
18 #include <linux/module.h>
19 #include <linux/pci.h>
20 #include <linux/pinctrl/consumer.h>
21 
22 #define GCCR		0x000	/* controller configuration */
23 #define GPLR		0x004	/* pin level r/o */
24 #define GPDR		0x01c	/* pin direction */
25 #define GPSR		0x034	/* pin set w/o */
26 #define GPCR		0x04c	/* pin clear w/o */
27 #define GRER		0x064	/* rising edge detect */
28 #define GFER		0x07c	/* falling edge detect */
29 #define GFBR		0x094	/* glitch filter bypass */
30 #define GIMR		0x0ac	/* interrupt mask */
31 #define GISR		0x0c4	/* interrupt source */
32 #define GITR		0x300	/* input type */
33 #define GLPR		0x318	/* level input polarity */
34 #define GWMR		0x400	/* wake mask */
35 #define GWSR		0x418	/* wake source */
36 #define GSIR		0xc00	/* secure input */
37 
38 /* Intel Merrifield has 192 GPIO pins */
39 #define MRFLD_NGPIO	192
40 
41 struct mrfld_gpio_pinrange {
42 	unsigned int gpio_base;
43 	unsigned int pin_base;
44 	unsigned int npins;
45 };
46 
47 #define GPIO_PINRANGE(gstart, gend, pstart)		\
48 	{						\
49 		.gpio_base = (gstart),			\
50 		.pin_base = (pstart),			\
51 		.npins = (gend) - (gstart) + 1,		\
52 	}
53 
54 struct mrfld_gpio {
55 	struct gpio_chip	chip;
56 	void __iomem		*reg_base;
57 	raw_spinlock_t		lock;
58 	struct device		*dev;
59 };
60 
61 static const struct mrfld_gpio_pinrange mrfld_gpio_ranges[] = {
62 	GPIO_PINRANGE(0, 11, 146),
63 	GPIO_PINRANGE(12, 13, 144),
64 	GPIO_PINRANGE(14, 15, 35),
65 	GPIO_PINRANGE(16, 16, 164),
66 	GPIO_PINRANGE(17, 18, 105),
67 	GPIO_PINRANGE(19, 22, 101),
68 	GPIO_PINRANGE(23, 30, 107),
69 	GPIO_PINRANGE(32, 43, 67),
70 	GPIO_PINRANGE(44, 63, 195),
71 	GPIO_PINRANGE(64, 67, 140),
72 	GPIO_PINRANGE(68, 69, 165),
73 	GPIO_PINRANGE(70, 71, 65),
74 	GPIO_PINRANGE(72, 76, 228),
75 	GPIO_PINRANGE(77, 86, 37),
76 	GPIO_PINRANGE(87, 87, 48),
77 	GPIO_PINRANGE(88, 88, 47),
78 	GPIO_PINRANGE(89, 96, 49),
79 	GPIO_PINRANGE(97, 97, 34),
80 	GPIO_PINRANGE(102, 119, 83),
81 	GPIO_PINRANGE(120, 123, 79),
82 	GPIO_PINRANGE(124, 135, 115),
83 	GPIO_PINRANGE(137, 142, 158),
84 	GPIO_PINRANGE(154, 163, 24),
85 	GPIO_PINRANGE(164, 176, 215),
86 	GPIO_PINRANGE(177, 189, 127),
87 	GPIO_PINRANGE(190, 191, 178),
88 };
89 
gpio_reg(struct gpio_chip * chip,unsigned int offset,unsigned int reg_type_offset)90 static void __iomem *gpio_reg(struct gpio_chip *chip, unsigned int offset,
91 			      unsigned int reg_type_offset)
92 {
93 	struct mrfld_gpio *priv = gpiochip_get_data(chip);
94 	u8 reg = offset / 32;
95 
96 	return priv->reg_base + reg_type_offset + reg * 4;
97 }
98 
mrfld_gpio_get(struct gpio_chip * chip,unsigned int offset)99 static int mrfld_gpio_get(struct gpio_chip *chip, unsigned int offset)
100 {
101 	void __iomem *gplr = gpio_reg(chip, offset, GPLR);
102 
103 	return !!(readl(gplr) & BIT(offset % 32));
104 }
105 
mrfld_gpio_set(struct gpio_chip * chip,unsigned int offset,int value)106 static void mrfld_gpio_set(struct gpio_chip *chip, unsigned int offset,
107 			   int value)
108 {
109 	struct mrfld_gpio *priv = gpiochip_get_data(chip);
110 	void __iomem *gpsr, *gpcr;
111 	unsigned long flags;
112 
113 	raw_spin_lock_irqsave(&priv->lock, flags);
114 
115 	if (value) {
116 		gpsr = gpio_reg(chip, offset, GPSR);
117 		writel(BIT(offset % 32), gpsr);
118 	} else {
119 		gpcr = gpio_reg(chip, offset, GPCR);
120 		writel(BIT(offset % 32), gpcr);
121 	}
122 
123 	raw_spin_unlock_irqrestore(&priv->lock, flags);
124 }
125 
mrfld_gpio_direction_input(struct gpio_chip * chip,unsigned int offset)126 static int mrfld_gpio_direction_input(struct gpio_chip *chip,
127 				      unsigned int offset)
128 {
129 	struct mrfld_gpio *priv = gpiochip_get_data(chip);
130 	void __iomem *gpdr = gpio_reg(chip, offset, GPDR);
131 	unsigned long flags;
132 	u32 value;
133 
134 	raw_spin_lock_irqsave(&priv->lock, flags);
135 
136 	value = readl(gpdr);
137 	value &= ~BIT(offset % 32);
138 	writel(value, gpdr);
139 
140 	raw_spin_unlock_irqrestore(&priv->lock, flags);
141 
142 	return 0;
143 }
144 
mrfld_gpio_direction_output(struct gpio_chip * chip,unsigned int offset,int value)145 static int mrfld_gpio_direction_output(struct gpio_chip *chip,
146 				       unsigned int offset, int value)
147 {
148 	struct mrfld_gpio *priv = gpiochip_get_data(chip);
149 	void __iomem *gpdr = gpio_reg(chip, offset, GPDR);
150 	unsigned long flags;
151 
152 	mrfld_gpio_set(chip, offset, value);
153 
154 	raw_spin_lock_irqsave(&priv->lock, flags);
155 
156 	value = readl(gpdr);
157 	value |= BIT(offset % 32);
158 	writel(value, gpdr);
159 
160 	raw_spin_unlock_irqrestore(&priv->lock, flags);
161 
162 	return 0;
163 }
164 
mrfld_gpio_get_direction(struct gpio_chip * chip,unsigned int offset)165 static int mrfld_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
166 {
167 	void __iomem *gpdr = gpio_reg(chip, offset, GPDR);
168 
169 	return !(readl(gpdr) & BIT(offset % 32));
170 }
171 
mrfld_gpio_set_debounce(struct gpio_chip * chip,unsigned int offset,unsigned int debounce)172 static int mrfld_gpio_set_debounce(struct gpio_chip *chip, unsigned int offset,
173 				   unsigned int debounce)
174 {
175 	struct mrfld_gpio *priv = gpiochip_get_data(chip);
176 	void __iomem *gfbr = gpio_reg(chip, offset, GFBR);
177 	unsigned long flags;
178 	u32 value;
179 
180 	raw_spin_lock_irqsave(&priv->lock, flags);
181 
182 	if (debounce)
183 		value = readl(gfbr) & ~BIT(offset % 32);
184 	else
185 		value = readl(gfbr) | BIT(offset % 32);
186 	writel(value, gfbr);
187 
188 	raw_spin_unlock_irqrestore(&priv->lock, flags);
189 
190 	return 0;
191 }
192 
mrfld_gpio_set_config(struct gpio_chip * chip,unsigned int offset,unsigned long config)193 static int mrfld_gpio_set_config(struct gpio_chip *chip, unsigned int offset,
194 				 unsigned long config)
195 {
196 	u32 debounce;
197 
198 	if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
199 		return -ENOTSUPP;
200 
201 	debounce = pinconf_to_config_argument(config);
202 	return mrfld_gpio_set_debounce(chip, offset, debounce);
203 }
204 
mrfld_irq_ack(struct irq_data * d)205 static void mrfld_irq_ack(struct irq_data *d)
206 {
207 	struct mrfld_gpio *priv = irq_data_get_irq_chip_data(d);
208 	u32 gpio = irqd_to_hwirq(d);
209 	void __iomem *gisr = gpio_reg(&priv->chip, gpio, GISR);
210 	unsigned long flags;
211 
212 	raw_spin_lock_irqsave(&priv->lock, flags);
213 
214 	writel(BIT(gpio % 32), gisr);
215 
216 	raw_spin_unlock_irqrestore(&priv->lock, flags);
217 }
218 
mrfld_irq_unmask_mask(struct irq_data * d,bool unmask)219 static void mrfld_irq_unmask_mask(struct irq_data *d, bool unmask)
220 {
221 	struct mrfld_gpio *priv = irq_data_get_irq_chip_data(d);
222 	u32 gpio = irqd_to_hwirq(d);
223 	void __iomem *gimr = gpio_reg(&priv->chip, gpio, GIMR);
224 	unsigned long flags;
225 	u32 value;
226 
227 	raw_spin_lock_irqsave(&priv->lock, flags);
228 
229 	if (unmask)
230 		value = readl(gimr) | BIT(gpio % 32);
231 	else
232 		value = readl(gimr) & ~BIT(gpio % 32);
233 	writel(value, gimr);
234 
235 	raw_spin_unlock_irqrestore(&priv->lock, flags);
236 }
237 
mrfld_irq_mask(struct irq_data * d)238 static void mrfld_irq_mask(struct irq_data *d)
239 {
240 	mrfld_irq_unmask_mask(d, false);
241 }
242 
mrfld_irq_unmask(struct irq_data * d)243 static void mrfld_irq_unmask(struct irq_data *d)
244 {
245 	mrfld_irq_unmask_mask(d, true);
246 }
247 
mrfld_irq_set_type(struct irq_data * d,unsigned int type)248 static int mrfld_irq_set_type(struct irq_data *d, unsigned int type)
249 {
250 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
251 	struct mrfld_gpio *priv = gpiochip_get_data(gc);
252 	u32 gpio = irqd_to_hwirq(d);
253 	void __iomem *grer = gpio_reg(&priv->chip, gpio, GRER);
254 	void __iomem *gfer = gpio_reg(&priv->chip, gpio, GFER);
255 	void __iomem *gitr = gpio_reg(&priv->chip, gpio, GITR);
256 	void __iomem *glpr = gpio_reg(&priv->chip, gpio, GLPR);
257 	unsigned long flags;
258 	u32 value;
259 
260 	raw_spin_lock_irqsave(&priv->lock, flags);
261 
262 	if (type & IRQ_TYPE_EDGE_RISING)
263 		value = readl(grer) | BIT(gpio % 32);
264 	else
265 		value = readl(grer) & ~BIT(gpio % 32);
266 	writel(value, grer);
267 
268 	if (type & IRQ_TYPE_EDGE_FALLING)
269 		value = readl(gfer) | BIT(gpio % 32);
270 	else
271 		value = readl(gfer) & ~BIT(gpio % 32);
272 	writel(value, gfer);
273 
274 	/*
275 	 * To prevent glitches from triggering an unintended level interrupt,
276 	 * configure GLPR register first and then configure GITR.
277 	 */
278 	if (type & IRQ_TYPE_LEVEL_LOW)
279 		value = readl(glpr) | BIT(gpio % 32);
280 	else
281 		value = readl(glpr) & ~BIT(gpio % 32);
282 	writel(value, glpr);
283 
284 	if (type & IRQ_TYPE_LEVEL_MASK) {
285 		value = readl(gitr) | BIT(gpio % 32);
286 		writel(value, gitr);
287 
288 		irq_set_handler_locked(d, handle_level_irq);
289 	} else if (type & IRQ_TYPE_EDGE_BOTH) {
290 		value = readl(gitr) & ~BIT(gpio % 32);
291 		writel(value, gitr);
292 
293 		irq_set_handler_locked(d, handle_edge_irq);
294 	}
295 
296 	raw_spin_unlock_irqrestore(&priv->lock, flags);
297 
298 	return 0;
299 }
300 
mrfld_irq_set_wake(struct irq_data * d,unsigned int on)301 static int mrfld_irq_set_wake(struct irq_data *d, unsigned int on)
302 {
303 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
304 	struct mrfld_gpio *priv = gpiochip_get_data(gc);
305 	u32 gpio = irqd_to_hwirq(d);
306 	void __iomem *gwmr = gpio_reg(&priv->chip, gpio, GWMR);
307 	void __iomem *gwsr = gpio_reg(&priv->chip, gpio, GWSR);
308 	unsigned long flags;
309 	u32 value;
310 
311 	raw_spin_lock_irqsave(&priv->lock, flags);
312 
313 	/* Clear the existing wake status */
314 	writel(BIT(gpio % 32), gwsr);
315 
316 	if (on)
317 		value = readl(gwmr) | BIT(gpio % 32);
318 	else
319 		value = readl(gwmr) & ~BIT(gpio % 32);
320 	writel(value, gwmr);
321 
322 	raw_spin_unlock_irqrestore(&priv->lock, flags);
323 
324 	dev_dbg(priv->dev, "%sable wake for gpio %u\n", on ? "en" : "dis", gpio);
325 	return 0;
326 }
327 
328 static struct irq_chip mrfld_irqchip = {
329 	.name		= "gpio-merrifield",
330 	.irq_ack	= mrfld_irq_ack,
331 	.irq_mask	= mrfld_irq_mask,
332 	.irq_unmask	= mrfld_irq_unmask,
333 	.irq_set_type	= mrfld_irq_set_type,
334 	.irq_set_wake	= mrfld_irq_set_wake,
335 };
336 
mrfld_irq_handler(struct irq_desc * desc)337 static void mrfld_irq_handler(struct irq_desc *desc)
338 {
339 	struct gpio_chip *gc = irq_desc_get_handler_data(desc);
340 	struct mrfld_gpio *priv = gpiochip_get_data(gc);
341 	struct irq_chip *irqchip = irq_desc_get_chip(desc);
342 	unsigned long base, gpio;
343 
344 	chained_irq_enter(irqchip, desc);
345 
346 	/* Check GPIO controller to check which pin triggered the interrupt */
347 	for (base = 0; base < priv->chip.ngpio; base += 32) {
348 		void __iomem *gisr = gpio_reg(&priv->chip, base, GISR);
349 		void __iomem *gimr = gpio_reg(&priv->chip, base, GIMR);
350 		unsigned long pending, enabled;
351 
352 		pending = readl(gisr);
353 		enabled = readl(gimr);
354 
355 		/* Only interrupts that are enabled */
356 		pending &= enabled;
357 
358 		for_each_set_bit(gpio, &pending, 32) {
359 			unsigned int irq;
360 
361 			irq = irq_find_mapping(gc->irq.domain, base + gpio);
362 			generic_handle_irq(irq);
363 		}
364 	}
365 
366 	chained_irq_exit(irqchip, desc);
367 }
368 
mrfld_irq_init_hw(struct mrfld_gpio * priv)369 static void mrfld_irq_init_hw(struct mrfld_gpio *priv)
370 {
371 	void __iomem *reg;
372 	unsigned int base;
373 
374 	for (base = 0; base < priv->chip.ngpio; base += 32) {
375 		/* Clear the rising-edge detect register */
376 		reg = gpio_reg(&priv->chip, base, GRER);
377 		writel(0, reg);
378 		/* Clear the falling-edge detect register */
379 		reg = gpio_reg(&priv->chip, base, GFER);
380 		writel(0, reg);
381 	}
382 }
383 
mrfld_gpio_get_pinctrl_dev_name(void)384 static const char *mrfld_gpio_get_pinctrl_dev_name(void)
385 {
386 	const char *dev_name = acpi_dev_get_first_match_name("INTC1002", NULL, -1);
387 	return dev_name ? dev_name : "pinctrl-merrifield";
388 }
389 
mrfld_gpio_probe(struct pci_dev * pdev,const struct pci_device_id * id)390 static int mrfld_gpio_probe(struct pci_dev *pdev, const struct pci_device_id *id)
391 {
392 	const struct mrfld_gpio_pinrange *range;
393 	const char *pinctrl_dev_name;
394 	struct mrfld_gpio *priv;
395 	u32 gpio_base, irq_base;
396 	void __iomem *base;
397 	unsigned int i;
398 	int retval;
399 
400 	retval = pcim_enable_device(pdev);
401 	if (retval)
402 		return retval;
403 
404 	retval = pcim_iomap_regions(pdev, BIT(1) | BIT(0), pci_name(pdev));
405 	if (retval) {
406 		dev_err(&pdev->dev, "I/O memory mapping error\n");
407 		return retval;
408 	}
409 
410 	base = pcim_iomap_table(pdev)[1];
411 
412 	irq_base = readl(base);
413 	gpio_base = readl(sizeof(u32) + base);
414 
415 	/* Release the IO mapping, since we already get the info from BAR1 */
416 	pcim_iounmap_regions(pdev, BIT(1));
417 
418 	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
419 	if (!priv)
420 		return -ENOMEM;
421 
422 	priv->dev = &pdev->dev;
423 	priv->reg_base = pcim_iomap_table(pdev)[0];
424 
425 	priv->chip.label = dev_name(&pdev->dev);
426 	priv->chip.parent = &pdev->dev;
427 	priv->chip.request = gpiochip_generic_request;
428 	priv->chip.free = gpiochip_generic_free;
429 	priv->chip.direction_input = mrfld_gpio_direction_input;
430 	priv->chip.direction_output = mrfld_gpio_direction_output;
431 	priv->chip.get = mrfld_gpio_get;
432 	priv->chip.set = mrfld_gpio_set;
433 	priv->chip.get_direction = mrfld_gpio_get_direction;
434 	priv->chip.set_config = mrfld_gpio_set_config;
435 	priv->chip.base = gpio_base;
436 	priv->chip.ngpio = MRFLD_NGPIO;
437 	priv->chip.can_sleep = false;
438 
439 	raw_spin_lock_init(&priv->lock);
440 
441 	pci_set_drvdata(pdev, priv);
442 	retval = devm_gpiochip_add_data(&pdev->dev, &priv->chip, priv);
443 	if (retval) {
444 		dev_err(&pdev->dev, "gpiochip_add error %d\n", retval);
445 		return retval;
446 	}
447 
448 	pinctrl_dev_name = mrfld_gpio_get_pinctrl_dev_name();
449 	for (i = 0; i < ARRAY_SIZE(mrfld_gpio_ranges); i++) {
450 		range = &mrfld_gpio_ranges[i];
451 		retval = gpiochip_add_pin_range(&priv->chip,
452 						pinctrl_dev_name,
453 						range->gpio_base,
454 						range->pin_base,
455 						range->npins);
456 		if (retval) {
457 			dev_err(&pdev->dev, "failed to add GPIO pin range\n");
458 			return retval;
459 		}
460 	}
461 
462 	retval = gpiochip_irqchip_add(&priv->chip, &mrfld_irqchip, irq_base,
463 				      handle_bad_irq, IRQ_TYPE_NONE);
464 	if (retval) {
465 		dev_err(&pdev->dev, "could not connect irqchip to gpiochip\n");
466 		return retval;
467 	}
468 
469 	mrfld_irq_init_hw(priv);
470 
471 	gpiochip_set_chained_irqchip(&priv->chip, &mrfld_irqchip, pdev->irq,
472 				     mrfld_irq_handler);
473 
474 	return 0;
475 }
476 
477 static const struct pci_device_id mrfld_gpio_ids[] = {
478 	{ PCI_VDEVICE(INTEL, 0x1199) },
479 	{ }
480 };
481 MODULE_DEVICE_TABLE(pci, mrfld_gpio_ids);
482 
483 static struct pci_driver mrfld_gpio_driver = {
484 	.name		= "gpio-merrifield",
485 	.id_table	= mrfld_gpio_ids,
486 	.probe		= mrfld_gpio_probe,
487 };
488 
489 module_pci_driver(mrfld_gpio_driver);
490 
491 MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>");
492 MODULE_DESCRIPTION("Intel Merrifield SoC GPIO driver");
493 MODULE_LICENSE("GPL v2");
494