1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * TI DaVinci GPIO Support
4 *
5 * Copyright (c) 2006-2007 David Brownell
6 * Copyright (c) 2007, MontaVista Software, Inc. <source@mvista.com>
7 */
8
9 #include <linux/gpio/driver.h>
10 #include <linux/errno.h>
11 #include <linux/kernel.h>
12 #include <linux/clk.h>
13 #include <linux/err.h>
14 #include <linux/io.h>
15 #include <linux/irq.h>
16 #include <linux/irqdomain.h>
17 #include <linux/module.h>
18 #include <linux/of.h>
19 #include <linux/of_device.h>
20 #include <linux/pinctrl/consumer.h>
21 #include <linux/platform_device.h>
22 #include <linux/platform_data/gpio-davinci.h>
23 #include <linux/irqchip/chained_irq.h>
24 #include <linux/spinlock.h>
25 #include <linux/pm_runtime.h>
26
27 #define MAX_REGS_BANKS 5
28 #define MAX_INT_PER_BANK 32
29
30 struct davinci_gpio_regs {
31 u32 dir;
32 u32 out_data;
33 u32 set_data;
34 u32 clr_data;
35 u32 in_data;
36 u32 set_rising;
37 u32 clr_rising;
38 u32 set_falling;
39 u32 clr_falling;
40 u32 intstat;
41 };
42
43 typedef struct irq_chip *(*gpio_get_irq_chip_cb_t)(unsigned int irq);
44
45 #define BINTEN 0x8 /* GPIO Interrupt Per-Bank Enable Register */
46
47 static void __iomem *gpio_base;
48 static unsigned int offset_array[5] = {0x10, 0x38, 0x60, 0x88, 0xb0};
49
50 struct davinci_gpio_irq_data {
51 void __iomem *regs;
52 struct davinci_gpio_controller *chip;
53 int bank_num;
54 };
55
56 struct davinci_gpio_controller {
57 struct gpio_chip chip;
58 struct irq_domain *irq_domain;
59 /* Serialize access to GPIO registers */
60 spinlock_t lock;
61 void __iomem *regs[MAX_REGS_BANKS];
62 int gpio_unbanked;
63 int irqs[MAX_INT_PER_BANK];
64 struct davinci_gpio_regs context[MAX_REGS_BANKS];
65 u32 binten_context;
66 };
67
__gpio_mask(unsigned gpio)68 static inline u32 __gpio_mask(unsigned gpio)
69 {
70 return 1 << (gpio % 32);
71 }
72
irq2regs(struct irq_data * d)73 static inline struct davinci_gpio_regs __iomem *irq2regs(struct irq_data *d)
74 {
75 struct davinci_gpio_regs __iomem *g;
76
77 g = (__force struct davinci_gpio_regs __iomem *)irq_data_get_irq_chip_data(d);
78
79 return g;
80 }
81
82 static int davinci_gpio_irq_setup(struct platform_device *pdev);
83
84 /*--------------------------------------------------------------------------*/
85
86 /* board setup code *MUST* setup pinmux and enable the GPIO clock. */
__davinci_direction(struct gpio_chip * chip,unsigned offset,bool out,int value)87 static inline int __davinci_direction(struct gpio_chip *chip,
88 unsigned offset, bool out, int value)
89 {
90 struct davinci_gpio_controller *d = gpiochip_get_data(chip);
91 struct davinci_gpio_regs __iomem *g;
92 unsigned long flags;
93 u32 temp;
94 int bank = offset / 32;
95 u32 mask = __gpio_mask(offset);
96
97 g = d->regs[bank];
98 spin_lock_irqsave(&d->lock, flags);
99 temp = readl_relaxed(&g->dir);
100 if (out) {
101 temp &= ~mask;
102 writel_relaxed(mask, value ? &g->set_data : &g->clr_data);
103 } else {
104 temp |= mask;
105 }
106 writel_relaxed(temp, &g->dir);
107 spin_unlock_irqrestore(&d->lock, flags);
108
109 return 0;
110 }
111
davinci_direction_in(struct gpio_chip * chip,unsigned offset)112 static int davinci_direction_in(struct gpio_chip *chip, unsigned offset)
113 {
114 return __davinci_direction(chip, offset, false, 0);
115 }
116
117 static int
davinci_direction_out(struct gpio_chip * chip,unsigned offset,int value)118 davinci_direction_out(struct gpio_chip *chip, unsigned offset, int value)
119 {
120 return __davinci_direction(chip, offset, true, value);
121 }
122
123 /*
124 * Read the pin's value (works even if it's set up as output);
125 * returns zero/nonzero.
126 *
127 * Note that changes are synched to the GPIO clock, so reading values back
128 * right after you've set them may give old values.
129 */
davinci_gpio_get(struct gpio_chip * chip,unsigned offset)130 static int davinci_gpio_get(struct gpio_chip *chip, unsigned offset)
131 {
132 struct davinci_gpio_controller *d = gpiochip_get_data(chip);
133 struct davinci_gpio_regs __iomem *g;
134 int bank = offset / 32;
135
136 g = d->regs[bank];
137
138 return !!(__gpio_mask(offset) & readl_relaxed(&g->in_data));
139 }
140
141 /*
142 * Assuming the pin is muxed as a gpio output, set its output value.
143 */
144 static void
davinci_gpio_set(struct gpio_chip * chip,unsigned offset,int value)145 davinci_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
146 {
147 struct davinci_gpio_controller *d = gpiochip_get_data(chip);
148 struct davinci_gpio_regs __iomem *g;
149 int bank = offset / 32;
150
151 g = d->regs[bank];
152
153 writel_relaxed(__gpio_mask(offset),
154 value ? &g->set_data : &g->clr_data);
155 }
156
157 static struct davinci_gpio_platform_data *
davinci_gpio_get_pdata(struct platform_device * pdev)158 davinci_gpio_get_pdata(struct platform_device *pdev)
159 {
160 struct device_node *dn = pdev->dev.of_node;
161 struct davinci_gpio_platform_data *pdata;
162 int ret;
163 u32 val;
164
165 if (!IS_ENABLED(CONFIG_OF) || !pdev->dev.of_node)
166 return dev_get_platdata(&pdev->dev);
167
168 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
169 if (!pdata)
170 return NULL;
171
172 ret = of_property_read_u32(dn, "ti,ngpio", &val);
173 if (ret)
174 goto of_err;
175
176 pdata->ngpio = val;
177
178 ret = of_property_read_u32(dn, "ti,davinci-gpio-unbanked", &val);
179 if (ret)
180 goto of_err;
181
182 pdata->gpio_unbanked = val;
183
184 return pdata;
185
186 of_err:
187 dev_err(&pdev->dev, "Populating pdata from DT failed: err %d\n", ret);
188 return NULL;
189 }
190
davinci_gpio_probe(struct platform_device * pdev)191 static int davinci_gpio_probe(struct platform_device *pdev)
192 {
193 int bank, i, ret = 0;
194 unsigned int ngpio, nbank, nirq;
195 struct davinci_gpio_controller *chips;
196 struct davinci_gpio_platform_data *pdata;
197 struct device *dev = &pdev->dev;
198
199 pdata = davinci_gpio_get_pdata(pdev);
200 if (!pdata) {
201 dev_err(dev, "No platform data found\n");
202 return -EINVAL;
203 }
204
205 dev->platform_data = pdata;
206
207 /*
208 * The gpio banks conceptually expose a segmented bitmap,
209 * and "ngpio" is one more than the largest zero-based
210 * bit index that's valid.
211 */
212 ngpio = pdata->ngpio;
213 if (ngpio == 0) {
214 dev_err(dev, "How many GPIOs?\n");
215 return -EINVAL;
216 }
217
218 /*
219 * If there are unbanked interrupts then the number of
220 * interrupts is equal to number of gpios else all are banked so
221 * number of interrupts is equal to number of banks(each with 16 gpios)
222 */
223 if (pdata->gpio_unbanked)
224 nirq = pdata->gpio_unbanked;
225 else
226 nirq = DIV_ROUND_UP(ngpio, 16);
227
228 chips = devm_kzalloc(dev, sizeof(*chips), GFP_KERNEL);
229 if (!chips)
230 return -ENOMEM;
231
232 gpio_base = devm_platform_ioremap_resource(pdev, 0);
233 if (IS_ERR(gpio_base))
234 return PTR_ERR(gpio_base);
235
236 for (i = 0; i < nirq; i++) {
237 chips->irqs[i] = platform_get_irq(pdev, i);
238 if (chips->irqs[i] < 0)
239 return chips->irqs[i];
240 }
241
242 chips->chip.label = dev_name(dev);
243
244 chips->chip.direction_input = davinci_direction_in;
245 chips->chip.get = davinci_gpio_get;
246 chips->chip.direction_output = davinci_direction_out;
247 chips->chip.set = davinci_gpio_set;
248
249 chips->chip.ngpio = ngpio;
250 chips->chip.base = pdata->no_auto_base ? pdata->base : -1;
251
252 #ifdef CONFIG_OF_GPIO
253 chips->chip.parent = dev;
254 chips->chip.request = gpiochip_generic_request;
255 chips->chip.free = gpiochip_generic_free;
256 #endif
257 spin_lock_init(&chips->lock);
258
259 nbank = DIV_ROUND_UP(ngpio, 32);
260 for (bank = 0; bank < nbank; bank++)
261 chips->regs[bank] = gpio_base + offset_array[bank];
262
263 ret = devm_gpiochip_add_data(dev, &chips->chip, chips);
264 if (ret)
265 return ret;
266
267 platform_set_drvdata(pdev, chips);
268 ret = davinci_gpio_irq_setup(pdev);
269 if (ret)
270 return ret;
271
272 return 0;
273 }
274
275 /*--------------------------------------------------------------------------*/
276 /*
277 * We expect irqs will normally be set up as input pins, but they can also be
278 * used as output pins ... which is convenient for testing.
279 *
280 * NOTE: The first few GPIOs also have direct INTC hookups in addition
281 * to their GPIOBNK0 irq, with a bit less overhead.
282 *
283 * All those INTC hookups (direct, plus several IRQ banks) can also
284 * serve as EDMA event triggers.
285 */
286
gpio_irq_disable(struct irq_data * d)287 static void gpio_irq_disable(struct irq_data *d)
288 {
289 struct davinci_gpio_regs __iomem *g = irq2regs(d);
290 uintptr_t mask = (uintptr_t)irq_data_get_irq_handler_data(d);
291
292 writel_relaxed(mask, &g->clr_falling);
293 writel_relaxed(mask, &g->clr_rising);
294 }
295
gpio_irq_enable(struct irq_data * d)296 static void gpio_irq_enable(struct irq_data *d)
297 {
298 struct davinci_gpio_regs __iomem *g = irq2regs(d);
299 uintptr_t mask = (uintptr_t)irq_data_get_irq_handler_data(d);
300 unsigned status = irqd_get_trigger_type(d);
301
302 status &= IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING;
303 if (!status)
304 status = IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING;
305
306 if (status & IRQ_TYPE_EDGE_FALLING)
307 writel_relaxed(mask, &g->set_falling);
308 if (status & IRQ_TYPE_EDGE_RISING)
309 writel_relaxed(mask, &g->set_rising);
310 }
311
gpio_irq_type(struct irq_data * d,unsigned trigger)312 static int gpio_irq_type(struct irq_data *d, unsigned trigger)
313 {
314 if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
315 return -EINVAL;
316
317 return 0;
318 }
319
320 static struct irq_chip gpio_irqchip = {
321 .name = "GPIO",
322 .irq_enable = gpio_irq_enable,
323 .irq_disable = gpio_irq_disable,
324 .irq_set_type = gpio_irq_type,
325 .flags = IRQCHIP_SET_TYPE_MASKED | IRQCHIP_SKIP_SET_WAKE,
326 };
327
gpio_irq_handler(struct irq_desc * desc)328 static void gpio_irq_handler(struct irq_desc *desc)
329 {
330 struct davinci_gpio_regs __iomem *g;
331 u32 mask = 0xffff;
332 int bank_num;
333 struct davinci_gpio_controller *d;
334 struct davinci_gpio_irq_data *irqdata;
335
336 irqdata = (struct davinci_gpio_irq_data *)irq_desc_get_handler_data(desc);
337 bank_num = irqdata->bank_num;
338 g = irqdata->regs;
339 d = irqdata->chip;
340
341 /* we only care about one bank */
342 if ((bank_num % 2) == 1)
343 mask <<= 16;
344
345 /* temporarily mask (level sensitive) parent IRQ */
346 chained_irq_enter(irq_desc_get_chip(desc), desc);
347 while (1) {
348 u32 status;
349 int bit;
350 irq_hw_number_t hw_irq;
351
352 /* ack any irqs */
353 status = readl_relaxed(&g->intstat) & mask;
354 if (!status)
355 break;
356 writel_relaxed(status, &g->intstat);
357
358 /* now demux them to the right lowlevel handler */
359
360 while (status) {
361 bit = __ffs(status);
362 status &= ~BIT(bit);
363 /* Max number of gpios per controller is 144 so
364 * hw_irq will be in [0..143]
365 */
366 hw_irq = (bank_num / 2) * 32 + bit;
367
368 generic_handle_domain_irq(d->irq_domain, hw_irq);
369 }
370 }
371 chained_irq_exit(irq_desc_get_chip(desc), desc);
372 /* now it may re-trigger */
373 }
374
gpio_to_irq_banked(struct gpio_chip * chip,unsigned offset)375 static int gpio_to_irq_banked(struct gpio_chip *chip, unsigned offset)
376 {
377 struct davinci_gpio_controller *d = gpiochip_get_data(chip);
378
379 if (d->irq_domain)
380 return irq_create_mapping(d->irq_domain, offset);
381 else
382 return -ENXIO;
383 }
384
gpio_to_irq_unbanked(struct gpio_chip * chip,unsigned offset)385 static int gpio_to_irq_unbanked(struct gpio_chip *chip, unsigned offset)
386 {
387 struct davinci_gpio_controller *d = gpiochip_get_data(chip);
388
389 /*
390 * NOTE: we assume for now that only irqs in the first gpio_chip
391 * can provide direct-mapped IRQs to AINTC (up to 32 GPIOs).
392 */
393 if (offset < d->gpio_unbanked)
394 return d->irqs[offset];
395 else
396 return -ENODEV;
397 }
398
gpio_irq_type_unbanked(struct irq_data * data,unsigned trigger)399 static int gpio_irq_type_unbanked(struct irq_data *data, unsigned trigger)
400 {
401 struct davinci_gpio_controller *d;
402 struct davinci_gpio_regs __iomem *g;
403 u32 mask, i;
404
405 d = (struct davinci_gpio_controller *)irq_data_get_irq_handler_data(data);
406 g = (struct davinci_gpio_regs __iomem *)d->regs[0];
407 for (i = 0; i < MAX_INT_PER_BANK; i++)
408 if (data->irq == d->irqs[i])
409 break;
410
411 if (i == MAX_INT_PER_BANK)
412 return -EINVAL;
413
414 mask = __gpio_mask(i);
415
416 if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
417 return -EINVAL;
418
419 writel_relaxed(mask, (trigger & IRQ_TYPE_EDGE_FALLING)
420 ? &g->set_falling : &g->clr_falling);
421 writel_relaxed(mask, (trigger & IRQ_TYPE_EDGE_RISING)
422 ? &g->set_rising : &g->clr_rising);
423
424 return 0;
425 }
426
427 static int
davinci_gpio_irq_map(struct irq_domain * d,unsigned int irq,irq_hw_number_t hw)428 davinci_gpio_irq_map(struct irq_domain *d, unsigned int irq,
429 irq_hw_number_t hw)
430 {
431 struct davinci_gpio_controller *chips =
432 (struct davinci_gpio_controller *)d->host_data;
433 struct davinci_gpio_regs __iomem *g = chips->regs[hw / 32];
434
435 irq_set_chip_and_handler_name(irq, &gpio_irqchip, handle_simple_irq,
436 "davinci_gpio");
437 irq_set_irq_type(irq, IRQ_TYPE_NONE);
438 irq_set_chip_data(irq, (__force void *)g);
439 irq_set_handler_data(irq, (void *)(uintptr_t)__gpio_mask(hw));
440
441 return 0;
442 }
443
444 static const struct irq_domain_ops davinci_gpio_irq_ops = {
445 .map = davinci_gpio_irq_map,
446 .xlate = irq_domain_xlate_onetwocell,
447 };
448
davinci_gpio_get_irq_chip(unsigned int irq)449 static struct irq_chip *davinci_gpio_get_irq_chip(unsigned int irq)
450 {
451 static struct irq_chip_type gpio_unbanked;
452
453 gpio_unbanked = *irq_data_get_chip_type(irq_get_irq_data(irq));
454
455 return &gpio_unbanked.chip;
456 };
457
keystone_gpio_get_irq_chip(unsigned int irq)458 static struct irq_chip *keystone_gpio_get_irq_chip(unsigned int irq)
459 {
460 static struct irq_chip gpio_unbanked;
461
462 gpio_unbanked = *irq_get_chip(irq);
463 return &gpio_unbanked;
464 };
465
466 static const struct of_device_id davinci_gpio_ids[];
467
468 /*
469 * NOTE: for suspend/resume, probably best to make a platform_device with
470 * suspend_late/resume_resume calls hooking into results of the set_wake()
471 * calls ... so if no gpios are wakeup events the clock can be disabled,
472 * with outputs left at previously set levels, and so that VDD3P3V.IOPWDN0
473 * (dm6446) can be set appropriately for GPIOV33 pins.
474 */
475
davinci_gpio_irq_setup(struct platform_device * pdev)476 static int davinci_gpio_irq_setup(struct platform_device *pdev)
477 {
478 unsigned gpio, bank;
479 int irq;
480 int ret;
481 struct clk *clk;
482 u32 binten = 0;
483 unsigned ngpio;
484 struct device *dev = &pdev->dev;
485 struct davinci_gpio_controller *chips = platform_get_drvdata(pdev);
486 struct davinci_gpio_platform_data *pdata = dev->platform_data;
487 struct davinci_gpio_regs __iomem *g;
488 struct irq_domain *irq_domain = NULL;
489 const struct of_device_id *match;
490 struct irq_chip *irq_chip;
491 struct davinci_gpio_irq_data *irqdata;
492 gpio_get_irq_chip_cb_t gpio_get_irq_chip;
493
494 /*
495 * Use davinci_gpio_get_irq_chip by default to handle non DT cases
496 */
497 gpio_get_irq_chip = davinci_gpio_get_irq_chip;
498 match = of_match_device(of_match_ptr(davinci_gpio_ids),
499 dev);
500 if (match)
501 gpio_get_irq_chip = (gpio_get_irq_chip_cb_t)match->data;
502
503 ngpio = pdata->ngpio;
504
505 clk = devm_clk_get(dev, "gpio");
506 if (IS_ERR(clk)) {
507 dev_err(dev, "Error %ld getting gpio clock\n", PTR_ERR(clk));
508 return PTR_ERR(clk);
509 }
510
511 ret = clk_prepare_enable(clk);
512 if (ret)
513 return ret;
514
515 if (!pdata->gpio_unbanked) {
516 irq = devm_irq_alloc_descs(dev, -1, 0, ngpio, 0);
517 if (irq < 0) {
518 dev_err(dev, "Couldn't allocate IRQ numbers\n");
519 clk_disable_unprepare(clk);
520 return irq;
521 }
522
523 irq_domain = irq_domain_add_legacy(dev->of_node, ngpio, irq, 0,
524 &davinci_gpio_irq_ops,
525 chips);
526 if (!irq_domain) {
527 dev_err(dev, "Couldn't register an IRQ domain\n");
528 clk_disable_unprepare(clk);
529 return -ENODEV;
530 }
531 }
532
533 /*
534 * Arrange gpiod_to_irq() support, handling either direct IRQs or
535 * banked IRQs. Having GPIOs in the first GPIO bank use direct
536 * IRQs, while the others use banked IRQs, would need some setup
537 * tweaks to recognize hardware which can do that.
538 */
539 chips->chip.to_irq = gpio_to_irq_banked;
540 chips->irq_domain = irq_domain;
541
542 /*
543 * AINTC can handle direct/unbanked IRQs for GPIOs, with the GPIO
544 * controller only handling trigger modes. We currently assume no
545 * IRQ mux conflicts; gpio_irq_type_unbanked() is only for GPIOs.
546 */
547 if (pdata->gpio_unbanked) {
548 /* pass "bank 0" GPIO IRQs to AINTC */
549 chips->chip.to_irq = gpio_to_irq_unbanked;
550 chips->gpio_unbanked = pdata->gpio_unbanked;
551 binten = GENMASK(pdata->gpio_unbanked / 16, 0);
552
553 /* AINTC handles mask/unmask; GPIO handles triggering */
554 irq = chips->irqs[0];
555 irq_chip = gpio_get_irq_chip(irq);
556 irq_chip->name = "GPIO-AINTC";
557 irq_chip->irq_set_type = gpio_irq_type_unbanked;
558
559 /* default trigger: both edges */
560 g = chips->regs[0];
561 writel_relaxed(~0, &g->set_falling);
562 writel_relaxed(~0, &g->set_rising);
563
564 /* set the direct IRQs up to use that irqchip */
565 for (gpio = 0; gpio < pdata->gpio_unbanked; gpio++) {
566 irq_set_chip(chips->irqs[gpio], irq_chip);
567 irq_set_handler_data(chips->irqs[gpio], chips);
568 irq_set_status_flags(chips->irqs[gpio],
569 IRQ_TYPE_EDGE_BOTH);
570 }
571
572 goto done;
573 }
574
575 /*
576 * Or, AINTC can handle IRQs for banks of 16 GPIO IRQs, which we
577 * then chain through our own handler.
578 */
579 for (gpio = 0, bank = 0; gpio < ngpio; bank++, gpio += 16) {
580 /* disabled by default, enabled only as needed
581 * There are register sets for 32 GPIOs. 2 banks of 16
582 * GPIOs are covered by each set of registers hence divide by 2
583 */
584 g = chips->regs[bank / 2];
585 writel_relaxed(~0, &g->clr_falling);
586 writel_relaxed(~0, &g->clr_rising);
587
588 /*
589 * Each chip handles 32 gpios, and each irq bank consists of 16
590 * gpio irqs. Pass the irq bank's corresponding controller to
591 * the chained irq handler.
592 */
593 irqdata = devm_kzalloc(&pdev->dev,
594 sizeof(struct
595 davinci_gpio_irq_data),
596 GFP_KERNEL);
597 if (!irqdata) {
598 clk_disable_unprepare(clk);
599 return -ENOMEM;
600 }
601
602 irqdata->regs = g;
603 irqdata->bank_num = bank;
604 irqdata->chip = chips;
605
606 irq_set_chained_handler_and_data(chips->irqs[bank],
607 gpio_irq_handler, irqdata);
608
609 binten |= BIT(bank);
610 }
611
612 done:
613 /*
614 * BINTEN -- per-bank interrupt enable. genirq would also let these
615 * bits be set/cleared dynamically.
616 */
617 writel_relaxed(binten, gpio_base + BINTEN);
618
619 return 0;
620 }
621
davinci_gpio_save_context(struct davinci_gpio_controller * chips,u32 nbank)622 static void davinci_gpio_save_context(struct davinci_gpio_controller *chips,
623 u32 nbank)
624 {
625 struct davinci_gpio_regs __iomem *g;
626 struct davinci_gpio_regs *context;
627 u32 bank;
628 void __iomem *base;
629
630 base = chips->regs[0] - offset_array[0];
631 chips->binten_context = readl_relaxed(base + BINTEN);
632
633 for (bank = 0; bank < nbank; bank++) {
634 g = chips->regs[bank];
635 context = &chips->context[bank];
636 context->dir = readl_relaxed(&g->dir);
637 context->set_data = readl_relaxed(&g->set_data);
638 context->set_rising = readl_relaxed(&g->set_rising);
639 context->set_falling = readl_relaxed(&g->set_falling);
640 }
641
642 /* Clear all interrupt status registers */
643 writel_relaxed(GENMASK(31, 0), &g->intstat);
644 }
645
davinci_gpio_restore_context(struct davinci_gpio_controller * chips,u32 nbank)646 static void davinci_gpio_restore_context(struct davinci_gpio_controller *chips,
647 u32 nbank)
648 {
649 struct davinci_gpio_regs __iomem *g;
650 struct davinci_gpio_regs *context;
651 u32 bank;
652 void __iomem *base;
653
654 base = chips->regs[0] - offset_array[0];
655
656 if (readl_relaxed(base + BINTEN) != chips->binten_context)
657 writel_relaxed(chips->binten_context, base + BINTEN);
658
659 for (bank = 0; bank < nbank; bank++) {
660 g = chips->regs[bank];
661 context = &chips->context[bank];
662 if (readl_relaxed(&g->dir) != context->dir)
663 writel_relaxed(context->dir, &g->dir);
664 if (readl_relaxed(&g->set_data) != context->set_data)
665 writel_relaxed(context->set_data, &g->set_data);
666 if (readl_relaxed(&g->set_rising) != context->set_rising)
667 writel_relaxed(context->set_rising, &g->set_rising);
668 if (readl_relaxed(&g->set_falling) != context->set_falling)
669 writel_relaxed(context->set_falling, &g->set_falling);
670 }
671 }
672
davinci_gpio_suspend(struct device * dev)673 static int davinci_gpio_suspend(struct device *dev)
674 {
675 struct davinci_gpio_controller *chips = dev_get_drvdata(dev);
676 struct davinci_gpio_platform_data *pdata = dev_get_platdata(dev);
677 u32 nbank = DIV_ROUND_UP(pdata->ngpio, 32);
678
679 davinci_gpio_save_context(chips, nbank);
680
681 return 0;
682 }
683
davinci_gpio_resume(struct device * dev)684 static int davinci_gpio_resume(struct device *dev)
685 {
686 struct davinci_gpio_controller *chips = dev_get_drvdata(dev);
687 struct davinci_gpio_platform_data *pdata = dev_get_platdata(dev);
688 u32 nbank = DIV_ROUND_UP(pdata->ngpio, 32);
689
690 davinci_gpio_restore_context(chips, nbank);
691
692 return 0;
693 }
694
695 static DEFINE_SIMPLE_DEV_PM_OPS(davinci_gpio_dev_pm_ops, davinci_gpio_suspend,
696 davinci_gpio_resume);
697
698 static const struct of_device_id davinci_gpio_ids[] = {
699 { .compatible = "ti,keystone-gpio", keystone_gpio_get_irq_chip},
700 { .compatible = "ti,am654-gpio", keystone_gpio_get_irq_chip},
701 { .compatible = "ti,dm6441-gpio", davinci_gpio_get_irq_chip},
702 { /* sentinel */ },
703 };
704 MODULE_DEVICE_TABLE(of, davinci_gpio_ids);
705
706 static struct platform_driver davinci_gpio_driver = {
707 .probe = davinci_gpio_probe,
708 .driver = {
709 .name = "davinci_gpio",
710 .pm = pm_sleep_ptr(&davinci_gpio_dev_pm_ops),
711 .of_match_table = of_match_ptr(davinci_gpio_ids),
712 },
713 };
714
715 /*
716 * GPIO driver registration needs to be done before machine_init functions
717 * access GPIO. Hence davinci_gpio_drv_reg() is a postcore_initcall.
718 */
davinci_gpio_drv_reg(void)719 static int __init davinci_gpio_drv_reg(void)
720 {
721 return platform_driver_register(&davinci_gpio_driver);
722 }
723 postcore_initcall(davinci_gpio_drv_reg);
724
davinci_gpio_exit(void)725 static void __exit davinci_gpio_exit(void)
726 {
727 platform_driver_unregister(&davinci_gpio_driver);
728 }
729 module_exit(davinci_gpio_exit);
730
731 MODULE_AUTHOR("Jan Kotas <jank@cadence.com>");
732 MODULE_DESCRIPTION("DAVINCI GPIO driver");
733 MODULE_LICENSE("GPL");
734 MODULE_ALIAS("platform:gpio-davinci");
735
