1 /*
2 * TI DaVinci GPIO Support
3 *
4 * Copyright (c) 2006-2007 David Brownell
5 * Copyright (c) 2007, MontaVista Software, Inc. <source@mvista.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 */
12 #include <linux/gpio/driver.h>
13 #include <linux/errno.h>
14 #include <linux/kernel.h>
15 #include <linux/clk.h>
16 #include <linux/err.h>
17 #include <linux/io.h>
18 #include <linux/irq.h>
19 #include <linux/irqdomain.h>
20 #include <linux/module.h>
21 #include <linux/of.h>
22 #include <linux/of_device.h>
23 #include <linux/pinctrl/consumer.h>
24 #include <linux/platform_device.h>
25 #include <linux/platform_data/gpio-davinci.h>
26 #include <linux/irqchip/chained_irq.h>
27
28 struct davinci_gpio_regs {
29 u32 dir;
30 u32 out_data;
31 u32 set_data;
32 u32 clr_data;
33 u32 in_data;
34 u32 set_rising;
35 u32 clr_rising;
36 u32 set_falling;
37 u32 clr_falling;
38 u32 intstat;
39 };
40
41 typedef struct irq_chip *(*gpio_get_irq_chip_cb_t)(unsigned int irq);
42
43 #define BINTEN 0x8 /* GPIO Interrupt Per-Bank Enable Register */
44 #define MAX_LABEL_SIZE 20
45
46 static void __iomem *gpio_base;
47 static unsigned int offset_array[5] = {0x10, 0x38, 0x60, 0x88, 0xb0};
48
irq2regs(struct irq_data * d)49 static inline struct davinci_gpio_regs __iomem *irq2regs(struct irq_data *d)
50 {
51 struct davinci_gpio_regs __iomem *g;
52
53 g = (__force struct davinci_gpio_regs __iomem *)irq_data_get_irq_chip_data(d);
54
55 return g;
56 }
57
58 static int davinci_gpio_irq_setup(struct platform_device *pdev);
59
60 /*--------------------------------------------------------------------------*/
61
62 /* board setup code *MUST* setup pinmux and enable the GPIO clock. */
__davinci_direction(struct gpio_chip * chip,unsigned offset,bool out,int value)63 static inline int __davinci_direction(struct gpio_chip *chip,
64 unsigned offset, bool out, int value)
65 {
66 struct davinci_gpio_controller *d = gpiochip_get_data(chip);
67 struct davinci_gpio_regs __iomem *g;
68 unsigned long flags;
69 u32 temp;
70 int bank = offset / 32;
71 u32 mask = __gpio_mask(offset);
72
73 g = d->regs[bank];
74 spin_lock_irqsave(&d->lock, flags);
75 temp = readl_relaxed(&g->dir);
76 if (out) {
77 temp &= ~mask;
78 writel_relaxed(mask, value ? &g->set_data : &g->clr_data);
79 } else {
80 temp |= mask;
81 }
82 writel_relaxed(temp, &g->dir);
83 spin_unlock_irqrestore(&d->lock, flags);
84
85 return 0;
86 }
87
davinci_direction_in(struct gpio_chip * chip,unsigned offset)88 static int davinci_direction_in(struct gpio_chip *chip, unsigned offset)
89 {
90 return __davinci_direction(chip, offset, false, 0);
91 }
92
93 static int
davinci_direction_out(struct gpio_chip * chip,unsigned offset,int value)94 davinci_direction_out(struct gpio_chip *chip, unsigned offset, int value)
95 {
96 return __davinci_direction(chip, offset, true, value);
97 }
98
99 /*
100 * Read the pin's value (works even if it's set up as output);
101 * returns zero/nonzero.
102 *
103 * Note that changes are synched to the GPIO clock, so reading values back
104 * right after you've set them may give old values.
105 */
davinci_gpio_get(struct gpio_chip * chip,unsigned offset)106 static int davinci_gpio_get(struct gpio_chip *chip, unsigned offset)
107 {
108 struct davinci_gpio_controller *d = gpiochip_get_data(chip);
109 struct davinci_gpio_regs __iomem *g;
110 int bank = offset / 32;
111
112 g = d->regs[bank];
113
114 return !!(__gpio_mask(offset) & readl_relaxed(&g->in_data));
115 }
116
117 /*
118 * Assuming the pin is muxed as a gpio output, set its output value.
119 */
120 static void
davinci_gpio_set(struct gpio_chip * chip,unsigned offset,int value)121 davinci_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
122 {
123 struct davinci_gpio_controller *d = gpiochip_get_data(chip);
124 struct davinci_gpio_regs __iomem *g;
125 int bank = offset / 32;
126
127 g = d->regs[bank];
128
129 writel_relaxed(__gpio_mask(offset),
130 value ? &g->set_data : &g->clr_data);
131 }
132
133 static struct davinci_gpio_platform_data *
davinci_gpio_get_pdata(struct platform_device * pdev)134 davinci_gpio_get_pdata(struct platform_device *pdev)
135 {
136 struct device_node *dn = pdev->dev.of_node;
137 struct davinci_gpio_platform_data *pdata;
138 int ret;
139 u32 val;
140
141 if (!IS_ENABLED(CONFIG_OF) || !pdev->dev.of_node)
142 return dev_get_platdata(&pdev->dev);
143
144 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
145 if (!pdata)
146 return NULL;
147
148 ret = of_property_read_u32(dn, "ti,ngpio", &val);
149 if (ret)
150 goto of_err;
151
152 pdata->ngpio = val;
153
154 ret = of_property_read_u32(dn, "ti,davinci-gpio-unbanked", &val);
155 if (ret)
156 goto of_err;
157
158 pdata->gpio_unbanked = val;
159
160 return pdata;
161
162 of_err:
163 dev_err(&pdev->dev, "Populating pdata from DT failed: err %d\n", ret);
164 return NULL;
165 }
166
davinci_gpio_probe(struct platform_device * pdev)167 static int davinci_gpio_probe(struct platform_device *pdev)
168 {
169 static int ctrl_num, bank_base;
170 int gpio, bank, i, ret = 0;
171 unsigned int ngpio, nbank, nirq;
172 struct davinci_gpio_controller *chips;
173 struct davinci_gpio_platform_data *pdata;
174 struct device *dev = &pdev->dev;
175 struct resource *res;
176 char label[MAX_LABEL_SIZE];
177
178 pdata = davinci_gpio_get_pdata(pdev);
179 if (!pdata) {
180 dev_err(dev, "No platform data found\n");
181 return -EINVAL;
182 }
183
184 dev->platform_data = pdata;
185
186 /*
187 * The gpio banks conceptually expose a segmented bitmap,
188 * and "ngpio" is one more than the largest zero-based
189 * bit index that's valid.
190 */
191 ngpio = pdata->ngpio;
192 if (ngpio == 0) {
193 dev_err(dev, "How many GPIOs?\n");
194 return -EINVAL;
195 }
196
197 if (WARN_ON(ARCH_NR_GPIOS < ngpio))
198 ngpio = ARCH_NR_GPIOS;
199
200 /*
201 * If there are unbanked interrupts then the number of
202 * interrupts is equal to number of gpios else all are banked so
203 * number of interrupts is equal to number of banks(each with 16 gpios)
204 */
205 if (pdata->gpio_unbanked)
206 nirq = pdata->gpio_unbanked;
207 else
208 nirq = DIV_ROUND_UP(ngpio, 16);
209
210 nbank = DIV_ROUND_UP(ngpio, 32);
211 chips = devm_kcalloc(dev,
212 nbank, sizeof(struct davinci_gpio_controller),
213 GFP_KERNEL);
214 if (!chips)
215 return -ENOMEM;
216
217 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
218 gpio_base = devm_ioremap_resource(dev, res);
219 if (IS_ERR(gpio_base))
220 return PTR_ERR(gpio_base);
221
222 for (i = 0; i < nirq; i++) {
223 chips->irqs[i] = platform_get_irq(pdev, i);
224 if (chips->irqs[i] < 0) {
225 dev_info(dev, "IRQ not populated, err = %d\n",
226 chips->irqs[i]);
227 return chips->irqs[i];
228 }
229 }
230
231 snprintf(label, MAX_LABEL_SIZE, "davinci_gpio.%d", ctrl_num++);
232 chips->chip.label = devm_kstrdup(dev, label, GFP_KERNEL);
233 if (!chips->chip.label)
234 return -ENOMEM;
235
236 chips->chip.direction_input = davinci_direction_in;
237 chips->chip.get = davinci_gpio_get;
238 chips->chip.direction_output = davinci_direction_out;
239 chips->chip.set = davinci_gpio_set;
240
241 chips->chip.ngpio = ngpio;
242 chips->chip.base = bank_base;
243
244 #ifdef CONFIG_OF_GPIO
245 chips->chip.of_gpio_n_cells = 2;
246 chips->chip.parent = dev;
247 chips->chip.of_node = dev->of_node;
248
249 if (of_property_read_bool(dev->of_node, "gpio-ranges")) {
250 chips->chip.request = gpiochip_generic_request;
251 chips->chip.free = gpiochip_generic_free;
252 }
253 #endif
254 spin_lock_init(&chips->lock);
255 bank_base += ngpio;
256
257 for (gpio = 0, bank = 0; gpio < ngpio; gpio += 32, bank++)
258 chips->regs[bank] = gpio_base + offset_array[bank];
259
260 ret = devm_gpiochip_add_data(dev, &chips->chip, chips);
261 if (ret)
262 goto err;
263
264 platform_set_drvdata(pdev, chips);
265 ret = davinci_gpio_irq_setup(pdev);
266 if (ret)
267 goto err;
268
269 return 0;
270
271 err:
272 /* Revert the static variable increments */
273 ctrl_num--;
274 bank_base -= ngpio;
275
276 return ret;
277 }
278
279 /*--------------------------------------------------------------------------*/
280 /*
281 * We expect irqs will normally be set up as input pins, but they can also be
282 * used as output pins ... which is convenient for testing.
283 *
284 * NOTE: The first few GPIOs also have direct INTC hookups in addition
285 * to their GPIOBNK0 irq, with a bit less overhead.
286 *
287 * All those INTC hookups (direct, plus several IRQ banks) can also
288 * serve as EDMA event triggers.
289 */
290
gpio_irq_disable(struct irq_data * d)291 static void gpio_irq_disable(struct irq_data *d)
292 {
293 struct davinci_gpio_regs __iomem *g = irq2regs(d);
294 u32 mask = (u32) irq_data_get_irq_handler_data(d);
295
296 writel_relaxed(mask, &g->clr_falling);
297 writel_relaxed(mask, &g->clr_rising);
298 }
299
gpio_irq_enable(struct irq_data * d)300 static void gpio_irq_enable(struct irq_data *d)
301 {
302 struct davinci_gpio_regs __iomem *g = irq2regs(d);
303 u32 mask = (u32) irq_data_get_irq_handler_data(d);
304 unsigned status = irqd_get_trigger_type(d);
305
306 status &= IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING;
307 if (!status)
308 status = IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING;
309
310 if (status & IRQ_TYPE_EDGE_FALLING)
311 writel_relaxed(mask, &g->set_falling);
312 if (status & IRQ_TYPE_EDGE_RISING)
313 writel_relaxed(mask, &g->set_rising);
314 }
315
gpio_irq_type(struct irq_data * d,unsigned trigger)316 static int gpio_irq_type(struct irq_data *d, unsigned trigger)
317 {
318 if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
319 return -EINVAL;
320
321 return 0;
322 }
323
324 static struct irq_chip gpio_irqchip = {
325 .name = "GPIO",
326 .irq_enable = gpio_irq_enable,
327 .irq_disable = gpio_irq_disable,
328 .irq_set_type = gpio_irq_type,
329 .flags = IRQCHIP_SET_TYPE_MASKED,
330 };
331
gpio_irq_handler(struct irq_desc * desc)332 static void gpio_irq_handler(struct irq_desc *desc)
333 {
334 struct davinci_gpio_regs __iomem *g;
335 u32 mask = 0xffff;
336 int bank_num;
337 struct davinci_gpio_controller *d;
338 struct davinci_gpio_irq_data *irqdata;
339
340 irqdata = (struct davinci_gpio_irq_data *)irq_desc_get_handler_data(desc);
341 bank_num = irqdata->bank_num;
342 g = irqdata->regs;
343 d = irqdata->chip;
344
345 /* we only care about one bank */
346 if ((bank_num % 2) == 1)
347 mask <<= 16;
348
349 /* temporarily mask (level sensitive) parent IRQ */
350 chained_irq_enter(irq_desc_get_chip(desc), desc);
351 while (1) {
352 u32 status;
353 int bit;
354 irq_hw_number_t hw_irq;
355
356 /* ack any irqs */
357 status = readl_relaxed(&g->intstat) & mask;
358 if (!status)
359 break;
360 writel_relaxed(status, &g->intstat);
361
362 /* now demux them to the right lowlevel handler */
363
364 while (status) {
365 bit = __ffs(status);
366 status &= ~BIT(bit);
367 /* Max number of gpios per controller is 144 so
368 * hw_irq will be in [0..143]
369 */
370 hw_irq = (bank_num / 2) * 32 + bit;
371
372 generic_handle_irq(
373 irq_find_mapping(d->irq_domain, hw_irq));
374 }
375 }
376 chained_irq_exit(irq_desc_get_chip(desc), desc);
377 /* now it may re-trigger */
378 }
379
gpio_to_irq_banked(struct gpio_chip * chip,unsigned offset)380 static int gpio_to_irq_banked(struct gpio_chip *chip, unsigned offset)
381 {
382 struct davinci_gpio_controller *d = gpiochip_get_data(chip);
383
384 if (d->irq_domain)
385 return irq_create_mapping(d->irq_domain, offset);
386 else
387 return -ENXIO;
388 }
389
gpio_to_irq_unbanked(struct gpio_chip * chip,unsigned offset)390 static int gpio_to_irq_unbanked(struct gpio_chip *chip, unsigned offset)
391 {
392 struct davinci_gpio_controller *d = gpiochip_get_data(chip);
393
394 /*
395 * NOTE: we assume for now that only irqs in the first gpio_chip
396 * can provide direct-mapped IRQs to AINTC (up to 32 GPIOs).
397 */
398 if (offset < d->gpio_unbanked)
399 return d->irqs[offset];
400 else
401 return -ENODEV;
402 }
403
gpio_irq_type_unbanked(struct irq_data * data,unsigned trigger)404 static int gpio_irq_type_unbanked(struct irq_data *data, unsigned trigger)
405 {
406 struct davinci_gpio_controller *d;
407 struct davinci_gpio_regs __iomem *g;
408 u32 mask, i;
409
410 d = (struct davinci_gpio_controller *)irq_data_get_irq_handler_data(data);
411 g = (struct davinci_gpio_regs __iomem *)d->regs[0];
412 for (i = 0; i < MAX_INT_PER_BANK; i++)
413 if (data->irq == d->irqs[i])
414 break;
415
416 if (i == MAX_INT_PER_BANK)
417 return -EINVAL;
418
419 mask = __gpio_mask(i);
420
421 if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
422 return -EINVAL;
423
424 writel_relaxed(mask, (trigger & IRQ_TYPE_EDGE_FALLING)
425 ? &g->set_falling : &g->clr_falling);
426 writel_relaxed(mask, (trigger & IRQ_TYPE_EDGE_RISING)
427 ? &g->set_rising : &g->clr_rising);
428
429 return 0;
430 }
431
432 static int
davinci_gpio_irq_map(struct irq_domain * d,unsigned int irq,irq_hw_number_t hw)433 davinci_gpio_irq_map(struct irq_domain *d, unsigned int irq,
434 irq_hw_number_t hw)
435 {
436 struct davinci_gpio_controller *chips =
437 (struct davinci_gpio_controller *)d->host_data;
438 struct davinci_gpio_regs __iomem *g = chips->regs[hw / 32];
439
440 irq_set_chip_and_handler_name(irq, &gpio_irqchip, handle_simple_irq,
441 "davinci_gpio");
442 irq_set_irq_type(irq, IRQ_TYPE_NONE);
443 irq_set_chip_data(irq, (__force void *)g);
444 irq_set_handler_data(irq, (void *)__gpio_mask(hw));
445
446 return 0;
447 }
448
449 static const struct irq_domain_ops davinci_gpio_irq_ops = {
450 .map = davinci_gpio_irq_map,
451 .xlate = irq_domain_xlate_onetwocell,
452 };
453
davinci_gpio_get_irq_chip(unsigned int irq)454 static struct irq_chip *davinci_gpio_get_irq_chip(unsigned int irq)
455 {
456 static struct irq_chip_type gpio_unbanked;
457
458 gpio_unbanked = *irq_data_get_chip_type(irq_get_irq_data(irq));
459
460 return &gpio_unbanked.chip;
461 };
462
keystone_gpio_get_irq_chip(unsigned int irq)463 static struct irq_chip *keystone_gpio_get_irq_chip(unsigned int irq)
464 {
465 static struct irq_chip gpio_unbanked;
466
467 gpio_unbanked = *irq_get_chip(irq);
468 return &gpio_unbanked;
469 };
470
471 static const struct of_device_id davinci_gpio_ids[];
472
473 /*
474 * NOTE: for suspend/resume, probably best to make a platform_device with
475 * suspend_late/resume_resume calls hooking into results of the set_wake()
476 * calls ... so if no gpios are wakeup events the clock can be disabled,
477 * with outputs left at previously set levels, and so that VDD3P3V.IOPWDN0
478 * (dm6446) can be set appropriately for GPIOV33 pins.
479 */
480
davinci_gpio_irq_setup(struct platform_device * pdev)481 static int davinci_gpio_irq_setup(struct platform_device *pdev)
482 {
483 unsigned gpio, bank;
484 int irq;
485 int ret;
486 struct clk *clk;
487 u32 binten = 0;
488 unsigned ngpio;
489 struct device *dev = &pdev->dev;
490 struct davinci_gpio_controller *chips = platform_get_drvdata(pdev);
491 struct davinci_gpio_platform_data *pdata = dev->platform_data;
492 struct davinci_gpio_regs __iomem *g;
493 struct irq_domain *irq_domain = NULL;
494 const struct of_device_id *match;
495 struct irq_chip *irq_chip;
496 struct davinci_gpio_irq_data *irqdata;
497 gpio_get_irq_chip_cb_t gpio_get_irq_chip;
498
499 /*
500 * Use davinci_gpio_get_irq_chip by default to handle non DT cases
501 */
502 gpio_get_irq_chip = davinci_gpio_get_irq_chip;
503 match = of_match_device(of_match_ptr(davinci_gpio_ids),
504 dev);
505 if (match)
506 gpio_get_irq_chip = (gpio_get_irq_chip_cb_t)match->data;
507
508 ngpio = pdata->ngpio;
509
510 clk = devm_clk_get(dev, "gpio");
511 if (IS_ERR(clk)) {
512 dev_err(dev, "Error %ld getting gpio clock\n", PTR_ERR(clk));
513 return PTR_ERR(clk);
514 }
515
516 ret = clk_prepare_enable(clk);
517 if (ret)
518 return ret;
519
520 if (!pdata->gpio_unbanked) {
521 irq = devm_irq_alloc_descs(dev, -1, 0, ngpio, 0);
522 if (irq < 0) {
523 dev_err(dev, "Couldn't allocate IRQ numbers\n");
524 clk_disable_unprepare(clk);
525 return irq;
526 }
527
528 irq_domain = irq_domain_add_legacy(dev->of_node, ngpio, irq, 0,
529 &davinci_gpio_irq_ops,
530 chips);
531 if (!irq_domain) {
532 dev_err(dev, "Couldn't register an IRQ domain\n");
533 clk_disable_unprepare(clk);
534 return -ENODEV;
535 }
536 }
537
538 /*
539 * Arrange gpio_to_irq() support, handling either direct IRQs or
540 * banked IRQs. Having GPIOs in the first GPIO bank use direct
541 * IRQs, while the others use banked IRQs, would need some setup
542 * tweaks to recognize hardware which can do that.
543 */
544 chips->chip.to_irq = gpio_to_irq_banked;
545 chips->irq_domain = irq_domain;
546
547 /*
548 * AINTC can handle direct/unbanked IRQs for GPIOs, with the GPIO
549 * controller only handling trigger modes. We currently assume no
550 * IRQ mux conflicts; gpio_irq_type_unbanked() is only for GPIOs.
551 */
552 if (pdata->gpio_unbanked) {
553 /* pass "bank 0" GPIO IRQs to AINTC */
554 chips->chip.to_irq = gpio_to_irq_unbanked;
555 chips->gpio_unbanked = pdata->gpio_unbanked;
556 binten = GENMASK(pdata->gpio_unbanked / 16, 0);
557
558 /* AINTC handles mask/unmask; GPIO handles triggering */
559 irq = chips->irqs[0];
560 irq_chip = gpio_get_irq_chip(irq);
561 irq_chip->name = "GPIO-AINTC";
562 irq_chip->irq_set_type = gpio_irq_type_unbanked;
563
564 /* default trigger: both edges */
565 g = chips->regs[0];
566 writel_relaxed(~0, &g->set_falling);
567 writel_relaxed(~0, &g->set_rising);
568
569 /* set the direct IRQs up to use that irqchip */
570 for (gpio = 0; gpio < pdata->gpio_unbanked; gpio++) {
571 irq_set_chip(chips->irqs[gpio], irq_chip);
572 irq_set_handler_data(chips->irqs[gpio], chips);
573 irq_set_status_flags(chips->irqs[gpio],
574 IRQ_TYPE_EDGE_BOTH);
575 }
576
577 goto done;
578 }
579
580 /*
581 * Or, AINTC can handle IRQs for banks of 16 GPIO IRQs, which we
582 * then chain through our own handler.
583 */
584 for (gpio = 0, bank = 0; gpio < ngpio; bank++, gpio += 16) {
585 /* disabled by default, enabled only as needed
586 * There are register sets for 32 GPIOs. 2 banks of 16
587 * GPIOs are covered by each set of registers hence divide by 2
588 */
589 g = chips->regs[bank / 2];
590 writel_relaxed(~0, &g->clr_falling);
591 writel_relaxed(~0, &g->clr_rising);
592
593 /*
594 * Each chip handles 32 gpios, and each irq bank consists of 16
595 * gpio irqs. Pass the irq bank's corresponding controller to
596 * the chained irq handler.
597 */
598 irqdata = devm_kzalloc(&pdev->dev,
599 sizeof(struct
600 davinci_gpio_irq_data),
601 GFP_KERNEL);
602 if (!irqdata) {
603 clk_disable_unprepare(clk);
604 return -ENOMEM;
605 }
606
607 irqdata->regs = g;
608 irqdata->bank_num = bank;
609 irqdata->chip = chips;
610
611 irq_set_chained_handler_and_data(chips->irqs[bank],
612 gpio_irq_handler, irqdata);
613
614 binten |= BIT(bank);
615 }
616
617 done:
618 /*
619 * BINTEN -- per-bank interrupt enable. genirq would also let these
620 * bits be set/cleared dynamically.
621 */
622 writel_relaxed(binten, gpio_base + BINTEN);
623
624 return 0;
625 }
626
627 static const struct of_device_id davinci_gpio_ids[] = {
628 { .compatible = "ti,keystone-gpio", keystone_gpio_get_irq_chip},
629 { .compatible = "ti,dm6441-gpio", davinci_gpio_get_irq_chip},
630 { /* sentinel */ },
631 };
632 MODULE_DEVICE_TABLE(of, davinci_gpio_ids);
633
634 static struct platform_driver davinci_gpio_driver = {
635 .probe = davinci_gpio_probe,
636 .driver = {
637 .name = "davinci_gpio",
638 .of_match_table = of_match_ptr(davinci_gpio_ids),
639 },
640 };
641
642 /**
643 * GPIO driver registration needs to be done before machine_init functions
644 * access GPIO. Hence davinci_gpio_drv_reg() is a postcore_initcall.
645 */
davinci_gpio_drv_reg(void)646 static int __init davinci_gpio_drv_reg(void)
647 {
648 return platform_driver_register(&davinci_gpio_driver);
649 }
650 postcore_initcall(davinci_gpio_drv_reg);
651