1 /*
2 * Header file for the Atmel AHB DMA Controller driver
3 *
4 * Copyright (C) 2008 Atmel Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 */
11 #ifndef AT_HDMAC_REGS_H
12 #define AT_HDMAC_REGS_H
13
14 #include <linux/platform_data/dma-atmel.h>
15
16 #define AT_DMA_MAX_NR_CHANNELS 8
17
18
19 #define AT_DMA_GCFG 0x00 /* Global Configuration Register */
20 #define AT_DMA_IF_BIGEND(i) (0x1 << (i)) /* AHB-Lite Interface i in Big-endian mode */
21 #define AT_DMA_ARB_CFG (0x1 << 4) /* Arbiter mode. */
22 #define AT_DMA_ARB_CFG_FIXED (0x0 << 4)
23 #define AT_DMA_ARB_CFG_ROUND_ROBIN (0x1 << 4)
24
25 #define AT_DMA_EN 0x04 /* Controller Enable Register */
26 #define AT_DMA_ENABLE (0x1 << 0)
27
28 #define AT_DMA_SREQ 0x08 /* Software Single Request Register */
29 #define AT_DMA_SSREQ(x) (0x1 << ((x) << 1)) /* Request a source single transfer on channel x */
30 #define AT_DMA_DSREQ(x) (0x1 << (1 + ((x) << 1))) /* Request a destination single transfer on channel x */
31
32 #define AT_DMA_CREQ 0x0C /* Software Chunk Transfer Request Register */
33 #define AT_DMA_SCREQ(x) (0x1 << ((x) << 1)) /* Request a source chunk transfer on channel x */
34 #define AT_DMA_DCREQ(x) (0x1 << (1 + ((x) << 1))) /* Request a destination chunk transfer on channel x */
35
36 #define AT_DMA_LAST 0x10 /* Software Last Transfer Flag Register */
37 #define AT_DMA_SLAST(x) (0x1 << ((x) << 1)) /* This src rq is last tx of buffer on channel x */
38 #define AT_DMA_DLAST(x) (0x1 << (1 + ((x) << 1))) /* This dst rq is last tx of buffer on channel x */
39
40 #define AT_DMA_SYNC 0x14 /* Request Synchronization Register */
41 #define AT_DMA_SYR(h) (0x1 << (h)) /* Synchronize handshake line h */
42
43 /* Error, Chained Buffer transfer completed and Buffer transfer completed Interrupt registers */
44 #define AT_DMA_EBCIER 0x18 /* Enable register */
45 #define AT_DMA_EBCIDR 0x1C /* Disable register */
46 #define AT_DMA_EBCIMR 0x20 /* Mask Register */
47 #define AT_DMA_EBCISR 0x24 /* Status Register */
48 #define AT_DMA_CBTC_OFFSET 8
49 #define AT_DMA_ERR_OFFSET 16
50 #define AT_DMA_BTC(x) (0x1 << (x))
51 #define AT_DMA_CBTC(x) (0x1 << (AT_DMA_CBTC_OFFSET + (x)))
52 #define AT_DMA_ERR(x) (0x1 << (AT_DMA_ERR_OFFSET + (x)))
53
54 #define AT_DMA_CHER 0x28 /* Channel Handler Enable Register */
55 #define AT_DMA_ENA(x) (0x1 << (x))
56 #define AT_DMA_SUSP(x) (0x1 << ( 8 + (x)))
57 #define AT_DMA_KEEP(x) (0x1 << (24 + (x)))
58
59 #define AT_DMA_CHDR 0x2C /* Channel Handler Disable Register */
60 #define AT_DMA_DIS(x) (0x1 << (x))
61 #define AT_DMA_RES(x) (0x1 << ( 8 + (x)))
62
63 #define AT_DMA_CHSR 0x30 /* Channel Handler Status Register */
64 #define AT_DMA_EMPT(x) (0x1 << (16 + (x)))
65 #define AT_DMA_STAL(x) (0x1 << (24 + (x)))
66
67
68 #define AT_DMA_CH_REGS_BASE 0x3C /* Channel registers base address */
69 #define ch_regs(x) (AT_DMA_CH_REGS_BASE + (x) * 0x28) /* Channel x base addr */
70
71 /* Hardware register offset for each channel */
72 #define ATC_SADDR_OFFSET 0x00 /* Source Address Register */
73 #define ATC_DADDR_OFFSET 0x04 /* Destination Address Register */
74 #define ATC_DSCR_OFFSET 0x08 /* Descriptor Address Register */
75 #define ATC_CTRLA_OFFSET 0x0C /* Control A Register */
76 #define ATC_CTRLB_OFFSET 0x10 /* Control B Register */
77 #define ATC_CFG_OFFSET 0x14 /* Configuration Register */
78 #define ATC_SPIP_OFFSET 0x18 /* Src PIP Configuration Register */
79 #define ATC_DPIP_OFFSET 0x1C /* Dst PIP Configuration Register */
80
81
82 /* Bitfield definitions */
83
84 /* Bitfields in DSCR */
85 #define ATC_DSCR_IF(i) (0x3 & (i)) /* Dsc feched via AHB-Lite Interface i */
86
87 /* Bitfields in CTRLA */
88 #define ATC_BTSIZE_MAX 0xFFFFUL /* Maximum Buffer Transfer Size */
89 #define ATC_BTSIZE(x) (ATC_BTSIZE_MAX & (x)) /* Buffer Transfer Size */
90 #define ATC_SCSIZE_MASK (0x7 << 16) /* Source Chunk Transfer Size */
91 #define ATC_SCSIZE(x) (ATC_SCSIZE_MASK & ((x) << 16))
92 #define ATC_SCSIZE_1 (0x0 << 16)
93 #define ATC_SCSIZE_4 (0x1 << 16)
94 #define ATC_SCSIZE_8 (0x2 << 16)
95 #define ATC_SCSIZE_16 (0x3 << 16)
96 #define ATC_SCSIZE_32 (0x4 << 16)
97 #define ATC_SCSIZE_64 (0x5 << 16)
98 #define ATC_SCSIZE_128 (0x6 << 16)
99 #define ATC_SCSIZE_256 (0x7 << 16)
100 #define ATC_DCSIZE_MASK (0x7 << 20) /* Destination Chunk Transfer Size */
101 #define ATC_DCSIZE(x) (ATC_DCSIZE_MASK & ((x) << 20))
102 #define ATC_DCSIZE_1 (0x0 << 20)
103 #define ATC_DCSIZE_4 (0x1 << 20)
104 #define ATC_DCSIZE_8 (0x2 << 20)
105 #define ATC_DCSIZE_16 (0x3 << 20)
106 #define ATC_DCSIZE_32 (0x4 << 20)
107 #define ATC_DCSIZE_64 (0x5 << 20)
108 #define ATC_DCSIZE_128 (0x6 << 20)
109 #define ATC_DCSIZE_256 (0x7 << 20)
110 #define ATC_SRC_WIDTH_MASK (0x3 << 24) /* Source Single Transfer Size */
111 #define ATC_SRC_WIDTH(x) ((x) << 24)
112 #define ATC_SRC_WIDTH_BYTE (0x0 << 24)
113 #define ATC_SRC_WIDTH_HALFWORD (0x1 << 24)
114 #define ATC_SRC_WIDTH_WORD (0x2 << 24)
115 #define ATC_REG_TO_SRC_WIDTH(r) (((r) >> 24) & 0x3)
116 #define ATC_DST_WIDTH_MASK (0x3 << 28) /* Destination Single Transfer Size */
117 #define ATC_DST_WIDTH(x) ((x) << 28)
118 #define ATC_DST_WIDTH_BYTE (0x0 << 28)
119 #define ATC_DST_WIDTH_HALFWORD (0x1 << 28)
120 #define ATC_DST_WIDTH_WORD (0x2 << 28)
121 #define ATC_DONE (0x1 << 31) /* Tx Done (only written back in descriptor) */
122
123 /* Bitfields in CTRLB */
124 #define ATC_SIF(i) (0x3 & (i)) /* Src tx done via AHB-Lite Interface i */
125 #define ATC_DIF(i) ((0x3 & (i)) << 4) /* Dst tx done via AHB-Lite Interface i */
126 /* Specify AHB interfaces */
127 #define AT_DMA_MEM_IF 0 /* interface 0 as memory interface */
128 #define AT_DMA_PER_IF 1 /* interface 1 as peripheral interface */
129
130 #define ATC_SRC_PIP (0x1 << 8) /* Source Picture-in-Picture enabled */
131 #define ATC_DST_PIP (0x1 << 12) /* Destination Picture-in-Picture enabled */
132 #define ATC_SRC_DSCR_DIS (0x1 << 16) /* Src Descriptor fetch disable */
133 #define ATC_DST_DSCR_DIS (0x1 << 20) /* Dst Descriptor fetch disable */
134 #define ATC_FC_MASK (0x7 << 21) /* Choose Flow Controller */
135 #define ATC_FC_MEM2MEM (0x0 << 21) /* Mem-to-Mem (DMA) */
136 #define ATC_FC_MEM2PER (0x1 << 21) /* Mem-to-Periph (DMA) */
137 #define ATC_FC_PER2MEM (0x2 << 21) /* Periph-to-Mem (DMA) */
138 #define ATC_FC_PER2PER (0x3 << 21) /* Periph-to-Periph (DMA) */
139 #define ATC_FC_PER2MEM_PER (0x4 << 21) /* Periph-to-Mem (Peripheral) */
140 #define ATC_FC_MEM2PER_PER (0x5 << 21) /* Mem-to-Periph (Peripheral) */
141 #define ATC_FC_PER2PER_SRCPER (0x6 << 21) /* Periph-to-Periph (Src Peripheral) */
142 #define ATC_FC_PER2PER_DSTPER (0x7 << 21) /* Periph-to-Periph (Dst Peripheral) */
143 #define ATC_SRC_ADDR_MODE_MASK (0x3 << 24)
144 #define ATC_SRC_ADDR_MODE_INCR (0x0 << 24) /* Incrementing Mode */
145 #define ATC_SRC_ADDR_MODE_DECR (0x1 << 24) /* Decrementing Mode */
146 #define ATC_SRC_ADDR_MODE_FIXED (0x2 << 24) /* Fixed Mode */
147 #define ATC_DST_ADDR_MODE_MASK (0x3 << 28)
148 #define ATC_DST_ADDR_MODE_INCR (0x0 << 28) /* Incrementing Mode */
149 #define ATC_DST_ADDR_MODE_DECR (0x1 << 28) /* Decrementing Mode */
150 #define ATC_DST_ADDR_MODE_FIXED (0x2 << 28) /* Fixed Mode */
151 #define ATC_IEN (0x1 << 30) /* BTC interrupt enable (active low) */
152 #define ATC_AUTO (0x1 << 31) /* Auto multiple buffer tx enable */
153
154 /* Bitfields in CFG */
155 /* are in at_hdmac.h */
156
157 /* Bitfields in SPIP */
158 #define ATC_SPIP_HOLE(x) (0xFFFFU & (x))
159 #define ATC_SPIP_BOUNDARY(x) ((0x3FF & (x)) << 16)
160
161 /* Bitfields in DPIP */
162 #define ATC_DPIP_HOLE(x) (0xFFFFU & (x))
163 #define ATC_DPIP_BOUNDARY(x) ((0x3FF & (x)) << 16)
164
165
166 /*-- descriptors -----------------------------------------------------*/
167
168 /* LLI == Linked List Item; aka DMA buffer descriptor */
169 struct at_lli {
170 /* values that are not changed by hardware */
171 dma_addr_t saddr;
172 dma_addr_t daddr;
173 /* value that may get written back: */
174 u32 ctrla;
175 /* more values that are not changed by hardware */
176 u32 ctrlb;
177 dma_addr_t dscr; /* chain to next lli */
178 };
179
180 /**
181 * struct at_desc - software descriptor
182 * @at_lli: hardware lli structure
183 * @txd: support for the async_tx api
184 * @desc_node: node on the channed descriptors list
185 * @len: descriptor byte count
186 * @total_len: total transaction byte count
187 */
188 struct at_desc {
189 /* FIRST values the hardware uses */
190 struct at_lli lli;
191
192 /* THEN values for driver housekeeping */
193 struct list_head tx_list;
194 struct dma_async_tx_descriptor txd;
195 struct list_head desc_node;
196 size_t len;
197 size_t total_len;
198
199 /* Interleaved data */
200 size_t boundary;
201 size_t dst_hole;
202 size_t src_hole;
203
204 /* Memset temporary buffer */
205 bool memset_buffer;
206 dma_addr_t memset_paddr;
207 int *memset_vaddr;
208 };
209
210 static inline struct at_desc *
txd_to_at_desc(struct dma_async_tx_descriptor * txd)211 txd_to_at_desc(struct dma_async_tx_descriptor *txd)
212 {
213 return container_of(txd, struct at_desc, txd);
214 }
215
216
217 /*-- Channels --------------------------------------------------------*/
218
219 /**
220 * atc_status - information bits stored in channel status flag
221 *
222 * Manipulated with atomic operations.
223 */
224 enum atc_status {
225 ATC_IS_ERROR = 0,
226 ATC_IS_PAUSED = 1,
227 ATC_IS_CYCLIC = 24,
228 };
229
230 /**
231 * struct at_dma_chan - internal representation of an Atmel HDMAC channel
232 * @chan_common: common dmaengine channel object members
233 * @device: parent device
234 * @ch_regs: memory mapped register base
235 * @mask: channel index in a mask
236 * @per_if: peripheral interface
237 * @mem_if: memory interface
238 * @status: transmit status information from irq/prep* functions
239 * to tasklet (use atomic operations)
240 * @tasklet: bottom half to finish transaction work
241 * @save_cfg: configuration register that is saved on suspend/resume cycle
242 * @save_dscr: for cyclic operations, preserve next descriptor address in
243 * the cyclic list on suspend/resume cycle
244 * @dma_sconfig: configuration for slave transfers, passed via
245 * .device_config
246 * @lock: serializes enqueue/dequeue operations to descriptors lists
247 * @active_list: list of descriptors dmaengine is being running on
248 * @queue: list of descriptors ready to be submitted to engine
249 * @free_list: list of descriptors usable by the channel
250 * @descs_allocated: records the actual size of the descriptor pool
251 */
252 struct at_dma_chan {
253 struct dma_chan chan_common;
254 struct at_dma *device;
255 void __iomem *ch_regs;
256 u8 mask;
257 u8 per_if;
258 u8 mem_if;
259 unsigned long status;
260 struct tasklet_struct tasklet;
261 u32 save_cfg;
262 u32 save_dscr;
263 struct dma_slave_config dma_sconfig;
264
265 spinlock_t lock;
266
267 /* these other elements are all protected by lock */
268 struct list_head active_list;
269 struct list_head queue;
270 struct list_head free_list;
271 unsigned int descs_allocated;
272 };
273
274 #define channel_readl(atchan, name) \
275 __raw_readl((atchan)->ch_regs + ATC_##name##_OFFSET)
276
277 #define channel_writel(atchan, name, val) \
278 __raw_writel((val), (atchan)->ch_regs + ATC_##name##_OFFSET)
279
to_at_dma_chan(struct dma_chan * dchan)280 static inline struct at_dma_chan *to_at_dma_chan(struct dma_chan *dchan)
281 {
282 return container_of(dchan, struct at_dma_chan, chan_common);
283 }
284
285 /*
286 * Fix sconfig's burst size according to at_hdmac. We need to convert them as:
287 * 1 -> 0, 4 -> 1, 8 -> 2, 16 -> 3, 32 -> 4, 64 -> 5, 128 -> 6, 256 -> 7.
288 *
289 * This can be done by finding most significant bit set.
290 */
convert_burst(u32 * maxburst)291 static inline void convert_burst(u32 *maxburst)
292 {
293 if (*maxburst > 1)
294 *maxburst = fls(*maxburst) - 2;
295 else
296 *maxburst = 0;
297 }
298
299 /*
300 * Fix sconfig's bus width according to at_hdmac.
301 * 1 byte -> 0, 2 bytes -> 1, 4 bytes -> 2.
302 */
convert_buswidth(enum dma_slave_buswidth addr_width)303 static inline u8 convert_buswidth(enum dma_slave_buswidth addr_width)
304 {
305 switch (addr_width) {
306 case DMA_SLAVE_BUSWIDTH_2_BYTES:
307 return 1;
308 case DMA_SLAVE_BUSWIDTH_4_BYTES:
309 return 2;
310 default:
311 /* For 1 byte width or fallback */
312 return 0;
313 }
314 }
315
316 /*-- Controller ------------------------------------------------------*/
317
318 /**
319 * struct at_dma - internal representation of an Atmel HDMA Controller
320 * @chan_common: common dmaengine dma_device object members
321 * @atdma_devtype: identifier of DMA controller compatibility
322 * @ch_regs: memory mapped register base
323 * @clk: dma controller clock
324 * @save_imr: interrupt mask register that is saved on suspend/resume cycle
325 * @all_chan_mask: all channels availlable in a mask
326 * @dma_desc_pool: base of DMA descriptor region (DMA address)
327 * @chan: channels table to store at_dma_chan structures
328 */
329 struct at_dma {
330 struct dma_device dma_common;
331 void __iomem *regs;
332 struct clk *clk;
333 u32 save_imr;
334
335 u8 all_chan_mask;
336
337 struct dma_pool *dma_desc_pool;
338 struct dma_pool *memset_pool;
339 /* AT THE END channels table */
340 struct at_dma_chan chan[0];
341 };
342
343 #define dma_readl(atdma, name) \
344 __raw_readl((atdma)->regs + AT_DMA_##name)
345 #define dma_writel(atdma, name, val) \
346 __raw_writel((val), (atdma)->regs + AT_DMA_##name)
347
to_at_dma(struct dma_device * ddev)348 static inline struct at_dma *to_at_dma(struct dma_device *ddev)
349 {
350 return container_of(ddev, struct at_dma, dma_common);
351 }
352
353
354 /*-- Helper functions ------------------------------------------------*/
355
chan2dev(struct dma_chan * chan)356 static struct device *chan2dev(struct dma_chan *chan)
357 {
358 return &chan->dev->device;
359 }
360
361 #if defined(VERBOSE_DEBUG)
vdbg_dump_regs(struct at_dma_chan * atchan)362 static void vdbg_dump_regs(struct at_dma_chan *atchan)
363 {
364 struct at_dma *atdma = to_at_dma(atchan->chan_common.device);
365
366 dev_err(chan2dev(&atchan->chan_common),
367 " channel %d : imr = 0x%x, chsr = 0x%x\n",
368 atchan->chan_common.chan_id,
369 dma_readl(atdma, EBCIMR),
370 dma_readl(atdma, CHSR));
371
372 dev_err(chan2dev(&atchan->chan_common),
373 " channel: s0x%x d0x%x ctrl0x%x:0x%x cfg0x%x l0x%x\n",
374 channel_readl(atchan, SADDR),
375 channel_readl(atchan, DADDR),
376 channel_readl(atchan, CTRLA),
377 channel_readl(atchan, CTRLB),
378 channel_readl(atchan, CFG),
379 channel_readl(atchan, DSCR));
380 }
381 #else
vdbg_dump_regs(struct at_dma_chan * atchan)382 static void vdbg_dump_regs(struct at_dma_chan *atchan) {}
383 #endif
384
atc_dump_lli(struct at_dma_chan * atchan,struct at_lli * lli)385 static void atc_dump_lli(struct at_dma_chan *atchan, struct at_lli *lli)
386 {
387 dev_crit(chan2dev(&atchan->chan_common),
388 "desc: s%pad d%pad ctrl0x%x:0x%x l%pad\n",
389 &lli->saddr, &lli->daddr,
390 lli->ctrla, lli->ctrlb, &lli->dscr);
391 }
392
393
atc_setup_irq(struct at_dma * atdma,int chan_id,int on)394 static void atc_setup_irq(struct at_dma *atdma, int chan_id, int on)
395 {
396 u32 ebci;
397
398 /* enable interrupts on buffer transfer completion & error */
399 ebci = AT_DMA_BTC(chan_id)
400 | AT_DMA_ERR(chan_id);
401 if (on)
402 dma_writel(atdma, EBCIER, ebci);
403 else
404 dma_writel(atdma, EBCIDR, ebci);
405 }
406
atc_enable_chan_irq(struct at_dma * atdma,int chan_id)407 static void atc_enable_chan_irq(struct at_dma *atdma, int chan_id)
408 {
409 atc_setup_irq(atdma, chan_id, 1);
410 }
411
atc_disable_chan_irq(struct at_dma * atdma,int chan_id)412 static void atc_disable_chan_irq(struct at_dma *atdma, int chan_id)
413 {
414 atc_setup_irq(atdma, chan_id, 0);
415 }
416
417
418 /**
419 * atc_chan_is_enabled - test if given channel is enabled
420 * @atchan: channel we want to test status
421 */
atc_chan_is_enabled(struct at_dma_chan * atchan)422 static inline int atc_chan_is_enabled(struct at_dma_chan *atchan)
423 {
424 struct at_dma *atdma = to_at_dma(atchan->chan_common.device);
425
426 return !!(dma_readl(atdma, CHSR) & atchan->mask);
427 }
428
429 /**
430 * atc_chan_is_paused - test channel pause/resume status
431 * @atchan: channel we want to test status
432 */
atc_chan_is_paused(struct at_dma_chan * atchan)433 static inline int atc_chan_is_paused(struct at_dma_chan *atchan)
434 {
435 return test_bit(ATC_IS_PAUSED, &atchan->status);
436 }
437
438 /**
439 * atc_chan_is_cyclic - test if given channel has cyclic property set
440 * @atchan: channel we want to test status
441 */
atc_chan_is_cyclic(struct at_dma_chan * atchan)442 static inline int atc_chan_is_cyclic(struct at_dma_chan *atchan)
443 {
444 return test_bit(ATC_IS_CYCLIC, &atchan->status);
445 }
446
447 /**
448 * set_desc_eol - set end-of-link to descriptor so it will end transfer
449 * @desc: descriptor, signle or at the end of a chain, to end chain on
450 */
set_desc_eol(struct at_desc * desc)451 static void set_desc_eol(struct at_desc *desc)
452 {
453 u32 ctrlb = desc->lli.ctrlb;
454
455 ctrlb &= ~ATC_IEN;
456 ctrlb |= ATC_SRC_DSCR_DIS | ATC_DST_DSCR_DIS;
457
458 desc->lli.ctrlb = ctrlb;
459 desc->lli.dscr = 0;
460 }
461
462 #endif /* AT_HDMAC_REGS_H */
463
