1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2019 HiSilicon Limited. */
3
4 #include <linux/acpi.h>
5 #include <linux/bitops.h>
6 #include <linux/debugfs.h>
7 #include <linux/init.h>
8 #include <linux/io.h>
9 #include <linux/iommu.h>
10 #include <linux/kernel.h>
11 #include <linux/module.h>
12 #include <linux/pci.h>
13 #include <linux/pm_runtime.h>
14 #include <linux/seq_file.h>
15 #include <linux/topology.h>
16 #include <linux/uacce.h>
17
18 #include "sec.h"
19
20 #define SEC_VF_NUM 63
21 #define SEC_QUEUE_NUM_V1 4096
22 #define PCI_DEVICE_ID_HUAWEI_SEC_PF 0xa255
23
24 #define SEC_BD_ERR_CHK_EN0 0xEFFFFFFF
25 #define SEC_BD_ERR_CHK_EN1 0x7ffff7fd
26 #define SEC_BD_ERR_CHK_EN3 0xffffbfff
27
28 #define SEC_SQE_SIZE 128
29 #define SEC_PF_DEF_Q_NUM 256
30 #define SEC_PF_DEF_Q_BASE 0
31 #define SEC_CTX_Q_NUM_DEF 2
32 #define SEC_CTX_Q_NUM_MAX 32
33
34 #define SEC_CTRL_CNT_CLR_CE 0x301120
35 #define SEC_CTRL_CNT_CLR_CE_BIT BIT(0)
36 #define SEC_CORE_INT_SOURCE 0x301010
37 #define SEC_CORE_INT_MASK 0x301000
38 #define SEC_CORE_INT_STATUS 0x301008
39 #define SEC_CORE_SRAM_ECC_ERR_INFO 0x301C14
40 #define SEC_ECC_NUM 16
41 #define SEC_ECC_MASH 0xFF
42 #define SEC_CORE_INT_DISABLE 0x0
43
44 #define SEC_RAS_CE_REG 0x301050
45 #define SEC_RAS_FE_REG 0x301054
46 #define SEC_RAS_NFE_REG 0x301058
47 #define SEC_RAS_FE_ENB_MSK 0x0
48 #define SEC_OOO_SHUTDOWN_SEL 0x301014
49 #define SEC_RAS_DISABLE 0x0
50 #define SEC_MEM_START_INIT_REG 0x301100
51 #define SEC_MEM_INIT_DONE_REG 0x301104
52
53 /* clock gating */
54 #define SEC_CONTROL_REG 0x301200
55 #define SEC_DYNAMIC_GATE_REG 0x30121c
56 #define SEC_CORE_AUTO_GATE 0x30212c
57 #define SEC_DYNAMIC_GATE_EN 0x7fff
58 #define SEC_CORE_AUTO_GATE_EN GENMASK(3, 0)
59 #define SEC_CLK_GATE_ENABLE BIT(3)
60 #define SEC_CLK_GATE_DISABLE (~BIT(3))
61
62 #define SEC_TRNG_EN_SHIFT 8
63 #define SEC_AXI_SHUTDOWN_ENABLE BIT(12)
64 #define SEC_AXI_SHUTDOWN_DISABLE 0xFFFFEFFF
65
66 #define SEC_INTERFACE_USER_CTRL0_REG 0x301220
67 #define SEC_INTERFACE_USER_CTRL1_REG 0x301224
68 #define SEC_SAA_EN_REG 0x301270
69 #define SEC_BD_ERR_CHK_EN_REG0 0x301380
70 #define SEC_BD_ERR_CHK_EN_REG1 0x301384
71 #define SEC_BD_ERR_CHK_EN_REG3 0x30138c
72
73 #define SEC_USER0_SMMU_NORMAL (BIT(23) | BIT(15))
74 #define SEC_USER1_SMMU_NORMAL (BIT(31) | BIT(23) | BIT(15) | BIT(7))
75 #define SEC_USER1_ENABLE_CONTEXT_SSV BIT(24)
76 #define SEC_USER1_ENABLE_DATA_SSV BIT(16)
77 #define SEC_USER1_WB_CONTEXT_SSV BIT(8)
78 #define SEC_USER1_WB_DATA_SSV BIT(0)
79 #define SEC_USER1_SVA_SET (SEC_USER1_ENABLE_CONTEXT_SSV | \
80 SEC_USER1_ENABLE_DATA_SSV | \
81 SEC_USER1_WB_CONTEXT_SSV | \
82 SEC_USER1_WB_DATA_SSV)
83 #define SEC_USER1_SMMU_SVA (SEC_USER1_SMMU_NORMAL | SEC_USER1_SVA_SET)
84 #define SEC_USER1_SMMU_MASK (~SEC_USER1_SVA_SET)
85 #define SEC_INTERFACE_USER_CTRL0_REG_V3 0x302220
86 #define SEC_INTERFACE_USER_CTRL1_REG_V3 0x302224
87 #define SEC_USER1_SMMU_NORMAL_V3 (BIT(23) | BIT(17) | BIT(11) | BIT(5))
88 #define SEC_USER1_SMMU_MASK_V3 0xFF79E79E
89 #define SEC_CORE_INT_STATUS_M_ECC BIT(2)
90
91 #define SEC_PREFETCH_CFG 0x301130
92 #define SEC_SVA_TRANS 0x301EC4
93 #define SEC_PREFETCH_ENABLE (~(BIT(0) | BIT(1) | BIT(11)))
94 #define SEC_PREFETCH_DISABLE BIT(1)
95 #define SEC_SVA_DISABLE_READY (BIT(7) | BIT(11))
96
97 #define SEC_DELAY_10_US 10
98 #define SEC_POLL_TIMEOUT_US 1000
99 #define SEC_DBGFS_VAL_MAX_LEN 20
100 #define SEC_SINGLE_PORT_MAX_TRANS 0x2060
101
102 #define SEC_SQE_MASK_OFFSET 64
103 #define SEC_SQE_MASK_LEN 48
104 #define SEC_SHAPER_TYPE_RATE 400
105
106 #define SEC_DFX_BASE 0x301000
107 #define SEC_DFX_CORE 0x302100
108 #define SEC_DFX_COMMON1 0x301600
109 #define SEC_DFX_COMMON2 0x301C00
110 #define SEC_DFX_BASE_LEN 0x9D
111 #define SEC_DFX_CORE_LEN 0x32B
112 #define SEC_DFX_COMMON1_LEN 0x45
113 #define SEC_DFX_COMMON2_LEN 0xBA
114
115 #define SEC_ALG_BITMAP_SHIFT 32
116
117 #define SEC_CIPHER_BITMAP (GENMASK_ULL(5, 0) | GENMASK_ULL(16, 12) | \
118 GENMASK(24, 21))
119 #define SEC_DIGEST_BITMAP (GENMASK_ULL(11, 8) | GENMASK_ULL(20, 19) | \
120 GENMASK_ULL(42, 25))
121 #define SEC_AEAD_BITMAP (GENMASK_ULL(7, 6) | GENMASK_ULL(18, 17) | \
122 GENMASK_ULL(45, 43))
123 #define SEC_DEV_ALG_MAX_LEN 256
124
125 struct sec_hw_error {
126 u32 int_msk;
127 const char *msg;
128 };
129
130 struct sec_dfx_item {
131 const char *name;
132 u32 offset;
133 };
134
135 struct sec_dev_alg {
136 u64 alg_msk;
137 const char *algs;
138 };
139
140 static const char sec_name[] = "hisi_sec2";
141 static struct dentry *sec_debugfs_root;
142
143 static struct hisi_qm_list sec_devices = {
144 .register_to_crypto = sec_register_to_crypto,
145 .unregister_from_crypto = sec_unregister_from_crypto,
146 };
147
148 static const struct hisi_qm_cap_info sec_basic_info[] = {
149 {SEC_QM_NFE_MASK_CAP, 0x3124, 0, GENMASK(31, 0), 0x0, 0x1C77, 0x7C77},
150 {SEC_QM_RESET_MASK_CAP, 0x3128, 0, GENMASK(31, 0), 0x0, 0xC77, 0x6C77},
151 {SEC_QM_OOO_SHUTDOWN_MASK_CAP, 0x3128, 0, GENMASK(31, 0), 0x0, 0x4, 0x6C77},
152 {SEC_QM_CE_MASK_CAP, 0x312C, 0, GENMASK(31, 0), 0x0, 0x8, 0x8},
153 {SEC_NFE_MASK_CAP, 0x3130, 0, GENMASK(31, 0), 0x0, 0x177, 0x60177},
154 {SEC_RESET_MASK_CAP, 0x3134, 0, GENMASK(31, 0), 0x0, 0x177, 0x177},
155 {SEC_OOO_SHUTDOWN_MASK_CAP, 0x3134, 0, GENMASK(31, 0), 0x0, 0x4, 0x177},
156 {SEC_CE_MASK_CAP, 0x3138, 0, GENMASK(31, 0), 0x0, 0x88, 0xC088},
157 {SEC_CLUSTER_NUM_CAP, 0x313c, 20, GENMASK(3, 0), 0x1, 0x1, 0x1},
158 {SEC_CORE_TYPE_NUM_CAP, 0x313c, 16, GENMASK(3, 0), 0x1, 0x1, 0x1},
159 {SEC_CORE_NUM_CAP, 0x313c, 8, GENMASK(7, 0), 0x4, 0x4, 0x4},
160 {SEC_CORES_PER_CLUSTER_NUM_CAP, 0x313c, 0, GENMASK(7, 0), 0x4, 0x4, 0x4},
161 {SEC_CORE_ENABLE_BITMAP, 0x3140, 32, GENMASK(31, 0), 0x17F, 0x17F, 0xF},
162 {SEC_DRV_ALG_BITMAP_LOW, 0x3144, 0, GENMASK(31, 0), 0x18050CB, 0x18050CB, 0x187F0FF},
163 {SEC_DRV_ALG_BITMAP_HIGH, 0x3148, 0, GENMASK(31, 0), 0x395C, 0x395C, 0x395C},
164 {SEC_DEV_ALG_BITMAP_LOW, 0x314c, 0, GENMASK(31, 0), 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF},
165 {SEC_DEV_ALG_BITMAP_HIGH, 0x3150, 0, GENMASK(31, 0), 0x3FFF, 0x3FFF, 0x3FFF},
166 {SEC_CORE1_ALG_BITMAP_LOW, 0x3154, 0, GENMASK(31, 0), 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF},
167 {SEC_CORE1_ALG_BITMAP_HIGH, 0x3158, 0, GENMASK(31, 0), 0x3FFF, 0x3FFF, 0x3FFF},
168 {SEC_CORE2_ALG_BITMAP_LOW, 0x315c, 0, GENMASK(31, 0), 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF},
169 {SEC_CORE2_ALG_BITMAP_HIGH, 0x3160, 0, GENMASK(31, 0), 0x3FFF, 0x3FFF, 0x3FFF},
170 {SEC_CORE3_ALG_BITMAP_LOW, 0x3164, 0, GENMASK(31, 0), 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF},
171 {SEC_CORE3_ALG_BITMAP_HIGH, 0x3168, 0, GENMASK(31, 0), 0x3FFF, 0x3FFF, 0x3FFF},
172 {SEC_CORE4_ALG_BITMAP_LOW, 0x316c, 0, GENMASK(31, 0), 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF},
173 {SEC_CORE4_ALG_BITMAP_HIGH, 0x3170, 0, GENMASK(31, 0), 0x3FFF, 0x3FFF, 0x3FFF},
174 };
175
176 static const struct sec_dev_alg sec_dev_algs[] = { {
177 .alg_msk = SEC_CIPHER_BITMAP,
178 .algs = "cipher\n",
179 }, {
180 .alg_msk = SEC_DIGEST_BITMAP,
181 .algs = "digest\n",
182 }, {
183 .alg_msk = SEC_AEAD_BITMAP,
184 .algs = "aead\n",
185 },
186 };
187
188 static const struct sec_hw_error sec_hw_errors[] = {
189 {
190 .int_msk = BIT(0),
191 .msg = "sec_axi_rresp_err_rint"
192 },
193 {
194 .int_msk = BIT(1),
195 .msg = "sec_axi_bresp_err_rint"
196 },
197 {
198 .int_msk = BIT(2),
199 .msg = "sec_ecc_2bit_err_rint"
200 },
201 {
202 .int_msk = BIT(3),
203 .msg = "sec_ecc_1bit_err_rint"
204 },
205 {
206 .int_msk = BIT(4),
207 .msg = "sec_req_trng_timeout_rint"
208 },
209 {
210 .int_msk = BIT(5),
211 .msg = "sec_fsm_hbeat_rint"
212 },
213 {
214 .int_msk = BIT(6),
215 .msg = "sec_channel_req_rng_timeout_rint"
216 },
217 {
218 .int_msk = BIT(7),
219 .msg = "sec_bd_err_rint"
220 },
221 {
222 .int_msk = BIT(8),
223 .msg = "sec_chain_buff_err_rint"
224 },
225 {
226 .int_msk = BIT(14),
227 .msg = "sec_no_secure_access"
228 },
229 {
230 .int_msk = BIT(15),
231 .msg = "sec_wrapping_key_auth_err"
232 },
233 {
234 .int_msk = BIT(16),
235 .msg = "sec_km_key_crc_fail"
236 },
237 {
238 .int_msk = BIT(17),
239 .msg = "sec_axi_poison_err"
240 },
241 {
242 .int_msk = BIT(18),
243 .msg = "sec_sva_err"
244 },
245 {}
246 };
247
248 static const char * const sec_dbg_file_name[] = {
249 [SEC_CLEAR_ENABLE] = "clear_enable",
250 };
251
252 static struct sec_dfx_item sec_dfx_labels[] = {
253 {"send_cnt", offsetof(struct sec_dfx, send_cnt)},
254 {"recv_cnt", offsetof(struct sec_dfx, recv_cnt)},
255 {"send_busy_cnt", offsetof(struct sec_dfx, send_busy_cnt)},
256 {"recv_busy_cnt", offsetof(struct sec_dfx, recv_busy_cnt)},
257 {"err_bd_cnt", offsetof(struct sec_dfx, err_bd_cnt)},
258 {"invalid_req_cnt", offsetof(struct sec_dfx, invalid_req_cnt)},
259 {"done_flag_cnt", offsetof(struct sec_dfx, done_flag_cnt)},
260 };
261
262 static const struct debugfs_reg32 sec_dfx_regs[] = {
263 {"SEC_PF_ABNORMAL_INT_SOURCE ", 0x301010},
264 {"SEC_SAA_EN ", 0x301270},
265 {"SEC_BD_LATENCY_MIN ", 0x301600},
266 {"SEC_BD_LATENCY_MAX ", 0x301608},
267 {"SEC_BD_LATENCY_AVG ", 0x30160C},
268 {"SEC_BD_NUM_IN_SAA0 ", 0x301670},
269 {"SEC_BD_NUM_IN_SAA1 ", 0x301674},
270 {"SEC_BD_NUM_IN_SEC ", 0x301680},
271 {"SEC_ECC_1BIT_CNT ", 0x301C00},
272 {"SEC_ECC_1BIT_INFO ", 0x301C04},
273 {"SEC_ECC_2BIT_CNT ", 0x301C10},
274 {"SEC_ECC_2BIT_INFO ", 0x301C14},
275 {"SEC_BD_SAA0 ", 0x301C20},
276 {"SEC_BD_SAA1 ", 0x301C24},
277 {"SEC_BD_SAA2 ", 0x301C28},
278 {"SEC_BD_SAA3 ", 0x301C2C},
279 {"SEC_BD_SAA4 ", 0x301C30},
280 {"SEC_BD_SAA5 ", 0x301C34},
281 {"SEC_BD_SAA6 ", 0x301C38},
282 {"SEC_BD_SAA7 ", 0x301C3C},
283 {"SEC_BD_SAA8 ", 0x301C40},
284 };
285
286 /* define the SEC's dfx regs region and region length */
287 static struct dfx_diff_registers sec_diff_regs[] = {
288 {
289 .reg_offset = SEC_DFX_BASE,
290 .reg_len = SEC_DFX_BASE_LEN,
291 }, {
292 .reg_offset = SEC_DFX_COMMON1,
293 .reg_len = SEC_DFX_COMMON1_LEN,
294 }, {
295 .reg_offset = SEC_DFX_COMMON2,
296 .reg_len = SEC_DFX_COMMON2_LEN,
297 }, {
298 .reg_offset = SEC_DFX_CORE,
299 .reg_len = SEC_DFX_CORE_LEN,
300 },
301 };
302
sec_diff_regs_show(struct seq_file * s,void * unused)303 static int sec_diff_regs_show(struct seq_file *s, void *unused)
304 {
305 struct hisi_qm *qm = s->private;
306
307 hisi_qm_acc_diff_regs_dump(qm, s, qm->debug.acc_diff_regs,
308 ARRAY_SIZE(sec_diff_regs));
309
310 return 0;
311 }
312 DEFINE_SHOW_ATTRIBUTE(sec_diff_regs);
313
sec_pf_q_num_set(const char * val,const struct kernel_param * kp)314 static int sec_pf_q_num_set(const char *val, const struct kernel_param *kp)
315 {
316 return q_num_set(val, kp, PCI_DEVICE_ID_HUAWEI_SEC_PF);
317 }
318
319 static const struct kernel_param_ops sec_pf_q_num_ops = {
320 .set = sec_pf_q_num_set,
321 .get = param_get_int,
322 };
323
324 static u32 pf_q_num = SEC_PF_DEF_Q_NUM;
325 module_param_cb(pf_q_num, &sec_pf_q_num_ops, &pf_q_num, 0444);
326 MODULE_PARM_DESC(pf_q_num, "Number of queues in PF(v1 2-4096, v2 2-1024)");
327
sec_ctx_q_num_set(const char * val,const struct kernel_param * kp)328 static int sec_ctx_q_num_set(const char *val, const struct kernel_param *kp)
329 {
330 u32 ctx_q_num;
331 int ret;
332
333 if (!val)
334 return -EINVAL;
335
336 ret = kstrtou32(val, 10, &ctx_q_num);
337 if (ret)
338 return -EINVAL;
339
340 if (!ctx_q_num || ctx_q_num > SEC_CTX_Q_NUM_MAX || ctx_q_num & 0x1) {
341 pr_err("ctx queue num[%u] is invalid!\n", ctx_q_num);
342 return -EINVAL;
343 }
344
345 return param_set_int(val, kp);
346 }
347
348 static const struct kernel_param_ops sec_ctx_q_num_ops = {
349 .set = sec_ctx_q_num_set,
350 .get = param_get_int,
351 };
352 static u32 ctx_q_num = SEC_CTX_Q_NUM_DEF;
353 module_param_cb(ctx_q_num, &sec_ctx_q_num_ops, &ctx_q_num, 0444);
354 MODULE_PARM_DESC(ctx_q_num, "Queue num in ctx (2 default, 2, 4, ..., 32)");
355
356 static const struct kernel_param_ops vfs_num_ops = {
357 .set = vfs_num_set,
358 .get = param_get_int,
359 };
360
361 static u32 vfs_num;
362 module_param_cb(vfs_num, &vfs_num_ops, &vfs_num, 0444);
363 MODULE_PARM_DESC(vfs_num, "Number of VFs to enable(1-63), 0(default)");
364
sec_destroy_qps(struct hisi_qp ** qps,int qp_num)365 void sec_destroy_qps(struct hisi_qp **qps, int qp_num)
366 {
367 hisi_qm_free_qps(qps, qp_num);
368 kfree(qps);
369 }
370
sec_create_qps(void)371 struct hisi_qp **sec_create_qps(void)
372 {
373 int node = cpu_to_node(smp_processor_id());
374 u32 ctx_num = ctx_q_num;
375 struct hisi_qp **qps;
376 int ret;
377
378 qps = kcalloc(ctx_num, sizeof(struct hisi_qp *), GFP_KERNEL);
379 if (!qps)
380 return NULL;
381
382 ret = hisi_qm_alloc_qps_node(&sec_devices, ctx_num, 0, node, qps);
383 if (!ret)
384 return qps;
385
386 kfree(qps);
387 return NULL;
388 }
389
sec_get_alg_bitmap(struct hisi_qm * qm,u32 high,u32 low)390 u64 sec_get_alg_bitmap(struct hisi_qm *qm, u32 high, u32 low)
391 {
392 u32 cap_val_h, cap_val_l;
393
394 cap_val_h = hisi_qm_get_hw_info(qm, sec_basic_info, high, qm->cap_ver);
395 cap_val_l = hisi_qm_get_hw_info(qm, sec_basic_info, low, qm->cap_ver);
396
397 return ((u64)cap_val_h << SEC_ALG_BITMAP_SHIFT) | (u64)cap_val_l;
398 }
399
400 static const struct kernel_param_ops sec_uacce_mode_ops = {
401 .set = uacce_mode_set,
402 .get = param_get_int,
403 };
404
405 /*
406 * uacce_mode = 0 means sec only register to crypto,
407 * uacce_mode = 1 means sec both register to crypto and uacce.
408 */
409 static u32 uacce_mode = UACCE_MODE_NOUACCE;
410 module_param_cb(uacce_mode, &sec_uacce_mode_ops, &uacce_mode, 0444);
411 MODULE_PARM_DESC(uacce_mode, UACCE_MODE_DESC);
412
413 static const struct pci_device_id sec_dev_ids[] = {
414 { PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, PCI_DEVICE_ID_HUAWEI_SEC_PF) },
415 { PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, PCI_DEVICE_ID_HUAWEI_SEC_VF) },
416 { 0, }
417 };
418 MODULE_DEVICE_TABLE(pci, sec_dev_ids);
419
sec_set_endian(struct hisi_qm * qm)420 static void sec_set_endian(struct hisi_qm *qm)
421 {
422 u32 reg;
423
424 reg = readl_relaxed(qm->io_base + SEC_CONTROL_REG);
425 reg &= ~(BIT(1) | BIT(0));
426 if (!IS_ENABLED(CONFIG_64BIT))
427 reg |= BIT(1);
428
429 if (!IS_ENABLED(CONFIG_CPU_LITTLE_ENDIAN))
430 reg |= BIT(0);
431
432 writel_relaxed(reg, qm->io_base + SEC_CONTROL_REG);
433 }
434
sec_engine_sva_config(struct hisi_qm * qm)435 static void sec_engine_sva_config(struct hisi_qm *qm)
436 {
437 u32 reg;
438
439 if (qm->ver > QM_HW_V2) {
440 reg = readl_relaxed(qm->io_base +
441 SEC_INTERFACE_USER_CTRL0_REG_V3);
442 reg |= SEC_USER0_SMMU_NORMAL;
443 writel_relaxed(reg, qm->io_base +
444 SEC_INTERFACE_USER_CTRL0_REG_V3);
445
446 reg = readl_relaxed(qm->io_base +
447 SEC_INTERFACE_USER_CTRL1_REG_V3);
448 reg &= SEC_USER1_SMMU_MASK_V3;
449 reg |= SEC_USER1_SMMU_NORMAL_V3;
450 writel_relaxed(reg, qm->io_base +
451 SEC_INTERFACE_USER_CTRL1_REG_V3);
452 } else {
453 reg = readl_relaxed(qm->io_base +
454 SEC_INTERFACE_USER_CTRL0_REG);
455 reg |= SEC_USER0_SMMU_NORMAL;
456 writel_relaxed(reg, qm->io_base +
457 SEC_INTERFACE_USER_CTRL0_REG);
458 reg = readl_relaxed(qm->io_base +
459 SEC_INTERFACE_USER_CTRL1_REG);
460 reg &= SEC_USER1_SMMU_MASK;
461 if (qm->use_sva)
462 reg |= SEC_USER1_SMMU_SVA;
463 else
464 reg |= SEC_USER1_SMMU_NORMAL;
465 writel_relaxed(reg, qm->io_base +
466 SEC_INTERFACE_USER_CTRL1_REG);
467 }
468 }
469
sec_open_sva_prefetch(struct hisi_qm * qm)470 static void sec_open_sva_prefetch(struct hisi_qm *qm)
471 {
472 u32 val;
473 int ret;
474
475 if (!test_bit(QM_SUPPORT_SVA_PREFETCH, &qm->caps))
476 return;
477
478 /* Enable prefetch */
479 val = readl_relaxed(qm->io_base + SEC_PREFETCH_CFG);
480 val &= SEC_PREFETCH_ENABLE;
481 writel(val, qm->io_base + SEC_PREFETCH_CFG);
482
483 ret = readl_relaxed_poll_timeout(qm->io_base + SEC_PREFETCH_CFG,
484 val, !(val & SEC_PREFETCH_DISABLE),
485 SEC_DELAY_10_US, SEC_POLL_TIMEOUT_US);
486 if (ret)
487 pci_err(qm->pdev, "failed to open sva prefetch\n");
488 }
489
sec_close_sva_prefetch(struct hisi_qm * qm)490 static void sec_close_sva_prefetch(struct hisi_qm *qm)
491 {
492 u32 val;
493 int ret;
494
495 if (!test_bit(QM_SUPPORT_SVA_PREFETCH, &qm->caps))
496 return;
497
498 val = readl_relaxed(qm->io_base + SEC_PREFETCH_CFG);
499 val |= SEC_PREFETCH_DISABLE;
500 writel(val, qm->io_base + SEC_PREFETCH_CFG);
501
502 ret = readl_relaxed_poll_timeout(qm->io_base + SEC_SVA_TRANS,
503 val, !(val & SEC_SVA_DISABLE_READY),
504 SEC_DELAY_10_US, SEC_POLL_TIMEOUT_US);
505 if (ret)
506 pci_err(qm->pdev, "failed to close sva prefetch\n");
507 }
508
sec_enable_clock_gate(struct hisi_qm * qm)509 static void sec_enable_clock_gate(struct hisi_qm *qm)
510 {
511 u32 val;
512
513 if (qm->ver < QM_HW_V3)
514 return;
515
516 val = readl_relaxed(qm->io_base + SEC_CONTROL_REG);
517 val |= SEC_CLK_GATE_ENABLE;
518 writel_relaxed(val, qm->io_base + SEC_CONTROL_REG);
519
520 val = readl(qm->io_base + SEC_DYNAMIC_GATE_REG);
521 val |= SEC_DYNAMIC_GATE_EN;
522 writel(val, qm->io_base + SEC_DYNAMIC_GATE_REG);
523
524 val = readl(qm->io_base + SEC_CORE_AUTO_GATE);
525 val |= SEC_CORE_AUTO_GATE_EN;
526 writel(val, qm->io_base + SEC_CORE_AUTO_GATE);
527 }
528
sec_disable_clock_gate(struct hisi_qm * qm)529 static void sec_disable_clock_gate(struct hisi_qm *qm)
530 {
531 u32 val;
532
533 /* Kunpeng920 needs to close clock gating */
534 val = readl_relaxed(qm->io_base + SEC_CONTROL_REG);
535 val &= SEC_CLK_GATE_DISABLE;
536 writel_relaxed(val, qm->io_base + SEC_CONTROL_REG);
537 }
538
sec_engine_init(struct hisi_qm * qm)539 static int sec_engine_init(struct hisi_qm *qm)
540 {
541 int ret;
542 u32 reg;
543
544 /* disable clock gate control before mem init */
545 sec_disable_clock_gate(qm);
546
547 writel_relaxed(0x1, qm->io_base + SEC_MEM_START_INIT_REG);
548
549 ret = readl_relaxed_poll_timeout(qm->io_base + SEC_MEM_INIT_DONE_REG,
550 reg, reg & 0x1, SEC_DELAY_10_US,
551 SEC_POLL_TIMEOUT_US);
552 if (ret) {
553 pci_err(qm->pdev, "fail to init sec mem\n");
554 return ret;
555 }
556
557 reg = readl_relaxed(qm->io_base + SEC_CONTROL_REG);
558 reg |= (0x1 << SEC_TRNG_EN_SHIFT);
559 writel_relaxed(reg, qm->io_base + SEC_CONTROL_REG);
560
561 sec_engine_sva_config(qm);
562
563 writel(SEC_SINGLE_PORT_MAX_TRANS,
564 qm->io_base + AM_CFG_SINGLE_PORT_MAX_TRANS);
565
566 reg = hisi_qm_get_hw_info(qm, sec_basic_info, SEC_CORE_ENABLE_BITMAP, qm->cap_ver);
567 writel(reg, qm->io_base + SEC_SAA_EN_REG);
568
569 if (qm->ver < QM_HW_V3) {
570 /* HW V2 enable sm4 extra mode, as ctr/ecb */
571 writel_relaxed(SEC_BD_ERR_CHK_EN0,
572 qm->io_base + SEC_BD_ERR_CHK_EN_REG0);
573
574 /* HW V2 enable sm4 xts mode multiple iv */
575 writel_relaxed(SEC_BD_ERR_CHK_EN1,
576 qm->io_base + SEC_BD_ERR_CHK_EN_REG1);
577 writel_relaxed(SEC_BD_ERR_CHK_EN3,
578 qm->io_base + SEC_BD_ERR_CHK_EN_REG3);
579 }
580
581 /* config endian */
582 sec_set_endian(qm);
583
584 sec_enable_clock_gate(qm);
585
586 return 0;
587 }
588
sec_set_user_domain_and_cache(struct hisi_qm * qm)589 static int sec_set_user_domain_and_cache(struct hisi_qm *qm)
590 {
591 /* qm user domain */
592 writel(AXUSER_BASE, qm->io_base + QM_ARUSER_M_CFG_1);
593 writel(ARUSER_M_CFG_ENABLE, qm->io_base + QM_ARUSER_M_CFG_ENABLE);
594 writel(AXUSER_BASE, qm->io_base + QM_AWUSER_M_CFG_1);
595 writel(AWUSER_M_CFG_ENABLE, qm->io_base + QM_AWUSER_M_CFG_ENABLE);
596 writel(WUSER_M_CFG_ENABLE, qm->io_base + QM_WUSER_M_CFG_ENABLE);
597
598 /* qm cache */
599 writel(AXI_M_CFG, qm->io_base + QM_AXI_M_CFG);
600 writel(AXI_M_CFG_ENABLE, qm->io_base + QM_AXI_M_CFG_ENABLE);
601
602 /* disable FLR triggered by BME(bus master enable) */
603 writel(PEH_AXUSER_CFG, qm->io_base + QM_PEH_AXUSER_CFG);
604 writel(PEH_AXUSER_CFG_ENABLE, qm->io_base + QM_PEH_AXUSER_CFG_ENABLE);
605
606 /* enable sqc,cqc writeback */
607 writel(SQC_CACHE_ENABLE | CQC_CACHE_ENABLE | SQC_CACHE_WB_ENABLE |
608 CQC_CACHE_WB_ENABLE | FIELD_PREP(SQC_CACHE_WB_THRD, 1) |
609 FIELD_PREP(CQC_CACHE_WB_THRD, 1), qm->io_base + QM_CACHE_CTL);
610
611 return sec_engine_init(qm);
612 }
613
614 /* sec_debug_regs_clear() - clear the sec debug regs */
sec_debug_regs_clear(struct hisi_qm * qm)615 static void sec_debug_regs_clear(struct hisi_qm *qm)
616 {
617 int i;
618
619 /* clear sec dfx regs */
620 writel(0x1, qm->io_base + SEC_CTRL_CNT_CLR_CE);
621 for (i = 0; i < ARRAY_SIZE(sec_dfx_regs); i++)
622 readl(qm->io_base + sec_dfx_regs[i].offset);
623
624 /* clear rdclr_en */
625 writel(0x0, qm->io_base + SEC_CTRL_CNT_CLR_CE);
626
627 hisi_qm_debug_regs_clear(qm);
628 }
629
sec_master_ooo_ctrl(struct hisi_qm * qm,bool enable)630 static void sec_master_ooo_ctrl(struct hisi_qm *qm, bool enable)
631 {
632 u32 val1, val2;
633
634 val1 = readl(qm->io_base + SEC_CONTROL_REG);
635 if (enable) {
636 val1 |= SEC_AXI_SHUTDOWN_ENABLE;
637 val2 = hisi_qm_get_hw_info(qm, sec_basic_info,
638 SEC_OOO_SHUTDOWN_MASK_CAP, qm->cap_ver);
639 } else {
640 val1 &= SEC_AXI_SHUTDOWN_DISABLE;
641 val2 = 0x0;
642 }
643
644 if (qm->ver > QM_HW_V2)
645 writel(val2, qm->io_base + SEC_OOO_SHUTDOWN_SEL);
646
647 writel(val1, qm->io_base + SEC_CONTROL_REG);
648 }
649
sec_hw_error_enable(struct hisi_qm * qm)650 static void sec_hw_error_enable(struct hisi_qm *qm)
651 {
652 u32 ce, nfe;
653
654 if (qm->ver == QM_HW_V1) {
655 writel(SEC_CORE_INT_DISABLE, qm->io_base + SEC_CORE_INT_MASK);
656 pci_info(qm->pdev, "V1 not support hw error handle\n");
657 return;
658 }
659
660 ce = hisi_qm_get_hw_info(qm, sec_basic_info, SEC_CE_MASK_CAP, qm->cap_ver);
661 nfe = hisi_qm_get_hw_info(qm, sec_basic_info, SEC_NFE_MASK_CAP, qm->cap_ver);
662
663 /* clear SEC hw error source if having */
664 writel(ce | nfe | SEC_RAS_FE_ENB_MSK, qm->io_base + SEC_CORE_INT_SOURCE);
665
666 /* enable RAS int */
667 writel(ce, qm->io_base + SEC_RAS_CE_REG);
668 writel(SEC_RAS_FE_ENB_MSK, qm->io_base + SEC_RAS_FE_REG);
669 writel(nfe, qm->io_base + SEC_RAS_NFE_REG);
670
671 /* enable SEC block master OOO when nfe occurs on Kunpeng930 */
672 sec_master_ooo_ctrl(qm, true);
673
674 /* enable SEC hw error interrupts */
675 writel(ce | nfe | SEC_RAS_FE_ENB_MSK, qm->io_base + SEC_CORE_INT_MASK);
676 }
677
sec_hw_error_disable(struct hisi_qm * qm)678 static void sec_hw_error_disable(struct hisi_qm *qm)
679 {
680 /* disable SEC hw error interrupts */
681 writel(SEC_CORE_INT_DISABLE, qm->io_base + SEC_CORE_INT_MASK);
682
683 /* disable SEC block master OOO when nfe occurs on Kunpeng930 */
684 sec_master_ooo_ctrl(qm, false);
685
686 /* disable RAS int */
687 writel(SEC_RAS_DISABLE, qm->io_base + SEC_RAS_CE_REG);
688 writel(SEC_RAS_DISABLE, qm->io_base + SEC_RAS_FE_REG);
689 writel(SEC_RAS_DISABLE, qm->io_base + SEC_RAS_NFE_REG);
690 }
691
sec_clear_enable_read(struct hisi_qm * qm)692 static u32 sec_clear_enable_read(struct hisi_qm *qm)
693 {
694 return readl(qm->io_base + SEC_CTRL_CNT_CLR_CE) &
695 SEC_CTRL_CNT_CLR_CE_BIT;
696 }
697
sec_clear_enable_write(struct hisi_qm * qm,u32 val)698 static int sec_clear_enable_write(struct hisi_qm *qm, u32 val)
699 {
700 u32 tmp;
701
702 if (val != 1 && val)
703 return -EINVAL;
704
705 tmp = (readl(qm->io_base + SEC_CTRL_CNT_CLR_CE) &
706 ~SEC_CTRL_CNT_CLR_CE_BIT) | val;
707 writel(tmp, qm->io_base + SEC_CTRL_CNT_CLR_CE);
708
709 return 0;
710 }
711
sec_debug_read(struct file * filp,char __user * buf,size_t count,loff_t * pos)712 static ssize_t sec_debug_read(struct file *filp, char __user *buf,
713 size_t count, loff_t *pos)
714 {
715 struct sec_debug_file *file = filp->private_data;
716 char tbuf[SEC_DBGFS_VAL_MAX_LEN];
717 struct hisi_qm *qm = file->qm;
718 u32 val;
719 int ret;
720
721 ret = hisi_qm_get_dfx_access(qm);
722 if (ret)
723 return ret;
724
725 spin_lock_irq(&file->lock);
726
727 switch (file->index) {
728 case SEC_CLEAR_ENABLE:
729 val = sec_clear_enable_read(qm);
730 break;
731 default:
732 goto err_input;
733 }
734
735 spin_unlock_irq(&file->lock);
736
737 hisi_qm_put_dfx_access(qm);
738 ret = snprintf(tbuf, SEC_DBGFS_VAL_MAX_LEN, "%u\n", val);
739 return simple_read_from_buffer(buf, count, pos, tbuf, ret);
740
741 err_input:
742 spin_unlock_irq(&file->lock);
743 hisi_qm_put_dfx_access(qm);
744 return -EINVAL;
745 }
746
sec_debug_write(struct file * filp,const char __user * buf,size_t count,loff_t * pos)747 static ssize_t sec_debug_write(struct file *filp, const char __user *buf,
748 size_t count, loff_t *pos)
749 {
750 struct sec_debug_file *file = filp->private_data;
751 char tbuf[SEC_DBGFS_VAL_MAX_LEN];
752 struct hisi_qm *qm = file->qm;
753 unsigned long val;
754 int len, ret;
755
756 if (*pos != 0)
757 return 0;
758
759 if (count >= SEC_DBGFS_VAL_MAX_LEN)
760 return -ENOSPC;
761
762 len = simple_write_to_buffer(tbuf, SEC_DBGFS_VAL_MAX_LEN - 1,
763 pos, buf, count);
764 if (len < 0)
765 return len;
766
767 tbuf[len] = '\0';
768 if (kstrtoul(tbuf, 0, &val))
769 return -EFAULT;
770
771 ret = hisi_qm_get_dfx_access(qm);
772 if (ret)
773 return ret;
774
775 spin_lock_irq(&file->lock);
776
777 switch (file->index) {
778 case SEC_CLEAR_ENABLE:
779 ret = sec_clear_enable_write(qm, val);
780 if (ret)
781 goto err_input;
782 break;
783 default:
784 ret = -EINVAL;
785 goto err_input;
786 }
787
788 ret = count;
789
790 err_input:
791 spin_unlock_irq(&file->lock);
792 hisi_qm_put_dfx_access(qm);
793 return ret;
794 }
795
796 static const struct file_operations sec_dbg_fops = {
797 .owner = THIS_MODULE,
798 .open = simple_open,
799 .read = sec_debug_read,
800 .write = sec_debug_write,
801 };
802
sec_debugfs_atomic64_get(void * data,u64 * val)803 static int sec_debugfs_atomic64_get(void *data, u64 *val)
804 {
805 *val = atomic64_read((atomic64_t *)data);
806
807 return 0;
808 }
809
sec_debugfs_atomic64_set(void * data,u64 val)810 static int sec_debugfs_atomic64_set(void *data, u64 val)
811 {
812 if (val)
813 return -EINVAL;
814
815 atomic64_set((atomic64_t *)data, 0);
816
817 return 0;
818 }
819
820 DEFINE_DEBUGFS_ATTRIBUTE(sec_atomic64_ops, sec_debugfs_atomic64_get,
821 sec_debugfs_atomic64_set, "%lld\n");
822
sec_regs_show(struct seq_file * s,void * unused)823 static int sec_regs_show(struct seq_file *s, void *unused)
824 {
825 hisi_qm_regs_dump(s, s->private);
826
827 return 0;
828 }
829
830 DEFINE_SHOW_ATTRIBUTE(sec_regs);
831
sec_core_debug_init(struct hisi_qm * qm)832 static int sec_core_debug_init(struct hisi_qm *qm)
833 {
834 struct dfx_diff_registers *sec_regs = qm->debug.acc_diff_regs;
835 struct sec_dev *sec = container_of(qm, struct sec_dev, qm);
836 struct device *dev = &qm->pdev->dev;
837 struct sec_dfx *dfx = &sec->debug.dfx;
838 struct debugfs_regset32 *regset;
839 struct dentry *tmp_d;
840 int i;
841
842 tmp_d = debugfs_create_dir("sec_dfx", qm->debug.debug_root);
843
844 regset = devm_kzalloc(dev, sizeof(*regset), GFP_KERNEL);
845 if (!regset)
846 return -ENOMEM;
847
848 regset->regs = sec_dfx_regs;
849 regset->nregs = ARRAY_SIZE(sec_dfx_regs);
850 regset->base = qm->io_base;
851 regset->dev = dev;
852
853 if (qm->pdev->device == PCI_DEVICE_ID_HUAWEI_SEC_PF)
854 debugfs_create_file("regs", 0444, tmp_d, regset, &sec_regs_fops);
855 if (qm->fun_type == QM_HW_PF && sec_regs)
856 debugfs_create_file("diff_regs", 0444, tmp_d,
857 qm, &sec_diff_regs_fops);
858
859 for (i = 0; i < ARRAY_SIZE(sec_dfx_labels); i++) {
860 atomic64_t *data = (atomic64_t *)((uintptr_t)dfx +
861 sec_dfx_labels[i].offset);
862 debugfs_create_file(sec_dfx_labels[i].name, 0644,
863 tmp_d, data, &sec_atomic64_ops);
864 }
865
866 return 0;
867 }
868
sec_debug_init(struct hisi_qm * qm)869 static int sec_debug_init(struct hisi_qm *qm)
870 {
871 struct sec_dev *sec = container_of(qm, struct sec_dev, qm);
872 int i;
873
874 if (qm->pdev->device == PCI_DEVICE_ID_HUAWEI_SEC_PF) {
875 for (i = SEC_CLEAR_ENABLE; i < SEC_DEBUG_FILE_NUM; i++) {
876 spin_lock_init(&sec->debug.files[i].lock);
877 sec->debug.files[i].index = i;
878 sec->debug.files[i].qm = qm;
879
880 debugfs_create_file(sec_dbg_file_name[i], 0600,
881 qm->debug.debug_root,
882 sec->debug.files + i,
883 &sec_dbg_fops);
884 }
885 }
886
887 return sec_core_debug_init(qm);
888 }
889
sec_debugfs_init(struct hisi_qm * qm)890 static int sec_debugfs_init(struct hisi_qm *qm)
891 {
892 struct device *dev = &qm->pdev->dev;
893 int ret;
894
895 qm->debug.debug_root = debugfs_create_dir(dev_name(dev),
896 sec_debugfs_root);
897 qm->debug.sqe_mask_offset = SEC_SQE_MASK_OFFSET;
898 qm->debug.sqe_mask_len = SEC_SQE_MASK_LEN;
899
900 ret = hisi_qm_regs_debugfs_init(qm, sec_diff_regs, ARRAY_SIZE(sec_diff_regs));
901 if (ret) {
902 dev_warn(dev, "Failed to init SEC diff regs!\n");
903 goto debugfs_remove;
904 }
905
906 hisi_qm_debug_init(qm);
907
908 ret = sec_debug_init(qm);
909 if (ret)
910 goto failed_to_create;
911
912 return 0;
913
914 failed_to_create:
915 hisi_qm_regs_debugfs_uninit(qm, ARRAY_SIZE(sec_diff_regs));
916 debugfs_remove:
917 debugfs_remove_recursive(sec_debugfs_root);
918 return ret;
919 }
920
sec_debugfs_exit(struct hisi_qm * qm)921 static void sec_debugfs_exit(struct hisi_qm *qm)
922 {
923 hisi_qm_regs_debugfs_uninit(qm, ARRAY_SIZE(sec_diff_regs));
924
925 debugfs_remove_recursive(qm->debug.debug_root);
926 }
927
sec_show_last_regs_init(struct hisi_qm * qm)928 static int sec_show_last_regs_init(struct hisi_qm *qm)
929 {
930 struct qm_debug *debug = &qm->debug;
931 int i;
932
933 debug->last_words = kcalloc(ARRAY_SIZE(sec_dfx_regs),
934 sizeof(unsigned int), GFP_KERNEL);
935 if (!debug->last_words)
936 return -ENOMEM;
937
938 for (i = 0; i < ARRAY_SIZE(sec_dfx_regs); i++)
939 debug->last_words[i] = readl_relaxed(qm->io_base +
940 sec_dfx_regs[i].offset);
941
942 return 0;
943 }
944
sec_show_last_regs_uninit(struct hisi_qm * qm)945 static void sec_show_last_regs_uninit(struct hisi_qm *qm)
946 {
947 struct qm_debug *debug = &qm->debug;
948
949 if (qm->fun_type == QM_HW_VF || !debug->last_words)
950 return;
951
952 kfree(debug->last_words);
953 debug->last_words = NULL;
954 }
955
sec_show_last_dfx_regs(struct hisi_qm * qm)956 static void sec_show_last_dfx_regs(struct hisi_qm *qm)
957 {
958 struct qm_debug *debug = &qm->debug;
959 struct pci_dev *pdev = qm->pdev;
960 u32 val;
961 int i;
962
963 if (qm->fun_type == QM_HW_VF || !debug->last_words)
964 return;
965
966 /* dumps last word of the debugging registers during controller reset */
967 for (i = 0; i < ARRAY_SIZE(sec_dfx_regs); i++) {
968 val = readl_relaxed(qm->io_base + sec_dfx_regs[i].offset);
969 if (val != debug->last_words[i])
970 pci_info(pdev, "%s \t= 0x%08x => 0x%08x\n",
971 sec_dfx_regs[i].name, debug->last_words[i], val);
972 }
973 }
974
sec_log_hw_error(struct hisi_qm * qm,u32 err_sts)975 static void sec_log_hw_error(struct hisi_qm *qm, u32 err_sts)
976 {
977 const struct sec_hw_error *errs = sec_hw_errors;
978 struct device *dev = &qm->pdev->dev;
979 u32 err_val;
980
981 while (errs->msg) {
982 if (errs->int_msk & err_sts) {
983 dev_err(dev, "%s [error status=0x%x] found\n",
984 errs->msg, errs->int_msk);
985
986 if (SEC_CORE_INT_STATUS_M_ECC & errs->int_msk) {
987 err_val = readl(qm->io_base +
988 SEC_CORE_SRAM_ECC_ERR_INFO);
989 dev_err(dev, "multi ecc sram num=0x%x\n",
990 ((err_val) >> SEC_ECC_NUM) &
991 SEC_ECC_MASH);
992 }
993 }
994 errs++;
995 }
996 }
997
sec_get_hw_err_status(struct hisi_qm * qm)998 static u32 sec_get_hw_err_status(struct hisi_qm *qm)
999 {
1000 return readl(qm->io_base + SEC_CORE_INT_STATUS);
1001 }
1002
sec_clear_hw_err_status(struct hisi_qm * qm,u32 err_sts)1003 static void sec_clear_hw_err_status(struct hisi_qm *qm, u32 err_sts)
1004 {
1005 u32 nfe;
1006
1007 writel(err_sts, qm->io_base + SEC_CORE_INT_SOURCE);
1008 nfe = hisi_qm_get_hw_info(qm, sec_basic_info, SEC_NFE_MASK_CAP, qm->cap_ver);
1009 writel(nfe, qm->io_base + SEC_RAS_NFE_REG);
1010 }
1011
sec_open_axi_master_ooo(struct hisi_qm * qm)1012 static void sec_open_axi_master_ooo(struct hisi_qm *qm)
1013 {
1014 u32 val;
1015
1016 val = readl(qm->io_base + SEC_CONTROL_REG);
1017 writel(val & SEC_AXI_SHUTDOWN_DISABLE, qm->io_base + SEC_CONTROL_REG);
1018 writel(val | SEC_AXI_SHUTDOWN_ENABLE, qm->io_base + SEC_CONTROL_REG);
1019 }
1020
sec_err_info_init(struct hisi_qm * qm)1021 static void sec_err_info_init(struct hisi_qm *qm)
1022 {
1023 struct hisi_qm_err_info *err_info = &qm->err_info;
1024
1025 err_info->fe = SEC_RAS_FE_ENB_MSK;
1026 err_info->ce = hisi_qm_get_hw_info(qm, sec_basic_info, SEC_QM_CE_MASK_CAP, qm->cap_ver);
1027 err_info->nfe = hisi_qm_get_hw_info(qm, sec_basic_info, SEC_QM_NFE_MASK_CAP, qm->cap_ver);
1028 err_info->ecc_2bits_mask = SEC_CORE_INT_STATUS_M_ECC;
1029 err_info->qm_shutdown_mask = hisi_qm_get_hw_info(qm, sec_basic_info,
1030 SEC_QM_OOO_SHUTDOWN_MASK_CAP, qm->cap_ver);
1031 err_info->dev_shutdown_mask = hisi_qm_get_hw_info(qm, sec_basic_info,
1032 SEC_OOO_SHUTDOWN_MASK_CAP, qm->cap_ver);
1033 err_info->qm_reset_mask = hisi_qm_get_hw_info(qm, sec_basic_info,
1034 SEC_QM_RESET_MASK_CAP, qm->cap_ver);
1035 err_info->dev_reset_mask = hisi_qm_get_hw_info(qm, sec_basic_info,
1036 SEC_RESET_MASK_CAP, qm->cap_ver);
1037 err_info->msi_wr_port = BIT(0);
1038 err_info->acpi_rst = "SRST";
1039 }
1040
1041 static const struct hisi_qm_err_ini sec_err_ini = {
1042 .hw_init = sec_set_user_domain_and_cache,
1043 .hw_err_enable = sec_hw_error_enable,
1044 .hw_err_disable = sec_hw_error_disable,
1045 .get_dev_hw_err_status = sec_get_hw_err_status,
1046 .clear_dev_hw_err_status = sec_clear_hw_err_status,
1047 .log_dev_hw_err = sec_log_hw_error,
1048 .open_axi_master_ooo = sec_open_axi_master_ooo,
1049 .open_sva_prefetch = sec_open_sva_prefetch,
1050 .close_sva_prefetch = sec_close_sva_prefetch,
1051 .show_last_dfx_regs = sec_show_last_dfx_regs,
1052 .err_info_init = sec_err_info_init,
1053 };
1054
sec_pf_probe_init(struct sec_dev * sec)1055 static int sec_pf_probe_init(struct sec_dev *sec)
1056 {
1057 struct hisi_qm *qm = &sec->qm;
1058 int ret;
1059
1060 qm->err_ini = &sec_err_ini;
1061 qm->err_ini->err_info_init(qm);
1062
1063 ret = sec_set_user_domain_and_cache(qm);
1064 if (ret)
1065 return ret;
1066
1067 sec_open_sva_prefetch(qm);
1068 hisi_qm_dev_err_init(qm);
1069 sec_debug_regs_clear(qm);
1070 ret = sec_show_last_regs_init(qm);
1071 if (ret)
1072 pci_err(qm->pdev, "Failed to init last word regs!\n");
1073
1074 return ret;
1075 }
1076
sec_set_qm_algs(struct hisi_qm * qm)1077 static int sec_set_qm_algs(struct hisi_qm *qm)
1078 {
1079 struct device *dev = &qm->pdev->dev;
1080 char *algs, *ptr;
1081 u64 alg_mask;
1082 int i;
1083
1084 if (!qm->use_sva)
1085 return 0;
1086
1087 algs = devm_kzalloc(dev, SEC_DEV_ALG_MAX_LEN * sizeof(char), GFP_KERNEL);
1088 if (!algs)
1089 return -ENOMEM;
1090
1091 alg_mask = sec_get_alg_bitmap(qm, SEC_DEV_ALG_BITMAP_HIGH, SEC_DEV_ALG_BITMAP_LOW);
1092
1093 for (i = 0; i < ARRAY_SIZE(sec_dev_algs); i++)
1094 if (alg_mask & sec_dev_algs[i].alg_msk)
1095 strcat(algs, sec_dev_algs[i].algs);
1096
1097 ptr = strrchr(algs, '\n');
1098 if (ptr)
1099 *ptr = '\0';
1100
1101 qm->uacce->algs = algs;
1102
1103 return 0;
1104 }
1105
sec_qm_init(struct hisi_qm * qm,struct pci_dev * pdev)1106 static int sec_qm_init(struct hisi_qm *qm, struct pci_dev *pdev)
1107 {
1108 int ret;
1109
1110 qm->pdev = pdev;
1111 qm->ver = pdev->revision;
1112 qm->mode = uacce_mode;
1113 qm->sqe_size = SEC_SQE_SIZE;
1114 qm->dev_name = sec_name;
1115
1116 qm->fun_type = (pdev->device == PCI_DEVICE_ID_HUAWEI_SEC_PF) ?
1117 QM_HW_PF : QM_HW_VF;
1118 if (qm->fun_type == QM_HW_PF) {
1119 qm->qp_base = SEC_PF_DEF_Q_BASE;
1120 qm->qp_num = pf_q_num;
1121 qm->debug.curr_qm_qp_num = pf_q_num;
1122 qm->qm_list = &sec_devices;
1123 } else if (qm->fun_type == QM_HW_VF && qm->ver == QM_HW_V1) {
1124 /*
1125 * have no way to get qm configure in VM in v1 hardware,
1126 * so currently force PF to uses SEC_PF_DEF_Q_NUM, and force
1127 * to trigger only one VF in v1 hardware.
1128 * v2 hardware has no such problem.
1129 */
1130 qm->qp_base = SEC_PF_DEF_Q_NUM;
1131 qm->qp_num = SEC_QUEUE_NUM_V1 - SEC_PF_DEF_Q_NUM;
1132 }
1133
1134 ret = hisi_qm_init(qm);
1135 if (ret) {
1136 pci_err(qm->pdev, "Failed to init sec qm configures!\n");
1137 return ret;
1138 }
1139
1140 ret = sec_set_qm_algs(qm);
1141 if (ret) {
1142 pci_err(qm->pdev, "Failed to set sec algs!\n");
1143 hisi_qm_uninit(qm);
1144 }
1145
1146 return ret;
1147 }
1148
sec_qm_uninit(struct hisi_qm * qm)1149 static void sec_qm_uninit(struct hisi_qm *qm)
1150 {
1151 hisi_qm_uninit(qm);
1152 }
1153
sec_probe_init(struct sec_dev * sec)1154 static int sec_probe_init(struct sec_dev *sec)
1155 {
1156 u32 type_rate = SEC_SHAPER_TYPE_RATE;
1157 struct hisi_qm *qm = &sec->qm;
1158 int ret;
1159
1160 if (qm->fun_type == QM_HW_PF) {
1161 ret = sec_pf_probe_init(sec);
1162 if (ret)
1163 return ret;
1164 /* enable shaper type 0 */
1165 if (qm->ver >= QM_HW_V3) {
1166 type_rate |= QM_SHAPER_ENABLE;
1167 qm->type_rate = type_rate;
1168 }
1169 }
1170
1171 return 0;
1172 }
1173
sec_probe_uninit(struct hisi_qm * qm)1174 static void sec_probe_uninit(struct hisi_qm *qm)
1175 {
1176 hisi_qm_dev_err_uninit(qm);
1177 }
1178
sec_iommu_used_check(struct sec_dev * sec)1179 static void sec_iommu_used_check(struct sec_dev *sec)
1180 {
1181 struct iommu_domain *domain;
1182 struct device *dev = &sec->qm.pdev->dev;
1183
1184 domain = iommu_get_domain_for_dev(dev);
1185
1186 /* Check if iommu is used */
1187 sec->iommu_used = false;
1188 if (domain) {
1189 if (domain->type & __IOMMU_DOMAIN_PAGING)
1190 sec->iommu_used = true;
1191 dev_info(dev, "SMMU Opened, the iommu type = %u\n",
1192 domain->type);
1193 }
1194 }
1195
sec_probe(struct pci_dev * pdev,const struct pci_device_id * id)1196 static int sec_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1197 {
1198 struct sec_dev *sec;
1199 struct hisi_qm *qm;
1200 int ret;
1201
1202 sec = devm_kzalloc(&pdev->dev, sizeof(*sec), GFP_KERNEL);
1203 if (!sec)
1204 return -ENOMEM;
1205
1206 qm = &sec->qm;
1207 ret = sec_qm_init(qm, pdev);
1208 if (ret) {
1209 pci_err(pdev, "Failed to init SEC QM (%d)!\n", ret);
1210 return ret;
1211 }
1212
1213 sec->ctx_q_num = ctx_q_num;
1214 sec_iommu_used_check(sec);
1215
1216 ret = sec_probe_init(sec);
1217 if (ret) {
1218 pci_err(pdev, "Failed to probe!\n");
1219 goto err_qm_uninit;
1220 }
1221
1222 ret = hisi_qm_start(qm);
1223 if (ret) {
1224 pci_err(pdev, "Failed to start sec qm!\n");
1225 goto err_probe_uninit;
1226 }
1227
1228 ret = sec_debugfs_init(qm);
1229 if (ret)
1230 pci_warn(pdev, "Failed to init debugfs!\n");
1231
1232 if (qm->qp_num >= ctx_q_num) {
1233 ret = hisi_qm_alg_register(qm, &sec_devices);
1234 if (ret < 0) {
1235 pr_err("Failed to register driver to crypto.\n");
1236 goto err_qm_stop;
1237 }
1238 } else {
1239 pci_warn(qm->pdev,
1240 "Failed to use kernel mode, qp not enough!\n");
1241 }
1242
1243 if (qm->uacce) {
1244 ret = uacce_register(qm->uacce);
1245 if (ret) {
1246 pci_err(pdev, "failed to register uacce (%d)!\n", ret);
1247 goto err_alg_unregister;
1248 }
1249 }
1250
1251 if (qm->fun_type == QM_HW_PF && vfs_num) {
1252 ret = hisi_qm_sriov_enable(pdev, vfs_num);
1253 if (ret < 0)
1254 goto err_alg_unregister;
1255 }
1256
1257 hisi_qm_pm_init(qm);
1258
1259 return 0;
1260
1261 err_alg_unregister:
1262 if (qm->qp_num >= ctx_q_num)
1263 hisi_qm_alg_unregister(qm, &sec_devices);
1264 err_qm_stop:
1265 sec_debugfs_exit(qm);
1266 hisi_qm_stop(qm, QM_NORMAL);
1267 err_probe_uninit:
1268 sec_show_last_regs_uninit(qm);
1269 sec_probe_uninit(qm);
1270 err_qm_uninit:
1271 sec_qm_uninit(qm);
1272 return ret;
1273 }
1274
sec_remove(struct pci_dev * pdev)1275 static void sec_remove(struct pci_dev *pdev)
1276 {
1277 struct hisi_qm *qm = pci_get_drvdata(pdev);
1278
1279 hisi_qm_pm_uninit(qm);
1280 hisi_qm_wait_task_finish(qm, &sec_devices);
1281 if (qm->qp_num >= ctx_q_num)
1282 hisi_qm_alg_unregister(qm, &sec_devices);
1283
1284 if (qm->fun_type == QM_HW_PF && qm->vfs_num)
1285 hisi_qm_sriov_disable(pdev, true);
1286
1287 sec_debugfs_exit(qm);
1288
1289 (void)hisi_qm_stop(qm, QM_NORMAL);
1290
1291 if (qm->fun_type == QM_HW_PF)
1292 sec_debug_regs_clear(qm);
1293 sec_show_last_regs_uninit(qm);
1294
1295 sec_probe_uninit(qm);
1296
1297 sec_qm_uninit(qm);
1298 }
1299
1300 static const struct dev_pm_ops sec_pm_ops = {
1301 SET_RUNTIME_PM_OPS(hisi_qm_suspend, hisi_qm_resume, NULL)
1302 };
1303
1304 static const struct pci_error_handlers sec_err_handler = {
1305 .error_detected = hisi_qm_dev_err_detected,
1306 .slot_reset = hisi_qm_dev_slot_reset,
1307 .reset_prepare = hisi_qm_reset_prepare,
1308 .reset_done = hisi_qm_reset_done,
1309 };
1310
1311 static struct pci_driver sec_pci_driver = {
1312 .name = "hisi_sec2",
1313 .id_table = sec_dev_ids,
1314 .probe = sec_probe,
1315 .remove = sec_remove,
1316 .err_handler = &sec_err_handler,
1317 .sriov_configure = hisi_qm_sriov_configure,
1318 .shutdown = hisi_qm_dev_shutdown,
1319 .driver.pm = &sec_pm_ops,
1320 };
1321
hisi_sec_get_pf_driver(void)1322 struct pci_driver *hisi_sec_get_pf_driver(void)
1323 {
1324 return &sec_pci_driver;
1325 }
1326 EXPORT_SYMBOL_GPL(hisi_sec_get_pf_driver);
1327
sec_register_debugfs(void)1328 static void sec_register_debugfs(void)
1329 {
1330 if (!debugfs_initialized())
1331 return;
1332
1333 sec_debugfs_root = debugfs_create_dir("hisi_sec2", NULL);
1334 }
1335
sec_unregister_debugfs(void)1336 static void sec_unregister_debugfs(void)
1337 {
1338 debugfs_remove_recursive(sec_debugfs_root);
1339 }
1340
sec_init(void)1341 static int __init sec_init(void)
1342 {
1343 int ret;
1344
1345 hisi_qm_init_list(&sec_devices);
1346 sec_register_debugfs();
1347
1348 ret = pci_register_driver(&sec_pci_driver);
1349 if (ret < 0) {
1350 sec_unregister_debugfs();
1351 pr_err("Failed to register pci driver.\n");
1352 return ret;
1353 }
1354
1355 return 0;
1356 }
1357
sec_exit(void)1358 static void __exit sec_exit(void)
1359 {
1360 pci_unregister_driver(&sec_pci_driver);
1361 sec_unregister_debugfs();
1362 }
1363
1364 module_init(sec_init);
1365 module_exit(sec_exit);
1366
1367 MODULE_LICENSE("GPL v2");
1368 MODULE_AUTHOR("Zaibo Xu <xuzaibo@huawei.com>");
1369 MODULE_AUTHOR("Longfang Liu <liulongfang@huawei.com>");
1370 MODULE_AUTHOR("Kai Ye <yekai13@huawei.com>");
1371 MODULE_AUTHOR("Wei Zhang <zhangwei375@huawei.com>");
1372 MODULE_DESCRIPTION("Driver for HiSilicon SEC accelerator");
1373
