1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2019 HiSilicon Limited. */
3
4 #include <linux/acpi.h>
5 #include <linux/aer.h>
6 #include <linux/bitops.h>
7 #include <linux/debugfs.h>
8 #include <linux/init.h>
9 #include <linux/io.h>
10 #include <linux/iommu.h>
11 #include <linux/kernel.h>
12 #include <linux/module.h>
13 #include <linux/pci.h>
14 #include <linux/pm_runtime.h>
15 #include <linux/seq_file.h>
16 #include <linux/topology.h>
17 #include <linux/uacce.h>
18
19 #include "sec.h"
20
21 #define SEC_VF_NUM 63
22 #define SEC_QUEUE_NUM_V1 4096
23 #define PCI_DEVICE_ID_HUAWEI_SEC_PF 0xa255
24
25 #define SEC_BD_ERR_CHK_EN0 0xEFFFFFFF
26 #define SEC_BD_ERR_CHK_EN1 0x7ffff7fd
27 #define SEC_BD_ERR_CHK_EN3 0xffffbfff
28
29 #define SEC_SQE_SIZE 128
30 #define SEC_PF_DEF_Q_NUM 256
31 #define SEC_PF_DEF_Q_BASE 0
32 #define SEC_CTX_Q_NUM_DEF 2
33 #define SEC_CTX_Q_NUM_MAX 32
34
35 #define SEC_CTRL_CNT_CLR_CE 0x301120
36 #define SEC_CTRL_CNT_CLR_CE_BIT BIT(0)
37 #define SEC_CORE_INT_SOURCE 0x301010
38 #define SEC_CORE_INT_MASK 0x301000
39 #define SEC_CORE_INT_STATUS 0x301008
40 #define SEC_CORE_SRAM_ECC_ERR_INFO 0x301C14
41 #define SEC_ECC_NUM 16
42 #define SEC_ECC_MASH 0xFF
43 #define SEC_CORE_INT_DISABLE 0x0
44
45 #define SEC_RAS_CE_REG 0x301050
46 #define SEC_RAS_FE_REG 0x301054
47 #define SEC_RAS_NFE_REG 0x301058
48 #define SEC_RAS_FE_ENB_MSK 0x0
49 #define SEC_OOO_SHUTDOWN_SEL 0x301014
50 #define SEC_RAS_DISABLE 0x0
51 #define SEC_MEM_START_INIT_REG 0x301100
52 #define SEC_MEM_INIT_DONE_REG 0x301104
53
54 /* clock gating */
55 #define SEC_CONTROL_REG 0x301200
56 #define SEC_DYNAMIC_GATE_REG 0x30121c
57 #define SEC_CORE_AUTO_GATE 0x30212c
58 #define SEC_DYNAMIC_GATE_EN 0x7bff
59 #define SEC_CORE_AUTO_GATE_EN GENMASK(3, 0)
60 #define SEC_CLK_GATE_ENABLE BIT(3)
61 #define SEC_CLK_GATE_DISABLE (~BIT(3))
62
63 #define SEC_TRNG_EN_SHIFT 8
64 #define SEC_AXI_SHUTDOWN_ENABLE BIT(12)
65 #define SEC_AXI_SHUTDOWN_DISABLE 0xFFFFEFFF
66
67 #define SEC_INTERFACE_USER_CTRL0_REG 0x301220
68 #define SEC_INTERFACE_USER_CTRL1_REG 0x301224
69 #define SEC_SAA_EN_REG 0x301270
70 #define SEC_BD_ERR_CHK_EN_REG0 0x301380
71 #define SEC_BD_ERR_CHK_EN_REG1 0x301384
72 #define SEC_BD_ERR_CHK_EN_REG3 0x30138c
73
74 #define SEC_USER0_SMMU_NORMAL (BIT(23) | BIT(15))
75 #define SEC_USER1_SMMU_NORMAL (BIT(31) | BIT(23) | BIT(15) | BIT(7))
76 #define SEC_USER1_ENABLE_CONTEXT_SSV BIT(24)
77 #define SEC_USER1_ENABLE_DATA_SSV BIT(16)
78 #define SEC_USER1_WB_CONTEXT_SSV BIT(8)
79 #define SEC_USER1_WB_DATA_SSV BIT(0)
80 #define SEC_USER1_SVA_SET (SEC_USER1_ENABLE_CONTEXT_SSV | \
81 SEC_USER1_ENABLE_DATA_SSV | \
82 SEC_USER1_WB_CONTEXT_SSV | \
83 SEC_USER1_WB_DATA_SSV)
84 #define SEC_USER1_SMMU_SVA (SEC_USER1_SMMU_NORMAL | SEC_USER1_SVA_SET)
85 #define SEC_USER1_SMMU_MASK (~SEC_USER1_SVA_SET)
86 #define SEC_INTERFACE_USER_CTRL0_REG_V3 0x302220
87 #define SEC_INTERFACE_USER_CTRL1_REG_V3 0x302224
88 #define SEC_USER1_SMMU_NORMAL_V3 (BIT(23) | BIT(17) | BIT(11) | BIT(5))
89 #define SEC_USER1_SMMU_MASK_V3 0xFF79E79E
90 #define SEC_CORE_INT_STATUS_M_ECC BIT(2)
91
92 #define SEC_PREFETCH_CFG 0x301130
93 #define SEC_SVA_TRANS 0x301EC4
94 #define SEC_PREFETCH_ENABLE (~(BIT(0) | BIT(1) | BIT(11)))
95 #define SEC_PREFETCH_DISABLE BIT(1)
96 #define SEC_SVA_DISABLE_READY (BIT(7) | BIT(11))
97
98 #define SEC_DELAY_10_US 10
99 #define SEC_POLL_TIMEOUT_US 1000
100 #define SEC_DBGFS_VAL_MAX_LEN 20
101 #define SEC_SINGLE_PORT_MAX_TRANS 0x2060
102
103 #define SEC_SQE_MASK_OFFSET 64
104 #define SEC_SQE_MASK_LEN 48
105 #define SEC_SHAPER_TYPE_RATE 400
106
107 #define SEC_DFX_BASE 0x301000
108 #define SEC_DFX_CORE 0x302100
109 #define SEC_DFX_COMMON1 0x301600
110 #define SEC_DFX_COMMON2 0x301C00
111 #define SEC_DFX_BASE_LEN 0x9D
112 #define SEC_DFX_CORE_LEN 0x32B
113 #define SEC_DFX_COMMON1_LEN 0x45
114 #define SEC_DFX_COMMON2_LEN 0xBA
115
116 #define SEC_ALG_BITMAP_SHIFT 32
117
118 #define SEC_CIPHER_BITMAP (GENMASK_ULL(5, 0) | GENMASK_ULL(16, 12) | \
119 GENMASK(24, 21))
120 #define SEC_DIGEST_BITMAP (GENMASK_ULL(11, 8) | GENMASK_ULL(20, 19) | \
121 GENMASK_ULL(42, 25))
122 #define SEC_AEAD_BITMAP (GENMASK_ULL(7, 6) | GENMASK_ULL(18, 17) | \
123 GENMASK_ULL(45, 43))
124 #define SEC_DEV_ALG_MAX_LEN 256
125
126 struct sec_hw_error {
127 u32 int_msk;
128 const char *msg;
129 };
130
131 struct sec_dfx_item {
132 const char *name;
133 u32 offset;
134 };
135
136 struct sec_dev_alg {
137 u64 alg_msk;
138 const char *algs;
139 };
140
141 static const char sec_name[] = "hisi_sec2";
142 static struct dentry *sec_debugfs_root;
143
144 static struct hisi_qm_list sec_devices = {
145 .register_to_crypto = sec_register_to_crypto,
146 .unregister_from_crypto = sec_unregister_from_crypto,
147 };
148
149 static const struct hisi_qm_cap_info sec_basic_info[] = {
150 {SEC_QM_NFE_MASK_CAP, 0x3124, 0, GENMASK(31, 0), 0x0, 0x1C77, 0x7C77},
151 {SEC_QM_RESET_MASK_CAP, 0x3128, 0, GENMASK(31, 0), 0x0, 0xC77, 0x6C77},
152 {SEC_QM_OOO_SHUTDOWN_MASK_CAP, 0x3128, 0, GENMASK(31, 0), 0x0, 0x4, 0x6C77},
153 {SEC_QM_CE_MASK_CAP, 0x312C, 0, GENMASK(31, 0), 0x0, 0x8, 0x8},
154 {SEC_NFE_MASK_CAP, 0x3130, 0, GENMASK(31, 0), 0x0, 0x177, 0x60177},
155 {SEC_RESET_MASK_CAP, 0x3134, 0, GENMASK(31, 0), 0x0, 0x177, 0x177},
156 {SEC_OOO_SHUTDOWN_MASK_CAP, 0x3134, 0, GENMASK(31, 0), 0x0, 0x4, 0x177},
157 {SEC_CE_MASK_CAP, 0x3138, 0, GENMASK(31, 0), 0x0, 0x88, 0xC088},
158 {SEC_CLUSTER_NUM_CAP, 0x313c, 20, GENMASK(3, 0), 0x1, 0x1, 0x1},
159 {SEC_CORE_TYPE_NUM_CAP, 0x313c, 16, GENMASK(3, 0), 0x1, 0x1, 0x1},
160 {SEC_CORE_NUM_CAP, 0x313c, 8, GENMASK(7, 0), 0x4, 0x4, 0x4},
161 {SEC_CORES_PER_CLUSTER_NUM_CAP, 0x313c, 0, GENMASK(7, 0), 0x4, 0x4, 0x4},
162 {SEC_CORE_ENABLE_BITMAP, 0x3140, 32, GENMASK(31, 0), 0x17F, 0x17F, 0xF},
163 {SEC_DRV_ALG_BITMAP_LOW, 0x3144, 0, GENMASK(31, 0), 0x18050CB, 0x18050CB, 0x187F0FF},
164 {SEC_DRV_ALG_BITMAP_HIGH, 0x3148, 0, GENMASK(31, 0), 0x395C, 0x395C, 0x395C},
165 {SEC_DEV_ALG_BITMAP_LOW, 0x314c, 0, GENMASK(31, 0), 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF},
166 {SEC_DEV_ALG_BITMAP_HIGH, 0x3150, 0, GENMASK(31, 0), 0x3FFF, 0x3FFF, 0x3FFF},
167 {SEC_CORE1_ALG_BITMAP_LOW, 0x3154, 0, GENMASK(31, 0), 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF},
168 {SEC_CORE1_ALG_BITMAP_HIGH, 0x3158, 0, GENMASK(31, 0), 0x3FFF, 0x3FFF, 0x3FFF},
169 {SEC_CORE2_ALG_BITMAP_LOW, 0x315c, 0, GENMASK(31, 0), 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF},
170 {SEC_CORE2_ALG_BITMAP_HIGH, 0x3160, 0, GENMASK(31, 0), 0x3FFF, 0x3FFF, 0x3FFF},
171 {SEC_CORE3_ALG_BITMAP_LOW, 0x3164, 0, GENMASK(31, 0), 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF},
172 {SEC_CORE3_ALG_BITMAP_HIGH, 0x3168, 0, GENMASK(31, 0), 0x3FFF, 0x3FFF, 0x3FFF},
173 {SEC_CORE4_ALG_BITMAP_LOW, 0x316c, 0, GENMASK(31, 0), 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF},
174 {SEC_CORE4_ALG_BITMAP_HIGH, 0x3170, 0, GENMASK(31, 0), 0x3FFF, 0x3FFF, 0x3FFF},
175 };
176
177 static const struct sec_dev_alg sec_dev_algs[] = { {
178 .alg_msk = SEC_CIPHER_BITMAP,
179 .algs = "cipher\n",
180 }, {
181 .alg_msk = SEC_DIGEST_BITMAP,
182 .algs = "digest\n",
183 }, {
184 .alg_msk = SEC_AEAD_BITMAP,
185 .algs = "aead\n",
186 },
187 };
188
189 static const struct sec_hw_error sec_hw_errors[] = {
190 {
191 .int_msk = BIT(0),
192 .msg = "sec_axi_rresp_err_rint"
193 },
194 {
195 .int_msk = BIT(1),
196 .msg = "sec_axi_bresp_err_rint"
197 },
198 {
199 .int_msk = BIT(2),
200 .msg = "sec_ecc_2bit_err_rint"
201 },
202 {
203 .int_msk = BIT(3),
204 .msg = "sec_ecc_1bit_err_rint"
205 },
206 {
207 .int_msk = BIT(4),
208 .msg = "sec_req_trng_timeout_rint"
209 },
210 {
211 .int_msk = BIT(5),
212 .msg = "sec_fsm_hbeat_rint"
213 },
214 {
215 .int_msk = BIT(6),
216 .msg = "sec_channel_req_rng_timeout_rint"
217 },
218 {
219 .int_msk = BIT(7),
220 .msg = "sec_bd_err_rint"
221 },
222 {
223 .int_msk = BIT(8),
224 .msg = "sec_chain_buff_err_rint"
225 },
226 {
227 .int_msk = BIT(14),
228 .msg = "sec_no_secure_access"
229 },
230 {
231 .int_msk = BIT(15),
232 .msg = "sec_wrapping_key_auth_err"
233 },
234 {
235 .int_msk = BIT(16),
236 .msg = "sec_km_key_crc_fail"
237 },
238 {
239 .int_msk = BIT(17),
240 .msg = "sec_axi_poison_err"
241 },
242 {
243 .int_msk = BIT(18),
244 .msg = "sec_sva_err"
245 },
246 {}
247 };
248
249 static const char * const sec_dbg_file_name[] = {
250 [SEC_CLEAR_ENABLE] = "clear_enable",
251 };
252
253 static struct sec_dfx_item sec_dfx_labels[] = {
254 {"send_cnt", offsetof(struct sec_dfx, send_cnt)},
255 {"recv_cnt", offsetof(struct sec_dfx, recv_cnt)},
256 {"send_busy_cnt", offsetof(struct sec_dfx, send_busy_cnt)},
257 {"recv_busy_cnt", offsetof(struct sec_dfx, recv_busy_cnt)},
258 {"err_bd_cnt", offsetof(struct sec_dfx, err_bd_cnt)},
259 {"invalid_req_cnt", offsetof(struct sec_dfx, invalid_req_cnt)},
260 {"done_flag_cnt", offsetof(struct sec_dfx, done_flag_cnt)},
261 };
262
263 static const struct debugfs_reg32 sec_dfx_regs[] = {
264 {"SEC_PF_ABNORMAL_INT_SOURCE ", 0x301010},
265 {"SEC_SAA_EN ", 0x301270},
266 {"SEC_BD_LATENCY_MIN ", 0x301600},
267 {"SEC_BD_LATENCY_MAX ", 0x301608},
268 {"SEC_BD_LATENCY_AVG ", 0x30160C},
269 {"SEC_BD_NUM_IN_SAA0 ", 0x301670},
270 {"SEC_BD_NUM_IN_SAA1 ", 0x301674},
271 {"SEC_BD_NUM_IN_SEC ", 0x301680},
272 {"SEC_ECC_1BIT_CNT ", 0x301C00},
273 {"SEC_ECC_1BIT_INFO ", 0x301C04},
274 {"SEC_ECC_2BIT_CNT ", 0x301C10},
275 {"SEC_ECC_2BIT_INFO ", 0x301C14},
276 {"SEC_BD_SAA0 ", 0x301C20},
277 {"SEC_BD_SAA1 ", 0x301C24},
278 {"SEC_BD_SAA2 ", 0x301C28},
279 {"SEC_BD_SAA3 ", 0x301C2C},
280 {"SEC_BD_SAA4 ", 0x301C30},
281 {"SEC_BD_SAA5 ", 0x301C34},
282 {"SEC_BD_SAA6 ", 0x301C38},
283 {"SEC_BD_SAA7 ", 0x301C3C},
284 {"SEC_BD_SAA8 ", 0x301C40},
285 };
286
287 /* define the SEC's dfx regs region and region length */
288 static struct dfx_diff_registers sec_diff_regs[] = {
289 {
290 .reg_offset = SEC_DFX_BASE,
291 .reg_len = SEC_DFX_BASE_LEN,
292 }, {
293 .reg_offset = SEC_DFX_COMMON1,
294 .reg_len = SEC_DFX_COMMON1_LEN,
295 }, {
296 .reg_offset = SEC_DFX_COMMON2,
297 .reg_len = SEC_DFX_COMMON2_LEN,
298 }, {
299 .reg_offset = SEC_DFX_CORE,
300 .reg_len = SEC_DFX_CORE_LEN,
301 },
302 };
303
sec_diff_regs_show(struct seq_file * s,void * unused)304 static int sec_diff_regs_show(struct seq_file *s, void *unused)
305 {
306 struct hisi_qm *qm = s->private;
307
308 hisi_qm_acc_diff_regs_dump(qm, s, qm->debug.acc_diff_regs,
309 ARRAY_SIZE(sec_diff_regs));
310
311 return 0;
312 }
313 DEFINE_SHOW_ATTRIBUTE(sec_diff_regs);
314
sec_pf_q_num_set(const char * val,const struct kernel_param * kp)315 static int sec_pf_q_num_set(const char *val, const struct kernel_param *kp)
316 {
317 return q_num_set(val, kp, PCI_DEVICE_ID_HUAWEI_SEC_PF);
318 }
319
320 static const struct kernel_param_ops sec_pf_q_num_ops = {
321 .set = sec_pf_q_num_set,
322 .get = param_get_int,
323 };
324
325 static u32 pf_q_num = SEC_PF_DEF_Q_NUM;
326 module_param_cb(pf_q_num, &sec_pf_q_num_ops, &pf_q_num, 0444);
327 MODULE_PARM_DESC(pf_q_num, "Number of queues in PF(v1 2-4096, v2 2-1024)");
328
sec_ctx_q_num_set(const char * val,const struct kernel_param * kp)329 static int sec_ctx_q_num_set(const char *val, const struct kernel_param *kp)
330 {
331 u32 ctx_q_num;
332 int ret;
333
334 if (!val)
335 return -EINVAL;
336
337 ret = kstrtou32(val, 10, &ctx_q_num);
338 if (ret)
339 return -EINVAL;
340
341 if (!ctx_q_num || ctx_q_num > SEC_CTX_Q_NUM_MAX || ctx_q_num & 0x1) {
342 pr_err("ctx queue num[%u] is invalid!\n", ctx_q_num);
343 return -EINVAL;
344 }
345
346 return param_set_int(val, kp);
347 }
348
349 static const struct kernel_param_ops sec_ctx_q_num_ops = {
350 .set = sec_ctx_q_num_set,
351 .get = param_get_int,
352 };
353 static u32 ctx_q_num = SEC_CTX_Q_NUM_DEF;
354 module_param_cb(ctx_q_num, &sec_ctx_q_num_ops, &ctx_q_num, 0444);
355 MODULE_PARM_DESC(ctx_q_num, "Queue num in ctx (2 default, 2, 4, ..., 32)");
356
357 static const struct kernel_param_ops vfs_num_ops = {
358 .set = vfs_num_set,
359 .get = param_get_int,
360 };
361
362 static u32 vfs_num;
363 module_param_cb(vfs_num, &vfs_num_ops, &vfs_num, 0444);
364 MODULE_PARM_DESC(vfs_num, "Number of VFs to enable(1-63), 0(default)");
365
sec_destroy_qps(struct hisi_qp ** qps,int qp_num)366 void sec_destroy_qps(struct hisi_qp **qps, int qp_num)
367 {
368 hisi_qm_free_qps(qps, qp_num);
369 kfree(qps);
370 }
371
sec_create_qps(void)372 struct hisi_qp **sec_create_qps(void)
373 {
374 int node = cpu_to_node(smp_processor_id());
375 u32 ctx_num = ctx_q_num;
376 struct hisi_qp **qps;
377 int ret;
378
379 qps = kcalloc(ctx_num, sizeof(struct hisi_qp *), GFP_KERNEL);
380 if (!qps)
381 return NULL;
382
383 ret = hisi_qm_alloc_qps_node(&sec_devices, ctx_num, 0, node, qps);
384 if (!ret)
385 return qps;
386
387 kfree(qps);
388 return NULL;
389 }
390
sec_get_alg_bitmap(struct hisi_qm * qm,u32 high,u32 low)391 u64 sec_get_alg_bitmap(struct hisi_qm *qm, u32 high, u32 low)
392 {
393 u32 cap_val_h, cap_val_l;
394
395 cap_val_h = hisi_qm_get_hw_info(qm, sec_basic_info, high, qm->cap_ver);
396 cap_val_l = hisi_qm_get_hw_info(qm, sec_basic_info, low, qm->cap_ver);
397
398 return ((u64)cap_val_h << SEC_ALG_BITMAP_SHIFT) | (u64)cap_val_l;
399 }
400
401 static const struct kernel_param_ops sec_uacce_mode_ops = {
402 .set = uacce_mode_set,
403 .get = param_get_int,
404 };
405
406 /*
407 * uacce_mode = 0 means sec only register to crypto,
408 * uacce_mode = 1 means sec both register to crypto and uacce.
409 */
410 static u32 uacce_mode = UACCE_MODE_NOUACCE;
411 module_param_cb(uacce_mode, &sec_uacce_mode_ops, &uacce_mode, 0444);
412 MODULE_PARM_DESC(uacce_mode, UACCE_MODE_DESC);
413
414 static const struct pci_device_id sec_dev_ids[] = {
415 { PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, PCI_DEVICE_ID_HUAWEI_SEC_PF) },
416 { PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, PCI_DEVICE_ID_HUAWEI_SEC_VF) },
417 { 0, }
418 };
419 MODULE_DEVICE_TABLE(pci, sec_dev_ids);
420
sec_set_endian(struct hisi_qm * qm)421 static void sec_set_endian(struct hisi_qm *qm)
422 {
423 u32 reg;
424
425 reg = readl_relaxed(qm->io_base + SEC_CONTROL_REG);
426 reg &= ~(BIT(1) | BIT(0));
427 if (!IS_ENABLED(CONFIG_64BIT))
428 reg |= BIT(1);
429
430
431 if (!IS_ENABLED(CONFIG_CPU_LITTLE_ENDIAN))
432 reg |= BIT(0);
433
434 writel_relaxed(reg, qm->io_base + SEC_CONTROL_REG);
435 }
436
sec_engine_sva_config(struct hisi_qm * qm)437 static void sec_engine_sva_config(struct hisi_qm *qm)
438 {
439 u32 reg;
440
441 if (qm->ver > QM_HW_V2) {
442 reg = readl_relaxed(qm->io_base +
443 SEC_INTERFACE_USER_CTRL0_REG_V3);
444 reg |= SEC_USER0_SMMU_NORMAL;
445 writel_relaxed(reg, qm->io_base +
446 SEC_INTERFACE_USER_CTRL0_REG_V3);
447
448 reg = readl_relaxed(qm->io_base +
449 SEC_INTERFACE_USER_CTRL1_REG_V3);
450 reg &= SEC_USER1_SMMU_MASK_V3;
451 reg |= SEC_USER1_SMMU_NORMAL_V3;
452 writel_relaxed(reg, qm->io_base +
453 SEC_INTERFACE_USER_CTRL1_REG_V3);
454 } else {
455 reg = readl_relaxed(qm->io_base +
456 SEC_INTERFACE_USER_CTRL0_REG);
457 reg |= SEC_USER0_SMMU_NORMAL;
458 writel_relaxed(reg, qm->io_base +
459 SEC_INTERFACE_USER_CTRL0_REG);
460 reg = readl_relaxed(qm->io_base +
461 SEC_INTERFACE_USER_CTRL1_REG);
462 reg &= SEC_USER1_SMMU_MASK;
463 if (qm->use_sva)
464 reg |= SEC_USER1_SMMU_SVA;
465 else
466 reg |= SEC_USER1_SMMU_NORMAL;
467 writel_relaxed(reg, qm->io_base +
468 SEC_INTERFACE_USER_CTRL1_REG);
469 }
470 }
471
sec_open_sva_prefetch(struct hisi_qm * qm)472 static void sec_open_sva_prefetch(struct hisi_qm *qm)
473 {
474 u32 val;
475 int ret;
476
477 if (!test_bit(QM_SUPPORT_SVA_PREFETCH, &qm->caps))
478 return;
479
480 /* Enable prefetch */
481 val = readl_relaxed(qm->io_base + SEC_PREFETCH_CFG);
482 val &= SEC_PREFETCH_ENABLE;
483 writel(val, qm->io_base + SEC_PREFETCH_CFG);
484
485 ret = readl_relaxed_poll_timeout(qm->io_base + SEC_PREFETCH_CFG,
486 val, !(val & SEC_PREFETCH_DISABLE),
487 SEC_DELAY_10_US, SEC_POLL_TIMEOUT_US);
488 if (ret)
489 pci_err(qm->pdev, "failed to open sva prefetch\n");
490 }
491
sec_close_sva_prefetch(struct hisi_qm * qm)492 static void sec_close_sva_prefetch(struct hisi_qm *qm)
493 {
494 u32 val;
495 int ret;
496
497 if (!test_bit(QM_SUPPORT_SVA_PREFETCH, &qm->caps))
498 return;
499
500 val = readl_relaxed(qm->io_base + SEC_PREFETCH_CFG);
501 val |= SEC_PREFETCH_DISABLE;
502 writel(val, qm->io_base + SEC_PREFETCH_CFG);
503
504 ret = readl_relaxed_poll_timeout(qm->io_base + SEC_SVA_TRANS,
505 val, !(val & SEC_SVA_DISABLE_READY),
506 SEC_DELAY_10_US, SEC_POLL_TIMEOUT_US);
507 if (ret)
508 pci_err(qm->pdev, "failed to close sva prefetch\n");
509 }
510
sec_enable_clock_gate(struct hisi_qm * qm)511 static void sec_enable_clock_gate(struct hisi_qm *qm)
512 {
513 u32 val;
514
515 if (qm->ver < QM_HW_V3)
516 return;
517
518 val = readl_relaxed(qm->io_base + SEC_CONTROL_REG);
519 val |= SEC_CLK_GATE_ENABLE;
520 writel_relaxed(val, qm->io_base + SEC_CONTROL_REG);
521
522 val = readl(qm->io_base + SEC_DYNAMIC_GATE_REG);
523 val |= SEC_DYNAMIC_GATE_EN;
524 writel(val, qm->io_base + SEC_DYNAMIC_GATE_REG);
525
526 val = readl(qm->io_base + SEC_CORE_AUTO_GATE);
527 val |= SEC_CORE_AUTO_GATE_EN;
528 writel(val, qm->io_base + SEC_CORE_AUTO_GATE);
529 }
530
sec_disable_clock_gate(struct hisi_qm * qm)531 static void sec_disable_clock_gate(struct hisi_qm *qm)
532 {
533 u32 val;
534
535 /* Kunpeng920 needs to close clock gating */
536 val = readl_relaxed(qm->io_base + SEC_CONTROL_REG);
537 val &= SEC_CLK_GATE_DISABLE;
538 writel_relaxed(val, qm->io_base + SEC_CONTROL_REG);
539 }
540
sec_engine_init(struct hisi_qm * qm)541 static int sec_engine_init(struct hisi_qm *qm)
542 {
543 int ret;
544 u32 reg;
545
546 /* disable clock gate control before mem init */
547 sec_disable_clock_gate(qm);
548
549 writel_relaxed(0x1, qm->io_base + SEC_MEM_START_INIT_REG);
550
551 ret = readl_relaxed_poll_timeout(qm->io_base + SEC_MEM_INIT_DONE_REG,
552 reg, reg & 0x1, SEC_DELAY_10_US,
553 SEC_POLL_TIMEOUT_US);
554 if (ret) {
555 pci_err(qm->pdev, "fail to init sec mem\n");
556 return ret;
557 }
558
559 reg = readl_relaxed(qm->io_base + SEC_CONTROL_REG);
560 reg |= (0x1 << SEC_TRNG_EN_SHIFT);
561 writel_relaxed(reg, qm->io_base + SEC_CONTROL_REG);
562
563 sec_engine_sva_config(qm);
564
565 writel(SEC_SINGLE_PORT_MAX_TRANS,
566 qm->io_base + AM_CFG_SINGLE_PORT_MAX_TRANS);
567
568 reg = hisi_qm_get_hw_info(qm, sec_basic_info, SEC_CORE_ENABLE_BITMAP, qm->cap_ver);
569 writel(reg, qm->io_base + SEC_SAA_EN_REG);
570
571 if (qm->ver < QM_HW_V3) {
572 /* HW V2 enable sm4 extra mode, as ctr/ecb */
573 writel_relaxed(SEC_BD_ERR_CHK_EN0,
574 qm->io_base + SEC_BD_ERR_CHK_EN_REG0);
575
576 /* HW V2 enable sm4 xts mode multiple iv */
577 writel_relaxed(SEC_BD_ERR_CHK_EN1,
578 qm->io_base + SEC_BD_ERR_CHK_EN_REG1);
579 writel_relaxed(SEC_BD_ERR_CHK_EN3,
580 qm->io_base + SEC_BD_ERR_CHK_EN_REG3);
581 }
582
583 /* config endian */
584 sec_set_endian(qm);
585
586 sec_enable_clock_gate(qm);
587
588 return 0;
589 }
590
sec_set_user_domain_and_cache(struct hisi_qm * qm)591 static int sec_set_user_domain_and_cache(struct hisi_qm *qm)
592 {
593 /* qm user domain */
594 writel(AXUSER_BASE, qm->io_base + QM_ARUSER_M_CFG_1);
595 writel(ARUSER_M_CFG_ENABLE, qm->io_base + QM_ARUSER_M_CFG_ENABLE);
596 writel(AXUSER_BASE, qm->io_base + QM_AWUSER_M_CFG_1);
597 writel(AWUSER_M_CFG_ENABLE, qm->io_base + QM_AWUSER_M_CFG_ENABLE);
598 writel(WUSER_M_CFG_ENABLE, qm->io_base + QM_WUSER_M_CFG_ENABLE);
599
600 /* qm cache */
601 writel(AXI_M_CFG, qm->io_base + QM_AXI_M_CFG);
602 writel(AXI_M_CFG_ENABLE, qm->io_base + QM_AXI_M_CFG_ENABLE);
603
604 /* disable FLR triggered by BME(bus master enable) */
605 writel(PEH_AXUSER_CFG, qm->io_base + QM_PEH_AXUSER_CFG);
606 writel(PEH_AXUSER_CFG_ENABLE, qm->io_base + QM_PEH_AXUSER_CFG_ENABLE);
607
608 /* enable sqc,cqc writeback */
609 writel(SQC_CACHE_ENABLE | CQC_CACHE_ENABLE | SQC_CACHE_WB_ENABLE |
610 CQC_CACHE_WB_ENABLE | FIELD_PREP(SQC_CACHE_WB_THRD, 1) |
611 FIELD_PREP(CQC_CACHE_WB_THRD, 1), qm->io_base + QM_CACHE_CTL);
612
613 return sec_engine_init(qm);
614 }
615
616 /* sec_debug_regs_clear() - clear the sec debug regs */
sec_debug_regs_clear(struct hisi_qm * qm)617 static void sec_debug_regs_clear(struct hisi_qm *qm)
618 {
619 int i;
620
621 /* clear sec dfx regs */
622 writel(0x1, qm->io_base + SEC_CTRL_CNT_CLR_CE);
623 for (i = 0; i < ARRAY_SIZE(sec_dfx_regs); i++)
624 readl(qm->io_base + sec_dfx_regs[i].offset);
625
626 /* clear rdclr_en */
627 writel(0x0, qm->io_base + SEC_CTRL_CNT_CLR_CE);
628
629 hisi_qm_debug_regs_clear(qm);
630 }
631
sec_master_ooo_ctrl(struct hisi_qm * qm,bool enable)632 static void sec_master_ooo_ctrl(struct hisi_qm *qm, bool enable)
633 {
634 u32 val1, val2;
635
636 val1 = readl(qm->io_base + SEC_CONTROL_REG);
637 if (enable) {
638 val1 |= SEC_AXI_SHUTDOWN_ENABLE;
639 val2 = hisi_qm_get_hw_info(qm, sec_basic_info,
640 SEC_OOO_SHUTDOWN_MASK_CAP, qm->cap_ver);
641 } else {
642 val1 &= SEC_AXI_SHUTDOWN_DISABLE;
643 val2 = 0x0;
644 }
645
646 if (qm->ver > QM_HW_V2)
647 writel(val2, qm->io_base + SEC_OOO_SHUTDOWN_SEL);
648
649 writel(val1, qm->io_base + SEC_CONTROL_REG);
650 }
651
sec_hw_error_enable(struct hisi_qm * qm)652 static void sec_hw_error_enable(struct hisi_qm *qm)
653 {
654 u32 ce, nfe;
655
656 if (qm->ver == QM_HW_V1) {
657 writel(SEC_CORE_INT_DISABLE, qm->io_base + SEC_CORE_INT_MASK);
658 pci_info(qm->pdev, "V1 not support hw error handle\n");
659 return;
660 }
661
662 ce = hisi_qm_get_hw_info(qm, sec_basic_info, SEC_CE_MASK_CAP, qm->cap_ver);
663 nfe = hisi_qm_get_hw_info(qm, sec_basic_info, SEC_NFE_MASK_CAP, qm->cap_ver);
664
665 /* clear SEC hw error source if having */
666 writel(ce | nfe | SEC_RAS_FE_ENB_MSK, qm->io_base + SEC_CORE_INT_SOURCE);
667
668 /* enable RAS int */
669 writel(ce, qm->io_base + SEC_RAS_CE_REG);
670 writel(SEC_RAS_FE_ENB_MSK, qm->io_base + SEC_RAS_FE_REG);
671 writel(nfe, qm->io_base + SEC_RAS_NFE_REG);
672
673 /* enable SEC block master OOO when nfe occurs on Kunpeng930 */
674 sec_master_ooo_ctrl(qm, true);
675
676 /* enable SEC hw error interrupts */
677 writel(ce | nfe | SEC_RAS_FE_ENB_MSK, qm->io_base + SEC_CORE_INT_MASK);
678 }
679
sec_hw_error_disable(struct hisi_qm * qm)680 static void sec_hw_error_disable(struct hisi_qm *qm)
681 {
682 /* disable SEC hw error interrupts */
683 writel(SEC_CORE_INT_DISABLE, qm->io_base + SEC_CORE_INT_MASK);
684
685 /* disable SEC block master OOO when nfe occurs on Kunpeng930 */
686 sec_master_ooo_ctrl(qm, false);
687
688 /* disable RAS int */
689 writel(SEC_RAS_DISABLE, qm->io_base + SEC_RAS_CE_REG);
690 writel(SEC_RAS_DISABLE, qm->io_base + SEC_RAS_FE_REG);
691 writel(SEC_RAS_DISABLE, qm->io_base + SEC_RAS_NFE_REG);
692 }
693
sec_clear_enable_read(struct hisi_qm * qm)694 static u32 sec_clear_enable_read(struct hisi_qm *qm)
695 {
696 return readl(qm->io_base + SEC_CTRL_CNT_CLR_CE) &
697 SEC_CTRL_CNT_CLR_CE_BIT;
698 }
699
sec_clear_enable_write(struct hisi_qm * qm,u32 val)700 static int sec_clear_enable_write(struct hisi_qm *qm, u32 val)
701 {
702 u32 tmp;
703
704 if (val != 1 && val)
705 return -EINVAL;
706
707 tmp = (readl(qm->io_base + SEC_CTRL_CNT_CLR_CE) &
708 ~SEC_CTRL_CNT_CLR_CE_BIT) | val;
709 writel(tmp, qm->io_base + SEC_CTRL_CNT_CLR_CE);
710
711 return 0;
712 }
713
sec_debug_read(struct file * filp,char __user * buf,size_t count,loff_t * pos)714 static ssize_t sec_debug_read(struct file *filp, char __user *buf,
715 size_t count, loff_t *pos)
716 {
717 struct sec_debug_file *file = filp->private_data;
718 char tbuf[SEC_DBGFS_VAL_MAX_LEN];
719 struct hisi_qm *qm = file->qm;
720 u32 val;
721 int ret;
722
723 ret = hisi_qm_get_dfx_access(qm);
724 if (ret)
725 return ret;
726
727 spin_lock_irq(&file->lock);
728
729 switch (file->index) {
730 case SEC_CLEAR_ENABLE:
731 val = sec_clear_enable_read(qm);
732 break;
733 default:
734 goto err_input;
735 }
736
737 spin_unlock_irq(&file->lock);
738
739 hisi_qm_put_dfx_access(qm);
740 ret = snprintf(tbuf, SEC_DBGFS_VAL_MAX_LEN, "%u\n", val);
741 return simple_read_from_buffer(buf, count, pos, tbuf, ret);
742
743 err_input:
744 spin_unlock_irq(&file->lock);
745 hisi_qm_put_dfx_access(qm);
746 return -EINVAL;
747 }
748
sec_debug_write(struct file * filp,const char __user * buf,size_t count,loff_t * pos)749 static ssize_t sec_debug_write(struct file *filp, const char __user *buf,
750 size_t count, loff_t *pos)
751 {
752 struct sec_debug_file *file = filp->private_data;
753 char tbuf[SEC_DBGFS_VAL_MAX_LEN];
754 struct hisi_qm *qm = file->qm;
755 unsigned long val;
756 int len, ret;
757
758 if (*pos != 0)
759 return 0;
760
761 if (count >= SEC_DBGFS_VAL_MAX_LEN)
762 return -ENOSPC;
763
764 len = simple_write_to_buffer(tbuf, SEC_DBGFS_VAL_MAX_LEN - 1,
765 pos, buf, count);
766 if (len < 0)
767 return len;
768
769 tbuf[len] = '\0';
770 if (kstrtoul(tbuf, 0, &val))
771 return -EFAULT;
772
773 ret = hisi_qm_get_dfx_access(qm);
774 if (ret)
775 return ret;
776
777 spin_lock_irq(&file->lock);
778
779 switch (file->index) {
780 case SEC_CLEAR_ENABLE:
781 ret = sec_clear_enable_write(qm, val);
782 if (ret)
783 goto err_input;
784 break;
785 default:
786 ret = -EINVAL;
787 goto err_input;
788 }
789
790 ret = count;
791
792 err_input:
793 spin_unlock_irq(&file->lock);
794 hisi_qm_put_dfx_access(qm);
795 return ret;
796 }
797
798 static const struct file_operations sec_dbg_fops = {
799 .owner = THIS_MODULE,
800 .open = simple_open,
801 .read = sec_debug_read,
802 .write = sec_debug_write,
803 };
804
sec_debugfs_atomic64_get(void * data,u64 * val)805 static int sec_debugfs_atomic64_get(void *data, u64 *val)
806 {
807 *val = atomic64_read((atomic64_t *)data);
808
809 return 0;
810 }
811
sec_debugfs_atomic64_set(void * data,u64 val)812 static int sec_debugfs_atomic64_set(void *data, u64 val)
813 {
814 if (val)
815 return -EINVAL;
816
817 atomic64_set((atomic64_t *)data, 0);
818
819 return 0;
820 }
821
822 DEFINE_DEBUGFS_ATTRIBUTE(sec_atomic64_ops, sec_debugfs_atomic64_get,
823 sec_debugfs_atomic64_set, "%lld\n");
824
sec_regs_show(struct seq_file * s,void * unused)825 static int sec_regs_show(struct seq_file *s, void *unused)
826 {
827 hisi_qm_regs_dump(s, s->private);
828
829 return 0;
830 }
831
832 DEFINE_SHOW_ATTRIBUTE(sec_regs);
833
sec_core_debug_init(struct hisi_qm * qm)834 static int sec_core_debug_init(struct hisi_qm *qm)
835 {
836 struct dfx_diff_registers *sec_regs = qm->debug.acc_diff_regs;
837 struct sec_dev *sec = container_of(qm, struct sec_dev, qm);
838 struct device *dev = &qm->pdev->dev;
839 struct sec_dfx *dfx = &sec->debug.dfx;
840 struct debugfs_regset32 *regset;
841 struct dentry *tmp_d;
842 int i;
843
844 tmp_d = debugfs_create_dir("sec_dfx", qm->debug.debug_root);
845
846 regset = devm_kzalloc(dev, sizeof(*regset), GFP_KERNEL);
847 if (!regset)
848 return -ENOMEM;
849
850 regset->regs = sec_dfx_regs;
851 regset->nregs = ARRAY_SIZE(sec_dfx_regs);
852 regset->base = qm->io_base;
853 regset->dev = dev;
854
855 if (qm->pdev->device == PCI_DEVICE_ID_HUAWEI_SEC_PF)
856 debugfs_create_file("regs", 0444, tmp_d, regset, &sec_regs_fops);
857 if (qm->fun_type == QM_HW_PF && sec_regs)
858 debugfs_create_file("diff_regs", 0444, tmp_d,
859 qm, &sec_diff_regs_fops);
860
861 for (i = 0; i < ARRAY_SIZE(sec_dfx_labels); i++) {
862 atomic64_t *data = (atomic64_t *)((uintptr_t)dfx +
863 sec_dfx_labels[i].offset);
864 debugfs_create_file(sec_dfx_labels[i].name, 0644,
865 tmp_d, data, &sec_atomic64_ops);
866 }
867
868 return 0;
869 }
870
sec_debug_init(struct hisi_qm * qm)871 static int sec_debug_init(struct hisi_qm *qm)
872 {
873 struct sec_dev *sec = container_of(qm, struct sec_dev, qm);
874 int i;
875
876 if (qm->pdev->device == PCI_DEVICE_ID_HUAWEI_SEC_PF) {
877 for (i = SEC_CLEAR_ENABLE; i < SEC_DEBUG_FILE_NUM; i++) {
878 spin_lock_init(&sec->debug.files[i].lock);
879 sec->debug.files[i].index = i;
880 sec->debug.files[i].qm = qm;
881
882 debugfs_create_file(sec_dbg_file_name[i], 0600,
883 qm->debug.debug_root,
884 sec->debug.files + i,
885 &sec_dbg_fops);
886 }
887 }
888
889 return sec_core_debug_init(qm);
890 }
891
sec_debugfs_init(struct hisi_qm * qm)892 static int sec_debugfs_init(struct hisi_qm *qm)
893 {
894 struct device *dev = &qm->pdev->dev;
895 int ret;
896
897 qm->debug.debug_root = debugfs_create_dir(dev_name(dev),
898 sec_debugfs_root);
899 qm->debug.sqe_mask_offset = SEC_SQE_MASK_OFFSET;
900 qm->debug.sqe_mask_len = SEC_SQE_MASK_LEN;
901
902 ret = hisi_qm_diff_regs_init(qm, sec_diff_regs,
903 ARRAY_SIZE(sec_diff_regs));
904 if (ret) {
905 dev_warn(dev, "Failed to init SEC diff regs!\n");
906 goto debugfs_remove;
907 }
908
909 hisi_qm_debug_init(qm);
910
911 ret = sec_debug_init(qm);
912 if (ret)
913 goto failed_to_create;
914
915 return 0;
916
917 failed_to_create:
918 hisi_qm_diff_regs_uninit(qm, ARRAY_SIZE(sec_diff_regs));
919 debugfs_remove:
920 debugfs_remove_recursive(sec_debugfs_root);
921 return ret;
922 }
923
sec_debugfs_exit(struct hisi_qm * qm)924 static void sec_debugfs_exit(struct hisi_qm *qm)
925 {
926 hisi_qm_diff_regs_uninit(qm, ARRAY_SIZE(sec_diff_regs));
927
928 debugfs_remove_recursive(qm->debug.debug_root);
929 }
930
sec_show_last_regs_init(struct hisi_qm * qm)931 static int sec_show_last_regs_init(struct hisi_qm *qm)
932 {
933 struct qm_debug *debug = &qm->debug;
934 int i;
935
936 debug->last_words = kcalloc(ARRAY_SIZE(sec_dfx_regs),
937 sizeof(unsigned int), GFP_KERNEL);
938 if (!debug->last_words)
939 return -ENOMEM;
940
941 for (i = 0; i < ARRAY_SIZE(sec_dfx_regs); i++)
942 debug->last_words[i] = readl_relaxed(qm->io_base +
943 sec_dfx_regs[i].offset);
944
945 return 0;
946 }
947
sec_show_last_regs_uninit(struct hisi_qm * qm)948 static void sec_show_last_regs_uninit(struct hisi_qm *qm)
949 {
950 struct qm_debug *debug = &qm->debug;
951
952 if (qm->fun_type == QM_HW_VF || !debug->last_words)
953 return;
954
955 kfree(debug->last_words);
956 debug->last_words = NULL;
957 }
958
sec_show_last_dfx_regs(struct hisi_qm * qm)959 static void sec_show_last_dfx_regs(struct hisi_qm *qm)
960 {
961 struct qm_debug *debug = &qm->debug;
962 struct pci_dev *pdev = qm->pdev;
963 u32 val;
964 int i;
965
966 if (qm->fun_type == QM_HW_VF || !debug->last_words)
967 return;
968
969 /* dumps last word of the debugging registers during controller reset */
970 for (i = 0; i < ARRAY_SIZE(sec_dfx_regs); i++) {
971 val = readl_relaxed(qm->io_base + sec_dfx_regs[i].offset);
972 if (val != debug->last_words[i])
973 pci_info(pdev, "%s \t= 0x%08x => 0x%08x\n",
974 sec_dfx_regs[i].name, debug->last_words[i], val);
975 }
976 }
977
sec_log_hw_error(struct hisi_qm * qm,u32 err_sts)978 static void sec_log_hw_error(struct hisi_qm *qm, u32 err_sts)
979 {
980 const struct sec_hw_error *errs = sec_hw_errors;
981 struct device *dev = &qm->pdev->dev;
982 u32 err_val;
983
984 while (errs->msg) {
985 if (errs->int_msk & err_sts) {
986 dev_err(dev, "%s [error status=0x%x] found\n",
987 errs->msg, errs->int_msk);
988
989 if (SEC_CORE_INT_STATUS_M_ECC & errs->int_msk) {
990 err_val = readl(qm->io_base +
991 SEC_CORE_SRAM_ECC_ERR_INFO);
992 dev_err(dev, "multi ecc sram num=0x%x\n",
993 ((err_val) >> SEC_ECC_NUM) &
994 SEC_ECC_MASH);
995 }
996 }
997 errs++;
998 }
999 }
1000
sec_get_hw_err_status(struct hisi_qm * qm)1001 static u32 sec_get_hw_err_status(struct hisi_qm *qm)
1002 {
1003 return readl(qm->io_base + SEC_CORE_INT_STATUS);
1004 }
1005
sec_clear_hw_err_status(struct hisi_qm * qm,u32 err_sts)1006 static void sec_clear_hw_err_status(struct hisi_qm *qm, u32 err_sts)
1007 {
1008 u32 nfe;
1009
1010 writel(err_sts, qm->io_base + SEC_CORE_INT_SOURCE);
1011 nfe = hisi_qm_get_hw_info(qm, sec_basic_info, SEC_NFE_MASK_CAP, qm->cap_ver);
1012 writel(nfe, qm->io_base + SEC_RAS_NFE_REG);
1013 }
1014
sec_open_axi_master_ooo(struct hisi_qm * qm)1015 static void sec_open_axi_master_ooo(struct hisi_qm *qm)
1016 {
1017 u32 val;
1018
1019 val = readl(qm->io_base + SEC_CONTROL_REG);
1020 writel(val & SEC_AXI_SHUTDOWN_DISABLE, qm->io_base + SEC_CONTROL_REG);
1021 writel(val | SEC_AXI_SHUTDOWN_ENABLE, qm->io_base + SEC_CONTROL_REG);
1022 }
1023
sec_err_info_init(struct hisi_qm * qm)1024 static void sec_err_info_init(struct hisi_qm *qm)
1025 {
1026 struct hisi_qm_err_info *err_info = &qm->err_info;
1027
1028 err_info->fe = SEC_RAS_FE_ENB_MSK;
1029 err_info->ce = hisi_qm_get_hw_info(qm, sec_basic_info, SEC_QM_CE_MASK_CAP, qm->cap_ver);
1030 err_info->nfe = hisi_qm_get_hw_info(qm, sec_basic_info, SEC_QM_NFE_MASK_CAP, qm->cap_ver);
1031 err_info->ecc_2bits_mask = SEC_CORE_INT_STATUS_M_ECC;
1032 err_info->qm_shutdown_mask = hisi_qm_get_hw_info(qm, sec_basic_info,
1033 SEC_QM_OOO_SHUTDOWN_MASK_CAP, qm->cap_ver);
1034 err_info->dev_shutdown_mask = hisi_qm_get_hw_info(qm, sec_basic_info,
1035 SEC_OOO_SHUTDOWN_MASK_CAP, qm->cap_ver);
1036 err_info->qm_reset_mask = hisi_qm_get_hw_info(qm, sec_basic_info,
1037 SEC_QM_RESET_MASK_CAP, qm->cap_ver);
1038 err_info->dev_reset_mask = hisi_qm_get_hw_info(qm, sec_basic_info,
1039 SEC_RESET_MASK_CAP, qm->cap_ver);
1040 err_info->msi_wr_port = BIT(0);
1041 err_info->acpi_rst = "SRST";
1042 }
1043
1044 static const struct hisi_qm_err_ini sec_err_ini = {
1045 .hw_init = sec_set_user_domain_and_cache,
1046 .hw_err_enable = sec_hw_error_enable,
1047 .hw_err_disable = sec_hw_error_disable,
1048 .get_dev_hw_err_status = sec_get_hw_err_status,
1049 .clear_dev_hw_err_status = sec_clear_hw_err_status,
1050 .log_dev_hw_err = sec_log_hw_error,
1051 .open_axi_master_ooo = sec_open_axi_master_ooo,
1052 .open_sva_prefetch = sec_open_sva_prefetch,
1053 .close_sva_prefetch = sec_close_sva_prefetch,
1054 .show_last_dfx_regs = sec_show_last_dfx_regs,
1055 .err_info_init = sec_err_info_init,
1056 };
1057
sec_pf_probe_init(struct sec_dev * sec)1058 static int sec_pf_probe_init(struct sec_dev *sec)
1059 {
1060 struct hisi_qm *qm = &sec->qm;
1061 int ret;
1062
1063 qm->err_ini = &sec_err_ini;
1064 qm->err_ini->err_info_init(qm);
1065
1066 ret = sec_set_user_domain_and_cache(qm);
1067 if (ret)
1068 return ret;
1069
1070 sec_open_sva_prefetch(qm);
1071 hisi_qm_dev_err_init(qm);
1072 sec_debug_regs_clear(qm);
1073 ret = sec_show_last_regs_init(qm);
1074 if (ret)
1075 pci_err(qm->pdev, "Failed to init last word regs!\n");
1076
1077 return ret;
1078 }
1079
sec_set_qm_algs(struct hisi_qm * qm)1080 static int sec_set_qm_algs(struct hisi_qm *qm)
1081 {
1082 struct device *dev = &qm->pdev->dev;
1083 char *algs, *ptr;
1084 u64 alg_mask;
1085 int i;
1086
1087 if (!qm->use_sva)
1088 return 0;
1089
1090 algs = devm_kzalloc(dev, SEC_DEV_ALG_MAX_LEN * sizeof(char), GFP_KERNEL);
1091 if (!algs)
1092 return -ENOMEM;
1093
1094 alg_mask = sec_get_alg_bitmap(qm, SEC_DEV_ALG_BITMAP_HIGH, SEC_DEV_ALG_BITMAP_LOW);
1095
1096 for (i = 0; i < ARRAY_SIZE(sec_dev_algs); i++)
1097 if (alg_mask & sec_dev_algs[i].alg_msk)
1098 strcat(algs, sec_dev_algs[i].algs);
1099
1100 ptr = strrchr(algs, '\n');
1101 if (ptr)
1102 *ptr = '\0';
1103
1104 qm->uacce->algs = algs;
1105
1106 return 0;
1107 }
1108
sec_qm_init(struct hisi_qm * qm,struct pci_dev * pdev)1109 static int sec_qm_init(struct hisi_qm *qm, struct pci_dev *pdev)
1110 {
1111 int ret;
1112
1113 qm->pdev = pdev;
1114 qm->ver = pdev->revision;
1115 qm->mode = uacce_mode;
1116 qm->sqe_size = SEC_SQE_SIZE;
1117 qm->dev_name = sec_name;
1118
1119 qm->fun_type = (pdev->device == PCI_DEVICE_ID_HUAWEI_SEC_PF) ?
1120 QM_HW_PF : QM_HW_VF;
1121 if (qm->fun_type == QM_HW_PF) {
1122 qm->qp_base = SEC_PF_DEF_Q_BASE;
1123 qm->qp_num = pf_q_num;
1124 qm->debug.curr_qm_qp_num = pf_q_num;
1125 qm->qm_list = &sec_devices;
1126 } else if (qm->fun_type == QM_HW_VF && qm->ver == QM_HW_V1) {
1127 /*
1128 * have no way to get qm configure in VM in v1 hardware,
1129 * so currently force PF to uses SEC_PF_DEF_Q_NUM, and force
1130 * to trigger only one VF in v1 hardware.
1131 * v2 hardware has no such problem.
1132 */
1133 qm->qp_base = SEC_PF_DEF_Q_NUM;
1134 qm->qp_num = SEC_QUEUE_NUM_V1 - SEC_PF_DEF_Q_NUM;
1135 }
1136
1137 ret = hisi_qm_init(qm);
1138 if (ret) {
1139 pci_err(qm->pdev, "Failed to init sec qm configures!\n");
1140 return ret;
1141 }
1142
1143 ret = sec_set_qm_algs(qm);
1144 if (ret) {
1145 pci_err(qm->pdev, "Failed to set sec algs!\n");
1146 hisi_qm_uninit(qm);
1147 }
1148
1149 return ret;
1150 }
1151
sec_qm_uninit(struct hisi_qm * qm)1152 static void sec_qm_uninit(struct hisi_qm *qm)
1153 {
1154 hisi_qm_uninit(qm);
1155 }
1156
sec_probe_init(struct sec_dev * sec)1157 static int sec_probe_init(struct sec_dev *sec)
1158 {
1159 u32 type_rate = SEC_SHAPER_TYPE_RATE;
1160 struct hisi_qm *qm = &sec->qm;
1161 int ret;
1162
1163 if (qm->fun_type == QM_HW_PF) {
1164 ret = sec_pf_probe_init(sec);
1165 if (ret)
1166 return ret;
1167 /* enable shaper type 0 */
1168 if (qm->ver >= QM_HW_V3) {
1169 type_rate |= QM_SHAPER_ENABLE;
1170 qm->type_rate = type_rate;
1171 }
1172 }
1173
1174 return 0;
1175 }
1176
sec_probe_uninit(struct hisi_qm * qm)1177 static void sec_probe_uninit(struct hisi_qm *qm)
1178 {
1179 hisi_qm_dev_err_uninit(qm);
1180 }
1181
sec_iommu_used_check(struct sec_dev * sec)1182 static void sec_iommu_used_check(struct sec_dev *sec)
1183 {
1184 struct iommu_domain *domain;
1185 struct device *dev = &sec->qm.pdev->dev;
1186
1187 domain = iommu_get_domain_for_dev(dev);
1188
1189 /* Check if iommu is used */
1190 sec->iommu_used = false;
1191 if (domain) {
1192 if (domain->type & __IOMMU_DOMAIN_PAGING)
1193 sec->iommu_used = true;
1194 dev_info(dev, "SMMU Opened, the iommu type = %u\n",
1195 domain->type);
1196 }
1197 }
1198
sec_probe(struct pci_dev * pdev,const struct pci_device_id * id)1199 static int sec_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1200 {
1201 struct sec_dev *sec;
1202 struct hisi_qm *qm;
1203 int ret;
1204
1205 sec = devm_kzalloc(&pdev->dev, sizeof(*sec), GFP_KERNEL);
1206 if (!sec)
1207 return -ENOMEM;
1208
1209 qm = &sec->qm;
1210 ret = sec_qm_init(qm, pdev);
1211 if (ret) {
1212 pci_err(pdev, "Failed to init SEC QM (%d)!\n", ret);
1213 return ret;
1214 }
1215
1216 sec->ctx_q_num = ctx_q_num;
1217 sec_iommu_used_check(sec);
1218
1219 ret = sec_probe_init(sec);
1220 if (ret) {
1221 pci_err(pdev, "Failed to probe!\n");
1222 goto err_qm_uninit;
1223 }
1224
1225 ret = hisi_qm_start(qm);
1226 if (ret) {
1227 pci_err(pdev, "Failed to start sec qm!\n");
1228 goto err_probe_uninit;
1229 }
1230
1231 ret = sec_debugfs_init(qm);
1232 if (ret)
1233 pci_warn(pdev, "Failed to init debugfs!\n");
1234
1235 if (qm->qp_num >= ctx_q_num) {
1236 ret = hisi_qm_alg_register(qm, &sec_devices);
1237 if (ret < 0) {
1238 pr_err("Failed to register driver to crypto.\n");
1239 goto err_qm_stop;
1240 }
1241 } else {
1242 pci_warn(qm->pdev,
1243 "Failed to use kernel mode, qp not enough!\n");
1244 }
1245
1246 if (qm->uacce) {
1247 ret = uacce_register(qm->uacce);
1248 if (ret) {
1249 pci_err(pdev, "failed to register uacce (%d)!\n", ret);
1250 goto err_alg_unregister;
1251 }
1252 }
1253
1254 if (qm->fun_type == QM_HW_PF && vfs_num) {
1255 ret = hisi_qm_sriov_enable(pdev, vfs_num);
1256 if (ret < 0)
1257 goto err_alg_unregister;
1258 }
1259
1260 hisi_qm_pm_init(qm);
1261
1262 return 0;
1263
1264 err_alg_unregister:
1265 if (qm->qp_num >= ctx_q_num)
1266 hisi_qm_alg_unregister(qm, &sec_devices);
1267 err_qm_stop:
1268 sec_debugfs_exit(qm);
1269 hisi_qm_stop(qm, QM_NORMAL);
1270 err_probe_uninit:
1271 sec_show_last_regs_uninit(qm);
1272 sec_probe_uninit(qm);
1273 err_qm_uninit:
1274 sec_qm_uninit(qm);
1275 return ret;
1276 }
1277
sec_remove(struct pci_dev * pdev)1278 static void sec_remove(struct pci_dev *pdev)
1279 {
1280 struct hisi_qm *qm = pci_get_drvdata(pdev);
1281
1282 hisi_qm_pm_uninit(qm);
1283 hisi_qm_wait_task_finish(qm, &sec_devices);
1284 if (qm->qp_num >= ctx_q_num)
1285 hisi_qm_alg_unregister(qm, &sec_devices);
1286
1287 if (qm->fun_type == QM_HW_PF && qm->vfs_num)
1288 hisi_qm_sriov_disable(pdev, true);
1289
1290 sec_debugfs_exit(qm);
1291
1292 (void)hisi_qm_stop(qm, QM_NORMAL);
1293
1294 if (qm->fun_type == QM_HW_PF)
1295 sec_debug_regs_clear(qm);
1296 sec_show_last_regs_uninit(qm);
1297
1298 sec_probe_uninit(qm);
1299
1300 sec_qm_uninit(qm);
1301 }
1302
1303 static const struct dev_pm_ops sec_pm_ops = {
1304 SET_RUNTIME_PM_OPS(hisi_qm_suspend, hisi_qm_resume, NULL)
1305 };
1306
1307 static const struct pci_error_handlers sec_err_handler = {
1308 .error_detected = hisi_qm_dev_err_detected,
1309 .slot_reset = hisi_qm_dev_slot_reset,
1310 .reset_prepare = hisi_qm_reset_prepare,
1311 .reset_done = hisi_qm_reset_done,
1312 };
1313
1314 static struct pci_driver sec_pci_driver = {
1315 .name = "hisi_sec2",
1316 .id_table = sec_dev_ids,
1317 .probe = sec_probe,
1318 .remove = sec_remove,
1319 .err_handler = &sec_err_handler,
1320 .sriov_configure = hisi_qm_sriov_configure,
1321 .shutdown = hisi_qm_dev_shutdown,
1322 .driver.pm = &sec_pm_ops,
1323 };
1324
hisi_sec_get_pf_driver(void)1325 struct pci_driver *hisi_sec_get_pf_driver(void)
1326 {
1327 return &sec_pci_driver;
1328 }
1329 EXPORT_SYMBOL_GPL(hisi_sec_get_pf_driver);
1330
sec_register_debugfs(void)1331 static void sec_register_debugfs(void)
1332 {
1333 if (!debugfs_initialized())
1334 return;
1335
1336 sec_debugfs_root = debugfs_create_dir("hisi_sec2", NULL);
1337 }
1338
sec_unregister_debugfs(void)1339 static void sec_unregister_debugfs(void)
1340 {
1341 debugfs_remove_recursive(sec_debugfs_root);
1342 }
1343
sec_init(void)1344 static int __init sec_init(void)
1345 {
1346 int ret;
1347
1348 hisi_qm_init_list(&sec_devices);
1349 sec_register_debugfs();
1350
1351 ret = pci_register_driver(&sec_pci_driver);
1352 if (ret < 0) {
1353 sec_unregister_debugfs();
1354 pr_err("Failed to register pci driver.\n");
1355 return ret;
1356 }
1357
1358 return 0;
1359 }
1360
sec_exit(void)1361 static void __exit sec_exit(void)
1362 {
1363 pci_unregister_driver(&sec_pci_driver);
1364 sec_unregister_debugfs();
1365 }
1366
1367 module_init(sec_init);
1368 module_exit(sec_exit);
1369
1370 MODULE_LICENSE("GPL v2");
1371 MODULE_AUTHOR("Zaibo Xu <xuzaibo@huawei.com>");
1372 MODULE_AUTHOR("Longfang Liu <liulongfang@huawei.com>");
1373 MODULE_AUTHOR("Kai Ye <yekai13@huawei.com>");
1374 MODULE_AUTHOR("Wei Zhang <zhangwei375@huawei.com>");
1375 MODULE_DESCRIPTION("Driver for HiSilicon SEC accelerator");
1376
