1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2018-2019 HiSilicon Limited. */
3 #include <linux/acpi.h>
4 #include <linux/bitops.h>
5 #include <linux/debugfs.h>
6 #include <linux/init.h>
7 #include <linux/io.h>
8 #include <linux/kernel.h>
9 #include <linux/module.h>
10 #include <linux/pci.h>
11 #include <linux/pm_runtime.h>
12 #include <linux/topology.h>
13 #include <linux/uacce.h>
14 #include "hpre.h"
15
16 #define HPRE_QM_ABNML_INT_MASK 0x100004
17 #define HPRE_CTRL_CNT_CLR_CE_BIT BIT(0)
18 #define HPRE_COMM_CNT_CLR_CE 0x0
19 #define HPRE_CTRL_CNT_CLR_CE 0x301000
20 #define HPRE_FSM_MAX_CNT 0x301008
21 #define HPRE_VFG_AXQOS 0x30100c
22 #define HPRE_VFG_AXCACHE 0x301010
23 #define HPRE_RDCHN_INI_CFG 0x301014
24 #define HPRE_AWUSR_FP_CFG 0x301018
25 #define HPRE_BD_ENDIAN 0x301020
26 #define HPRE_ECC_BYPASS 0x301024
27 #define HPRE_RAS_WIDTH_CFG 0x301028
28 #define HPRE_POISON_BYPASS 0x30102c
29 #define HPRE_BD_ARUSR_CFG 0x301030
30 #define HPRE_BD_AWUSR_CFG 0x301034
31 #define HPRE_TYPES_ENB 0x301038
32 #define HPRE_RSA_ENB BIT(0)
33 #define HPRE_ECC_ENB BIT(1)
34 #define HPRE_DATA_RUSER_CFG 0x30103c
35 #define HPRE_DATA_WUSER_CFG 0x301040
36 #define HPRE_INT_MASK 0x301400
37 #define HPRE_INT_STATUS 0x301800
38 #define HPRE_HAC_INT_MSK 0x301400
39 #define HPRE_HAC_RAS_CE_ENB 0x301410
40 #define HPRE_HAC_RAS_NFE_ENB 0x301414
41 #define HPRE_HAC_RAS_FE_ENB 0x301418
42 #define HPRE_HAC_INT_SET 0x301500
43 #define HPRE_RNG_TIMEOUT_NUM 0x301A34
44 #define HPRE_CORE_INT_ENABLE 0
45 #define HPRE_CORE_INT_DISABLE GENMASK(21, 0)
46 #define HPRE_RDCHN_INI_ST 0x301a00
47 #define HPRE_CLSTR_BASE 0x302000
48 #define HPRE_CORE_EN_OFFSET 0x04
49 #define HPRE_CORE_INI_CFG_OFFSET 0x20
50 #define HPRE_CORE_INI_STATUS_OFFSET 0x80
51 #define HPRE_CORE_HTBT_WARN_OFFSET 0x8c
52 #define HPRE_CORE_IS_SCHD_OFFSET 0x90
53
54 #define HPRE_RAS_CE_ENB 0x301410
55 #define HPRE_RAS_NFE_ENB 0x301414
56 #define HPRE_RAS_FE_ENB 0x301418
57 #define HPRE_OOO_SHUTDOWN_SEL 0x301a3c
58 #define HPRE_HAC_RAS_FE_ENABLE 0
59
60 #define HPRE_CORE_ENB (HPRE_CLSTR_BASE + HPRE_CORE_EN_OFFSET)
61 #define HPRE_CORE_INI_CFG (HPRE_CLSTR_BASE + HPRE_CORE_INI_CFG_OFFSET)
62 #define HPRE_CORE_INI_STATUS (HPRE_CLSTR_BASE + HPRE_CORE_INI_STATUS_OFFSET)
63 #define HPRE_HAC_ECC1_CNT 0x301a04
64 #define HPRE_HAC_ECC2_CNT 0x301a08
65 #define HPRE_HAC_SOURCE_INT 0x301600
66 #define HPRE_CLSTR_ADDR_INTRVL 0x1000
67 #define HPRE_CLUSTER_INQURY 0x100
68 #define HPRE_CLSTR_ADDR_INQRY_RSLT 0x104
69 #define HPRE_TIMEOUT_ABNML_BIT 6
70 #define HPRE_PASID_EN_BIT 9
71 #define HPRE_REG_RD_INTVRL_US 10
72 #define HPRE_REG_RD_TMOUT_US 1000
73 #define HPRE_DBGFS_VAL_MAX_LEN 20
74 #define PCI_DEVICE_ID_HUAWEI_HPRE_PF 0xa258
75 #define HPRE_QM_USR_CFG_MASK GENMASK(31, 1)
76 #define HPRE_QM_AXI_CFG_MASK GENMASK(15, 0)
77 #define HPRE_QM_VFG_AX_MASK GENMASK(7, 0)
78 #define HPRE_BD_USR_MASK GENMASK(1, 0)
79 #define HPRE_PREFETCH_CFG 0x301130
80 #define HPRE_SVA_PREFTCH_DFX 0x30115C
81 #define HPRE_PREFETCH_ENABLE (~(BIT(0) | BIT(30)))
82 #define HPRE_PREFETCH_DISABLE BIT(30)
83 #define HPRE_SVA_DISABLE_READY (BIT(4) | BIT(8))
84
85 /* clock gate */
86 #define HPRE_CLKGATE_CTL 0x301a10
87 #define HPRE_PEH_CFG_AUTO_GATE 0x301a2c
88 #define HPRE_CLUSTER_DYN_CTL 0x302010
89 #define HPRE_CORE_SHB_CFG 0x302088
90 #define HPRE_CLKGATE_CTL_EN BIT(0)
91 #define HPRE_PEH_CFG_AUTO_GATE_EN BIT(0)
92 #define HPRE_CLUSTER_DYN_CTL_EN BIT(0)
93 #define HPRE_CORE_GATE_EN (BIT(30) | BIT(31))
94
95 #define HPRE_AM_OOO_SHUTDOWN_ENB 0x301044
96 #define HPRE_AM_OOO_SHUTDOWN_ENABLE BIT(0)
97 #define HPRE_WR_MSI_PORT BIT(2)
98
99 #define HPRE_CORE_ECC_2BIT_ERR BIT(1)
100 #define HPRE_OOO_ECC_2BIT_ERR BIT(5)
101
102 #define HPRE_QM_BME_FLR BIT(7)
103 #define HPRE_QM_PM_FLR BIT(11)
104 #define HPRE_QM_SRIOV_FLR BIT(12)
105
106 #define HPRE_SHAPER_TYPE_RATE 640
107 #define HPRE_VIA_MSI_DSM 1
108 #define HPRE_SQE_MASK_OFFSET 8
109 #define HPRE_SQE_MASK_LEN 24
110
111 #define HPRE_DFX_BASE 0x301000
112 #define HPRE_DFX_COMMON1 0x301400
113 #define HPRE_DFX_COMMON2 0x301A00
114 #define HPRE_DFX_CORE 0x302000
115 #define HPRE_DFX_BASE_LEN 0x55
116 #define HPRE_DFX_COMMON1_LEN 0x41
117 #define HPRE_DFX_COMMON2_LEN 0xE
118 #define HPRE_DFX_CORE_LEN 0x43
119
120 #define HPRE_DEV_ALG_MAX_LEN 256
121
122 static const char hpre_name[] = "hisi_hpre";
123 static struct dentry *hpre_debugfs_root;
124 static const struct pci_device_id hpre_dev_ids[] = {
125 { PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, PCI_DEVICE_ID_HUAWEI_HPRE_PF) },
126 { PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, PCI_DEVICE_ID_HUAWEI_HPRE_VF) },
127 { 0, }
128 };
129
130 MODULE_DEVICE_TABLE(pci, hpre_dev_ids);
131
132 struct hpre_hw_error {
133 u32 int_msk;
134 const char *msg;
135 };
136
137 struct hpre_dev_alg {
138 u32 alg_msk;
139 const char *alg;
140 };
141
142 static const struct hpre_dev_alg hpre_dev_algs[] = {
143 {
144 .alg_msk = BIT(0),
145 .alg = "rsa\n"
146 }, {
147 .alg_msk = BIT(1),
148 .alg = "dh\n"
149 }, {
150 .alg_msk = BIT(2),
151 .alg = "ecdh\n"
152 }, {
153 .alg_msk = BIT(3),
154 .alg = "ecdsa\n"
155 }, {
156 .alg_msk = BIT(4),
157 .alg = "sm2\n"
158 }, {
159 .alg_msk = BIT(5),
160 .alg = "x25519\n"
161 }, {
162 .alg_msk = BIT(6),
163 .alg = "x448\n"
164 }, {
165 /* sentinel */
166 }
167 };
168
169 static struct hisi_qm_list hpre_devices = {
170 .register_to_crypto = hpre_algs_register,
171 .unregister_from_crypto = hpre_algs_unregister,
172 };
173
174 static const char * const hpre_debug_file_name[] = {
175 [HPRE_CLEAR_ENABLE] = "rdclr_en",
176 [HPRE_CLUSTER_CTRL] = "cluster_ctrl",
177 };
178
179 enum hpre_cap_type {
180 HPRE_QM_NFE_MASK_CAP,
181 HPRE_QM_RESET_MASK_CAP,
182 HPRE_QM_OOO_SHUTDOWN_MASK_CAP,
183 HPRE_QM_CE_MASK_CAP,
184 HPRE_NFE_MASK_CAP,
185 HPRE_RESET_MASK_CAP,
186 HPRE_OOO_SHUTDOWN_MASK_CAP,
187 HPRE_CE_MASK_CAP,
188 HPRE_CLUSTER_NUM_CAP,
189 HPRE_CORE_TYPE_NUM_CAP,
190 HPRE_CORE_NUM_CAP,
191 HPRE_CLUSTER_CORE_NUM_CAP,
192 HPRE_CORE_ENABLE_BITMAP_CAP,
193 HPRE_DRV_ALG_BITMAP_CAP,
194 HPRE_DEV_ALG_BITMAP_CAP,
195 HPRE_CORE1_ALG_BITMAP_CAP,
196 HPRE_CORE2_ALG_BITMAP_CAP,
197 HPRE_CORE3_ALG_BITMAP_CAP,
198 HPRE_CORE4_ALG_BITMAP_CAP,
199 HPRE_CORE5_ALG_BITMAP_CAP,
200 HPRE_CORE6_ALG_BITMAP_CAP,
201 HPRE_CORE7_ALG_BITMAP_CAP,
202 HPRE_CORE8_ALG_BITMAP_CAP,
203 HPRE_CORE9_ALG_BITMAP_CAP,
204 HPRE_CORE10_ALG_BITMAP_CAP
205 };
206
207 static const struct hisi_qm_cap_info hpre_basic_info[] = {
208 {HPRE_QM_NFE_MASK_CAP, 0x3124, 0, GENMASK(31, 0), 0x0, 0x1C37, 0x7C37},
209 {HPRE_QM_RESET_MASK_CAP, 0x3128, 0, GENMASK(31, 0), 0x0, 0xC37, 0x6C37},
210 {HPRE_QM_OOO_SHUTDOWN_MASK_CAP, 0x3128, 0, GENMASK(31, 0), 0x0, 0x4, 0x6C37},
211 {HPRE_QM_CE_MASK_CAP, 0x312C, 0, GENMASK(31, 0), 0x0, 0x8, 0x8},
212 {HPRE_NFE_MASK_CAP, 0x3130, 0, GENMASK(31, 0), 0x0, 0x3FFFFE, 0x1FFFFFE},
213 {HPRE_RESET_MASK_CAP, 0x3134, 0, GENMASK(31, 0), 0x0, 0x3FFFFE, 0xBFFFFE},
214 {HPRE_OOO_SHUTDOWN_MASK_CAP, 0x3134, 0, GENMASK(31, 0), 0x0, 0x22, 0xBFFFFE},
215 {HPRE_CE_MASK_CAP, 0x3138, 0, GENMASK(31, 0), 0x0, 0x1, 0x1},
216 {HPRE_CLUSTER_NUM_CAP, 0x313c, 20, GENMASK(3, 0), 0x0, 0x4, 0x1},
217 {HPRE_CORE_TYPE_NUM_CAP, 0x313c, 16, GENMASK(3, 0), 0x0, 0x2, 0x2},
218 {HPRE_CORE_NUM_CAP, 0x313c, 8, GENMASK(7, 0), 0x0, 0x8, 0xA},
219 {HPRE_CLUSTER_CORE_NUM_CAP, 0x313c, 0, GENMASK(7, 0), 0x0, 0x2, 0xA},
220 {HPRE_CORE_ENABLE_BITMAP_CAP, 0x3140, 0, GENMASK(31, 0), 0x0, 0xF, 0x3FF},
221 {HPRE_DRV_ALG_BITMAP_CAP, 0x3144, 0, GENMASK(31, 0), 0x0, 0x03, 0x27},
222 {HPRE_DEV_ALG_BITMAP_CAP, 0x3148, 0, GENMASK(31, 0), 0x0, 0x03, 0x7F},
223 {HPRE_CORE1_ALG_BITMAP_CAP, 0x314c, 0, GENMASK(31, 0), 0x0, 0x7F, 0x7F},
224 {HPRE_CORE2_ALG_BITMAP_CAP, 0x3150, 0, GENMASK(31, 0), 0x0, 0x7F, 0x7F},
225 {HPRE_CORE3_ALG_BITMAP_CAP, 0x3154, 0, GENMASK(31, 0), 0x0, 0x7F, 0x7F},
226 {HPRE_CORE4_ALG_BITMAP_CAP, 0x3158, 0, GENMASK(31, 0), 0x0, 0x7F, 0x7F},
227 {HPRE_CORE5_ALG_BITMAP_CAP, 0x315c, 0, GENMASK(31, 0), 0x0, 0x7F, 0x7F},
228 {HPRE_CORE6_ALG_BITMAP_CAP, 0x3160, 0, GENMASK(31, 0), 0x0, 0x7F, 0x7F},
229 {HPRE_CORE7_ALG_BITMAP_CAP, 0x3164, 0, GENMASK(31, 0), 0x0, 0x7F, 0x7F},
230 {HPRE_CORE8_ALG_BITMAP_CAP, 0x3168, 0, GENMASK(31, 0), 0x0, 0x7F, 0x7F},
231 {HPRE_CORE9_ALG_BITMAP_CAP, 0x316c, 0, GENMASK(31, 0), 0x0, 0x10, 0x10},
232 {HPRE_CORE10_ALG_BITMAP_CAP, 0x3170, 0, GENMASK(31, 0), 0x0, 0x10, 0x10}
233 };
234
235 static const struct hpre_hw_error hpre_hw_errors[] = {
236 {
237 .int_msk = BIT(0),
238 .msg = "core_ecc_1bit_err_int_set"
239 }, {
240 .int_msk = BIT(1),
241 .msg = "core_ecc_2bit_err_int_set"
242 }, {
243 .int_msk = BIT(2),
244 .msg = "dat_wb_poison_int_set"
245 }, {
246 .int_msk = BIT(3),
247 .msg = "dat_rd_poison_int_set"
248 }, {
249 .int_msk = BIT(4),
250 .msg = "bd_rd_poison_int_set"
251 }, {
252 .int_msk = BIT(5),
253 .msg = "ooo_ecc_2bit_err_int_set"
254 }, {
255 .int_msk = BIT(6),
256 .msg = "cluster1_shb_timeout_int_set"
257 }, {
258 .int_msk = BIT(7),
259 .msg = "cluster2_shb_timeout_int_set"
260 }, {
261 .int_msk = BIT(8),
262 .msg = "cluster3_shb_timeout_int_set"
263 }, {
264 .int_msk = BIT(9),
265 .msg = "cluster4_shb_timeout_int_set"
266 }, {
267 .int_msk = GENMASK(15, 10),
268 .msg = "ooo_rdrsp_err_int_set"
269 }, {
270 .int_msk = GENMASK(21, 16),
271 .msg = "ooo_wrrsp_err_int_set"
272 }, {
273 .int_msk = BIT(22),
274 .msg = "pt_rng_timeout_int_set"
275 }, {
276 .int_msk = BIT(23),
277 .msg = "sva_fsm_timeout_int_set"
278 }, {
279 .int_msk = BIT(24),
280 .msg = "sva_int_set"
281 }, {
282 /* sentinel */
283 }
284 };
285
286 static const u64 hpre_cluster_offsets[] = {
287 [HPRE_CLUSTER0] =
288 HPRE_CLSTR_BASE + HPRE_CLUSTER0 * HPRE_CLSTR_ADDR_INTRVL,
289 [HPRE_CLUSTER1] =
290 HPRE_CLSTR_BASE + HPRE_CLUSTER1 * HPRE_CLSTR_ADDR_INTRVL,
291 [HPRE_CLUSTER2] =
292 HPRE_CLSTR_BASE + HPRE_CLUSTER2 * HPRE_CLSTR_ADDR_INTRVL,
293 [HPRE_CLUSTER3] =
294 HPRE_CLSTR_BASE + HPRE_CLUSTER3 * HPRE_CLSTR_ADDR_INTRVL,
295 };
296
297 static const struct debugfs_reg32 hpre_cluster_dfx_regs[] = {
298 {"CORES_EN_STATUS ", HPRE_CORE_EN_OFFSET},
299 {"CORES_INI_CFG ", HPRE_CORE_INI_CFG_OFFSET},
300 {"CORES_INI_STATUS ", HPRE_CORE_INI_STATUS_OFFSET},
301 {"CORES_HTBT_WARN ", HPRE_CORE_HTBT_WARN_OFFSET},
302 {"CORES_IS_SCHD ", HPRE_CORE_IS_SCHD_OFFSET},
303 };
304
305 static const struct debugfs_reg32 hpre_com_dfx_regs[] = {
306 {"READ_CLR_EN ", HPRE_CTRL_CNT_CLR_CE},
307 {"AXQOS ", HPRE_VFG_AXQOS},
308 {"AWUSR_CFG ", HPRE_AWUSR_FP_CFG},
309 {"BD_ENDIAN ", HPRE_BD_ENDIAN},
310 {"ECC_CHECK_CTRL ", HPRE_ECC_BYPASS},
311 {"RAS_INT_WIDTH ", HPRE_RAS_WIDTH_CFG},
312 {"POISON_BYPASS ", HPRE_POISON_BYPASS},
313 {"BD_ARUSER ", HPRE_BD_ARUSR_CFG},
314 {"BD_AWUSER ", HPRE_BD_AWUSR_CFG},
315 {"DATA_ARUSER ", HPRE_DATA_RUSER_CFG},
316 {"DATA_AWUSER ", HPRE_DATA_WUSER_CFG},
317 {"INT_STATUS ", HPRE_INT_STATUS},
318 {"INT_MASK ", HPRE_HAC_INT_MSK},
319 {"RAS_CE_ENB ", HPRE_HAC_RAS_CE_ENB},
320 {"RAS_NFE_ENB ", HPRE_HAC_RAS_NFE_ENB},
321 {"RAS_FE_ENB ", HPRE_HAC_RAS_FE_ENB},
322 {"INT_SET ", HPRE_HAC_INT_SET},
323 {"RNG_TIMEOUT_NUM ", HPRE_RNG_TIMEOUT_NUM},
324 };
325
326 static const char *hpre_dfx_files[HPRE_DFX_FILE_NUM] = {
327 "send_cnt",
328 "recv_cnt",
329 "send_fail_cnt",
330 "send_busy_cnt",
331 "over_thrhld_cnt",
332 "overtime_thrhld",
333 "invalid_req_cnt"
334 };
335
336 /* define the HPRE's dfx regs region and region length */
337 static struct dfx_diff_registers hpre_diff_regs[] = {
338 {
339 .reg_offset = HPRE_DFX_BASE,
340 .reg_len = HPRE_DFX_BASE_LEN,
341 }, {
342 .reg_offset = HPRE_DFX_COMMON1,
343 .reg_len = HPRE_DFX_COMMON1_LEN,
344 }, {
345 .reg_offset = HPRE_DFX_COMMON2,
346 .reg_len = HPRE_DFX_COMMON2_LEN,
347 }, {
348 .reg_offset = HPRE_DFX_CORE,
349 .reg_len = HPRE_DFX_CORE_LEN,
350 },
351 };
352
hpre_check_alg_support(struct hisi_qm * qm,u32 alg)353 bool hpre_check_alg_support(struct hisi_qm *qm, u32 alg)
354 {
355 u32 cap_val;
356
357 cap_val = hisi_qm_get_hw_info(qm, hpre_basic_info, HPRE_DRV_ALG_BITMAP_CAP, qm->cap_ver);
358 if (alg & cap_val)
359 return true;
360
361 return false;
362 }
363
hpre_set_qm_algs(struct hisi_qm * qm)364 static int hpre_set_qm_algs(struct hisi_qm *qm)
365 {
366 struct device *dev = &qm->pdev->dev;
367 char *algs, *ptr;
368 u32 alg_msk;
369 int i;
370
371 if (!qm->use_sva)
372 return 0;
373
374 algs = devm_kzalloc(dev, HPRE_DEV_ALG_MAX_LEN * sizeof(char), GFP_KERNEL);
375 if (!algs)
376 return -ENOMEM;
377
378 alg_msk = hisi_qm_get_hw_info(qm, hpre_basic_info, HPRE_DEV_ALG_BITMAP_CAP, qm->cap_ver);
379
380 for (i = 0; i < ARRAY_SIZE(hpre_dev_algs); i++)
381 if (alg_msk & hpre_dev_algs[i].alg_msk)
382 strcat(algs, hpre_dev_algs[i].alg);
383
384 ptr = strrchr(algs, '\n');
385 if (ptr)
386 *ptr = '\0';
387
388 qm->uacce->algs = algs;
389
390 return 0;
391 }
392
hpre_diff_regs_show(struct seq_file * s,void * unused)393 static int hpre_diff_regs_show(struct seq_file *s, void *unused)
394 {
395 struct hisi_qm *qm = s->private;
396
397 hisi_qm_acc_diff_regs_dump(qm, s, qm->debug.acc_diff_regs,
398 ARRAY_SIZE(hpre_diff_regs));
399
400 return 0;
401 }
402
403 DEFINE_SHOW_ATTRIBUTE(hpre_diff_regs);
404
hpre_com_regs_show(struct seq_file * s,void * unused)405 static int hpre_com_regs_show(struct seq_file *s, void *unused)
406 {
407 hisi_qm_regs_dump(s, s->private);
408
409 return 0;
410 }
411
412 DEFINE_SHOW_ATTRIBUTE(hpre_com_regs);
413
hpre_cluster_regs_show(struct seq_file * s,void * unused)414 static int hpre_cluster_regs_show(struct seq_file *s, void *unused)
415 {
416 hisi_qm_regs_dump(s, s->private);
417
418 return 0;
419 }
420
421 DEFINE_SHOW_ATTRIBUTE(hpre_cluster_regs);
422
423 static const struct kernel_param_ops hpre_uacce_mode_ops = {
424 .set = uacce_mode_set,
425 .get = param_get_int,
426 };
427
428 /*
429 * uacce_mode = 0 means hpre only register to crypto,
430 * uacce_mode = 1 means hpre both register to crypto and uacce.
431 */
432 static u32 uacce_mode = UACCE_MODE_NOUACCE;
433 module_param_cb(uacce_mode, &hpre_uacce_mode_ops, &uacce_mode, 0444);
434 MODULE_PARM_DESC(uacce_mode, UACCE_MODE_DESC);
435
pf_q_num_set(const char * val,const struct kernel_param * kp)436 static int pf_q_num_set(const char *val, const struct kernel_param *kp)
437 {
438 return q_num_set(val, kp, PCI_DEVICE_ID_HUAWEI_HPRE_PF);
439 }
440
441 static const struct kernel_param_ops hpre_pf_q_num_ops = {
442 .set = pf_q_num_set,
443 .get = param_get_int,
444 };
445
446 static u32 pf_q_num = HPRE_PF_DEF_Q_NUM;
447 module_param_cb(pf_q_num, &hpre_pf_q_num_ops, &pf_q_num, 0444);
448 MODULE_PARM_DESC(pf_q_num, "Number of queues in PF of CS(2-1024)");
449
450 static const struct kernel_param_ops vfs_num_ops = {
451 .set = vfs_num_set,
452 .get = param_get_int,
453 };
454
455 static u32 vfs_num;
456 module_param_cb(vfs_num, &vfs_num_ops, &vfs_num, 0444);
457 MODULE_PARM_DESC(vfs_num, "Number of VFs to enable(1-63), 0(default)");
458
hpre_cluster_num(struct hisi_qm * qm)459 static inline int hpre_cluster_num(struct hisi_qm *qm)
460 {
461 return hisi_qm_get_hw_info(qm, hpre_basic_info, HPRE_CLUSTER_NUM_CAP, qm->cap_ver);
462 }
463
hpre_cluster_core_mask(struct hisi_qm * qm)464 static inline int hpre_cluster_core_mask(struct hisi_qm *qm)
465 {
466 return hisi_qm_get_hw_info(qm, hpre_basic_info, HPRE_CORE_ENABLE_BITMAP_CAP, qm->cap_ver);
467 }
468
hpre_create_qp(u8 type)469 struct hisi_qp *hpre_create_qp(u8 type)
470 {
471 int node = cpu_to_node(smp_processor_id());
472 struct hisi_qp *qp = NULL;
473 int ret;
474
475 if (type != HPRE_V2_ALG_TYPE && type != HPRE_V3_ECC_ALG_TYPE)
476 return NULL;
477
478 /*
479 * type: 0 - RSA/DH. algorithm supported in V2,
480 * 1 - ECC algorithm in V3.
481 */
482 ret = hisi_qm_alloc_qps_node(&hpre_devices, 1, type, node, &qp);
483 if (!ret)
484 return qp;
485
486 return NULL;
487 }
488
hpre_config_pasid(struct hisi_qm * qm)489 static void hpre_config_pasid(struct hisi_qm *qm)
490 {
491 u32 val1, val2;
492
493 if (qm->ver >= QM_HW_V3)
494 return;
495
496 val1 = readl_relaxed(qm->io_base + HPRE_DATA_RUSER_CFG);
497 val2 = readl_relaxed(qm->io_base + HPRE_DATA_WUSER_CFG);
498 if (qm->use_sva) {
499 val1 |= BIT(HPRE_PASID_EN_BIT);
500 val2 |= BIT(HPRE_PASID_EN_BIT);
501 } else {
502 val1 &= ~BIT(HPRE_PASID_EN_BIT);
503 val2 &= ~BIT(HPRE_PASID_EN_BIT);
504 }
505 writel_relaxed(val1, qm->io_base + HPRE_DATA_RUSER_CFG);
506 writel_relaxed(val2, qm->io_base + HPRE_DATA_WUSER_CFG);
507 }
508
hpre_cfg_by_dsm(struct hisi_qm * qm)509 static int hpre_cfg_by_dsm(struct hisi_qm *qm)
510 {
511 struct device *dev = &qm->pdev->dev;
512 union acpi_object *obj;
513 guid_t guid;
514
515 if (guid_parse("b06b81ab-0134-4a45-9b0c-483447b95fa7", &guid)) {
516 dev_err(dev, "Hpre GUID failed\n");
517 return -EINVAL;
518 }
519
520 /* Switch over to MSI handling due to non-standard PCI implementation */
521 obj = acpi_evaluate_dsm(ACPI_HANDLE(dev), &guid,
522 0, HPRE_VIA_MSI_DSM, NULL);
523 if (!obj) {
524 dev_err(dev, "ACPI handle failed!\n");
525 return -EIO;
526 }
527
528 ACPI_FREE(obj);
529
530 return 0;
531 }
532
hpre_set_cluster(struct hisi_qm * qm)533 static int hpre_set_cluster(struct hisi_qm *qm)
534 {
535 u32 cluster_core_mask = hpre_cluster_core_mask(qm);
536 u8 clusters_num = hpre_cluster_num(qm);
537 struct device *dev = &qm->pdev->dev;
538 unsigned long offset;
539 u32 val = 0;
540 int ret, i;
541
542 for (i = 0; i < clusters_num; i++) {
543 offset = i * HPRE_CLSTR_ADDR_INTRVL;
544
545 /* clusters initiating */
546 writel(cluster_core_mask,
547 qm->io_base + offset + HPRE_CORE_ENB);
548 writel(0x1, qm->io_base + offset + HPRE_CORE_INI_CFG);
549 ret = readl_relaxed_poll_timeout(qm->io_base + offset +
550 HPRE_CORE_INI_STATUS, val,
551 ((val & cluster_core_mask) ==
552 cluster_core_mask),
553 HPRE_REG_RD_INTVRL_US,
554 HPRE_REG_RD_TMOUT_US);
555 if (ret) {
556 dev_err(dev,
557 "cluster %d int st status timeout!\n", i);
558 return -ETIMEDOUT;
559 }
560 }
561
562 return 0;
563 }
564
565 /*
566 * For Kunpeng 920, we should disable FLR triggered by hardware (BME/PM/SRIOV).
567 * Or it may stay in D3 state when we bind and unbind hpre quickly,
568 * as it does FLR triggered by hardware.
569 */
disable_flr_of_bme(struct hisi_qm * qm)570 static void disable_flr_of_bme(struct hisi_qm *qm)
571 {
572 u32 val;
573
574 val = readl(qm->io_base + QM_PEH_AXUSER_CFG);
575 val &= ~(HPRE_QM_BME_FLR | HPRE_QM_SRIOV_FLR);
576 val |= HPRE_QM_PM_FLR;
577 writel(val, qm->io_base + QM_PEH_AXUSER_CFG);
578 writel(PEH_AXUSER_CFG_ENABLE, qm->io_base + QM_PEH_AXUSER_CFG_ENABLE);
579 }
580
hpre_open_sva_prefetch(struct hisi_qm * qm)581 static void hpre_open_sva_prefetch(struct hisi_qm *qm)
582 {
583 u32 val;
584 int ret;
585
586 if (!test_bit(QM_SUPPORT_SVA_PREFETCH, &qm->caps))
587 return;
588
589 /* Enable prefetch */
590 val = readl_relaxed(qm->io_base + HPRE_PREFETCH_CFG);
591 val &= HPRE_PREFETCH_ENABLE;
592 writel(val, qm->io_base + HPRE_PREFETCH_CFG);
593
594 ret = readl_relaxed_poll_timeout(qm->io_base + HPRE_PREFETCH_CFG,
595 val, !(val & HPRE_PREFETCH_DISABLE),
596 HPRE_REG_RD_INTVRL_US,
597 HPRE_REG_RD_TMOUT_US);
598 if (ret)
599 pci_err(qm->pdev, "failed to open sva prefetch\n");
600 }
601
hpre_close_sva_prefetch(struct hisi_qm * qm)602 static void hpre_close_sva_prefetch(struct hisi_qm *qm)
603 {
604 u32 val;
605 int ret;
606
607 if (!test_bit(QM_SUPPORT_SVA_PREFETCH, &qm->caps))
608 return;
609
610 val = readl_relaxed(qm->io_base + HPRE_PREFETCH_CFG);
611 val |= HPRE_PREFETCH_DISABLE;
612 writel(val, qm->io_base + HPRE_PREFETCH_CFG);
613
614 ret = readl_relaxed_poll_timeout(qm->io_base + HPRE_SVA_PREFTCH_DFX,
615 val, !(val & HPRE_SVA_DISABLE_READY),
616 HPRE_REG_RD_INTVRL_US,
617 HPRE_REG_RD_TMOUT_US);
618 if (ret)
619 pci_err(qm->pdev, "failed to close sva prefetch\n");
620 }
621
hpre_enable_clock_gate(struct hisi_qm * qm)622 static void hpre_enable_clock_gate(struct hisi_qm *qm)
623 {
624 u32 val;
625
626 if (qm->ver < QM_HW_V3)
627 return;
628
629 val = readl(qm->io_base + HPRE_CLKGATE_CTL);
630 val |= HPRE_CLKGATE_CTL_EN;
631 writel(val, qm->io_base + HPRE_CLKGATE_CTL);
632
633 val = readl(qm->io_base + HPRE_PEH_CFG_AUTO_GATE);
634 val |= HPRE_PEH_CFG_AUTO_GATE_EN;
635 writel(val, qm->io_base + HPRE_PEH_CFG_AUTO_GATE);
636
637 val = readl(qm->io_base + HPRE_CLUSTER_DYN_CTL);
638 val |= HPRE_CLUSTER_DYN_CTL_EN;
639 writel(val, qm->io_base + HPRE_CLUSTER_DYN_CTL);
640
641 val = readl_relaxed(qm->io_base + HPRE_CORE_SHB_CFG);
642 val |= HPRE_CORE_GATE_EN;
643 writel(val, qm->io_base + HPRE_CORE_SHB_CFG);
644 }
645
hpre_disable_clock_gate(struct hisi_qm * qm)646 static void hpre_disable_clock_gate(struct hisi_qm *qm)
647 {
648 u32 val;
649
650 if (qm->ver < QM_HW_V3)
651 return;
652
653 val = readl(qm->io_base + HPRE_CLKGATE_CTL);
654 val &= ~HPRE_CLKGATE_CTL_EN;
655 writel(val, qm->io_base + HPRE_CLKGATE_CTL);
656
657 val = readl(qm->io_base + HPRE_PEH_CFG_AUTO_GATE);
658 val &= ~HPRE_PEH_CFG_AUTO_GATE_EN;
659 writel(val, qm->io_base + HPRE_PEH_CFG_AUTO_GATE);
660
661 val = readl(qm->io_base + HPRE_CLUSTER_DYN_CTL);
662 val &= ~HPRE_CLUSTER_DYN_CTL_EN;
663 writel(val, qm->io_base + HPRE_CLUSTER_DYN_CTL);
664
665 val = readl_relaxed(qm->io_base + HPRE_CORE_SHB_CFG);
666 val &= ~HPRE_CORE_GATE_EN;
667 writel(val, qm->io_base + HPRE_CORE_SHB_CFG);
668 }
669
hpre_set_user_domain_and_cache(struct hisi_qm * qm)670 static int hpre_set_user_domain_and_cache(struct hisi_qm *qm)
671 {
672 struct device *dev = &qm->pdev->dev;
673 u32 val;
674 int ret;
675
676 /* disabel dynamic clock gate before sram init */
677 hpre_disable_clock_gate(qm);
678
679 writel(HPRE_QM_USR_CFG_MASK, qm->io_base + QM_ARUSER_M_CFG_ENABLE);
680 writel(HPRE_QM_USR_CFG_MASK, qm->io_base + QM_AWUSER_M_CFG_ENABLE);
681 writel_relaxed(HPRE_QM_AXI_CFG_MASK, qm->io_base + QM_AXI_M_CFG);
682
683 /* HPRE need more time, we close this interrupt */
684 val = readl_relaxed(qm->io_base + HPRE_QM_ABNML_INT_MASK);
685 val |= BIT(HPRE_TIMEOUT_ABNML_BIT);
686 writel_relaxed(val, qm->io_base + HPRE_QM_ABNML_INT_MASK);
687
688 if (qm->ver >= QM_HW_V3)
689 writel(HPRE_RSA_ENB | HPRE_ECC_ENB,
690 qm->io_base + HPRE_TYPES_ENB);
691 else
692 writel(HPRE_RSA_ENB, qm->io_base + HPRE_TYPES_ENB);
693
694 writel(HPRE_QM_VFG_AX_MASK, qm->io_base + HPRE_VFG_AXCACHE);
695 writel(0x0, qm->io_base + HPRE_BD_ENDIAN);
696 writel(0x0, qm->io_base + HPRE_INT_MASK);
697 writel(0x0, qm->io_base + HPRE_POISON_BYPASS);
698 writel(0x0, qm->io_base + HPRE_COMM_CNT_CLR_CE);
699 writel(0x0, qm->io_base + HPRE_ECC_BYPASS);
700
701 writel(HPRE_BD_USR_MASK, qm->io_base + HPRE_BD_ARUSR_CFG);
702 writel(HPRE_BD_USR_MASK, qm->io_base + HPRE_BD_AWUSR_CFG);
703 writel(0x1, qm->io_base + HPRE_RDCHN_INI_CFG);
704 ret = readl_relaxed_poll_timeout(qm->io_base + HPRE_RDCHN_INI_ST, val,
705 val & BIT(0),
706 HPRE_REG_RD_INTVRL_US,
707 HPRE_REG_RD_TMOUT_US);
708 if (ret) {
709 dev_err(dev, "read rd channel timeout fail!\n");
710 return -ETIMEDOUT;
711 }
712
713 ret = hpre_set_cluster(qm);
714 if (ret)
715 return -ETIMEDOUT;
716
717 /* This setting is only needed by Kunpeng 920. */
718 if (qm->ver == QM_HW_V2) {
719 ret = hpre_cfg_by_dsm(qm);
720 if (ret)
721 return ret;
722
723 disable_flr_of_bme(qm);
724 }
725
726 /* Config data buffer pasid needed by Kunpeng 920 */
727 hpre_config_pasid(qm);
728
729 hpre_enable_clock_gate(qm);
730
731 return ret;
732 }
733
hpre_cnt_regs_clear(struct hisi_qm * qm)734 static void hpre_cnt_regs_clear(struct hisi_qm *qm)
735 {
736 u8 clusters_num = hpre_cluster_num(qm);
737 unsigned long offset;
738 int i;
739
740 /* clear clusterX/cluster_ctrl */
741 for (i = 0; i < clusters_num; i++) {
742 offset = HPRE_CLSTR_BASE + i * HPRE_CLSTR_ADDR_INTRVL;
743 writel(0x0, qm->io_base + offset + HPRE_CLUSTER_INQURY);
744 }
745
746 /* clear rdclr_en */
747 writel(0x0, qm->io_base + HPRE_CTRL_CNT_CLR_CE);
748
749 hisi_qm_debug_regs_clear(qm);
750 }
751
hpre_master_ooo_ctrl(struct hisi_qm * qm,bool enable)752 static void hpre_master_ooo_ctrl(struct hisi_qm *qm, bool enable)
753 {
754 u32 val1, val2;
755
756 val1 = readl(qm->io_base + HPRE_AM_OOO_SHUTDOWN_ENB);
757 if (enable) {
758 val1 |= HPRE_AM_OOO_SHUTDOWN_ENABLE;
759 val2 = hisi_qm_get_hw_info(qm, hpre_basic_info,
760 HPRE_OOO_SHUTDOWN_MASK_CAP, qm->cap_ver);
761 } else {
762 val1 &= ~HPRE_AM_OOO_SHUTDOWN_ENABLE;
763 val2 = 0x0;
764 }
765
766 if (qm->ver > QM_HW_V2)
767 writel(val2, qm->io_base + HPRE_OOO_SHUTDOWN_SEL);
768
769 writel(val1, qm->io_base + HPRE_AM_OOO_SHUTDOWN_ENB);
770 }
771
hpre_hw_error_disable(struct hisi_qm * qm)772 static void hpre_hw_error_disable(struct hisi_qm *qm)
773 {
774 u32 ce, nfe;
775
776 ce = hisi_qm_get_hw_info(qm, hpre_basic_info, HPRE_CE_MASK_CAP, qm->cap_ver);
777 nfe = hisi_qm_get_hw_info(qm, hpre_basic_info, HPRE_NFE_MASK_CAP, qm->cap_ver);
778
779 /* disable hpre hw error interrupts */
780 writel(ce | nfe | HPRE_HAC_RAS_FE_ENABLE, qm->io_base + HPRE_INT_MASK);
781 /* disable HPRE block master OOO when nfe occurs on Kunpeng930 */
782 hpre_master_ooo_ctrl(qm, false);
783 }
784
hpre_hw_error_enable(struct hisi_qm * qm)785 static void hpre_hw_error_enable(struct hisi_qm *qm)
786 {
787 u32 ce, nfe;
788
789 ce = hisi_qm_get_hw_info(qm, hpre_basic_info, HPRE_CE_MASK_CAP, qm->cap_ver);
790 nfe = hisi_qm_get_hw_info(qm, hpre_basic_info, HPRE_NFE_MASK_CAP, qm->cap_ver);
791
792 /* clear HPRE hw error source if having */
793 writel(ce | nfe | HPRE_HAC_RAS_FE_ENABLE, qm->io_base + HPRE_HAC_SOURCE_INT);
794
795 /* configure error type */
796 writel(ce, qm->io_base + HPRE_RAS_CE_ENB);
797 writel(nfe, qm->io_base + HPRE_RAS_NFE_ENB);
798 writel(HPRE_HAC_RAS_FE_ENABLE, qm->io_base + HPRE_RAS_FE_ENB);
799
800 /* enable HPRE block master OOO when nfe occurs on Kunpeng930 */
801 hpre_master_ooo_ctrl(qm, true);
802
803 /* enable hpre hw error interrupts */
804 writel(HPRE_CORE_INT_ENABLE, qm->io_base + HPRE_INT_MASK);
805 }
806
hpre_file_to_qm(struct hpre_debugfs_file * file)807 static inline struct hisi_qm *hpre_file_to_qm(struct hpre_debugfs_file *file)
808 {
809 struct hpre *hpre = container_of(file->debug, struct hpre, debug);
810
811 return &hpre->qm;
812 }
813
hpre_clear_enable_read(struct hpre_debugfs_file * file)814 static u32 hpre_clear_enable_read(struct hpre_debugfs_file *file)
815 {
816 struct hisi_qm *qm = hpre_file_to_qm(file);
817
818 return readl(qm->io_base + HPRE_CTRL_CNT_CLR_CE) &
819 HPRE_CTRL_CNT_CLR_CE_BIT;
820 }
821
hpre_clear_enable_write(struct hpre_debugfs_file * file,u32 val)822 static int hpre_clear_enable_write(struct hpre_debugfs_file *file, u32 val)
823 {
824 struct hisi_qm *qm = hpre_file_to_qm(file);
825 u32 tmp;
826
827 if (val != 1 && val != 0)
828 return -EINVAL;
829
830 tmp = (readl(qm->io_base + HPRE_CTRL_CNT_CLR_CE) &
831 ~HPRE_CTRL_CNT_CLR_CE_BIT) | val;
832 writel(tmp, qm->io_base + HPRE_CTRL_CNT_CLR_CE);
833
834 return 0;
835 }
836
hpre_cluster_inqry_read(struct hpre_debugfs_file * file)837 static u32 hpre_cluster_inqry_read(struct hpre_debugfs_file *file)
838 {
839 struct hisi_qm *qm = hpre_file_to_qm(file);
840 int cluster_index = file->index - HPRE_CLUSTER_CTRL;
841 unsigned long offset = HPRE_CLSTR_BASE +
842 cluster_index * HPRE_CLSTR_ADDR_INTRVL;
843
844 return readl(qm->io_base + offset + HPRE_CLSTR_ADDR_INQRY_RSLT);
845 }
846
hpre_cluster_inqry_write(struct hpre_debugfs_file * file,u32 val)847 static void hpre_cluster_inqry_write(struct hpre_debugfs_file *file, u32 val)
848 {
849 struct hisi_qm *qm = hpre_file_to_qm(file);
850 int cluster_index = file->index - HPRE_CLUSTER_CTRL;
851 unsigned long offset = HPRE_CLSTR_BASE + cluster_index *
852 HPRE_CLSTR_ADDR_INTRVL;
853
854 writel(val, qm->io_base + offset + HPRE_CLUSTER_INQURY);
855 }
856
hpre_ctrl_debug_read(struct file * filp,char __user * buf,size_t count,loff_t * pos)857 static ssize_t hpre_ctrl_debug_read(struct file *filp, char __user *buf,
858 size_t count, loff_t *pos)
859 {
860 struct hpre_debugfs_file *file = filp->private_data;
861 struct hisi_qm *qm = hpre_file_to_qm(file);
862 char tbuf[HPRE_DBGFS_VAL_MAX_LEN];
863 u32 val;
864 int ret;
865
866 ret = hisi_qm_get_dfx_access(qm);
867 if (ret)
868 return ret;
869
870 spin_lock_irq(&file->lock);
871 switch (file->type) {
872 case HPRE_CLEAR_ENABLE:
873 val = hpre_clear_enable_read(file);
874 break;
875 case HPRE_CLUSTER_CTRL:
876 val = hpre_cluster_inqry_read(file);
877 break;
878 default:
879 goto err_input;
880 }
881 spin_unlock_irq(&file->lock);
882
883 hisi_qm_put_dfx_access(qm);
884 ret = snprintf(tbuf, HPRE_DBGFS_VAL_MAX_LEN, "%u\n", val);
885 return simple_read_from_buffer(buf, count, pos, tbuf, ret);
886
887 err_input:
888 spin_unlock_irq(&file->lock);
889 hisi_qm_put_dfx_access(qm);
890 return -EINVAL;
891 }
892
hpre_ctrl_debug_write(struct file * filp,const char __user * buf,size_t count,loff_t * pos)893 static ssize_t hpre_ctrl_debug_write(struct file *filp, const char __user *buf,
894 size_t count, loff_t *pos)
895 {
896 struct hpre_debugfs_file *file = filp->private_data;
897 struct hisi_qm *qm = hpre_file_to_qm(file);
898 char tbuf[HPRE_DBGFS_VAL_MAX_LEN];
899 unsigned long val;
900 int len, ret;
901
902 if (*pos != 0)
903 return 0;
904
905 if (count >= HPRE_DBGFS_VAL_MAX_LEN)
906 return -ENOSPC;
907
908 len = simple_write_to_buffer(tbuf, HPRE_DBGFS_VAL_MAX_LEN - 1,
909 pos, buf, count);
910 if (len < 0)
911 return len;
912
913 tbuf[len] = '\0';
914 if (kstrtoul(tbuf, 0, &val))
915 return -EFAULT;
916
917 ret = hisi_qm_get_dfx_access(qm);
918 if (ret)
919 return ret;
920
921 spin_lock_irq(&file->lock);
922 switch (file->type) {
923 case HPRE_CLEAR_ENABLE:
924 ret = hpre_clear_enable_write(file, val);
925 if (ret)
926 goto err_input;
927 break;
928 case HPRE_CLUSTER_CTRL:
929 hpre_cluster_inqry_write(file, val);
930 break;
931 default:
932 ret = -EINVAL;
933 goto err_input;
934 }
935
936 ret = count;
937
938 err_input:
939 spin_unlock_irq(&file->lock);
940 hisi_qm_put_dfx_access(qm);
941 return ret;
942 }
943
944 static const struct file_operations hpre_ctrl_debug_fops = {
945 .owner = THIS_MODULE,
946 .open = simple_open,
947 .read = hpre_ctrl_debug_read,
948 .write = hpre_ctrl_debug_write,
949 };
950
hpre_debugfs_atomic64_get(void * data,u64 * val)951 static int hpre_debugfs_atomic64_get(void *data, u64 *val)
952 {
953 struct hpre_dfx *dfx_item = data;
954
955 *val = atomic64_read(&dfx_item->value);
956
957 return 0;
958 }
959
hpre_debugfs_atomic64_set(void * data,u64 val)960 static int hpre_debugfs_atomic64_set(void *data, u64 val)
961 {
962 struct hpre_dfx *dfx_item = data;
963 struct hpre_dfx *hpre_dfx = NULL;
964
965 if (dfx_item->type == HPRE_OVERTIME_THRHLD) {
966 hpre_dfx = dfx_item - HPRE_OVERTIME_THRHLD;
967 atomic64_set(&hpre_dfx[HPRE_OVER_THRHLD_CNT].value, 0);
968 } else if (val) {
969 return -EINVAL;
970 }
971
972 atomic64_set(&dfx_item->value, val);
973
974 return 0;
975 }
976
977 DEFINE_DEBUGFS_ATTRIBUTE(hpre_atomic64_ops, hpre_debugfs_atomic64_get,
978 hpre_debugfs_atomic64_set, "%llu\n");
979
hpre_create_debugfs_file(struct hisi_qm * qm,struct dentry * dir,enum hpre_ctrl_dbgfs_file type,int indx)980 static int hpre_create_debugfs_file(struct hisi_qm *qm, struct dentry *dir,
981 enum hpre_ctrl_dbgfs_file type, int indx)
982 {
983 struct hpre *hpre = container_of(qm, struct hpre, qm);
984 struct hpre_debug *dbg = &hpre->debug;
985 struct dentry *file_dir;
986
987 if (dir)
988 file_dir = dir;
989 else
990 file_dir = qm->debug.debug_root;
991
992 if (type >= HPRE_DEBUG_FILE_NUM)
993 return -EINVAL;
994
995 spin_lock_init(&dbg->files[indx].lock);
996 dbg->files[indx].debug = dbg;
997 dbg->files[indx].type = type;
998 dbg->files[indx].index = indx;
999 debugfs_create_file(hpre_debug_file_name[type], 0600, file_dir,
1000 dbg->files + indx, &hpre_ctrl_debug_fops);
1001
1002 return 0;
1003 }
1004
hpre_pf_comm_regs_debugfs_init(struct hisi_qm * qm)1005 static int hpre_pf_comm_regs_debugfs_init(struct hisi_qm *qm)
1006 {
1007 struct device *dev = &qm->pdev->dev;
1008 struct debugfs_regset32 *regset;
1009
1010 regset = devm_kzalloc(dev, sizeof(*regset), GFP_KERNEL);
1011 if (!regset)
1012 return -ENOMEM;
1013
1014 regset->regs = hpre_com_dfx_regs;
1015 regset->nregs = ARRAY_SIZE(hpre_com_dfx_regs);
1016 regset->base = qm->io_base;
1017 regset->dev = dev;
1018
1019 debugfs_create_file("regs", 0444, qm->debug.debug_root,
1020 regset, &hpre_com_regs_fops);
1021
1022 return 0;
1023 }
1024
hpre_cluster_debugfs_init(struct hisi_qm * qm)1025 static int hpre_cluster_debugfs_init(struct hisi_qm *qm)
1026 {
1027 u8 clusters_num = hpre_cluster_num(qm);
1028 struct device *dev = &qm->pdev->dev;
1029 char buf[HPRE_DBGFS_VAL_MAX_LEN];
1030 struct debugfs_regset32 *regset;
1031 struct dentry *tmp_d;
1032 int i, ret;
1033
1034 for (i = 0; i < clusters_num; i++) {
1035 ret = snprintf(buf, HPRE_DBGFS_VAL_MAX_LEN, "cluster%d", i);
1036 if (ret < 0)
1037 return -EINVAL;
1038 tmp_d = debugfs_create_dir(buf, qm->debug.debug_root);
1039
1040 regset = devm_kzalloc(dev, sizeof(*regset), GFP_KERNEL);
1041 if (!regset)
1042 return -ENOMEM;
1043
1044 regset->regs = hpre_cluster_dfx_regs;
1045 regset->nregs = ARRAY_SIZE(hpre_cluster_dfx_regs);
1046 regset->base = qm->io_base + hpre_cluster_offsets[i];
1047 regset->dev = dev;
1048
1049 debugfs_create_file("regs", 0444, tmp_d, regset,
1050 &hpre_cluster_regs_fops);
1051 ret = hpre_create_debugfs_file(qm, tmp_d, HPRE_CLUSTER_CTRL,
1052 i + HPRE_CLUSTER_CTRL);
1053 if (ret)
1054 return ret;
1055 }
1056
1057 return 0;
1058 }
1059
hpre_ctrl_debug_init(struct hisi_qm * qm)1060 static int hpre_ctrl_debug_init(struct hisi_qm *qm)
1061 {
1062 int ret;
1063
1064 ret = hpre_create_debugfs_file(qm, NULL, HPRE_CLEAR_ENABLE,
1065 HPRE_CLEAR_ENABLE);
1066 if (ret)
1067 return ret;
1068
1069 ret = hpre_pf_comm_regs_debugfs_init(qm);
1070 if (ret)
1071 return ret;
1072
1073 return hpre_cluster_debugfs_init(qm);
1074 }
1075
hpre_dfx_debug_init(struct hisi_qm * qm)1076 static void hpre_dfx_debug_init(struct hisi_qm *qm)
1077 {
1078 struct dfx_diff_registers *hpre_regs = qm->debug.acc_diff_regs;
1079 struct hpre *hpre = container_of(qm, struct hpre, qm);
1080 struct hpre_dfx *dfx = hpre->debug.dfx;
1081 struct dentry *parent;
1082 int i;
1083
1084 parent = debugfs_create_dir("hpre_dfx", qm->debug.debug_root);
1085 for (i = 0; i < HPRE_DFX_FILE_NUM; i++) {
1086 dfx[i].type = i;
1087 debugfs_create_file(hpre_dfx_files[i], 0644, parent, &dfx[i],
1088 &hpre_atomic64_ops);
1089 }
1090
1091 if (qm->fun_type == QM_HW_PF && hpre_regs)
1092 debugfs_create_file("diff_regs", 0444, parent,
1093 qm, &hpre_diff_regs_fops);
1094 }
1095
hpre_debugfs_init(struct hisi_qm * qm)1096 static int hpre_debugfs_init(struct hisi_qm *qm)
1097 {
1098 struct device *dev = &qm->pdev->dev;
1099 int ret;
1100
1101 qm->debug.debug_root = debugfs_create_dir(dev_name(dev),
1102 hpre_debugfs_root);
1103
1104 qm->debug.sqe_mask_offset = HPRE_SQE_MASK_OFFSET;
1105 qm->debug.sqe_mask_len = HPRE_SQE_MASK_LEN;
1106 ret = hisi_qm_regs_debugfs_init(qm, hpre_diff_regs, ARRAY_SIZE(hpre_diff_regs));
1107 if (ret) {
1108 dev_warn(dev, "Failed to init HPRE diff regs!\n");
1109 goto debugfs_remove;
1110 }
1111
1112 hisi_qm_debug_init(qm);
1113
1114 if (qm->pdev->device == PCI_DEVICE_ID_HUAWEI_HPRE_PF) {
1115 ret = hpre_ctrl_debug_init(qm);
1116 if (ret)
1117 goto failed_to_create;
1118 }
1119
1120 hpre_dfx_debug_init(qm);
1121
1122 return 0;
1123
1124 failed_to_create:
1125 hisi_qm_regs_debugfs_uninit(qm, ARRAY_SIZE(hpre_diff_regs));
1126 debugfs_remove:
1127 debugfs_remove_recursive(qm->debug.debug_root);
1128 return ret;
1129 }
1130
hpre_debugfs_exit(struct hisi_qm * qm)1131 static void hpre_debugfs_exit(struct hisi_qm *qm)
1132 {
1133 hisi_qm_regs_debugfs_uninit(qm, ARRAY_SIZE(hpre_diff_regs));
1134
1135 debugfs_remove_recursive(qm->debug.debug_root);
1136 }
1137
hpre_qm_init(struct hisi_qm * qm,struct pci_dev * pdev)1138 static int hpre_qm_init(struct hisi_qm *qm, struct pci_dev *pdev)
1139 {
1140 int ret;
1141
1142 if (pdev->revision == QM_HW_V1) {
1143 pci_warn(pdev, "HPRE version 1 is not supported!\n");
1144 return -EINVAL;
1145 }
1146
1147 qm->mode = uacce_mode;
1148 qm->pdev = pdev;
1149 qm->ver = pdev->revision;
1150 qm->sqe_size = HPRE_SQE_SIZE;
1151 qm->dev_name = hpre_name;
1152
1153 qm->fun_type = (pdev->device == PCI_DEVICE_ID_HUAWEI_HPRE_PF) ?
1154 QM_HW_PF : QM_HW_VF;
1155 if (qm->fun_type == QM_HW_PF) {
1156 qm->qp_base = HPRE_PF_DEF_Q_BASE;
1157 qm->qp_num = pf_q_num;
1158 qm->debug.curr_qm_qp_num = pf_q_num;
1159 qm->qm_list = &hpre_devices;
1160 }
1161
1162 ret = hisi_qm_init(qm);
1163 if (ret) {
1164 pci_err(pdev, "Failed to init hpre qm configures!\n");
1165 return ret;
1166 }
1167
1168 ret = hpre_set_qm_algs(qm);
1169 if (ret) {
1170 pci_err(pdev, "Failed to set hpre algs!\n");
1171 hisi_qm_uninit(qm);
1172 }
1173
1174 return ret;
1175 }
1176
hpre_show_last_regs_init(struct hisi_qm * qm)1177 static int hpre_show_last_regs_init(struct hisi_qm *qm)
1178 {
1179 int cluster_dfx_regs_num = ARRAY_SIZE(hpre_cluster_dfx_regs);
1180 int com_dfx_regs_num = ARRAY_SIZE(hpre_com_dfx_regs);
1181 u8 clusters_num = hpre_cluster_num(qm);
1182 struct qm_debug *debug = &qm->debug;
1183 void __iomem *io_base;
1184 int i, j, idx;
1185
1186 debug->last_words = kcalloc(cluster_dfx_regs_num * clusters_num +
1187 com_dfx_regs_num, sizeof(unsigned int), GFP_KERNEL);
1188 if (!debug->last_words)
1189 return -ENOMEM;
1190
1191 for (i = 0; i < com_dfx_regs_num; i++)
1192 debug->last_words[i] = readl_relaxed(qm->io_base +
1193 hpre_com_dfx_regs[i].offset);
1194
1195 for (i = 0; i < clusters_num; i++) {
1196 io_base = qm->io_base + hpre_cluster_offsets[i];
1197 for (j = 0; j < cluster_dfx_regs_num; j++) {
1198 idx = com_dfx_regs_num + i * cluster_dfx_regs_num + j;
1199 debug->last_words[idx] = readl_relaxed(
1200 io_base + hpre_cluster_dfx_regs[j].offset);
1201 }
1202 }
1203
1204 return 0;
1205 }
1206
hpre_show_last_regs_uninit(struct hisi_qm * qm)1207 static void hpre_show_last_regs_uninit(struct hisi_qm *qm)
1208 {
1209 struct qm_debug *debug = &qm->debug;
1210
1211 if (qm->fun_type == QM_HW_VF || !debug->last_words)
1212 return;
1213
1214 kfree(debug->last_words);
1215 debug->last_words = NULL;
1216 }
1217
hpre_show_last_dfx_regs(struct hisi_qm * qm)1218 static void hpre_show_last_dfx_regs(struct hisi_qm *qm)
1219 {
1220 int cluster_dfx_regs_num = ARRAY_SIZE(hpre_cluster_dfx_regs);
1221 int com_dfx_regs_num = ARRAY_SIZE(hpre_com_dfx_regs);
1222 u8 clusters_num = hpre_cluster_num(qm);
1223 struct qm_debug *debug = &qm->debug;
1224 struct pci_dev *pdev = qm->pdev;
1225 void __iomem *io_base;
1226 int i, j, idx;
1227 u32 val;
1228
1229 if (qm->fun_type == QM_HW_VF || !debug->last_words)
1230 return;
1231
1232 /* dumps last word of the debugging registers during controller reset */
1233 for (i = 0; i < com_dfx_regs_num; i++) {
1234 val = readl_relaxed(qm->io_base + hpre_com_dfx_regs[i].offset);
1235 if (debug->last_words[i] != val)
1236 pci_info(pdev, "Common_core:%s \t= 0x%08x => 0x%08x\n",
1237 hpre_com_dfx_regs[i].name, debug->last_words[i], val);
1238 }
1239
1240 for (i = 0; i < clusters_num; i++) {
1241 io_base = qm->io_base + hpre_cluster_offsets[i];
1242 for (j = 0; j < cluster_dfx_regs_num; j++) {
1243 val = readl_relaxed(io_base +
1244 hpre_cluster_dfx_regs[j].offset);
1245 idx = com_dfx_regs_num + i * cluster_dfx_regs_num + j;
1246 if (debug->last_words[idx] != val)
1247 pci_info(pdev, "cluster-%d:%s \t= 0x%08x => 0x%08x\n",
1248 i, hpre_cluster_dfx_regs[j].name, debug->last_words[idx], val);
1249 }
1250 }
1251 }
1252
hpre_log_hw_error(struct hisi_qm * qm,u32 err_sts)1253 static void hpre_log_hw_error(struct hisi_qm *qm, u32 err_sts)
1254 {
1255 const struct hpre_hw_error *err = hpre_hw_errors;
1256 struct device *dev = &qm->pdev->dev;
1257
1258 while (err->msg) {
1259 if (err->int_msk & err_sts)
1260 dev_warn(dev, "%s [error status=0x%x] found\n",
1261 err->msg, err->int_msk);
1262 err++;
1263 }
1264 }
1265
hpre_get_hw_err_status(struct hisi_qm * qm)1266 static u32 hpre_get_hw_err_status(struct hisi_qm *qm)
1267 {
1268 return readl(qm->io_base + HPRE_INT_STATUS);
1269 }
1270
hpre_clear_hw_err_status(struct hisi_qm * qm,u32 err_sts)1271 static void hpre_clear_hw_err_status(struct hisi_qm *qm, u32 err_sts)
1272 {
1273 u32 nfe;
1274
1275 writel(err_sts, qm->io_base + HPRE_HAC_SOURCE_INT);
1276 nfe = hisi_qm_get_hw_info(qm, hpre_basic_info, HPRE_NFE_MASK_CAP, qm->cap_ver);
1277 writel(nfe, qm->io_base + HPRE_RAS_NFE_ENB);
1278 }
1279
hpre_open_axi_master_ooo(struct hisi_qm * qm)1280 static void hpre_open_axi_master_ooo(struct hisi_qm *qm)
1281 {
1282 u32 value;
1283
1284 value = readl(qm->io_base + HPRE_AM_OOO_SHUTDOWN_ENB);
1285 writel(value & ~HPRE_AM_OOO_SHUTDOWN_ENABLE,
1286 qm->io_base + HPRE_AM_OOO_SHUTDOWN_ENB);
1287 writel(value | HPRE_AM_OOO_SHUTDOWN_ENABLE,
1288 qm->io_base + HPRE_AM_OOO_SHUTDOWN_ENB);
1289 }
1290
hpre_err_info_init(struct hisi_qm * qm)1291 static void hpre_err_info_init(struct hisi_qm *qm)
1292 {
1293 struct hisi_qm_err_info *err_info = &qm->err_info;
1294
1295 err_info->fe = HPRE_HAC_RAS_FE_ENABLE;
1296 err_info->ce = hisi_qm_get_hw_info(qm, hpre_basic_info, HPRE_QM_CE_MASK_CAP, qm->cap_ver);
1297 err_info->nfe = hisi_qm_get_hw_info(qm, hpre_basic_info, HPRE_QM_NFE_MASK_CAP, qm->cap_ver);
1298 err_info->ecc_2bits_mask = HPRE_CORE_ECC_2BIT_ERR | HPRE_OOO_ECC_2BIT_ERR;
1299 err_info->dev_shutdown_mask = hisi_qm_get_hw_info(qm, hpre_basic_info,
1300 HPRE_OOO_SHUTDOWN_MASK_CAP, qm->cap_ver);
1301 err_info->qm_shutdown_mask = hisi_qm_get_hw_info(qm, hpre_basic_info,
1302 HPRE_QM_OOO_SHUTDOWN_MASK_CAP, qm->cap_ver);
1303 err_info->qm_reset_mask = hisi_qm_get_hw_info(qm, hpre_basic_info,
1304 HPRE_QM_RESET_MASK_CAP, qm->cap_ver);
1305 err_info->dev_reset_mask = hisi_qm_get_hw_info(qm, hpre_basic_info,
1306 HPRE_RESET_MASK_CAP, qm->cap_ver);
1307 err_info->msi_wr_port = HPRE_WR_MSI_PORT;
1308 err_info->acpi_rst = "HRST";
1309 }
1310
1311 static const struct hisi_qm_err_ini hpre_err_ini = {
1312 .hw_init = hpre_set_user_domain_and_cache,
1313 .hw_err_enable = hpre_hw_error_enable,
1314 .hw_err_disable = hpre_hw_error_disable,
1315 .get_dev_hw_err_status = hpre_get_hw_err_status,
1316 .clear_dev_hw_err_status = hpre_clear_hw_err_status,
1317 .log_dev_hw_err = hpre_log_hw_error,
1318 .open_axi_master_ooo = hpre_open_axi_master_ooo,
1319 .open_sva_prefetch = hpre_open_sva_prefetch,
1320 .close_sva_prefetch = hpre_close_sva_prefetch,
1321 .show_last_dfx_regs = hpre_show_last_dfx_regs,
1322 .err_info_init = hpre_err_info_init,
1323 };
1324
hpre_pf_probe_init(struct hpre * hpre)1325 static int hpre_pf_probe_init(struct hpre *hpre)
1326 {
1327 struct hisi_qm *qm = &hpre->qm;
1328 int ret;
1329
1330 ret = hpre_set_user_domain_and_cache(qm);
1331 if (ret)
1332 return ret;
1333
1334 hpre_open_sva_prefetch(qm);
1335
1336 qm->err_ini = &hpre_err_ini;
1337 qm->err_ini->err_info_init(qm);
1338 hisi_qm_dev_err_init(qm);
1339 ret = hpre_show_last_regs_init(qm);
1340 if (ret)
1341 pci_err(qm->pdev, "Failed to init last word regs!\n");
1342
1343 return ret;
1344 }
1345
hpre_probe_init(struct hpre * hpre)1346 static int hpre_probe_init(struct hpre *hpre)
1347 {
1348 u32 type_rate = HPRE_SHAPER_TYPE_RATE;
1349 struct hisi_qm *qm = &hpre->qm;
1350 int ret;
1351
1352 if (qm->fun_type == QM_HW_PF) {
1353 ret = hpre_pf_probe_init(hpre);
1354 if (ret)
1355 return ret;
1356 /* Enable shaper type 0 */
1357 if (qm->ver >= QM_HW_V3) {
1358 type_rate |= QM_SHAPER_ENABLE;
1359 qm->type_rate = type_rate;
1360 }
1361 }
1362
1363 return 0;
1364 }
1365
hpre_probe(struct pci_dev * pdev,const struct pci_device_id * id)1366 static int hpre_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1367 {
1368 struct hisi_qm *qm;
1369 struct hpre *hpre;
1370 int ret;
1371
1372 hpre = devm_kzalloc(&pdev->dev, sizeof(*hpre), GFP_KERNEL);
1373 if (!hpre)
1374 return -ENOMEM;
1375
1376 qm = &hpre->qm;
1377 ret = hpre_qm_init(qm, pdev);
1378 if (ret) {
1379 pci_err(pdev, "Failed to init HPRE QM (%d)!\n", ret);
1380 return ret;
1381 }
1382
1383 ret = hpre_probe_init(hpre);
1384 if (ret) {
1385 pci_err(pdev, "Failed to probe (%d)!\n", ret);
1386 goto err_with_qm_init;
1387 }
1388
1389 ret = hisi_qm_start(qm);
1390 if (ret)
1391 goto err_with_err_init;
1392
1393 ret = hpre_debugfs_init(qm);
1394 if (ret)
1395 dev_warn(&pdev->dev, "init debugfs fail!\n");
1396
1397 ret = hisi_qm_alg_register(qm, &hpre_devices);
1398 if (ret < 0) {
1399 pci_err(pdev, "fail to register algs to crypto!\n");
1400 goto err_with_qm_start;
1401 }
1402
1403 if (qm->uacce) {
1404 ret = uacce_register(qm->uacce);
1405 if (ret) {
1406 pci_err(pdev, "failed to register uacce (%d)!\n", ret);
1407 goto err_with_alg_register;
1408 }
1409 }
1410
1411 if (qm->fun_type == QM_HW_PF && vfs_num) {
1412 ret = hisi_qm_sriov_enable(pdev, vfs_num);
1413 if (ret < 0)
1414 goto err_with_alg_register;
1415 }
1416
1417 hisi_qm_pm_init(qm);
1418
1419 return 0;
1420
1421 err_with_alg_register:
1422 hisi_qm_alg_unregister(qm, &hpre_devices);
1423
1424 err_with_qm_start:
1425 hpre_debugfs_exit(qm);
1426 hisi_qm_stop(qm, QM_NORMAL);
1427
1428 err_with_err_init:
1429 hpre_show_last_regs_uninit(qm);
1430 hisi_qm_dev_err_uninit(qm);
1431
1432 err_with_qm_init:
1433 hisi_qm_uninit(qm);
1434
1435 return ret;
1436 }
1437
hpre_remove(struct pci_dev * pdev)1438 static void hpre_remove(struct pci_dev *pdev)
1439 {
1440 struct hisi_qm *qm = pci_get_drvdata(pdev);
1441
1442 hisi_qm_pm_uninit(qm);
1443 hisi_qm_wait_task_finish(qm, &hpre_devices);
1444 hisi_qm_alg_unregister(qm, &hpre_devices);
1445 if (qm->fun_type == QM_HW_PF && qm->vfs_num)
1446 hisi_qm_sriov_disable(pdev, true);
1447
1448 hpre_debugfs_exit(qm);
1449 hisi_qm_stop(qm, QM_NORMAL);
1450
1451 if (qm->fun_type == QM_HW_PF) {
1452 hpre_cnt_regs_clear(qm);
1453 qm->debug.curr_qm_qp_num = 0;
1454 hpre_show_last_regs_uninit(qm);
1455 hisi_qm_dev_err_uninit(qm);
1456 }
1457
1458 hisi_qm_uninit(qm);
1459 }
1460
1461 static const struct dev_pm_ops hpre_pm_ops = {
1462 SET_RUNTIME_PM_OPS(hisi_qm_suspend, hisi_qm_resume, NULL)
1463 };
1464
1465 static const struct pci_error_handlers hpre_err_handler = {
1466 .error_detected = hisi_qm_dev_err_detected,
1467 .slot_reset = hisi_qm_dev_slot_reset,
1468 .reset_prepare = hisi_qm_reset_prepare,
1469 .reset_done = hisi_qm_reset_done,
1470 };
1471
1472 static struct pci_driver hpre_pci_driver = {
1473 .name = hpre_name,
1474 .id_table = hpre_dev_ids,
1475 .probe = hpre_probe,
1476 .remove = hpre_remove,
1477 .sriov_configure = IS_ENABLED(CONFIG_PCI_IOV) ?
1478 hisi_qm_sriov_configure : NULL,
1479 .err_handler = &hpre_err_handler,
1480 .shutdown = hisi_qm_dev_shutdown,
1481 .driver.pm = &hpre_pm_ops,
1482 };
1483
hisi_hpre_get_pf_driver(void)1484 struct pci_driver *hisi_hpre_get_pf_driver(void)
1485 {
1486 return &hpre_pci_driver;
1487 }
1488 EXPORT_SYMBOL_GPL(hisi_hpre_get_pf_driver);
1489
hpre_register_debugfs(void)1490 static void hpre_register_debugfs(void)
1491 {
1492 if (!debugfs_initialized())
1493 return;
1494
1495 hpre_debugfs_root = debugfs_create_dir(hpre_name, NULL);
1496 }
1497
hpre_unregister_debugfs(void)1498 static void hpre_unregister_debugfs(void)
1499 {
1500 debugfs_remove_recursive(hpre_debugfs_root);
1501 }
1502
hpre_init(void)1503 static int __init hpre_init(void)
1504 {
1505 int ret;
1506
1507 hisi_qm_init_list(&hpre_devices);
1508 hpre_register_debugfs();
1509
1510 ret = pci_register_driver(&hpre_pci_driver);
1511 if (ret) {
1512 hpre_unregister_debugfs();
1513 pr_err("hpre: can't register hisi hpre driver.\n");
1514 }
1515
1516 return ret;
1517 }
1518
hpre_exit(void)1519 static void __exit hpre_exit(void)
1520 {
1521 pci_unregister_driver(&hpre_pci_driver);
1522 hpre_unregister_debugfs();
1523 }
1524
1525 module_init(hpre_init);
1526 module_exit(hpre_exit);
1527
1528 MODULE_LICENSE("GPL v2");
1529 MODULE_AUTHOR("Zaibo Xu <xuzaibo@huawei.com>");
1530 MODULE_AUTHOR("Meng Yu <yumeng18@huawei.com>");
1531 MODULE_DESCRIPTION("Driver for HiSilicon HPRE accelerator");
1532
