1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Mediatek MT7621 Clock Driver
4 * Author: Sergio Paracuellos <sergio.paracuellos@gmail.com>
5 */
6
7 #include <linux/bitfield.h>
8 #include <linux/bitops.h>
9 #include <linux/clk-provider.h>
10 #include <linux/clk.h>
11 #include <linux/mfd/syscon.h>
12 #include <linux/platform_device.h>
13 #include <linux/regmap.h>
14 #include <linux/reset-controller.h>
15 #include <linux/slab.h>
16 #include <dt-bindings/clock/mt7621-clk.h>
17 #include <dt-bindings/reset/mt7621-reset.h>
18
19 /* Configuration registers */
20 #define SYSC_REG_SYSTEM_CONFIG0 0x10
21 #define SYSC_REG_SYSTEM_CONFIG1 0x14
22 #define SYSC_REG_CLKCFG0 0x2c
23 #define SYSC_REG_CLKCFG1 0x30
24 #define SYSC_REG_RESET_CTRL 0x34
25 #define SYSC_REG_CUR_CLK_STS 0x44
26 #define MEMC_REG_CPU_PLL 0x648
27
28 #define XTAL_MODE_SEL_MASK GENMASK(8, 6)
29 #define CPU_CLK_SEL_MASK GENMASK(31, 30)
30 #define CUR_CPU_FDIV_MASK GENMASK(12, 8)
31 #define CUR_CPU_FFRAC_MASK GENMASK(4, 0)
32 #define CPU_PLL_PREDIV_MASK GENMASK(13, 12)
33 #define CPU_PLL_FBDIV_MASK GENMASK(10, 4)
34
35 struct mt7621_clk_priv {
36 struct regmap *sysc;
37 struct regmap *memc;
38 };
39
40 struct mt7621_clk {
41 struct clk_hw hw;
42 struct mt7621_clk_priv *priv;
43 };
44
45 struct mt7621_fixed_clk {
46 u8 idx;
47 const char *name;
48 const char *parent_name;
49 unsigned long rate;
50 struct clk_hw *hw;
51 };
52
53 struct mt7621_gate {
54 u8 idx;
55 const char *name;
56 const char *parent_name;
57 struct mt7621_clk_priv *priv;
58 u32 bit_idx;
59 struct clk_hw hw;
60 };
61
62 #define GATE(_id, _name, _pname, _shift) \
63 { \
64 .idx = _id, \
65 .name = _name, \
66 .parent_name = _pname, \
67 .bit_idx = _shift \
68 }
69
70 static struct mt7621_gate mt7621_gates[] = {
71 GATE(MT7621_CLK_HSDMA, "hsdma", "150m", BIT(5)),
72 GATE(MT7621_CLK_FE, "fe", "250m", BIT(6)),
73 GATE(MT7621_CLK_SP_DIVTX, "sp_divtx", "270m", BIT(7)),
74 GATE(MT7621_CLK_TIMER, "timer", "50m", BIT(8)),
75 GATE(MT7621_CLK_PCM, "pcm", "270m", BIT(11)),
76 GATE(MT7621_CLK_PIO, "pio", "50m", BIT(13)),
77 GATE(MT7621_CLK_GDMA, "gdma", "bus", BIT(14)),
78 GATE(MT7621_CLK_NAND, "nand", "125m", BIT(15)),
79 GATE(MT7621_CLK_I2C, "i2c", "50m", BIT(16)),
80 GATE(MT7621_CLK_I2S, "i2s", "270m", BIT(17)),
81 GATE(MT7621_CLK_SPI, "spi", "bus", BIT(18)),
82 GATE(MT7621_CLK_UART1, "uart1", "50m", BIT(19)),
83 GATE(MT7621_CLK_UART2, "uart2", "50m", BIT(20)),
84 GATE(MT7621_CLK_UART3, "uart3", "50m", BIT(21)),
85 GATE(MT7621_CLK_ETH, "eth", "50m", BIT(23)),
86 GATE(MT7621_CLK_PCIE0, "pcie0", "125m", BIT(24)),
87 GATE(MT7621_CLK_PCIE1, "pcie1", "125m", BIT(25)),
88 GATE(MT7621_CLK_PCIE2, "pcie2", "125m", BIT(26)),
89 GATE(MT7621_CLK_CRYPTO, "crypto", "250m", BIT(29)),
90 GATE(MT7621_CLK_SHXC, "shxc", "50m", BIT(30))
91 };
92
to_mt7621_gate(struct clk_hw * hw)93 static inline struct mt7621_gate *to_mt7621_gate(struct clk_hw *hw)
94 {
95 return container_of(hw, struct mt7621_gate, hw);
96 }
97
mt7621_gate_enable(struct clk_hw * hw)98 static int mt7621_gate_enable(struct clk_hw *hw)
99 {
100 struct mt7621_gate *clk_gate = to_mt7621_gate(hw);
101 struct regmap *sysc = clk_gate->priv->sysc;
102
103 return regmap_update_bits(sysc, SYSC_REG_CLKCFG1,
104 clk_gate->bit_idx, clk_gate->bit_idx);
105 }
106
mt7621_gate_disable(struct clk_hw * hw)107 static void mt7621_gate_disable(struct clk_hw *hw)
108 {
109 struct mt7621_gate *clk_gate = to_mt7621_gate(hw);
110 struct regmap *sysc = clk_gate->priv->sysc;
111
112 regmap_update_bits(sysc, SYSC_REG_CLKCFG1, clk_gate->bit_idx, 0);
113 }
114
mt7621_gate_is_enabled(struct clk_hw * hw)115 static int mt7621_gate_is_enabled(struct clk_hw *hw)
116 {
117 struct mt7621_gate *clk_gate = to_mt7621_gate(hw);
118 struct regmap *sysc = clk_gate->priv->sysc;
119 u32 val;
120
121 if (regmap_read(sysc, SYSC_REG_CLKCFG1, &val))
122 return 0;
123
124 return val & BIT(clk_gate->bit_idx);
125 }
126
127 static const struct clk_ops mt7621_gate_ops = {
128 .enable = mt7621_gate_enable,
129 .disable = mt7621_gate_disable,
130 .is_enabled = mt7621_gate_is_enabled,
131 };
132
mt7621_gate_ops_init(struct device * dev,struct mt7621_gate * sclk)133 static int mt7621_gate_ops_init(struct device *dev,
134 struct mt7621_gate *sclk)
135 {
136 struct clk_init_data init = {
137 .flags = CLK_SET_RATE_PARENT,
138 .num_parents = 1,
139 .parent_names = &sclk->parent_name,
140 .ops = &mt7621_gate_ops,
141 .name = sclk->name,
142 };
143
144 sclk->hw.init = &init;
145 return devm_clk_hw_register(dev, &sclk->hw);
146 }
147
mt7621_register_gates(struct device * dev,struct clk_hw_onecell_data * clk_data,struct mt7621_clk_priv * priv)148 static int mt7621_register_gates(struct device *dev,
149 struct clk_hw_onecell_data *clk_data,
150 struct mt7621_clk_priv *priv)
151 {
152 struct clk_hw **hws = clk_data->hws;
153 struct mt7621_gate *sclk;
154 int ret, i;
155
156 for (i = 0; i < ARRAY_SIZE(mt7621_gates); i++) {
157 sclk = &mt7621_gates[i];
158 sclk->priv = priv;
159 ret = mt7621_gate_ops_init(dev, sclk);
160 if (ret) {
161 dev_err(dev, "Couldn't register clock %s\n", sclk->name);
162 goto err_clk_unreg;
163 }
164
165 hws[sclk->idx] = &sclk->hw;
166 }
167
168 return 0;
169
170 err_clk_unreg:
171 while (--i >= 0) {
172 sclk = &mt7621_gates[i];
173 clk_hw_unregister(&sclk->hw);
174 }
175 return ret;
176 }
177
178 #define FIXED(_id, _name, _rate) \
179 { \
180 .idx = _id, \
181 .name = _name, \
182 .parent_name = "xtal", \
183 .rate = _rate \
184 }
185
186 static struct mt7621_fixed_clk mt7621_fixed_clks[] = {
187 FIXED(MT7621_CLK_50M, "50m", 50000000),
188 FIXED(MT7621_CLK_125M, "125m", 125000000),
189 FIXED(MT7621_CLK_150M, "150m", 150000000),
190 FIXED(MT7621_CLK_250M, "250m", 250000000),
191 FIXED(MT7621_CLK_270M, "270m", 270000000),
192 };
193
mt7621_register_fixed_clocks(struct device * dev,struct clk_hw_onecell_data * clk_data)194 static int mt7621_register_fixed_clocks(struct device *dev,
195 struct clk_hw_onecell_data *clk_data)
196 {
197 struct clk_hw **hws = clk_data->hws;
198 struct mt7621_fixed_clk *sclk;
199 int ret, i;
200
201 for (i = 0; i < ARRAY_SIZE(mt7621_fixed_clks); i++) {
202 sclk = &mt7621_fixed_clks[i];
203 sclk->hw = clk_hw_register_fixed_rate(dev, sclk->name,
204 sclk->parent_name, 0,
205 sclk->rate);
206 if (IS_ERR(sclk->hw)) {
207 dev_err(dev, "Couldn't register clock %s\n", sclk->name);
208 ret = PTR_ERR(sclk->hw);
209 goto err_clk_unreg;
210 }
211
212 hws[sclk->idx] = sclk->hw;
213 }
214
215 return 0;
216
217 err_clk_unreg:
218 while (--i >= 0) {
219 sclk = &mt7621_fixed_clks[i];
220 clk_hw_unregister_fixed_rate(sclk->hw);
221 }
222 return ret;
223 }
224
to_mt7621_clk(struct clk_hw * hw)225 static inline struct mt7621_clk *to_mt7621_clk(struct clk_hw *hw)
226 {
227 return container_of(hw, struct mt7621_clk, hw);
228 }
229
mt7621_xtal_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)230 static unsigned long mt7621_xtal_recalc_rate(struct clk_hw *hw,
231 unsigned long parent_rate)
232 {
233 struct mt7621_clk *clk = to_mt7621_clk(hw);
234 struct regmap *sysc = clk->priv->sysc;
235 u32 val;
236
237 regmap_read(sysc, SYSC_REG_SYSTEM_CONFIG0, &val);
238 val = FIELD_GET(XTAL_MODE_SEL_MASK, val);
239
240 if (val <= 2)
241 return 20000000;
242 if (val <= 5)
243 return 40000000;
244
245 return 25000000;
246 }
247
mt7621_cpu_recalc_rate(struct clk_hw * hw,unsigned long xtal_clk)248 static unsigned long mt7621_cpu_recalc_rate(struct clk_hw *hw,
249 unsigned long xtal_clk)
250 {
251 static const u32 prediv_tbl[] = { 0, 1, 2, 2 };
252 struct mt7621_clk *clk = to_mt7621_clk(hw);
253 struct regmap *sysc = clk->priv->sysc;
254 struct regmap *memc = clk->priv->memc;
255 u32 clkcfg, clk_sel, curclk, ffiv, ffrac;
256 u32 pll, prediv, fbdiv;
257 unsigned long cpu_clk;
258
259 regmap_read(sysc, SYSC_REG_CLKCFG0, &clkcfg);
260 clk_sel = FIELD_GET(CPU_CLK_SEL_MASK, clkcfg);
261
262 regmap_read(sysc, SYSC_REG_CUR_CLK_STS, &curclk);
263 ffiv = FIELD_GET(CUR_CPU_FDIV_MASK, curclk);
264 ffrac = FIELD_GET(CUR_CPU_FFRAC_MASK, curclk);
265
266 switch (clk_sel) {
267 case 0:
268 cpu_clk = 500000000;
269 break;
270 case 1:
271 regmap_read(memc, MEMC_REG_CPU_PLL, &pll);
272 fbdiv = FIELD_GET(CPU_PLL_FBDIV_MASK, pll);
273 prediv = FIELD_GET(CPU_PLL_PREDIV_MASK, pll);
274 cpu_clk = ((fbdiv + 1) * xtal_clk) >> prediv_tbl[prediv];
275 break;
276 default:
277 cpu_clk = xtal_clk;
278 }
279
280 return cpu_clk / ffiv * ffrac;
281 }
282
mt7621_bus_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)283 static unsigned long mt7621_bus_recalc_rate(struct clk_hw *hw,
284 unsigned long parent_rate)
285 {
286 return parent_rate / 4;
287 }
288
289 #define CLK_BASE(_name, _parent, _recalc) { \
290 .init = &(struct clk_init_data) { \
291 .name = _name, \
292 .ops = &(const struct clk_ops) { \
293 .recalc_rate = _recalc, \
294 }, \
295 .parent_data = &(const struct clk_parent_data) { \
296 .name = _parent, \
297 .fw_name = _parent \
298 }, \
299 .num_parents = _parent ? 1 : 0 \
300 }, \
301 }
302
303 static struct mt7621_clk mt7621_clks_base[] = {
304 { CLK_BASE("xtal", NULL, mt7621_xtal_recalc_rate) },
305 { CLK_BASE("cpu", "xtal", mt7621_cpu_recalc_rate) },
306 { CLK_BASE("bus", "cpu", mt7621_bus_recalc_rate) },
307 };
308
309 static struct clk_hw *mt7621_clk_early[MT7621_CLK_MAX];
310
mt7621_register_early_clocks(struct device_node * np,struct clk_hw_onecell_data * clk_data,struct mt7621_clk_priv * priv)311 static int mt7621_register_early_clocks(struct device_node *np,
312 struct clk_hw_onecell_data *clk_data,
313 struct mt7621_clk_priv *priv)
314 {
315 struct clk_hw **hws = clk_data->hws;
316 struct mt7621_clk *sclk;
317 int ret, i, j;
318
319 for (i = 0; i < ARRAY_SIZE(mt7621_clks_base); i++) {
320 sclk = &mt7621_clks_base[i];
321 sclk->priv = priv;
322 ret = of_clk_hw_register(np, &sclk->hw);
323 if (ret) {
324 pr_err("Couldn't register top clock %i\n", i);
325 goto err_clk_unreg;
326 }
327
328 hws[i] = &sclk->hw;
329 mt7621_clk_early[i] = &sclk->hw;
330 }
331
332 for (j = i; j < MT7621_CLK_MAX; j++)
333 mt7621_clk_early[j] = ERR_PTR(-EPROBE_DEFER);
334
335 return 0;
336
337 err_clk_unreg:
338 while (--i >= 0) {
339 sclk = &mt7621_clks_base[i];
340 clk_hw_unregister(&sclk->hw);
341 }
342 return ret;
343 }
344
mt7621_clk_init(struct device_node * node)345 static void __init mt7621_clk_init(struct device_node *node)
346 {
347 struct mt7621_clk_priv *priv;
348 struct clk_hw_onecell_data *clk_data;
349 int ret, i, count;
350
351 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
352 if (!priv)
353 return;
354
355 priv->sysc = syscon_node_to_regmap(node);
356 if (IS_ERR(priv->sysc)) {
357 pr_err("Could not get sysc syscon regmap\n");
358 goto free_clk_priv;
359 }
360
361 priv->memc = syscon_regmap_lookup_by_phandle(node, "ralink,memctl");
362 if (IS_ERR(priv->memc)) {
363 pr_err("Could not get memc syscon regmap\n");
364 goto free_clk_priv;
365 }
366
367 count = ARRAY_SIZE(mt7621_clks_base) +
368 ARRAY_SIZE(mt7621_fixed_clks) + ARRAY_SIZE(mt7621_gates);
369 clk_data = kzalloc(struct_size(clk_data, hws, count), GFP_KERNEL);
370 if (!clk_data)
371 goto free_clk_priv;
372
373 ret = mt7621_register_early_clocks(node, clk_data, priv);
374 if (ret) {
375 pr_err("Couldn't register top clocks\n");
376 goto free_clk_data;
377 }
378
379 clk_data->num = count;
380
381 ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
382 if (ret) {
383 pr_err("Couldn't add clk hw provider\n");
384 goto unreg_clk_top;
385 }
386
387 return;
388
389 unreg_clk_top:
390 for (i = 0; i < ARRAY_SIZE(mt7621_clks_base); i++) {
391 struct mt7621_clk *sclk = &mt7621_clks_base[i];
392
393 clk_hw_unregister(&sclk->hw);
394 }
395
396 free_clk_data:
397 kfree(clk_data);
398
399 free_clk_priv:
400 kfree(priv);
401 }
402 CLK_OF_DECLARE_DRIVER(mt7621_clk, "mediatek,mt7621-sysc", mt7621_clk_init);
403
404 struct mt7621_rst {
405 struct reset_controller_dev rcdev;
406 struct regmap *sysc;
407 };
408
to_mt7621_rst(struct reset_controller_dev * dev)409 static struct mt7621_rst *to_mt7621_rst(struct reset_controller_dev *dev)
410 {
411 return container_of(dev, struct mt7621_rst, rcdev);
412 }
413
mt7621_assert_device(struct reset_controller_dev * rcdev,unsigned long id)414 static int mt7621_assert_device(struct reset_controller_dev *rcdev,
415 unsigned long id)
416 {
417 struct mt7621_rst *data = to_mt7621_rst(rcdev);
418 struct regmap *sysc = data->sysc;
419
420 return regmap_update_bits(sysc, SYSC_REG_RESET_CTRL, BIT(id), BIT(id));
421 }
422
mt7621_deassert_device(struct reset_controller_dev * rcdev,unsigned long id)423 static int mt7621_deassert_device(struct reset_controller_dev *rcdev,
424 unsigned long id)
425 {
426 struct mt7621_rst *data = to_mt7621_rst(rcdev);
427 struct regmap *sysc = data->sysc;
428
429 return regmap_update_bits(sysc, SYSC_REG_RESET_CTRL, BIT(id), 0);
430 }
431
mt7621_reset_device(struct reset_controller_dev * rcdev,unsigned long id)432 static int mt7621_reset_device(struct reset_controller_dev *rcdev,
433 unsigned long id)
434 {
435 int ret;
436
437 ret = mt7621_assert_device(rcdev, id);
438 if (ret < 0)
439 return ret;
440
441 return mt7621_deassert_device(rcdev, id);
442 }
443
mt7621_rst_xlate(struct reset_controller_dev * rcdev,const struct of_phandle_args * reset_spec)444 static int mt7621_rst_xlate(struct reset_controller_dev *rcdev,
445 const struct of_phandle_args *reset_spec)
446 {
447 unsigned long id = reset_spec->args[0];
448
449 if (id == MT7621_RST_SYS || id >= rcdev->nr_resets)
450 return -EINVAL;
451
452 return id;
453 }
454
455 static const struct reset_control_ops reset_ops = {
456 .reset = mt7621_reset_device,
457 .assert = mt7621_assert_device,
458 .deassert = mt7621_deassert_device
459 };
460
mt7621_reset_init(struct device * dev,struct regmap * sysc)461 static int mt7621_reset_init(struct device *dev, struct regmap *sysc)
462 {
463 struct mt7621_rst *rst_data;
464
465 rst_data = devm_kzalloc(dev, sizeof(*rst_data), GFP_KERNEL);
466 if (!rst_data)
467 return -ENOMEM;
468
469 rst_data->sysc = sysc;
470 rst_data->rcdev.ops = &reset_ops;
471 rst_data->rcdev.owner = THIS_MODULE;
472 rst_data->rcdev.nr_resets = 32;
473 rst_data->rcdev.of_reset_n_cells = 1;
474 rst_data->rcdev.of_xlate = mt7621_rst_xlate;
475 rst_data->rcdev.of_node = dev_of_node(dev);
476
477 return devm_reset_controller_register(dev, &rst_data->rcdev);
478 }
479
mt7621_clk_probe(struct platform_device * pdev)480 static int mt7621_clk_probe(struct platform_device *pdev)
481 {
482 struct device_node *np = pdev->dev.of_node;
483 struct clk_hw_onecell_data *clk_data;
484 struct device *dev = &pdev->dev;
485 struct mt7621_clk_priv *priv;
486 int ret, i, count;
487
488 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
489 if (!priv)
490 return -ENOMEM;
491
492 priv->sysc = syscon_node_to_regmap(np);
493 if (IS_ERR(priv->sysc)) {
494 ret = PTR_ERR(priv->sysc);
495 dev_err(dev, "Could not get sysc syscon regmap\n");
496 return ret;
497 }
498
499 priv->memc = syscon_regmap_lookup_by_phandle(np, "ralink,memctl");
500 if (IS_ERR(priv->memc)) {
501 ret = PTR_ERR(priv->memc);
502 dev_err(dev, "Could not get memc syscon regmap\n");
503 return ret;
504 }
505
506 ret = mt7621_reset_init(dev, priv->sysc);
507 if (ret) {
508 dev_err(dev, "Could not init reset controller\n");
509 return ret;
510 }
511
512 count = ARRAY_SIZE(mt7621_clks_base) +
513 ARRAY_SIZE(mt7621_fixed_clks) + ARRAY_SIZE(mt7621_gates);
514 clk_data = devm_kzalloc(dev, struct_size(clk_data, hws, count),
515 GFP_KERNEL);
516 if (!clk_data)
517 return -ENOMEM;
518
519 for (i = 0; i < ARRAY_SIZE(mt7621_clks_base); i++)
520 clk_data->hws[i] = mt7621_clk_early[i];
521
522 ret = mt7621_register_fixed_clocks(dev, clk_data);
523 if (ret) {
524 dev_err(dev, "Couldn't register fixed clocks\n");
525 return ret;
526 }
527
528 ret = mt7621_register_gates(dev, clk_data, priv);
529 if (ret) {
530 dev_err(dev, "Couldn't register fixed clock gates\n");
531 goto unreg_clk_fixed;
532 }
533
534 clk_data->num = count;
535
536 ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, clk_data);
537 if (ret) {
538 dev_err(dev, "Couldn't add clk hw provider\n");
539 goto unreg_clk_gates;
540 }
541
542 return 0;
543
544 unreg_clk_gates:
545 for (i = 0; i < ARRAY_SIZE(mt7621_gates); i++) {
546 struct mt7621_gate *sclk = &mt7621_gates[i];
547
548 clk_hw_unregister(&sclk->hw);
549 }
550
551 unreg_clk_fixed:
552 for (i = 0; i < ARRAY_SIZE(mt7621_fixed_clks); i++) {
553 struct mt7621_fixed_clk *sclk = &mt7621_fixed_clks[i];
554
555 clk_hw_unregister_fixed_rate(sclk->hw);
556 }
557
558 return ret;
559 }
560
561 static const struct of_device_id mt7621_clk_of_match[] = {
562 { .compatible = "mediatek,mt7621-sysc" },
563 {}
564 };
565
566 static struct platform_driver mt7621_clk_driver = {
567 .probe = mt7621_clk_probe,
568 .driver = {
569 .name = "mt7621-clk",
570 .of_match_table = mt7621_clk_of_match,
571 },
572 };
573
mt7621_clk_reset_init(void)574 static int __init mt7621_clk_reset_init(void)
575 {
576 return platform_driver_register(&mt7621_clk_driver);
577 }
578 arch_initcall(mt7621_clk_reset_init);
579
