1 /*
2 * Faraday Technology FTIDE010 driver
3 * Copyright (C) 2017 Linus Walleij <linus.walleij@linaro.org>
4 *
5 * Includes portions of the SL2312/SL3516/Gemini PATA driver
6 * Copyright (C) 2003 StorLine, Inc <jason@storlink.com.tw>
7 * Copyright (C) 2009 Janos Laube <janos.dev@gmail.com>
8 * Copyright (C) 2010 Frederic Pecourt <opengemini@free.fr>
9 * Copyright (C) 2011 Tobias Waldvogel <tobias.waldvogel@gmail.com>
10 */
11
12 #include <linux/platform_device.h>
13 #include <linux/module.h>
14 #include <linux/libata.h>
15 #include <linux/bitops.h>
16 #include <linux/of_address.h>
17 #include <linux/of_device.h>
18 #include <linux/clk.h>
19 #include "sata_gemini.h"
20
21 #define DRV_NAME "pata_ftide010"
22
23 /**
24 * struct ftide010 - state container for the Faraday FTIDE010
25 * @dev: pointer back to the device representing this controller
26 * @base: remapped I/O space address
27 * @pclk: peripheral clock for the IDE block
28 * @host: pointer to the ATA host for this device
29 * @master_cbl: master cable type
30 * @slave_cbl: slave cable type
31 * @sg: Gemini SATA bridge pointer, if running on the Gemini
32 * @master_to_sata0: Gemini SATA bridge: the ATA master is connected
33 * to the SATA0 bridge
34 * @slave_to_sata0: Gemini SATA bridge: the ATA slave is connected
35 * to the SATA0 bridge
36 * @master_to_sata1: Gemini SATA bridge: the ATA master is connected
37 * to the SATA1 bridge
38 * @slave_to_sata1: Gemini SATA bridge: the ATA slave is connected
39 * to the SATA1 bridge
40 */
41 struct ftide010 {
42 struct device *dev;
43 void __iomem *base;
44 struct clk *pclk;
45 struct ata_host *host;
46 unsigned int master_cbl;
47 unsigned int slave_cbl;
48 /* Gemini-specific properties */
49 struct sata_gemini *sg;
50 bool master_to_sata0;
51 bool slave_to_sata0;
52 bool master_to_sata1;
53 bool slave_to_sata1;
54 };
55
56 #define FTIDE010_DMA_REG 0x00
57 #define FTIDE010_DMA_STATUS 0x02
58 #define FTIDE010_IDE_BMDTPR 0x04
59 #define FTIDE010_IDE_DEVICE_ID 0x08
60 #define FTIDE010_PIO_TIMING 0x10
61 #define FTIDE010_MWDMA_TIMING 0x11
62 #define FTIDE010_UDMA_TIMING0 0x12 /* Master */
63 #define FTIDE010_UDMA_TIMING1 0x13 /* Slave */
64 #define FTIDE010_CLK_MOD 0x14
65 /* These registers are mapped directly to the IDE registers */
66 #define FTIDE010_CMD_DATA 0x20
67 #define FTIDE010_ERROR_FEATURES 0x21
68 #define FTIDE010_NSECT 0x22
69 #define FTIDE010_LBAL 0x23
70 #define FTIDE010_LBAM 0x24
71 #define FTIDE010_LBAH 0x25
72 #define FTIDE010_DEVICE 0x26
73 #define FTIDE010_STATUS_COMMAND 0x27
74 #define FTIDE010_ALTSTAT_CTRL 0x36
75
76 /* Set this bit for UDMA mode 5 and 6 */
77 #define FTIDE010_UDMA_TIMING_MODE_56 BIT(7)
78
79 /* 0 = 50 MHz, 1 = 66 MHz */
80 #define FTIDE010_CLK_MOD_DEV0_CLK_SEL BIT(0)
81 #define FTIDE010_CLK_MOD_DEV1_CLK_SEL BIT(1)
82 /* Enable UDMA on a device */
83 #define FTIDE010_CLK_MOD_DEV0_UDMA_EN BIT(4)
84 #define FTIDE010_CLK_MOD_DEV1_UDMA_EN BIT(5)
85
86 static struct scsi_host_template pata_ftide010_sht = {
87 ATA_BMDMA_SHT(DRV_NAME),
88 };
89
90 /*
91 * Bus timings
92 *
93 * The unit of the below required timings is two clock periods of the ATA
94 * reference clock which is 30 nanoseconds per unit at 66MHz and 20
95 * nanoseconds per unit at 50 MHz. The PIO timings assume 33MHz speed for
96 * PIO.
97 *
98 * pio_active_time: array of 5 elements for T2 timing for Mode 0,
99 * 1, 2, 3 and 4. Range 0..15.
100 * pio_recovery_time: array of 5 elements for T2l timing for Mode 0,
101 * 1, 2, 3 and 4. Range 0..15.
102 * mdma_50_active_time: array of 4 elements for Td timing for multi
103 * word DMA, Mode 0, 1, and 2 at 50 MHz. Range 0..15.
104 * mdma_50_recovery_time: array of 4 elements for Tk timing for
105 * multi word DMA, Mode 0, 1 and 2 at 50 MHz. Range 0..15.
106 * mdma_66_active_time: array of 4 elements for Td timing for multi
107 * word DMA, Mode 0, 1 and 2 at 66 MHz. Range 0..15.
108 * mdma_66_recovery_time: array of 4 elements for Tk timing for
109 * multi word DMA, Mode 0, 1 and 2 at 66 MHz. Range 0..15.
110 * udma_50_setup_time: array of 4 elements for Tvds timing for ultra
111 * DMA, Mode 0, 1, 2, 3, 4 and 5 at 50 MHz. Range 0..7.
112 * udma_50_hold_time: array of 4 elements for Tdvh timing for
113 * multi word DMA, Mode 0, 1, 2, 3, 4 and 5 at 50 MHz, Range 0..7.
114 * udma_66_setup_time: array of 4 elements for Tvds timing for multi
115 * word DMA, Mode 0, 1, 2, 3, 4, 5 and 6 at 66 MHz. Range 0..7.
116 * udma_66_hold_time: array of 4 elements for Tdvh timing for
117 * multi word DMA, Mode 0, 1, 2, 3, 4, 5 and 6 at 66 MHz. Range 0..7.
118 */
119 static const u8 pio_active_time[5] = {10, 10, 10, 3, 3};
120 static const u8 pio_recovery_time[5] = {10, 3, 1, 3, 1};
121 static const u8 mwdma_50_active_time[3] = {6, 2, 2};
122 static const u8 mwdma_50_recovery_time[3] = {6, 2, 1};
123 static const u8 mwdma_66_active_time[3] = {8, 3, 3};
124 static const u8 mwdma_66_recovery_time[3] = {8, 2, 1};
125 static const u8 udma_50_setup_time[6] = {3, 3, 2, 2, 1, 1};
126 static const u8 udma_50_hold_time[6] = {3, 1, 1, 1, 1, 1};
127 static const u8 udma_66_setup_time[7] = {4, 4, 3, 2, };
128 static const u8 udma_66_hold_time[7] = {};
129
130 /*
131 * We set 66 MHz for all MWDMA modes
132 */
133 static const bool set_mdma_66_mhz[] = { true, true, true, true };
134
135 /*
136 * We set 66 MHz for UDMA modes 3, 4 and 6 and no others
137 */
138 static const bool set_udma_66_mhz[] = { false, false, false, true, true, false, true };
139
ftide010_set_dmamode(struct ata_port * ap,struct ata_device * adev)140 static void ftide010_set_dmamode(struct ata_port *ap, struct ata_device *adev)
141 {
142 struct ftide010 *ftide = ap->host->private_data;
143 u8 speed = adev->dma_mode;
144 u8 devno = adev->devno & 1;
145 u8 udma_en_mask;
146 u8 f66m_en_mask;
147 u8 clkreg;
148 u8 timreg;
149 u8 i;
150
151 /* Target device 0 (master) or 1 (slave) */
152 if (!devno) {
153 udma_en_mask = FTIDE010_CLK_MOD_DEV0_UDMA_EN;
154 f66m_en_mask = FTIDE010_CLK_MOD_DEV0_CLK_SEL;
155 } else {
156 udma_en_mask = FTIDE010_CLK_MOD_DEV1_UDMA_EN;
157 f66m_en_mask = FTIDE010_CLK_MOD_DEV1_CLK_SEL;
158 }
159
160 clkreg = readb(ftide->base + FTIDE010_CLK_MOD);
161 clkreg &= ~udma_en_mask;
162 clkreg &= ~f66m_en_mask;
163
164 if (speed & XFER_UDMA_0) {
165 i = speed & ~XFER_UDMA_0;
166 dev_dbg(ftide->dev, "set UDMA mode %02x, index %d\n",
167 speed, i);
168
169 clkreg |= udma_en_mask;
170 if (set_udma_66_mhz[i]) {
171 clkreg |= f66m_en_mask;
172 timreg = udma_66_setup_time[i] << 4 |
173 udma_66_hold_time[i];
174 } else {
175 timreg = udma_50_setup_time[i] << 4 |
176 udma_50_hold_time[i];
177 }
178
179 /* A special bit needs to be set for modes 5 and 6 */
180 if (i >= 5)
181 timreg |= FTIDE010_UDMA_TIMING_MODE_56;
182
183 dev_dbg(ftide->dev, "UDMA write clkreg = %02x, timreg = %02x\n",
184 clkreg, timreg);
185
186 writeb(clkreg, ftide->base + FTIDE010_CLK_MOD);
187 writeb(timreg, ftide->base + FTIDE010_UDMA_TIMING0 + devno);
188 } else {
189 i = speed & ~XFER_MW_DMA_0;
190 dev_dbg(ftide->dev, "set MWDMA mode %02x, index %d\n",
191 speed, i);
192
193 if (set_mdma_66_mhz[i]) {
194 clkreg |= f66m_en_mask;
195 timreg = mwdma_66_active_time[i] << 4 |
196 mwdma_66_recovery_time[i];
197 } else {
198 timreg = mwdma_50_active_time[i] << 4 |
199 mwdma_50_recovery_time[i];
200 }
201 dev_dbg(ftide->dev,
202 "MWDMA write clkreg = %02x, timreg = %02x\n",
203 clkreg, timreg);
204 /* This will affect all devices */
205 writeb(clkreg, ftide->base + FTIDE010_CLK_MOD);
206 writeb(timreg, ftide->base + FTIDE010_MWDMA_TIMING);
207 }
208
209 /*
210 * Store the current device (master or slave) in ap->private_data
211 * so that .qc_issue() can detect if this changes and reprogram
212 * the DMA settings.
213 */
214 ap->private_data = adev;
215
216 return;
217 }
218
ftide010_set_piomode(struct ata_port * ap,struct ata_device * adev)219 static void ftide010_set_piomode(struct ata_port *ap, struct ata_device *adev)
220 {
221 struct ftide010 *ftide = ap->host->private_data;
222 u8 pio = adev->pio_mode - XFER_PIO_0;
223
224 dev_dbg(ftide->dev, "set PIO mode %02x, index %d\n",
225 adev->pio_mode, pio);
226 writeb(pio_active_time[pio] << 4 | pio_recovery_time[pio],
227 ftide->base + FTIDE010_PIO_TIMING);
228 }
229
230 /*
231 * We implement our own qc_issue() callback since we may need to set up
232 * the timings differently for master and slave transfers: the CLK_MOD_REG
233 * and MWDMA_TIMING_REG is shared between master and slave, so reprogramming
234 * this may be necessary.
235 */
ftide010_qc_issue(struct ata_queued_cmd * qc)236 static unsigned int ftide010_qc_issue(struct ata_queued_cmd *qc)
237 {
238 struct ata_port *ap = qc->ap;
239 struct ata_device *adev = qc->dev;
240
241 /*
242 * If the device changed, i.e. slave->master, master->slave,
243 * then set up the DMA mode again so we are sure the timings
244 * are correct.
245 */
246 if (adev != ap->private_data && ata_dma_enabled(adev))
247 ftide010_set_dmamode(ap, adev);
248
249 return ata_bmdma_qc_issue(qc);
250 }
251
252 static struct ata_port_operations pata_ftide010_port_ops = {
253 .inherits = &ata_bmdma_port_ops,
254 .set_dmamode = ftide010_set_dmamode,
255 .set_piomode = ftide010_set_piomode,
256 .qc_issue = ftide010_qc_issue,
257 };
258
259 static struct ata_port_info ftide010_port_info = {
260 .flags = ATA_FLAG_SLAVE_POSS,
261 .mwdma_mask = ATA_MWDMA2,
262 .udma_mask = ATA_UDMA6,
263 .pio_mask = ATA_PIO4,
264 .port_ops = &pata_ftide010_port_ops,
265 };
266
267 #if IS_ENABLED(CONFIG_SATA_GEMINI)
268
pata_ftide010_gemini_port_start(struct ata_port * ap)269 static int pata_ftide010_gemini_port_start(struct ata_port *ap)
270 {
271 struct ftide010 *ftide = ap->host->private_data;
272 struct device *dev = ftide->dev;
273 struct sata_gemini *sg = ftide->sg;
274 int bridges = 0;
275 int ret;
276
277 ret = ata_bmdma_port_start(ap);
278 if (ret)
279 return ret;
280
281 if (ftide->master_to_sata0) {
282 dev_info(dev, "SATA0 (master) start\n");
283 ret = gemini_sata_start_bridge(sg, 0);
284 if (!ret)
285 bridges++;
286 }
287 if (ftide->master_to_sata1) {
288 dev_info(dev, "SATA1 (master) start\n");
289 ret = gemini_sata_start_bridge(sg, 1);
290 if (!ret)
291 bridges++;
292 }
293 /* Avoid double-starting */
294 if (ftide->slave_to_sata0 && !ftide->master_to_sata0) {
295 dev_info(dev, "SATA0 (slave) start\n");
296 ret = gemini_sata_start_bridge(sg, 0);
297 if (!ret)
298 bridges++;
299 }
300 /* Avoid double-starting */
301 if (ftide->slave_to_sata1 && !ftide->master_to_sata1) {
302 dev_info(dev, "SATA1 (slave) start\n");
303 ret = gemini_sata_start_bridge(sg, 1);
304 if (!ret)
305 bridges++;
306 }
307
308 dev_info(dev, "brought %d bridges online\n", bridges);
309 return (bridges > 0) ? 0 : -EINVAL; // -ENODEV;
310 }
311
pata_ftide010_gemini_port_stop(struct ata_port * ap)312 static void pata_ftide010_gemini_port_stop(struct ata_port *ap)
313 {
314 struct ftide010 *ftide = ap->host->private_data;
315 struct device *dev = ftide->dev;
316 struct sata_gemini *sg = ftide->sg;
317
318 if (ftide->master_to_sata0) {
319 dev_info(dev, "SATA0 (master) stop\n");
320 gemini_sata_stop_bridge(sg, 0);
321 }
322 if (ftide->master_to_sata1) {
323 dev_info(dev, "SATA1 (master) stop\n");
324 gemini_sata_stop_bridge(sg, 1);
325 }
326 /* Avoid double-stopping */
327 if (ftide->slave_to_sata0 && !ftide->master_to_sata0) {
328 dev_info(dev, "SATA0 (slave) stop\n");
329 gemini_sata_stop_bridge(sg, 0);
330 }
331 /* Avoid double-stopping */
332 if (ftide->slave_to_sata1 && !ftide->master_to_sata1) {
333 dev_info(dev, "SATA1 (slave) stop\n");
334 gemini_sata_stop_bridge(sg, 1);
335 }
336 }
337
pata_ftide010_gemini_cable_detect(struct ata_port * ap)338 static int pata_ftide010_gemini_cable_detect(struct ata_port *ap)
339 {
340 struct ftide010 *ftide = ap->host->private_data;
341
342 /*
343 * Return the master cable, I have no clue how to return a different
344 * cable for the slave than for the master.
345 */
346 return ftide->master_cbl;
347 }
348
pata_ftide010_gemini_init(struct ftide010 * ftide,struct ata_port_info * pi,bool is_ata1)349 static int pata_ftide010_gemini_init(struct ftide010 *ftide,
350 struct ata_port_info *pi,
351 bool is_ata1)
352 {
353 struct device *dev = ftide->dev;
354 struct sata_gemini *sg;
355 enum gemini_muxmode muxmode;
356
357 /* Look up SATA bridge */
358 sg = gemini_sata_bridge_get();
359 if (IS_ERR(sg))
360 return PTR_ERR(sg);
361 ftide->sg = sg;
362
363 muxmode = gemini_sata_get_muxmode(sg);
364
365 /* Special ops */
366 pata_ftide010_port_ops.port_start =
367 pata_ftide010_gemini_port_start;
368 pata_ftide010_port_ops.port_stop =
369 pata_ftide010_gemini_port_stop;
370 pata_ftide010_port_ops.cable_detect =
371 pata_ftide010_gemini_cable_detect;
372
373 /* Flag port as SATA-capable */
374 if (gemini_sata_bridge_enabled(sg, is_ata1))
375 pi->flags |= ATA_FLAG_SATA;
376
377 /* This device has broken DMA, only PIO works */
378 if (of_machine_is_compatible("itian,sq201")) {
379 pi->mwdma_mask = 0;
380 pi->udma_mask = 0;
381 }
382
383 /*
384 * We assume that a simple 40-wire cable is used in the PATA mode.
385 * if you're adding a system using the PATA interface, make sure
386 * the right cable is set up here, it might be necessary to use
387 * special hardware detection or encode the cable type in the device
388 * tree with special properties.
389 */
390 if (!is_ata1) {
391 switch (muxmode) {
392 case GEMINI_MUXMODE_0:
393 ftide->master_cbl = ATA_CBL_SATA;
394 ftide->slave_cbl = ATA_CBL_PATA40;
395 ftide->master_to_sata0 = true;
396 break;
397 case GEMINI_MUXMODE_1:
398 ftide->master_cbl = ATA_CBL_SATA;
399 ftide->slave_cbl = ATA_CBL_NONE;
400 ftide->master_to_sata0 = true;
401 break;
402 case GEMINI_MUXMODE_2:
403 ftide->master_cbl = ATA_CBL_PATA40;
404 ftide->slave_cbl = ATA_CBL_PATA40;
405 break;
406 case GEMINI_MUXMODE_3:
407 ftide->master_cbl = ATA_CBL_SATA;
408 ftide->slave_cbl = ATA_CBL_SATA;
409 ftide->master_to_sata0 = true;
410 ftide->slave_to_sata1 = true;
411 break;
412 }
413 } else {
414 switch (muxmode) {
415 case GEMINI_MUXMODE_0:
416 ftide->master_cbl = ATA_CBL_SATA;
417 ftide->slave_cbl = ATA_CBL_NONE;
418 ftide->master_to_sata1 = true;
419 break;
420 case GEMINI_MUXMODE_1:
421 ftide->master_cbl = ATA_CBL_SATA;
422 ftide->slave_cbl = ATA_CBL_PATA40;
423 ftide->master_to_sata1 = true;
424 break;
425 case GEMINI_MUXMODE_2:
426 ftide->master_cbl = ATA_CBL_SATA;
427 ftide->slave_cbl = ATA_CBL_SATA;
428 ftide->slave_to_sata0 = true;
429 ftide->master_to_sata1 = true;
430 break;
431 case GEMINI_MUXMODE_3:
432 ftide->master_cbl = ATA_CBL_PATA40;
433 ftide->slave_cbl = ATA_CBL_PATA40;
434 break;
435 }
436 }
437 dev_info(dev, "set up Gemini PATA%d\n", is_ata1);
438
439 return 0;
440 }
441 #else
pata_ftide010_gemini_init(struct ftide010 * ftide,struct ata_port_info * pi,bool is_ata1)442 static int pata_ftide010_gemini_init(struct ftide010 *ftide,
443 struct ata_port_info *pi,
444 bool is_ata1)
445 {
446 return -ENOTSUPP;
447 }
448 #endif
449
450
pata_ftide010_probe(struct platform_device * pdev)451 static int pata_ftide010_probe(struct platform_device *pdev)
452 {
453 struct device *dev = &pdev->dev;
454 struct device_node *np = dev->of_node;
455 struct ata_port_info pi = ftide010_port_info;
456 const struct ata_port_info *ppi[] = { &pi, NULL };
457 struct ftide010 *ftide;
458 struct resource *res;
459 int irq;
460 int ret;
461 int i;
462
463 ftide = devm_kzalloc(dev, sizeof(*ftide), GFP_KERNEL);
464 if (!ftide)
465 return -ENOMEM;
466 ftide->dev = dev;
467
468 irq = platform_get_irq(pdev, 0);
469 if (irq < 0)
470 return irq;
471
472 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
473 if (!res)
474 return -ENODEV;
475
476 ftide->base = devm_ioremap_resource(dev, res);
477 if (IS_ERR(ftide->base))
478 return PTR_ERR(ftide->base);
479
480 ftide->pclk = devm_clk_get(dev, "PCLK");
481 if (!IS_ERR(ftide->pclk)) {
482 ret = clk_prepare_enable(ftide->pclk);
483 if (ret) {
484 dev_err(dev, "failed to enable PCLK\n");
485 return ret;
486 }
487 }
488
489 /* Some special Cortina Gemini init, if needed */
490 if (of_device_is_compatible(np, "cortina,gemini-pata")) {
491 /*
492 * We need to know which instance is probing (the
493 * Gemini has two instances of FTIDE010) and we do
494 * this simply by looking at the physical base
495 * address, which is 0x63400000 for ATA1, else we
496 * are ATA0. This will also set up the cable types.
497 */
498 ret = pata_ftide010_gemini_init(ftide,
499 &pi,
500 (res->start == 0x63400000));
501 if (ret)
502 goto err_dis_clk;
503 } else {
504 /* Else assume we are connected using PATA40 */
505 ftide->master_cbl = ATA_CBL_PATA40;
506 ftide->slave_cbl = ATA_CBL_PATA40;
507 }
508
509 ftide->host = ata_host_alloc_pinfo(dev, ppi, 1);
510 if (!ftide->host) {
511 ret = -ENOMEM;
512 goto err_dis_clk;
513 }
514 ftide->host->private_data = ftide;
515
516 for (i = 0; i < ftide->host->n_ports; i++) {
517 struct ata_port *ap = ftide->host->ports[i];
518 struct ata_ioports *ioaddr = &ap->ioaddr;
519
520 ioaddr->bmdma_addr = ftide->base + FTIDE010_DMA_REG;
521 ioaddr->cmd_addr = ftide->base + FTIDE010_CMD_DATA;
522 ioaddr->ctl_addr = ftide->base + FTIDE010_ALTSTAT_CTRL;
523 ioaddr->altstatus_addr = ftide->base + FTIDE010_ALTSTAT_CTRL;
524 ata_sff_std_ports(ioaddr);
525 }
526
527 dev_info(dev, "device ID %08x, irq %d, reg %pR\n",
528 readl(ftide->base + FTIDE010_IDE_DEVICE_ID), irq, res);
529
530 ret = ata_host_activate(ftide->host, irq, ata_bmdma_interrupt,
531 0, &pata_ftide010_sht);
532 if (ret)
533 goto err_dis_clk;
534
535 return 0;
536
537 err_dis_clk:
538 if (!IS_ERR(ftide->pclk))
539 clk_disable_unprepare(ftide->pclk);
540 return ret;
541 }
542
pata_ftide010_remove(struct platform_device * pdev)543 static int pata_ftide010_remove(struct platform_device *pdev)
544 {
545 struct ata_host *host = platform_get_drvdata(pdev);
546 struct ftide010 *ftide = host->private_data;
547
548 ata_host_detach(ftide->host);
549 if (!IS_ERR(ftide->pclk))
550 clk_disable_unprepare(ftide->pclk);
551
552 return 0;
553 }
554
555 static const struct of_device_id pata_ftide010_of_match[] = {
556 {
557 .compatible = "faraday,ftide010",
558 },
559 {},
560 };
561
562 static struct platform_driver pata_ftide010_driver = {
563 .driver = {
564 .name = DRV_NAME,
565 .of_match_table = of_match_ptr(pata_ftide010_of_match),
566 },
567 .probe = pata_ftide010_probe,
568 .remove = pata_ftide010_remove,
569 };
570 module_platform_driver(pata_ftide010_driver);
571
572 MODULE_AUTHOR("Linus Walleij <linus.walleij@linaro.org>");
573 MODULE_LICENSE("GPL");
574 MODULE_ALIAS("platform:" DRV_NAME);
575
