1/* 2 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 * Based on "omap4.dtsi" 8 */ 9 10#include <dt-bindings/bus/ti-sysc.h> 11#include <dt-bindings/clock/dra7.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13#include <dt-bindings/pinctrl/dra.h> 14#include <dt-bindings/clock/dra7.h> 15 16#define MAX_SOURCES 400 17 18/ { 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 compatible = "ti,dra7xx"; 23 interrupt-parent = <&crossbar_mpu>; 24 chosen { }; 25 26 aliases { 27 i2c0 = &i2c1; 28 i2c1 = &i2c2; 29 i2c2 = &i2c3; 30 i2c3 = &i2c4; 31 i2c4 = &i2c5; 32 serial0 = &uart1; 33 serial1 = &uart2; 34 serial2 = &uart3; 35 serial3 = &uart4; 36 serial4 = &uart5; 37 serial5 = &uart6; 38 serial6 = &uart7; 39 serial7 = &uart8; 40 serial8 = &uart9; 41 serial9 = &uart10; 42 ethernet0 = &cpsw_emac0; 43 ethernet1 = &cpsw_emac1; 44 d_can0 = &dcan1; 45 d_can1 = &dcan2; 46 spi0 = &qspi; 47 }; 48 49 timer { 50 compatible = "arm,armv7-timer"; 51 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 52 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 53 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 54 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; 55 interrupt-parent = <&gic>; 56 }; 57 58 gic: interrupt-controller@48211000 { 59 compatible = "arm,cortex-a15-gic"; 60 interrupt-controller; 61 #interrupt-cells = <3>; 62 reg = <0x0 0x48211000 0x0 0x1000>, 63 <0x0 0x48212000 0x0 0x2000>, 64 <0x0 0x48214000 0x0 0x2000>, 65 <0x0 0x48216000 0x0 0x2000>; 66 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; 67 interrupt-parent = <&gic>; 68 }; 69 70 wakeupgen: interrupt-controller@48281000 { 71 compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu"; 72 interrupt-controller; 73 #interrupt-cells = <3>; 74 reg = <0x0 0x48281000 0x0 0x1000>; 75 interrupt-parent = <&gic>; 76 }; 77 78 cpus { 79 #address-cells = <1>; 80 #size-cells = <0>; 81 82 cpu0: cpu@0 { 83 device_type = "cpu"; 84 compatible = "arm,cortex-a15"; 85 reg = <0>; 86 87 operating-points-v2 = <&cpu0_opp_table>; 88 89 clocks = <&dpll_mpu_ck>; 90 clock-names = "cpu"; 91 92 clock-latency = <300000>; /* From omap-cpufreq driver */ 93 94 /* cooling options */ 95 #cooling-cells = <2>; /* min followed by max */ 96 97 vbb-supply = <&abb_mpu>; 98 }; 99 }; 100 101 cpu0_opp_table: opp-table { 102 compatible = "operating-points-v2-ti-cpu"; 103 syscon = <&scm_wkup>; 104 105 opp_nom-1000000000 { 106 opp-hz = /bits/ 64 <1000000000>; 107 opp-microvolt = <1060000 850000 1150000>, 108 <1060000 850000 1150000>; 109 opp-supported-hw = <0xFF 0x01>; 110 opp-suspend; 111 }; 112 113 opp_od-1176000000 { 114 opp-hz = /bits/ 64 <1176000000>; 115 opp-microvolt = <1160000 885000 1160000>, 116 <1160000 885000 1160000>; 117 118 opp-supported-hw = <0xFF 0x02>; 119 }; 120 121 opp_high@1500000000 { 122 opp-hz = /bits/ 64 <1500000000>; 123 opp-microvolt = <1210000 950000 1250000>, 124 <1210000 950000 1250000>; 125 opp-supported-hw = <0xFF 0x04>; 126 }; 127 }; 128 129 /* 130 * The soc node represents the soc top level view. It is used for IPs 131 * that are not memory mapped in the MPU view or for the MPU itself. 132 */ 133 soc { 134 compatible = "ti,omap-infra"; 135 mpu { 136 compatible = "ti,omap5-mpu"; 137 ti,hwmods = "mpu"; 138 }; 139 }; 140 141 /* 142 * XXX: Use a flat representation of the SOC interconnect. 143 * The real OMAP interconnect network is quite complex. 144 * Since it will not bring real advantage to represent that in DT for 145 * the moment, just use a fake OCP bus entry to represent the whole bus 146 * hierarchy. 147 */ 148 ocp { 149 compatible = "ti,dra7-l3-noc", "simple-bus"; 150 #address-cells = <1>; 151 #size-cells = <1>; 152 ranges = <0x0 0x0 0x0 0xc0000000>; 153 ti,hwmods = "l3_main_1", "l3_main_2"; 154 reg = <0x0 0x44000000 0x0 0x1000000>, 155 <0x0 0x45000000 0x0 0x1000>; 156 interrupts-extended = <&crossbar_mpu GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 157 <&wakeupgen GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 158 159 l4_cfg: l4@4a000000 { 160 compatible = "ti,dra7-l4-cfg", "simple-bus"; 161 #address-cells = <1>; 162 #size-cells = <1>; 163 ranges = <0 0x4a000000 0x22c000>; 164 165 scm: scm@2000 { 166 compatible = "ti,dra7-scm-core", "simple-bus"; 167 reg = <0x2000 0x2000>; 168 #address-cells = <1>; 169 #size-cells = <1>; 170 ranges = <0 0x2000 0x2000>; 171 172 scm_conf: scm_conf@0 { 173 compatible = "syscon", "simple-bus"; 174 reg = <0x0 0x1400>; 175 #address-cells = <1>; 176 #size-cells = <1>; 177 ranges = <0 0x0 0x1400>; 178 179 pbias_regulator: pbias_regulator@e00 { 180 compatible = "ti,pbias-dra7", "ti,pbias-omap"; 181 reg = <0xe00 0x4>; 182 syscon = <&scm_conf>; 183 pbias_mmc_reg: pbias_mmc_omap5 { 184 regulator-name = "pbias_mmc_omap5"; 185 regulator-min-microvolt = <1800000>; 186 regulator-max-microvolt = <3300000>; 187 }; 188 }; 189 190 scm_conf_clocks: clocks { 191 #address-cells = <1>; 192 #size-cells = <0>; 193 }; 194 }; 195 196 dra7_pmx_core: pinmux@1400 { 197 compatible = "ti,dra7-padconf", 198 "pinctrl-single"; 199 reg = <0x1400 0x0468>; 200 #address-cells = <1>; 201 #size-cells = <0>; 202 #pinctrl-cells = <1>; 203 #interrupt-cells = <1>; 204 interrupt-controller; 205 pinctrl-single,register-width = <32>; 206 pinctrl-single,function-mask = <0x3fffffff>; 207 }; 208 209 scm_conf1: scm_conf@1c04 { 210 compatible = "syscon"; 211 reg = <0x1c04 0x0020>; 212 #syscon-cells = <2>; 213 }; 214 215 scm_conf_pcie: scm_conf@1c24 { 216 compatible = "syscon"; 217 reg = <0x1c24 0x0024>; 218 }; 219 220 sdma_xbar: dma-router@b78 { 221 compatible = "ti,dra7-dma-crossbar"; 222 reg = <0xb78 0xfc>; 223 #dma-cells = <1>; 224 dma-requests = <205>; 225 ti,dma-safe-map = <0>; 226 dma-masters = <&sdma>; 227 }; 228 229 edma_xbar: dma-router@c78 { 230 compatible = "ti,dra7-dma-crossbar"; 231 reg = <0xc78 0x7c>; 232 #dma-cells = <2>; 233 dma-requests = <204>; 234 ti,dma-safe-map = <0>; 235 dma-masters = <&edma>; 236 }; 237 }; 238 239 cm_core_aon: cm_core_aon@5000 { 240 compatible = "ti,dra7-cm-core-aon", 241 "simple-bus"; 242 #address-cells = <1>; 243 #size-cells = <1>; 244 reg = <0x5000 0x2000>; 245 ranges = <0 0x5000 0x2000>; 246 247 cm_core_aon_clocks: clocks { 248 #address-cells = <1>; 249 #size-cells = <0>; 250 }; 251 252 cm_core_aon_clockdomains: clockdomains { 253 }; 254 }; 255 256 cm_core: cm_core@8000 { 257 compatible = "ti,dra7-cm-core", "simple-bus"; 258 #address-cells = <1>; 259 #size-cells = <1>; 260 reg = <0x8000 0x3000>; 261 ranges = <0 0x8000 0x3000>; 262 263 cm_core_clocks: clocks { 264 #address-cells = <1>; 265 #size-cells = <0>; 266 }; 267 268 cm_core_clockdomains: clockdomains { 269 }; 270 }; 271 }; 272 273 l4_wkup: l4@4ae00000 { 274 compatible = "ti,dra7-l4-wkup", "simple-bus"; 275 #address-cells = <1>; 276 #size-cells = <1>; 277 ranges = <0 0x4ae00000 0x3f000>; 278 279 counter32k: counter@4000 { 280 compatible = "ti,omap-counter32k"; 281 reg = <0x4000 0x40>; 282 ti,hwmods = "counter_32k"; 283 }; 284 285 prm: prm@6000 { 286 compatible = "ti,dra7-prm", "simple-bus"; 287 reg = <0x6000 0x3000>; 288 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 289 #address-cells = <1>; 290 #size-cells = <1>; 291 ranges = <0 0x6000 0x3000>; 292 293 prm_clocks: clocks { 294 #address-cells = <1>; 295 #size-cells = <0>; 296 }; 297 298 prm_clockdomains: clockdomains { 299 }; 300 }; 301 302 scm_wkup: scm_conf@c000 { 303 compatible = "syscon"; 304 reg = <0xc000 0x1000>; 305 }; 306 }; 307 308 axi@0 { 309 compatible = "simple-bus"; 310 #size-cells = <1>; 311 #address-cells = <1>; 312 ranges = <0x51000000 0x51000000 0x3000 313 0x0 0x20000000 0x10000000>; 314 /** 315 * To enable PCI endpoint mode, disable the pcie1_rc 316 * node and enable pcie1_ep mode. 317 */ 318 pcie1_rc: pcie@51000000 { 319 reg = <0x51000000 0x2000>, <0x51002000 0x14c>, <0x1000 0x2000>; 320 reg-names = "rc_dbics", "ti_conf", "config"; 321 interrupts = <0 232 0x4>, <0 233 0x4>; 322 #address-cells = <3>; 323 #size-cells = <2>; 324 device_type = "pci"; 325 ranges = <0x81000000 0 0 0x03000 0 0x00010000 326 0x82000000 0 0x20013000 0x13000 0 0xffed000>; 327 bus-range = <0x00 0xff>; 328 #interrupt-cells = <1>; 329 num-lanes = <1>; 330 linux,pci-domain = <0>; 331 ti,hwmods = "pcie1"; 332 phys = <&pcie1_phy>; 333 phy-names = "pcie-phy0"; 334 interrupt-map-mask = <0 0 0 7>; 335 interrupt-map = <0 0 0 1 &pcie1_intc 1>, 336 <0 0 0 2 &pcie1_intc 2>, 337 <0 0 0 3 &pcie1_intc 3>, 338 <0 0 0 4 &pcie1_intc 4>; 339 status = "disabled"; 340 pcie1_intc: interrupt-controller { 341 interrupt-controller; 342 #address-cells = <0>; 343 #interrupt-cells = <1>; 344 }; 345 }; 346 347 pcie1_ep: pcie_ep@51000000 { 348 reg = <0x51000000 0x28>, <0x51002000 0x14c>, <0x51001000 0x28>, <0x1000 0x10000000>; 349 reg-names = "ep_dbics", "ti_conf", "ep_dbics2", "addr_space"; 350 interrupts = <0 232 0x4>; 351 num-lanes = <1>; 352 num-ib-windows = <4>; 353 num-ob-windows = <16>; 354 ti,hwmods = "pcie1"; 355 phys = <&pcie1_phy>; 356 phy-names = "pcie-phy0"; 357 ti,syscon-unaligned-access = <&scm_conf1 0x14 2>; 358 status = "disabled"; 359 }; 360 }; 361 362 axi@1 { 363 compatible = "simple-bus"; 364 #size-cells = <1>; 365 #address-cells = <1>; 366 ranges = <0x51800000 0x51800000 0x3000 367 0x0 0x30000000 0x10000000>; 368 status = "disabled"; 369 pcie2_rc: pcie@51800000 { 370 reg = <0x51800000 0x2000>, <0x51802000 0x14c>, <0x1000 0x2000>; 371 reg-names = "rc_dbics", "ti_conf", "config"; 372 interrupts = <0 355 0x4>, <0 356 0x4>; 373 #address-cells = <3>; 374 #size-cells = <2>; 375 device_type = "pci"; 376 ranges = <0x81000000 0 0 0x03000 0 0x00010000 377 0x82000000 0 0x30013000 0x13000 0 0xffed000>; 378 bus-range = <0x00 0xff>; 379 #interrupt-cells = <1>; 380 num-lanes = <1>; 381 linux,pci-domain = <1>; 382 ti,hwmods = "pcie2"; 383 phys = <&pcie2_phy>; 384 phy-names = "pcie-phy0"; 385 interrupt-map-mask = <0 0 0 7>; 386 interrupt-map = <0 0 0 1 &pcie2_intc 1>, 387 <0 0 0 2 &pcie2_intc 2>, 388 <0 0 0 3 &pcie2_intc 3>, 389 <0 0 0 4 &pcie2_intc 4>; 390 pcie2_intc: interrupt-controller { 391 interrupt-controller; 392 #address-cells = <0>; 393 #interrupt-cells = <1>; 394 }; 395 }; 396 }; 397 398 ocmcram1: ocmcram@40300000 { 399 compatible = "mmio-sram"; 400 reg = <0x40300000 0x80000>; 401 ranges = <0x0 0x40300000 0x80000>; 402 #address-cells = <1>; 403 #size-cells = <1>; 404 /* 405 * This is a placeholder for an optional reserved 406 * region for use by secure software. The size 407 * of this region is not known until runtime so it 408 * is set as zero to either be updated to reserve 409 * space or left unchanged to leave all SRAM for use. 410 * On HS parts that that require the reserved region 411 * either the bootloader can update the size to 412 * the required amount or the node can be overridden 413 * from the board dts file for the secure platform. 414 */ 415 sram-hs@0 { 416 compatible = "ti,secure-ram"; 417 reg = <0x0 0x0>; 418 }; 419 }; 420 421 /* 422 * NOTE: ocmcram2 and ocmcram3 are not available on all 423 * DRA7xx and AM57xx variants. Confirm availability in 424 * the data manual for the exact part number in use 425 * before enabling these nodes in the board dts file. 426 */ 427 ocmcram2: ocmcram@40400000 { 428 status = "disabled"; 429 compatible = "mmio-sram"; 430 reg = <0x40400000 0x100000>; 431 ranges = <0x0 0x40400000 0x100000>; 432 #address-cells = <1>; 433 #size-cells = <1>; 434 }; 435 436 ocmcram3: ocmcram@40500000 { 437 status = "disabled"; 438 compatible = "mmio-sram"; 439 reg = <0x40500000 0x100000>; 440 ranges = <0x0 0x40500000 0x100000>; 441 #address-cells = <1>; 442 #size-cells = <1>; 443 }; 444 445 bandgap: bandgap@4a0021e0 { 446 reg = <0x4a0021e0 0xc 447 0x4a00232c 0xc 448 0x4a002380 0x2c 449 0x4a0023C0 0x3c 450 0x4a002564 0x8 451 0x4a002574 0x50>; 452 compatible = "ti,dra752-bandgap"; 453 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 454 #thermal-sensor-cells = <1>; 455 }; 456 457 dsp1_system: dsp_system@40d00000 { 458 compatible = "syscon"; 459 reg = <0x40d00000 0x100>; 460 }; 461 462 dra7_iodelay_core: padconf@4844a000 { 463 compatible = "ti,dra7-iodelay"; 464 reg = <0x4844a000 0x0d1c>; 465 #address-cells = <1>; 466 #size-cells = <0>; 467 #pinctrl-cells = <2>; 468 }; 469 470 sdma: dma-controller@4a056000 { 471 compatible = "ti,omap4430-sdma"; 472 reg = <0x4a056000 0x1000>; 473 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 474 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 475 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 476 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 477 #dma-cells = <1>; 478 dma-channels = <32>; 479 dma-requests = <127>; 480 ti,hwmods = "dma_system"; 481 }; 482 483 edma: edma@43300000 { 484 compatible = "ti,edma3-tpcc"; 485 ti,hwmods = "tpcc"; 486 reg = <0x43300000 0x100000>; 487 reg-names = "edma3_cc"; 488 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>, 489 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, 490 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 491 interrupt-names = "edma3_ccint", "edma3_mperr", 492 "edma3_ccerrint"; 493 dma-requests = <64>; 494 #dma-cells = <2>; 495 496 ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 0>; 497 498 /* 499 * memcpy is disabled, can be enabled with: 500 * ti,edma-memcpy-channels = <20 21>; 501 * for example. Note that these channels need to be 502 * masked in the xbar as well. 503 */ 504 }; 505 506 edma_tptc0: tptc@43400000 { 507 compatible = "ti,edma3-tptc"; 508 ti,hwmods = "tptc0"; 509 reg = <0x43400000 0x100000>; 510 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>; 511 interrupt-names = "edma3_tcerrint"; 512 }; 513 514 edma_tptc1: tptc@43500000 { 515 compatible = "ti,edma3-tptc"; 516 ti,hwmods = "tptc1"; 517 reg = <0x43500000 0x100000>; 518 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; 519 interrupt-names = "edma3_tcerrint"; 520 }; 521 522 gpio1: gpio@4ae10000 { 523 compatible = "ti,omap4-gpio"; 524 reg = <0x4ae10000 0x200>; 525 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 526 ti,hwmods = "gpio1"; 527 gpio-controller; 528 #gpio-cells = <2>; 529 interrupt-controller; 530 #interrupt-cells = <2>; 531 }; 532 533 gpio2: gpio@48055000 { 534 compatible = "ti,omap4-gpio"; 535 reg = <0x48055000 0x200>; 536 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 537 ti,hwmods = "gpio2"; 538 gpio-controller; 539 #gpio-cells = <2>; 540 interrupt-controller; 541 #interrupt-cells = <2>; 542 }; 543 544 gpio3: gpio@48057000 { 545 compatible = "ti,omap4-gpio"; 546 reg = <0x48057000 0x200>; 547 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 548 ti,hwmods = "gpio3"; 549 gpio-controller; 550 #gpio-cells = <2>; 551 interrupt-controller; 552 #interrupt-cells = <2>; 553 }; 554 555 gpio4: gpio@48059000 { 556 compatible = "ti,omap4-gpio"; 557 reg = <0x48059000 0x200>; 558 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 559 ti,hwmods = "gpio4"; 560 gpio-controller; 561 #gpio-cells = <2>; 562 interrupt-controller; 563 #interrupt-cells = <2>; 564 }; 565 566 gpio5: gpio@4805b000 { 567 compatible = "ti,omap4-gpio"; 568 reg = <0x4805b000 0x200>; 569 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 570 ti,hwmods = "gpio5"; 571 gpio-controller; 572 #gpio-cells = <2>; 573 interrupt-controller; 574 #interrupt-cells = <2>; 575 }; 576 577 gpio6: gpio@4805d000 { 578 compatible = "ti,omap4-gpio"; 579 reg = <0x4805d000 0x200>; 580 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 581 ti,hwmods = "gpio6"; 582 gpio-controller; 583 #gpio-cells = <2>; 584 interrupt-controller; 585 #interrupt-cells = <2>; 586 }; 587 588 gpio7: gpio@48051000 { 589 compatible = "ti,omap4-gpio"; 590 reg = <0x48051000 0x200>; 591 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 592 ti,hwmods = "gpio7"; 593 gpio-controller; 594 #gpio-cells = <2>; 595 interrupt-controller; 596 #interrupt-cells = <2>; 597 }; 598 599 gpio8: gpio@48053000 { 600 compatible = "ti,omap4-gpio"; 601 reg = <0x48053000 0x200>; 602 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 603 ti,hwmods = "gpio8"; 604 gpio-controller; 605 #gpio-cells = <2>; 606 interrupt-controller; 607 #interrupt-cells = <2>; 608 }; 609 610 uart1: serial@4806a000 { 611 compatible = "ti,dra742-uart", "ti,omap4-uart"; 612 reg = <0x4806a000 0x100>; 613 interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 614 ti,hwmods = "uart1"; 615 clock-frequency = <48000000>; 616 status = "disabled"; 617 dmas = <&sdma_xbar 49>, <&sdma_xbar 50>; 618 dma-names = "tx", "rx"; 619 }; 620 621 uart2: serial@4806c000 { 622 compatible = "ti,dra742-uart", "ti,omap4-uart"; 623 reg = <0x4806c000 0x100>; 624 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 625 ti,hwmods = "uart2"; 626 clock-frequency = <48000000>; 627 status = "disabled"; 628 dmas = <&sdma_xbar 51>, <&sdma_xbar 52>; 629 dma-names = "tx", "rx"; 630 }; 631 632 uart3: serial@48020000 { 633 compatible = "ti,dra742-uart", "ti,omap4-uart"; 634 reg = <0x48020000 0x100>; 635 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 636 ti,hwmods = "uart3"; 637 clock-frequency = <48000000>; 638 status = "disabled"; 639 dmas = <&sdma_xbar 53>, <&sdma_xbar 54>; 640 dma-names = "tx", "rx"; 641 }; 642 643 uart4: serial@4806e000 { 644 compatible = "ti,dra742-uart", "ti,omap4-uart"; 645 reg = <0x4806e000 0x100>; 646 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 647 ti,hwmods = "uart4"; 648 clock-frequency = <48000000>; 649 status = "disabled"; 650 dmas = <&sdma_xbar 55>, <&sdma_xbar 56>; 651 dma-names = "tx", "rx"; 652 }; 653 654 uart5: serial@48066000 { 655 compatible = "ti,dra742-uart", "ti,omap4-uart"; 656 reg = <0x48066000 0x100>; 657 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 658 ti,hwmods = "uart5"; 659 clock-frequency = <48000000>; 660 status = "disabled"; 661 dmas = <&sdma_xbar 63>, <&sdma_xbar 64>; 662 dma-names = "tx", "rx"; 663 }; 664 665 uart6: serial@48068000 { 666 compatible = "ti,dra742-uart", "ti,omap4-uart"; 667 reg = <0x48068000 0x100>; 668 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 669 ti,hwmods = "uart6"; 670 clock-frequency = <48000000>; 671 status = "disabled"; 672 dmas = <&sdma_xbar 79>, <&sdma_xbar 80>; 673 dma-names = "tx", "rx"; 674 }; 675 676 uart7: serial@48420000 { 677 compatible = "ti,dra742-uart", "ti,omap4-uart"; 678 reg = <0x48420000 0x100>; 679 interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>; 680 ti,hwmods = "uart7"; 681 clock-frequency = <48000000>; 682 status = "disabled"; 683 }; 684 685 uart8: serial@48422000 { 686 compatible = "ti,dra742-uart", "ti,omap4-uart"; 687 reg = <0x48422000 0x100>; 688 interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>; 689 ti,hwmods = "uart8"; 690 clock-frequency = <48000000>; 691 status = "disabled"; 692 }; 693 694 uart9: serial@48424000 { 695 compatible = "ti,dra742-uart", "ti,omap4-uart"; 696 reg = <0x48424000 0x100>; 697 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>; 698 ti,hwmods = "uart9"; 699 clock-frequency = <48000000>; 700 status = "disabled"; 701 }; 702 703 uart10: serial@4ae2b000 { 704 compatible = "ti,dra742-uart", "ti,omap4-uart"; 705 reg = <0x4ae2b000 0x100>; 706 interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 707 ti,hwmods = "uart10"; 708 clock-frequency = <48000000>; 709 status = "disabled"; 710 }; 711 712 mailbox1: mailbox@4a0f4000 { 713 compatible = "ti,omap4-mailbox"; 714 reg = <0x4a0f4000 0x200>; 715 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 716 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 717 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 718 ti,hwmods = "mailbox1"; 719 #mbox-cells = <1>; 720 ti,mbox-num-users = <3>; 721 ti,mbox-num-fifos = <8>; 722 status = "disabled"; 723 }; 724 725 mailbox2: mailbox@4883a000 { 726 compatible = "ti,omap4-mailbox"; 727 reg = <0x4883a000 0x200>; 728 interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>, 729 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 730 <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>, 731 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 732 ti,hwmods = "mailbox2"; 733 #mbox-cells = <1>; 734 ti,mbox-num-users = <4>; 735 ti,mbox-num-fifos = <12>; 736 status = "disabled"; 737 }; 738 739 mailbox3: mailbox@4883c000 { 740 compatible = "ti,omap4-mailbox"; 741 reg = <0x4883c000 0x200>; 742 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>, 743 <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>, 744 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>, 745 <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>; 746 ti,hwmods = "mailbox3"; 747 #mbox-cells = <1>; 748 ti,mbox-num-users = <4>; 749 ti,mbox-num-fifos = <12>; 750 status = "disabled"; 751 }; 752 753 mailbox4: mailbox@4883e000 { 754 compatible = "ti,omap4-mailbox"; 755 reg = <0x4883e000 0x200>; 756 interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 757 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 758 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 759 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>; 760 ti,hwmods = "mailbox4"; 761 #mbox-cells = <1>; 762 ti,mbox-num-users = <4>; 763 ti,mbox-num-fifos = <12>; 764 status = "disabled"; 765 }; 766 767 mailbox5: mailbox@48840000 { 768 compatible = "ti,omap4-mailbox"; 769 reg = <0x48840000 0x200>; 770 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 771 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 772 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 773 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>; 774 ti,hwmods = "mailbox5"; 775 #mbox-cells = <1>; 776 ti,mbox-num-users = <4>; 777 ti,mbox-num-fifos = <12>; 778 status = "disabled"; 779 }; 780 781 mailbox6: mailbox@48842000 { 782 compatible = "ti,omap4-mailbox"; 783 reg = <0x48842000 0x200>; 784 interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 785 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 786 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 787 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; 788 ti,hwmods = "mailbox6"; 789 #mbox-cells = <1>; 790 ti,mbox-num-users = <4>; 791 ti,mbox-num-fifos = <12>; 792 status = "disabled"; 793 }; 794 795 mailbox7: mailbox@48844000 { 796 compatible = "ti,omap4-mailbox"; 797 reg = <0x48844000 0x200>; 798 interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, 799 <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, 800 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, 801 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>; 802 ti,hwmods = "mailbox7"; 803 #mbox-cells = <1>; 804 ti,mbox-num-users = <4>; 805 ti,mbox-num-fifos = <12>; 806 status = "disabled"; 807 }; 808 809 mailbox8: mailbox@48846000 { 810 compatible = "ti,omap4-mailbox"; 811 reg = <0x48846000 0x200>; 812 interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 813 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 814 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, 815 <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>; 816 ti,hwmods = "mailbox8"; 817 #mbox-cells = <1>; 818 ti,mbox-num-users = <4>; 819 ti,mbox-num-fifos = <12>; 820 status = "disabled"; 821 }; 822 823 mailbox9: mailbox@4885e000 { 824 compatible = "ti,omap4-mailbox"; 825 reg = <0x4885e000 0x200>; 826 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 827 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, 828 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, 829 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; 830 ti,hwmods = "mailbox9"; 831 #mbox-cells = <1>; 832 ti,mbox-num-users = <4>; 833 ti,mbox-num-fifos = <12>; 834 status = "disabled"; 835 }; 836 837 mailbox10: mailbox@48860000 { 838 compatible = "ti,omap4-mailbox"; 839 reg = <0x48860000 0x200>; 840 interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>, 841 <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>, 842 <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>, 843 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 844 ti,hwmods = "mailbox10"; 845 #mbox-cells = <1>; 846 ti,mbox-num-users = <4>; 847 ti,mbox-num-fifos = <12>; 848 status = "disabled"; 849 }; 850 851 mailbox11: mailbox@48862000 { 852 compatible = "ti,omap4-mailbox"; 853 reg = <0x48862000 0x200>; 854 interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, 855 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, 856 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, 857 <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>; 858 ti,hwmods = "mailbox11"; 859 #mbox-cells = <1>; 860 ti,mbox-num-users = <4>; 861 ti,mbox-num-fifos = <12>; 862 status = "disabled"; 863 }; 864 865 mailbox12: mailbox@48864000 { 866 compatible = "ti,omap4-mailbox"; 867 reg = <0x48864000 0x200>; 868 interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>, 869 <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, 870 <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 871 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>; 872 ti,hwmods = "mailbox12"; 873 #mbox-cells = <1>; 874 ti,mbox-num-users = <4>; 875 ti,mbox-num-fifos = <12>; 876 status = "disabled"; 877 }; 878 879 mailbox13: mailbox@48802000 { 880 compatible = "ti,omap4-mailbox"; 881 reg = <0x48802000 0x200>; 882 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>, 883 <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>, 884 <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>, 885 <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>; 886 ti,hwmods = "mailbox13"; 887 #mbox-cells = <1>; 888 ti,mbox-num-users = <4>; 889 ti,mbox-num-fifos = <12>; 890 status = "disabled"; 891 }; 892 893 timer1: timer@4ae18000 { 894 compatible = "ti,omap5430-timer"; 895 reg = <0x4ae18000 0x80>; 896 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 897 ti,hwmods = "timer1"; 898 ti,timer-alwon; 899 clock-names = "fck"; 900 clocks = <&wkupaon_clkctrl DRA7_TIMER1_CLKCTRL 24>; 901 }; 902 903 timer2: timer@48032000 { 904 compatible = "ti,omap5430-timer"; 905 reg = <0x48032000 0x80>; 906 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 907 ti,hwmods = "timer2"; 908 }; 909 910 timer3: timer@48034000 { 911 compatible = "ti,omap5430-timer"; 912 reg = <0x48034000 0x80>; 913 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 914 ti,hwmods = "timer3"; 915 }; 916 917 timer4: timer@48036000 { 918 compatible = "ti,omap5430-timer"; 919 reg = <0x48036000 0x80>; 920 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 921 ti,hwmods = "timer4"; 922 }; 923 924 timer5: timer@48820000 { 925 compatible = "ti,omap5430-timer"; 926 reg = <0x48820000 0x80>; 927 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 928 ti,hwmods = "timer5"; 929 }; 930 931 timer6: timer@48822000 { 932 compatible = "ti,omap5430-timer"; 933 reg = <0x48822000 0x80>; 934 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 935 ti,hwmods = "timer6"; 936 }; 937 938 timer7: timer@48824000 { 939 compatible = "ti,omap5430-timer"; 940 reg = <0x48824000 0x80>; 941 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 942 ti,hwmods = "timer7"; 943 }; 944 945 timer8: timer@48826000 { 946 compatible = "ti,omap5430-timer"; 947 reg = <0x48826000 0x80>; 948 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 949 ti,hwmods = "timer8"; 950 }; 951 952 timer9: timer@4803e000 { 953 compatible = "ti,omap5430-timer"; 954 reg = <0x4803e000 0x80>; 955 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 956 ti,hwmods = "timer9"; 957 }; 958 959 timer10: timer@48086000 { 960 compatible = "ti,omap5430-timer"; 961 reg = <0x48086000 0x80>; 962 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 963 ti,hwmods = "timer10"; 964 }; 965 966 timer11: timer@48088000 { 967 compatible = "ti,omap5430-timer"; 968 reg = <0x48088000 0x80>; 969 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 970 ti,hwmods = "timer11"; 971 }; 972 973 timer12: timer@4ae20000 { 974 compatible = "ti,omap5430-timer"; 975 reg = <0x4ae20000 0x80>; 976 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 977 ti,hwmods = "timer12"; 978 ti,timer-alwon; 979 ti,timer-secure; 980 }; 981 982 timer13: timer@48828000 { 983 compatible = "ti,omap5430-timer"; 984 reg = <0x48828000 0x80>; 985 interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>; 986 ti,hwmods = "timer13"; 987 }; 988 989 timer14: timer@4882a000 { 990 compatible = "ti,omap5430-timer"; 991 reg = <0x4882a000 0x80>; 992 interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>; 993 ti,hwmods = "timer14"; 994 }; 995 996 timer15: timer@4882c000 { 997 compatible = "ti,omap5430-timer"; 998 reg = <0x4882c000 0x80>; 999 interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>; 1000 ti,hwmods = "timer15"; 1001 }; 1002 1003 timer16: timer@4882e000 { 1004 compatible = "ti,omap5430-timer"; 1005 reg = <0x4882e000 0x80>; 1006 interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>; 1007 ti,hwmods = "timer16"; 1008 }; 1009 1010 wdt2: wdt@4ae14000 { 1011 compatible = "ti,omap3-wdt"; 1012 reg = <0x4ae14000 0x80>; 1013 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 1014 ti,hwmods = "wd_timer2"; 1015 }; 1016 1017 hwspinlock: spinlock@4a0f6000 { 1018 compatible = "ti,omap4-hwspinlock"; 1019 reg = <0x4a0f6000 0x1000>; 1020 ti,hwmods = "spinlock"; 1021 #hwlock-cells = <1>; 1022 }; 1023 1024 dmm@4e000000 { 1025 compatible = "ti,omap5-dmm"; 1026 reg = <0x4e000000 0x800>; 1027 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1028 ti,hwmods = "dmm"; 1029 }; 1030 1031 i2c1: i2c@48070000 { 1032 compatible = "ti,omap4-i2c"; 1033 reg = <0x48070000 0x100>; 1034 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 1035 #address-cells = <1>; 1036 #size-cells = <0>; 1037 ti,hwmods = "i2c1"; 1038 status = "disabled"; 1039 }; 1040 1041 i2c2: i2c@48072000 { 1042 compatible = "ti,omap4-i2c"; 1043 reg = <0x48072000 0x100>; 1044 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 1045 #address-cells = <1>; 1046 #size-cells = <0>; 1047 ti,hwmods = "i2c2"; 1048 status = "disabled"; 1049 }; 1050 1051 i2c3: i2c@48060000 { 1052 compatible = "ti,omap4-i2c"; 1053 reg = <0x48060000 0x100>; 1054 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 1055 #address-cells = <1>; 1056 #size-cells = <0>; 1057 ti,hwmods = "i2c3"; 1058 status = "disabled"; 1059 }; 1060 1061 i2c4: i2c@4807a000 { 1062 compatible = "ti,omap4-i2c"; 1063 reg = <0x4807a000 0x100>; 1064 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 1065 #address-cells = <1>; 1066 #size-cells = <0>; 1067 ti,hwmods = "i2c4"; 1068 status = "disabled"; 1069 }; 1070 1071 i2c5: i2c@4807c000 { 1072 compatible = "ti,omap4-i2c"; 1073 reg = <0x4807c000 0x100>; 1074 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 1075 #address-cells = <1>; 1076 #size-cells = <0>; 1077 ti,hwmods = "i2c5"; 1078 status = "disabled"; 1079 }; 1080 1081 mmc1: mmc@4809c000 { 1082 compatible = "ti,dra7-sdhci"; 1083 reg = <0x4809c000 0x400>; 1084 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 1085 ti,hwmods = "mmc1"; 1086 status = "disabled"; 1087 pbias-supply = <&pbias_mmc_reg>; 1088 max-frequency = <192000000>; 1089 mmc-ddr-1_8v; 1090 mmc-ddr-3_3v; 1091 }; 1092 1093 hdqw1w: 1w@480b2000 { 1094 compatible = "ti,omap3-1w"; 1095 reg = <0x480b2000 0x1000>; 1096 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 1097 ti,hwmods = "hdq1w"; 1098 }; 1099 1100 mmc2: mmc@480b4000 { 1101 compatible = "ti,dra7-sdhci"; 1102 reg = <0x480b4000 0x400>; 1103 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 1104 ti,hwmods = "mmc2"; 1105 status = "disabled"; 1106 max-frequency = <192000000>; 1107 /* SDR104/DDR50/SDR50 bits in CAPA2 is not supported */ 1108 sdhci-caps-mask = <0x7 0x0>; 1109 mmc-hs200-1_8v; 1110 mmc-ddr-1_8v; 1111 mmc-ddr-3_3v; 1112 }; 1113 1114 mmc3: mmc@480ad000 { 1115 compatible = "ti,dra7-sdhci"; 1116 reg = <0x480ad000 0x400>; 1117 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 1118 ti,hwmods = "mmc3"; 1119 status = "disabled"; 1120 /* Errata i887 limits max-frequency of MMC3 to 64 MHz */ 1121 max-frequency = <64000000>; 1122 /* SDMA is not supported */ 1123 sdhci-caps-mask = <0x0 0x400000>; 1124 }; 1125 1126 mmc4: mmc@480d1000 { 1127 compatible = "ti,dra7-sdhci"; 1128 reg = <0x480d1000 0x400>; 1129 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 1130 ti,hwmods = "mmc4"; 1131 status = "disabled"; 1132 max-frequency = <192000000>; 1133 /* SDMA is not supported */ 1134 sdhci-caps-mask = <0x0 0x400000>; 1135 }; 1136 1137 mmu0_dsp1: mmu@40d01000 { 1138 compatible = "ti,dra7-dsp-iommu"; 1139 reg = <0x40d01000 0x100>; 1140 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1141 ti,hwmods = "mmu0_dsp1"; 1142 #iommu-cells = <0>; 1143 ti,syscon-mmuconfig = <&dsp1_system 0x0>; 1144 status = "disabled"; 1145 }; 1146 1147 mmu1_dsp1: mmu@40d02000 { 1148 compatible = "ti,dra7-dsp-iommu"; 1149 reg = <0x40d02000 0x100>; 1150 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 1151 ti,hwmods = "mmu1_dsp1"; 1152 #iommu-cells = <0>; 1153 ti,syscon-mmuconfig = <&dsp1_system 0x1>; 1154 status = "disabled"; 1155 }; 1156 1157 mmu_ipu1: mmu@58882000 { 1158 compatible = "ti,dra7-iommu"; 1159 reg = <0x58882000 0x100>; 1160 interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>; 1161 ti,hwmods = "mmu_ipu1"; 1162 #iommu-cells = <0>; 1163 ti,iommu-bus-err-back; 1164 status = "disabled"; 1165 }; 1166 1167 mmu_ipu2: mmu@55082000 { 1168 compatible = "ti,dra7-iommu"; 1169 reg = <0x55082000 0x100>; 1170 interrupts = <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>; 1171 ti,hwmods = "mmu_ipu2"; 1172 #iommu-cells = <0>; 1173 ti,iommu-bus-err-back; 1174 status = "disabled"; 1175 }; 1176 1177 abb_mpu: regulator-abb-mpu { 1178 compatible = "ti,abb-v3"; 1179 regulator-name = "abb_mpu"; 1180 #address-cells = <0>; 1181 #size-cells = <0>; 1182 clocks = <&sys_clkin1>; 1183 ti,settling-time = <50>; 1184 ti,clock-cycles = <16>; 1185 1186 reg = <0x4ae07ddc 0x4>, <0x4ae07de0 0x4>, 1187 <0x4ae06014 0x4>, <0x4a003b20 0xc>, 1188 <0x4ae0c158 0x4>; 1189 reg-names = "setup-address", "control-address", 1190 "int-address", "efuse-address", 1191 "ldo-address"; 1192 ti,tranxdone-status-mask = <0x80>; 1193 /* LDOVBBMPU_FBB_MUX_CTRL */ 1194 ti,ldovbb-override-mask = <0x400>; 1195 /* LDOVBBMPU_FBB_VSET_OUT */ 1196 ti,ldovbb-vset-mask = <0x1F>; 1197 1198 /* 1199 * NOTE: only FBB mode used but actual vset will 1200 * determine final biasing 1201 */ 1202 ti,abb_info = < 1203 /*uV ABB efuse rbb_m fbb_m vset_m*/ 1204 1060000 0 0x0 0 0x02000000 0x01F00000 1205 1160000 0 0x4 0 0x02000000 0x01F00000 1206 1210000 0 0x8 0 0x02000000 0x01F00000 1207 >; 1208 }; 1209 1210 abb_ivahd: regulator-abb-ivahd { 1211 compatible = "ti,abb-v3"; 1212 regulator-name = "abb_ivahd"; 1213 #address-cells = <0>; 1214 #size-cells = <0>; 1215 clocks = <&sys_clkin1>; 1216 ti,settling-time = <50>; 1217 ti,clock-cycles = <16>; 1218 1219 reg = <0x4ae07e34 0x4>, <0x4ae07e24 0x4>, 1220 <0x4ae06010 0x4>, <0x4a0025cc 0xc>, 1221 <0x4a002470 0x4>; 1222 reg-names = "setup-address", "control-address", 1223 "int-address", "efuse-address", 1224 "ldo-address"; 1225 ti,tranxdone-status-mask = <0x40000000>; 1226 /* LDOVBBIVA_FBB_MUX_CTRL */ 1227 ti,ldovbb-override-mask = <0x400>; 1228 /* LDOVBBIVA_FBB_VSET_OUT */ 1229 ti,ldovbb-vset-mask = <0x1F>; 1230 1231 /* 1232 * NOTE: only FBB mode used but actual vset will 1233 * determine final biasing 1234 */ 1235 ti,abb_info = < 1236 /*uV ABB efuse rbb_m fbb_m vset_m*/ 1237 1055000 0 0x0 0 0x02000000 0x01F00000 1238 1150000 0 0x4 0 0x02000000 0x01F00000 1239 1250000 0 0x8 0 0x02000000 0x01F00000 1240 >; 1241 }; 1242 1243 abb_dspeve: regulator-abb-dspeve { 1244 compatible = "ti,abb-v3"; 1245 regulator-name = "abb_dspeve"; 1246 #address-cells = <0>; 1247 #size-cells = <0>; 1248 clocks = <&sys_clkin1>; 1249 ti,settling-time = <50>; 1250 ti,clock-cycles = <16>; 1251 1252 reg = <0x4ae07e30 0x4>, <0x4ae07e20 0x4>, 1253 <0x4ae06010 0x4>, <0x4a0025e0 0xc>, 1254 <0x4a00246c 0x4>; 1255 reg-names = "setup-address", "control-address", 1256 "int-address", "efuse-address", 1257 "ldo-address"; 1258 ti,tranxdone-status-mask = <0x20000000>; 1259 /* LDOVBBDSPEVE_FBB_MUX_CTRL */ 1260 ti,ldovbb-override-mask = <0x400>; 1261 /* LDOVBBDSPEVE_FBB_VSET_OUT */ 1262 ti,ldovbb-vset-mask = <0x1F>; 1263 1264 /* 1265 * NOTE: only FBB mode used but actual vset will 1266 * determine final biasing 1267 */ 1268 ti,abb_info = < 1269 /*uV ABB efuse rbb_m fbb_m vset_m*/ 1270 1055000 0 0x0 0 0x02000000 0x01F00000 1271 1150000 0 0x4 0 0x02000000 0x01F00000 1272 1250000 0 0x8 0 0x02000000 0x01F00000 1273 >; 1274 }; 1275 1276 abb_gpu: regulator-abb-gpu { 1277 compatible = "ti,abb-v3"; 1278 regulator-name = "abb_gpu"; 1279 #address-cells = <0>; 1280 #size-cells = <0>; 1281 clocks = <&sys_clkin1>; 1282 ti,settling-time = <50>; 1283 ti,clock-cycles = <16>; 1284 1285 reg = <0x4ae07de4 0x4>, <0x4ae07de8 0x4>, 1286 <0x4ae06010 0x4>, <0x4a003b08 0xc>, 1287 <0x4ae0c154 0x4>; 1288 reg-names = "setup-address", "control-address", 1289 "int-address", "efuse-address", 1290 "ldo-address"; 1291 ti,tranxdone-status-mask = <0x10000000>; 1292 /* LDOVBBGPU_FBB_MUX_CTRL */ 1293 ti,ldovbb-override-mask = <0x400>; 1294 /* LDOVBBGPU_FBB_VSET_OUT */ 1295 ti,ldovbb-vset-mask = <0x1F>; 1296 1297 /* 1298 * NOTE: only FBB mode used but actual vset will 1299 * determine final biasing 1300 */ 1301 ti,abb_info = < 1302 /*uV ABB efuse rbb_m fbb_m vset_m*/ 1303 1090000 0 0x0 0 0x02000000 0x01F00000 1304 1210000 0 0x4 0 0x02000000 0x01F00000 1305 1280000 0 0x8 0 0x02000000 0x01F00000 1306 >; 1307 }; 1308 1309 mcspi1: spi@48098000 { 1310 compatible = "ti,omap4-mcspi"; 1311 reg = <0x48098000 0x200>; 1312 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 1313 #address-cells = <1>; 1314 #size-cells = <0>; 1315 ti,hwmods = "mcspi1"; 1316 ti,spi-num-cs = <4>; 1317 dmas = <&sdma_xbar 35>, 1318 <&sdma_xbar 36>, 1319 <&sdma_xbar 37>, 1320 <&sdma_xbar 38>, 1321 <&sdma_xbar 39>, 1322 <&sdma_xbar 40>, 1323 <&sdma_xbar 41>, 1324 <&sdma_xbar 42>; 1325 dma-names = "tx0", "rx0", "tx1", "rx1", 1326 "tx2", "rx2", "tx3", "rx3"; 1327 status = "disabled"; 1328 }; 1329 1330 mcspi2: spi@4809a000 { 1331 compatible = "ti,omap4-mcspi"; 1332 reg = <0x4809a000 0x200>; 1333 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 1334 #address-cells = <1>; 1335 #size-cells = <0>; 1336 ti,hwmods = "mcspi2"; 1337 ti,spi-num-cs = <2>; 1338 dmas = <&sdma_xbar 43>, 1339 <&sdma_xbar 44>, 1340 <&sdma_xbar 45>, 1341 <&sdma_xbar 46>; 1342 dma-names = "tx0", "rx0", "tx1", "rx1"; 1343 status = "disabled"; 1344 }; 1345 1346 mcspi3: spi@480b8000 { 1347 compatible = "ti,omap4-mcspi"; 1348 reg = <0x480b8000 0x200>; 1349 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 1350 #address-cells = <1>; 1351 #size-cells = <0>; 1352 ti,hwmods = "mcspi3"; 1353 ti,spi-num-cs = <2>; 1354 dmas = <&sdma_xbar 15>, <&sdma_xbar 16>; 1355 dma-names = "tx0", "rx0"; 1356 status = "disabled"; 1357 }; 1358 1359 mcspi4: spi@480ba000 { 1360 compatible = "ti,omap4-mcspi"; 1361 reg = <0x480ba000 0x200>; 1362 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 1363 #address-cells = <1>; 1364 #size-cells = <0>; 1365 ti,hwmods = "mcspi4"; 1366 ti,spi-num-cs = <1>; 1367 dmas = <&sdma_xbar 70>, <&sdma_xbar 71>; 1368 dma-names = "tx0", "rx0"; 1369 status = "disabled"; 1370 }; 1371 1372 qspi: qspi@4b300000 { 1373 compatible = "ti,dra7xxx-qspi"; 1374 reg = <0x4b300000 0x100>, 1375 <0x5c000000 0x4000000>; 1376 reg-names = "qspi_base", "qspi_mmap"; 1377 syscon-chipselects = <&scm_conf 0x558>; 1378 #address-cells = <1>; 1379 #size-cells = <0>; 1380 ti,hwmods = "qspi"; 1381 clocks = <&l4per_clkctrl DRA7_QSPI_CLKCTRL 25>; 1382 clock-names = "fck"; 1383 num-cs = <4>; 1384 interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>; 1385 status = "disabled"; 1386 }; 1387 1388 /* OCP2SCP3 */ 1389 ocp2scp@4a090000 { 1390 compatible = "ti,omap-ocp2scp"; 1391 #address-cells = <1>; 1392 #size-cells = <1>; 1393 ranges; 1394 reg = <0x4a090000 0x20>; 1395 ti,hwmods = "ocp2scp3"; 1396 sata_phy: phy@4a096000 { 1397 compatible = "ti,phy-pipe3-sata"; 1398 reg = <0x4A096000 0x80>, /* phy_rx */ 1399 <0x4A096400 0x64>, /* phy_tx */ 1400 <0x4A096800 0x40>; /* pll_ctrl */ 1401 reg-names = "phy_rx", "phy_tx", "pll_ctrl"; 1402 syscon-phy-power = <&scm_conf 0x374>; 1403 clocks = <&sys_clkin1>, 1404 <&l3init_clkctrl DRA7_SATA_CLKCTRL 8>; 1405 clock-names = "sysclk", "refclk"; 1406 syscon-pllreset = <&scm_conf 0x3fc>; 1407 #phy-cells = <0>; 1408 }; 1409 1410 pcie1_phy: pciephy@4a094000 { 1411 compatible = "ti,phy-pipe3-pcie"; 1412 reg = <0x4a094000 0x80>, /* phy_rx */ 1413 <0x4a094400 0x64>; /* phy_tx */ 1414 reg-names = "phy_rx", "phy_tx"; 1415 syscon-phy-power = <&scm_conf_pcie 0x1c>; 1416 syscon-pcs = <&scm_conf_pcie 0x10>; 1417 clocks = <&dpll_pcie_ref_ck>, 1418 <&dpll_pcie_ref_m2ldo_ck>, 1419 <&l3init_clkctrl DRA7_PCIE1_CLKCTRL 8>, 1420 <&l3init_clkctrl DRA7_PCIE1_CLKCTRL 9>, 1421 <&l3init_clkctrl DRA7_PCIE1_CLKCTRL 10>, 1422 <&optfclk_pciephy_div>, 1423 <&sys_clkin1>; 1424 clock-names = "dpll_ref", "dpll_ref_m2", 1425 "wkupclk", "refclk", 1426 "div-clk", "phy-div", "sysclk"; 1427 #phy-cells = <0>; 1428 }; 1429 1430 pcie2_phy: pciephy@4a095000 { 1431 compatible = "ti,phy-pipe3-pcie"; 1432 reg = <0x4a095000 0x80>, /* phy_rx */ 1433 <0x4a095400 0x64>; /* phy_tx */ 1434 reg-names = "phy_rx", "phy_tx"; 1435 syscon-phy-power = <&scm_conf_pcie 0x20>; 1436 syscon-pcs = <&scm_conf_pcie 0x10>; 1437 clocks = <&dpll_pcie_ref_ck>, 1438 <&dpll_pcie_ref_m2ldo_ck>, 1439 <&l3init_clkctrl DRA7_PCIE2_CLKCTRL 8>, 1440 <&l3init_clkctrl DRA7_PCIE2_CLKCTRL 9>, 1441 <&l3init_clkctrl DRA7_PCIE2_CLKCTRL 10>, 1442 <&optfclk_pciephy_div>, 1443 <&sys_clkin1>; 1444 clock-names = "dpll_ref", "dpll_ref_m2", 1445 "wkupclk", "refclk", 1446 "div-clk", "phy-div", "sysclk"; 1447 #phy-cells = <0>; 1448 status = "disabled"; 1449 }; 1450 }; 1451 1452 sata: sata@4a141100 { 1453 compatible = "snps,dwc-ahci"; 1454 reg = <0x4a140000 0x1100>, <0x4a141100 0x7>; 1455 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 1456 phys = <&sata_phy>; 1457 phy-names = "sata-phy"; 1458 clocks = <&l3init_clkctrl DRA7_SATA_CLKCTRL 8>; 1459 ti,hwmods = "sata"; 1460 ports-implemented = <0x1>; 1461 }; 1462 1463 rtc: rtc@48838000 { 1464 compatible = "ti,am3352-rtc"; 1465 reg = <0x48838000 0x100>; 1466 interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, 1467 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>; 1468 ti,hwmods = "rtcss"; 1469 clocks = <&sys_32k_ck>; 1470 }; 1471 1472 /* OCP2SCP1 */ 1473 ocp2scp@4a080000 { 1474 compatible = "ti,omap-ocp2scp"; 1475 #address-cells = <1>; 1476 #size-cells = <1>; 1477 ranges; 1478 reg = <0x4a080000 0x20>; 1479 ti,hwmods = "ocp2scp1"; 1480 1481 usb2_phy1: phy@4a084000 { 1482 compatible = "ti,dra7x-usb2", "ti,omap-usb2"; 1483 reg = <0x4a084000 0x400>; 1484 syscon-phy-power = <&scm_conf 0x300>; 1485 clocks = <&usb_phy1_always_on_clk32k>, 1486 <&l3init_clkctrl DRA7_USB_OTG_SS1_CLKCTRL 8>; 1487 clock-names = "wkupclk", 1488 "refclk"; 1489 #phy-cells = <0>; 1490 }; 1491 1492 usb2_phy2: phy@4a085000 { 1493 compatible = "ti,dra7x-usb2-phy2", 1494 "ti,omap-usb2"; 1495 reg = <0x4a085000 0x400>; 1496 syscon-phy-power = <&scm_conf 0xe74>; 1497 clocks = <&usb_phy2_always_on_clk32k>, 1498 <&l3init_clkctrl DRA7_USB_OTG_SS2_CLKCTRL 8>; 1499 clock-names = "wkupclk", 1500 "refclk"; 1501 #phy-cells = <0>; 1502 }; 1503 1504 usb3_phy1: phy@4a084400 { 1505 compatible = "ti,omap-usb3"; 1506 reg = <0x4a084400 0x80>, 1507 <0x4a084800 0x64>, 1508 <0x4a084c00 0x40>; 1509 reg-names = "phy_rx", "phy_tx", "pll_ctrl"; 1510 syscon-phy-power = <&scm_conf 0x370>; 1511 clocks = <&usb_phy3_always_on_clk32k>, 1512 <&sys_clkin1>, 1513 <&l3init_clkctrl DRA7_USB_OTG_SS1_CLKCTRL 8>; 1514 clock-names = "wkupclk", 1515 "sysclk", 1516 "refclk"; 1517 #phy-cells = <0>; 1518 }; 1519 }; 1520 1521 target-module@4a0dd000 { 1522 compatible = "ti,sysc-omap4-sr", "ti,sysc"; 1523 ti,hwmods = "smartreflex_core"; 1524 reg = <0x4a0dd038 0x4>; 1525 reg-names = "sysc"; 1526 ti,sysc-mask = <SYSC_OMAP3_SR_ENAWAKEUP>; 1527 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1528 <SYSC_IDLE_NO>, 1529 <SYSC_IDLE_SMART>, 1530 <SYSC_IDLE_SMART_WKUP>; 1531 clocks = <&coreaon_clkctrl DRA7_SMARTREFLEX_CORE_CLKCTRL 0>; 1532 clock-names = "fck"; 1533 #address-cells = <1>; 1534 #size-cells = <1>; 1535 ranges = <0 0x4a0dd000 0x001000>; 1536 1537 /* SmartReflex child device marked reserved in TRM */ 1538 }; 1539 1540 target-module@4a0d9000 { 1541 compatible = "ti,sysc-omap4-sr", "ti,sysc"; 1542 ti,hwmods = "smartreflex_mpu"; 1543 reg = <0x4a0d9038 0x4>; 1544 reg-names = "sysc"; 1545 ti,sysc-mask = <SYSC_OMAP3_SR_ENAWAKEUP>; 1546 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1547 <SYSC_IDLE_NO>, 1548 <SYSC_IDLE_SMART>, 1549 <SYSC_IDLE_SMART_WKUP>; 1550 clocks = <&coreaon_clkctrl DRA7_SMARTREFLEX_MPU_CLKCTRL 0>; 1551 clock-names = "fck"; 1552 #address-cells = <1>; 1553 #size-cells = <1>; 1554 ranges = <0 0x4a0d9000 0x001000>; 1555 1556 /* SmartReflex child device marked reserved in TRM */ 1557 }; 1558 1559 omap_dwc3_1: omap_dwc3_1@48880000 { 1560 compatible = "ti,dwc3"; 1561 ti,hwmods = "usb_otg_ss1"; 1562 reg = <0x48880000 0x10000>; 1563 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 1564 #address-cells = <1>; 1565 #size-cells = <1>; 1566 utmi-mode = <2>; 1567 ranges; 1568 usb1: usb@48890000 { 1569 compatible = "snps,dwc3"; 1570 reg = <0x48890000 0x17000>; 1571 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, 1572 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, 1573 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 1574 interrupt-names = "peripheral", 1575 "host", 1576 "otg"; 1577 phys = <&usb2_phy1>, <&usb3_phy1>; 1578 phy-names = "usb2-phy", "usb3-phy"; 1579 maximum-speed = "super-speed"; 1580 dr_mode = "otg"; 1581 snps,dis_u3_susphy_quirk; 1582 snps,dis_u2_susphy_quirk; 1583 }; 1584 }; 1585 1586 omap_dwc3_2: omap_dwc3_2@488c0000 { 1587 compatible = "ti,dwc3"; 1588 ti,hwmods = "usb_otg_ss2"; 1589 reg = <0x488c0000 0x10000>; 1590 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 1591 #address-cells = <1>; 1592 #size-cells = <1>; 1593 utmi-mode = <2>; 1594 ranges; 1595 usb2: usb@488d0000 { 1596 compatible = "snps,dwc3"; 1597 reg = <0x488d0000 0x17000>; 1598 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 1599 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 1600 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 1601 interrupt-names = "peripheral", 1602 "host", 1603 "otg"; 1604 phys = <&usb2_phy2>; 1605 phy-names = "usb2-phy"; 1606 maximum-speed = "high-speed"; 1607 dr_mode = "otg"; 1608 snps,dis_u3_susphy_quirk; 1609 snps,dis_u2_susphy_quirk; 1610 snps,dis_metastability_quirk; 1611 }; 1612 }; 1613 1614 /* IRQ for DWC3_3 and DWC3_4 need IRQ crossbar */ 1615 omap_dwc3_3: omap_dwc3_3@48900000 { 1616 compatible = "ti,dwc3"; 1617 ti,hwmods = "usb_otg_ss3"; 1618 reg = <0x48900000 0x10000>; 1619 interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>; 1620 #address-cells = <1>; 1621 #size-cells = <1>; 1622 utmi-mode = <2>; 1623 ranges; 1624 status = "disabled"; 1625 usb3: usb@48910000 { 1626 compatible = "snps,dwc3"; 1627 reg = <0x48910000 0x17000>; 1628 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 1629 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 1630 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>; 1631 interrupt-names = "peripheral", 1632 "host", 1633 "otg"; 1634 maximum-speed = "high-speed"; 1635 dr_mode = "otg"; 1636 snps,dis_u3_susphy_quirk; 1637 snps,dis_u2_susphy_quirk; 1638 }; 1639 }; 1640 1641 elm: elm@48078000 { 1642 compatible = "ti,am3352-elm"; 1643 reg = <0x48078000 0xfc0>; /* device IO registers */ 1644 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 1645 ti,hwmods = "elm"; 1646 status = "disabled"; 1647 }; 1648 1649 gpmc: gpmc@50000000 { 1650 compatible = "ti,am3352-gpmc"; 1651 ti,hwmods = "gpmc"; 1652 reg = <0x50000000 0x37c>; /* device IO registers */ 1653 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 1654 dmas = <&edma_xbar 4 0>; 1655 dma-names = "rxtx"; 1656 gpmc,num-cs = <8>; 1657 gpmc,num-waitpins = <2>; 1658 #address-cells = <2>; 1659 #size-cells = <1>; 1660 interrupt-controller; 1661 #interrupt-cells = <2>; 1662 gpio-controller; 1663 #gpio-cells = <2>; 1664 status = "disabled"; 1665 }; 1666 1667 atl: atl@4843c000 { 1668 compatible = "ti,dra7-atl"; 1669 reg = <0x4843c000 0x3ff>; 1670 ti,hwmods = "atl"; 1671 ti,provided-clocks = <&atl_clkin0_ck>, <&atl_clkin1_ck>, 1672 <&atl_clkin2_ck>, <&atl_clkin3_ck>; 1673 clocks = <&atl_clkctrl DRA7_ATL_CLKCTRL 26>; 1674 clock-names = "fck"; 1675 status = "disabled"; 1676 }; 1677 1678 mcasp1: mcasp@48460000 { 1679 compatible = "ti,dra7-mcasp-audio"; 1680 ti,hwmods = "mcasp1"; 1681 reg = <0x48460000 0x2000>, 1682 <0x45800000 0x1000>; 1683 reg-names = "mpu","dat"; 1684 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 1685 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 1686 interrupt-names = "tx", "rx"; 1687 dmas = <&edma_xbar 129 1>, <&edma_xbar 128 1>; 1688 dma-names = "tx", "rx"; 1689 clocks = <&ipu_clkctrl DRA7_MCASP1_CLKCTRL 22>, <&ipu_clkctrl DRA7_MCASP1_CLKCTRL 24>, 1690 <&ipu_clkctrl DRA7_MCASP1_CLKCTRL 28>; 1691 clock-names = "fck", "ahclkx", "ahclkr"; 1692 status = "disabled"; 1693 }; 1694 1695 mcasp2: mcasp@48464000 { 1696 compatible = "ti,dra7-mcasp-audio"; 1697 ti,hwmods = "mcasp2"; 1698 reg = <0x48464000 0x2000>, 1699 <0x45c00000 0x1000>; 1700 reg-names = "mpu","dat"; 1701 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 1702 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 1703 interrupt-names = "tx", "rx"; 1704 dmas = <&edma_xbar 131 1>, <&edma_xbar 130 1>; 1705 dma-names = "tx", "rx"; 1706 clocks = <&l4per_clkctrl DRA7_MCASP2_CLKCTRL 22>, 1707 <&l4per_clkctrl DRA7_MCASP2_CLKCTRL 24>, 1708 <&l4per_clkctrl DRA7_MCASP2_CLKCTRL 28>; 1709 clock-names = "fck", "ahclkx", "ahclkr"; 1710 status = "disabled"; 1711 }; 1712 1713 mcasp3: mcasp@48468000 { 1714 compatible = "ti,dra7-mcasp-audio"; 1715 ti,hwmods = "mcasp3"; 1716 reg = <0x48468000 0x2000>, 1717 <0x46000000 0x1000>; 1718 reg-names = "mpu","dat"; 1719 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 1720 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; 1721 interrupt-names = "tx", "rx"; 1722 dmas = <&edma_xbar 133 1>, <&edma_xbar 132 1>; 1723 dma-names = "tx", "rx"; 1724 clocks = <&l4per_clkctrl DRA7_MCASP3_CLKCTRL 22>, 1725 <&l4per_clkctrl DRA7_MCASP3_CLKCTRL 24>; 1726 clock-names = "fck", "ahclkx"; 1727 status = "disabled"; 1728 }; 1729 1730 mcasp4: mcasp@4846c000 { 1731 compatible = "ti,dra7-mcasp-audio"; 1732 ti,hwmods = "mcasp4"; 1733 reg = <0x4846c000 0x2000>, 1734 <0x48436000 0x1000>; 1735 reg-names = "mpu","dat"; 1736 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 1737 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 1738 interrupt-names = "tx", "rx"; 1739 dmas = <&edma_xbar 135 1>, <&edma_xbar 134 1>; 1740 dma-names = "tx", "rx"; 1741 clocks = <&l4per_clkctrl DRA7_MCASP4_CLKCTRL 22>, 1742 <&l4per_clkctrl DRA7_MCASP4_CLKCTRL 24>; 1743 clock-names = "fck", "ahclkx"; 1744 status = "disabled"; 1745 }; 1746 1747 mcasp5: mcasp@48470000 { 1748 compatible = "ti,dra7-mcasp-audio"; 1749 ti,hwmods = "mcasp5"; 1750 reg = <0x48470000 0x2000>, 1751 <0x4843a000 0x1000>; 1752 reg-names = "mpu","dat"; 1753 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 1754 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 1755 interrupt-names = "tx", "rx"; 1756 dmas = <&edma_xbar 137 1>, <&edma_xbar 136 1>; 1757 dma-names = "tx", "rx"; 1758 clocks = <&l4per_clkctrl DRA7_MCASP5_CLKCTRL 22>, 1759 <&l4per_clkctrl DRA7_MCASP5_CLKCTRL 24>; 1760 clock-names = "fck", "ahclkx"; 1761 status = "disabled"; 1762 }; 1763 1764 mcasp6: mcasp@48474000 { 1765 compatible = "ti,dra7-mcasp-audio"; 1766 ti,hwmods = "mcasp6"; 1767 reg = <0x48474000 0x2000>, 1768 <0x4844c000 0x1000>; 1769 reg-names = "mpu","dat"; 1770 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 1771 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 1772 interrupt-names = "tx", "rx"; 1773 dmas = <&edma_xbar 139 1>, <&edma_xbar 138 1>; 1774 dma-names = "tx", "rx"; 1775 clocks = <&l4per_clkctrl DRA7_MCASP6_CLKCTRL 22>, 1776 <&l4per_clkctrl DRA7_MCASP6_CLKCTRL 24>; 1777 clock-names = "fck", "ahclkx"; 1778 status = "disabled"; 1779 }; 1780 1781 mcasp7: mcasp@48478000 { 1782 compatible = "ti,dra7-mcasp-audio"; 1783 ti,hwmods = "mcasp7"; 1784 reg = <0x48478000 0x2000>, 1785 <0x48450000 0x1000>; 1786 reg-names = "mpu","dat"; 1787 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, 1788 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 1789 interrupt-names = "tx", "rx"; 1790 dmas = <&edma_xbar 141 1>, <&edma_xbar 140 1>; 1791 dma-names = "tx", "rx"; 1792 clocks = <&l4per_clkctrl DRA7_MCASP7_CLKCTRL 22>, 1793 <&l4per_clkctrl DRA7_MCASP7_CLKCTRL 24>; 1794 clock-names = "fck", "ahclkx"; 1795 status = "disabled"; 1796 }; 1797 1798 mcasp8: mcasp@4847c000 { 1799 compatible = "ti,dra7-mcasp-audio"; 1800 ti,hwmods = "mcasp8"; 1801 reg = <0x4847c000 0x2000>, 1802 <0x48454000 0x1000>; 1803 reg-names = "mpu","dat"; 1804 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, 1805 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 1806 interrupt-names = "tx", "rx"; 1807 dmas = <&edma_xbar 143 1>, <&edma_xbar 142 1>; 1808 dma-names = "tx", "rx"; 1809 clocks = <&l4per_clkctrl DRA7_MCASP8_CLKCTRL 22>, 1810 <&l4per_clkctrl DRA7_MCASP8_CLKCTRL 24>; 1811 clock-names = "fck", "ahclkx"; 1812 status = "disabled"; 1813 }; 1814 1815 crossbar_mpu: crossbar@4a002a48 { 1816 compatible = "ti,irq-crossbar"; 1817 reg = <0x4a002a48 0x130>; 1818 interrupt-controller; 1819 interrupt-parent = <&wakeupgen>; 1820 #interrupt-cells = <3>; 1821 ti,max-irqs = <160>; 1822 ti,max-crossbar-sources = <MAX_SOURCES>; 1823 ti,reg-size = <2>; 1824 ti,irqs-reserved = <0 1 2 3 5 6 131 132>; 1825 ti,irqs-skip = <10 133 139 140>; 1826 ti,irqs-safe-map = <0>; 1827 }; 1828 1829 mac: ethernet@48484000 { 1830 compatible = "ti,dra7-cpsw","ti,cpsw"; 1831 ti,hwmods = "gmac"; 1832 clocks = <&gmac_main_clk>, <&l3init_clkctrl DRA7_GMAC_CLKCTRL 25>; 1833 clock-names = "fck", "cpts"; 1834 cpdma_channels = <8>; 1835 ale_entries = <1024>; 1836 bd_ram_size = <0x2000>; 1837 mac_control = <0x20>; 1838 slaves = <2>; 1839 active_slave = <0>; 1840 cpts_clock_mult = <0x784CFE14>; 1841 cpts_clock_shift = <29>; 1842 reg = <0x48484000 0x1000 1843 0x48485200 0x2E00>; 1844 #address-cells = <1>; 1845 #size-cells = <1>; 1846 1847 /* 1848 * Do not allow gating of cpsw clock as workaround 1849 * for errata i877. Keeping internal clock disabled 1850 * causes the device switching characteristics 1851 * to degrade over time and eventually fail to meet 1852 * the data manual delay time/skew specs. 1853 */ 1854 ti,no-idle; 1855 1856 /* 1857 * rx_thresh_pend 1858 * rx_pend 1859 * tx_pend 1860 * misc_pend 1861 */ 1862 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 1863 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 1864 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 1865 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>; 1866 ranges; 1867 syscon = <&scm_conf>; 1868 status = "disabled"; 1869 1870 davinci_mdio: mdio@48485000 { 1871 compatible = "ti,cpsw-mdio","ti,davinci_mdio"; 1872 #address-cells = <1>; 1873 #size-cells = <0>; 1874 ti,hwmods = "davinci_mdio"; 1875 bus_freq = <1000000>; 1876 reg = <0x48485000 0x100>; 1877 }; 1878 1879 cpsw_emac0: slave@48480200 { 1880 /* Filled in by U-Boot */ 1881 mac-address = [ 00 00 00 00 00 00 ]; 1882 }; 1883 1884 cpsw_emac1: slave@48480300 { 1885 /* Filled in by U-Boot */ 1886 mac-address = [ 00 00 00 00 00 00 ]; 1887 }; 1888 1889 phy_sel: cpsw-phy-sel@4a002554 { 1890 compatible = "ti,dra7xx-cpsw-phy-sel"; 1891 reg= <0x4a002554 0x4>; 1892 reg-names = "gmii-sel"; 1893 }; 1894 }; 1895 1896 dcan1: can@4ae3c000 { 1897 compatible = "ti,dra7-d_can"; 1898 ti,hwmods = "dcan1"; 1899 reg = <0x4ae3c000 0x2000>; 1900 syscon-raminit = <&scm_conf 0x558 0>; 1901 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 1902 clocks = <&wkupaon_clkctrl DRA7_DCAN1_CLKCTRL 24>; 1903 status = "disabled"; 1904 }; 1905 1906 dcan2: can@48480000 { 1907 compatible = "ti,dra7-d_can"; 1908 ti,hwmods = "dcan2"; 1909 reg = <0x48480000 0x2000>; 1910 syscon-raminit = <&scm_conf 0x558 1>; 1911 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; 1912 clocks = <&sys_clkin1>; 1913 status = "disabled"; 1914 }; 1915 1916 dss: dss@58000000 { 1917 compatible = "ti,dra7-dss"; 1918 /* 'reg' defined in dra72x.dtsi and dra74x.dtsi */ 1919 /* 'clocks' defined in dra72x.dtsi and dra74x.dtsi */ 1920 status = "disabled"; 1921 ti,hwmods = "dss_core"; 1922 /* CTRL_CORE_DSS_PLL_CONTROL */ 1923 syscon-pll-ctrl = <&scm_conf 0x538>; 1924 #address-cells = <1>; 1925 #size-cells = <1>; 1926 ranges; 1927 1928 dispc@58001000 { 1929 compatible = "ti,dra7-dispc"; 1930 reg = <0x58001000 0x1000>; 1931 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 1932 ti,hwmods = "dss_dispc"; 1933 clocks = <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 8>; 1934 clock-names = "fck"; 1935 /* CTRL_CORE_SMA_SW_1 */ 1936 syscon-pol = <&scm_conf 0x534>; 1937 }; 1938 1939 hdmi: encoder@58060000 { 1940 compatible = "ti,dra7-hdmi"; 1941 reg = <0x58040000 0x200>, 1942 <0x58040200 0x80>, 1943 <0x58040300 0x80>, 1944 <0x58060000 0x19000>; 1945 reg-names = "wp", "pll", "phy", "core"; 1946 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 1947 status = "disabled"; 1948 ti,hwmods = "dss_hdmi"; 1949 clocks = <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 9>, 1950 <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 10>; 1951 clock-names = "fck", "sys_clk"; 1952 dmas = <&sdma_xbar 76>; 1953 dma-names = "audio_tx"; 1954 }; 1955 }; 1956 1957 epwmss0: epwmss@4843e000 { 1958 compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss"; 1959 reg = <0x4843e000 0x30>; 1960 ti,hwmods = "epwmss0"; 1961 #address-cells = <1>; 1962 #size-cells = <1>; 1963 status = "disabled"; 1964 ranges; 1965 1966 ehrpwm0: pwm@4843e200 { 1967 compatible = "ti,dra746-ehrpwm", 1968 "ti,am3352-ehrpwm"; 1969 #pwm-cells = <3>; 1970 reg = <0x4843e200 0x80>; 1971 clocks = <&ehrpwm0_tbclk>, <&l4_root_clk_div>; 1972 clock-names = "tbclk", "fck"; 1973 status = "disabled"; 1974 }; 1975 1976 ecap0: ecap@4843e100 { 1977 compatible = "ti,dra746-ecap", 1978 "ti,am3352-ecap"; 1979 #pwm-cells = <3>; 1980 reg = <0x4843e100 0x80>; 1981 clocks = <&l4_root_clk_div>; 1982 clock-names = "fck"; 1983 status = "disabled"; 1984 }; 1985 }; 1986 1987 epwmss1: epwmss@48440000 { 1988 compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss"; 1989 reg = <0x48440000 0x30>; 1990 ti,hwmods = "epwmss1"; 1991 #address-cells = <1>; 1992 #size-cells = <1>; 1993 status = "disabled"; 1994 ranges; 1995 1996 ehrpwm1: pwm@48440200 { 1997 compatible = "ti,dra746-ehrpwm", 1998 "ti,am3352-ehrpwm"; 1999 #pwm-cells = <3>; 2000 reg = <0x48440200 0x80>; 2001 clocks = <&ehrpwm1_tbclk>, <&l4_root_clk_div>; 2002 clock-names = "tbclk", "fck"; 2003 status = "disabled"; 2004 }; 2005 2006 ecap1: ecap@48440100 { 2007 compatible = "ti,dra746-ecap", 2008 "ti,am3352-ecap"; 2009 #pwm-cells = <3>; 2010 reg = <0x48440100 0x80>; 2011 clocks = <&l4_root_clk_div>; 2012 clock-names = "fck"; 2013 status = "disabled"; 2014 }; 2015 }; 2016 2017 epwmss2: epwmss@48442000 { 2018 compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss"; 2019 reg = <0x48442000 0x30>; 2020 ti,hwmods = "epwmss2"; 2021 #address-cells = <1>; 2022 #size-cells = <1>; 2023 status = "disabled"; 2024 ranges; 2025 2026 ehrpwm2: pwm@48442200 { 2027 compatible = "ti,dra746-ehrpwm", 2028 "ti,am3352-ehrpwm"; 2029 #pwm-cells = <3>; 2030 reg = <0x48442200 0x80>; 2031 clocks = <&ehrpwm2_tbclk>, <&l4_root_clk_div>; 2032 clock-names = "tbclk", "fck"; 2033 status = "disabled"; 2034 }; 2035 2036 ecap2: ecap@48442100 { 2037 compatible = "ti,dra746-ecap", 2038 "ti,am3352-ecap"; 2039 #pwm-cells = <3>; 2040 reg = <0x48442100 0x80>; 2041 clocks = <&l4_root_clk_div>; 2042 clock-names = "fck"; 2043 status = "disabled"; 2044 }; 2045 }; 2046 2047 aes1: aes@4b500000 { 2048 compatible = "ti,omap4-aes"; 2049 ti,hwmods = "aes1"; 2050 reg = <0x4b500000 0xa0>; 2051 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 2052 dmas = <&edma_xbar 111 0>, <&edma_xbar 110 0>; 2053 dma-names = "tx", "rx"; 2054 clocks = <&l3_iclk_div>; 2055 clock-names = "fck"; 2056 }; 2057 2058 aes2: aes@4b700000 { 2059 compatible = "ti,omap4-aes"; 2060 ti,hwmods = "aes2"; 2061 reg = <0x4b700000 0xa0>; 2062 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 2063 dmas = <&edma_xbar 114 0>, <&edma_xbar 113 0>; 2064 dma-names = "tx", "rx"; 2065 clocks = <&l3_iclk_div>; 2066 clock-names = "fck"; 2067 }; 2068 2069 des: des@480a5000 { 2070 compatible = "ti,omap4-des"; 2071 ti,hwmods = "des"; 2072 reg = <0x480a5000 0xa0>; 2073 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 2074 dmas = <&sdma_xbar 117>, <&sdma_xbar 116>; 2075 dma-names = "tx", "rx"; 2076 clocks = <&l3_iclk_div>; 2077 clock-names = "fck"; 2078 }; 2079 2080 sham: sham@53100000 { 2081 compatible = "ti,omap5-sham"; 2082 ti,hwmods = "sham"; 2083 reg = <0x4b101000 0x300>; 2084 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 2085 dmas = <&edma_xbar 119 0>; 2086 dma-names = "rx"; 2087 clocks = <&l3_iclk_div>; 2088 clock-names = "fck"; 2089 }; 2090 2091 rng: rng@48090000 { 2092 compatible = "ti,omap4-rng"; 2093 ti,hwmods = "rng"; 2094 reg = <0x48090000 0x2000>; 2095 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 2096 clocks = <&l3_iclk_div>; 2097 clock-names = "fck"; 2098 }; 2099 2100 opp_supply_mpu: opp-supply@4a003b20 { 2101 compatible = "ti,omap5-opp-supply"; 2102 reg = <0x4a003b20 0xc>; 2103 ti,efuse-settings = < 2104 /* uV offset */ 2105 1060000 0x0 2106 1160000 0x4 2107 1210000 0x8 2108 >; 2109 ti,absolute-max-voltage-uv = <1500000>; 2110 }; 2111 2112 }; 2113 2114 thermal_zones: thermal-zones { 2115 #include "omap4-cpu-thermal.dtsi" 2116 #include "omap5-gpu-thermal.dtsi" 2117 #include "omap5-core-thermal.dtsi" 2118 #include "dra7-dspeve-thermal.dtsi" 2119 #include "dra7-iva-thermal.dtsi" 2120 }; 2121 2122}; 2123 2124&cpu_thermal { 2125 polling-delay = <500>; /* milliseconds */ 2126 coefficients = <0 2000>; 2127}; 2128 2129&gpu_thermal { 2130 coefficients = <0 2000>; 2131}; 2132 2133&core_thermal { 2134 coefficients = <0 2000>; 2135}; 2136 2137&dspeve_thermal { 2138 coefficients = <0 2000>; 2139}; 2140 2141&iva_thermal { 2142 coefficients = <0 2000>; 2143}; 2144 2145&cpu_crit { 2146 temperature = <120000>; /* milli Celsius */ 2147}; 2148 2149#include "dra7xx-clocks.dtsi" 2150 2151&core_crit { 2152 temperature = <120000>; /* milli Celsius */ 2153}; 2154 2155&gpu_crit { 2156 temperature = <120000>; /* milli Celsius */ 2157}; 2158 2159&dspeve_crit { 2160 temperature = <120000>; /* milli Celsius */ 2161}; 2162 2163&iva_crit { 2164 temperature = <120000>; /* milli Celsius */ 2165}; 2166
